drivers/gpu/drm/i915/gt/intel_workarounds.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2014-2018 Intel Corporation
   4  */
   5
   6 #include "i915_drv.h"
   7 #include "i915_reg.h"
   8 #include "intel_context.h"
   9 #include "intel_engine_pm.h"
  10 #include "intel_engine_regs.h"
  11 #include "intel_gpu_commands.h"
  12 #include "intel_gt.h"
  13 #include "intel_gt_mcr.h"
  14 #include "intel_gt_regs.h"
  15 #include "intel_ring.h"
  16 #include "intel_workarounds.h"
  17
  18 /**
  19  * DOC: Hardware workarounds
  20  *
  21  * Hardware workarounds are register programming documented to be executed in
  22  * the driver that fall outside of the normal programming sequences for a
  23  * platform. There are some basic categories of workarounds, depending on
  24  * how/when they are applied:
  25  *
  26  * - Context workarounds: workarounds that touch registers that are
  27  *   saved/restored to/from the HW context image. The list is emitted (via Load
  28  *   Register Immediate commands) once when initializing the device and saved in
  29  *   the default context. That default context is then used on every context
  30  *   creation to have a "primed golden context", i.e. a context image that
  31  *   already contains the changes needed to all the registers.
  32  *
  33  *   Context workarounds should be implemented in the \*_ctx_workarounds_init()
  34  *   variants respective to the targeted platforms.
  35  *
  36  * - Engine workarounds: the list of these WAs is applied whenever the specific
  37  *   engine is reset. It's also possible that a set of engine classes share a
  38  *   common power domain and they are reset together. This happens on some
  39  *   platforms with render and compute engines. In this case (at least) one of
  40  *   them need to keeep the workaround programming: the approach taken in the
  41  *   driver is to tie those workarounds to the first compute/render engine that
  42  *   is registered.  When executing with GuC submission, engine resets are
  43  *   outside of kernel driver control, hence the list of registers involved in
  44  *   written once, on engine initialization, and then passed to GuC, that
  45  *   saves/restores their values before/after the reset takes place. See
  46  *   ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference.
  47  *
  48  *   Workarounds for registers specific to RCS and CCS should be implemented in
  49  *   rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for
  50  *   registers belonging to BCS, VCS or VECS should be implemented in
  51  *   xcs_engine_wa_init(). Workarounds for registers not belonging to a specific
  52  *   engine's MMIO range but that are part of of the common RCS/CCS reset domain
  53  *   should be implemented in general_render_compute_wa_init().
  54  *
  55  * - GT workarounds: the list of these WAs is applied whenever these registers
  56  *   revert to their default values: on GPU reset, suspend/resume [1]_, etc.
  57  *
  58  *   GT workarounds should be implemented in the \*_gt_workarounds_init()
  59  *   variants respective to the targeted platforms.
  60  *
  61  * - Register whitelist: some workarounds need to be implemented in userspace,
  62  *   but need to touch privileged registers. The whitelist in the kernel
  63  *   instructs the hardware to allow the access to happen. From the kernel side,
  64  *   this is just a special case of a MMIO workaround (as we write the list of
  65  *   these to/be-whitelisted registers to some special HW registers).
  66  *
  67  *   Register whitelisting should be done in the \*_whitelist_build() variants
  68  *   respective to the targeted platforms.
  69  *
  70  * - Workaround batchbuffers: buffers that get executed automatically by the
  71  *   hardware on every HW context restore. These buffers are created and
  72  *   programmed in the default context so the hardware always go through those
  73  *   programming sequences when switching contexts. The support for workaround
  74  *   batchbuffers is enabled these hardware mechanisms:
  75  *
  76  *   #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
  77  *      context, pointing the hardware to jump to that location when that offset
  78  *      is reached in the context restore. Workaround batchbuffer in the driver
  79  *      currently uses this mechanism for all platforms.
  80  *
  81  *   #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
  82  *      pointing the hardware to a buffer to continue executing after the
  83  *      engine registers are restored in a context restore sequence. This is
  84  *      currently not used in the driver.
  85  *
  86  * - Other:  There are WAs that, due to their nature, cannot be applied from a
  87  *   central place. Those are peppered around the rest of the code, as needed.
  88  *   Workarounds related to the display IP are the main example.
  89  *
  90  * .. [1] Technically, some registers are powercontext saved & restored, so they
  91  *    survive a suspend/resume. In practice, writing them again is not too
  92  *    costly and simplifies things, so it's the approach taken in the driver.
  93  */
  94
  95 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt,
  96                           const char *name, const char *engine_name)
  97 {
  98         wal->gt = gt;
  99         wal->name = name;
 100         wal->engine_name = engine_name;
 101 }
 102
 103 #define WA_LIST_CHUNK (1 << 4)
 104
 105 static void wa_init_finish(struct i915_wa_list *wal)
 106 {
 107         /* Trim unused entries. */
 108         if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) {
 109                 struct i915_wa *list = kmemdup(wal->list,
 110                                                wal->count * sizeof(*list),
 111                                                GFP_KERNEL);
 112
 113                 if (list) {
 114                         kfree(wal->list);
 115                         wal->list = list;
 116                 }
 117         }
 118
 119         if (!wal->count)
 120                 return;
 121
 122         drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n",
 123                 wal->wa_count, wal->name, wal->engine_name);
 124 }
 125
 126 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 127 {
 128         unsigned int addr = i915_mmio_reg_offset(wa->reg);
 129         struct drm_i915_private *i915 = wal->gt->i915;
 130         unsigned int start = 0, end = wal->count;
 131         const unsigned int grow = WA_LIST_CHUNK;
 132         struct i915_wa *wa_;
 133
 134         GEM_BUG_ON(!is_power_of_2(grow));
 135
 136         if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
 137                 struct i915_wa *list;
 138
 139                 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
 140                                      GFP_KERNEL);
 141                 if (!list) {
 142                         drm_err(&i915->drm, "No space for workaround init!\n");
 143                         return;
 144                 }
 145
 146                 if (wal->list) {
 147                         memcpy(list, wal->list, sizeof(*wa) * wal->count);
 148                         kfree(wal->list);
 149                 }
 150
 151                 wal->list = list;
 152         }
 153
 154         while (start < end) {
 155                 unsigned int mid = start + (end - start) / 2;
 156
 157                 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
 158                         start = mid + 1;
 159                 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
 160                         end = mid;
 161                 } else {
 162                         wa_ = &wal->list[mid];
 163
 164                         if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
 165                                 drm_err(&i915->drm,
 166                                         "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",
 167                                         i915_mmio_reg_offset(wa_->reg),
 168                                         wa_->clr, wa_->set);
 169
 170                                 wa_->set &= ~wa->clr;
 171                         }
 172
 173                         wal->wa_count++;
 174                         wa_->set |= wa->set;
 175                         wa_->clr |= wa->clr;
 176                         wa_->read |= wa->read;
 177                         return;
 178                 }
 179         }
 180
 181         wal->wa_count++;
 182         wa_ = &wal->list[wal->count++];
 183         *wa_ = *wa;
 184
 185         while (wa_-- > wal->list) {
 186                 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
 187                            i915_mmio_reg_offset(wa_[1].reg));
 188                 if (i915_mmio_reg_offset(wa_[1].reg) >
 189                     i915_mmio_reg_offset(wa_[0].reg))
 190                         break;
 191
 192                 swap(wa_[1], wa_[0]);
 193         }
 194 }
 195
 196 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
 197                    u32 clear, u32 set, u32 read_mask, bool masked_reg)
 198 {
 199         struct i915_wa wa = {
 200                 .reg  = reg,
 201                 .clr  = clear,
 202                 .set  = set,
 203                 .read = read_mask,
 204                 .masked_reg = masked_reg,
 205         };
 206
 207         _wa_add(wal, &wa);
 208 }
 209
 210 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg,
 211                        u32 clear, u32 set, u32 read_mask, bool masked_reg)
 212 {
 213         struct i915_wa wa = {
 214                 .mcr_reg = reg,
 215                 .clr  = clear,
 216                 .set  = set,
 217                 .read = read_mask,
 218                 .masked_reg = masked_reg,
 219                 .is_mcr = 1,
 220         };
 221
 222         _wa_add(wal, &wa);
 223 }
 224
 225 static void
 226 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
 227 {
 228         wa_add(wal, reg, clear, set, clear, false);
 229 }
 230
 231 static void
 232 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set)
 233 {
 234         wa_mcr_add(wal, reg, clear, set, clear, false);
 235 }
 236
 237 static void
 238 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 239 {
 240         wa_write_clr_set(wal, reg, ~0, set);
 241 }
 242
 243 static void
 244 wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
 245 {
 246         wa_mcr_write_clr_set(wal, reg, ~0, set);
 247 }
 248
 249 static void
 250 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
 251 {
 252         wa_write_clr_set(wal, reg, set, set);
 253 }
 254
 255 static void
 256 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
 257 {
 258         wa_mcr_write_clr_set(wal, reg, set, set);
 259 }
 260
 261 static void
 262 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
 263 {
 264         wa_write_clr_set(wal, reg, clr, 0);
 265 }
 266
 267 static void
 268 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr)
 269 {
 270         wa_mcr_write_clr_set(wal, reg, clr, 0);
 271 }
 272
 273 /*
 274  * WA operations on "masked register". A masked register has the upper 16 bits
 275  * documented as "masked" in b-spec. Its purpose is to allow writing to just a
 276  * portion of the register without a rmw: you simply write in the upper 16 bits
 277  * the mask of bits you are going to modify.
 278  *
 279  * The wa_masked_* family of functions already does the necessary operations to
 280  * calculate the mask based on the parameters passed, so user only has to
 281  * provide the lower 16 bits of that register.
 282  */
 283
 284 static void
 285 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 286 {
 287         wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
 288 }
 289
 290 static void
 291 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
 292 {
 293         wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
 294 }
 295
 296 static void
 297 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 298 {
 299         wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
 300 }
 301
 302 static void
 303 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
 304 {
 305         wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
 306 }
 307
 308 static void
 309 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
 310                     u32 mask, u32 val)
 311 {
 312         wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
 313 }
 314
 315 static void
 316 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg,
 317                         u32 mask, u32 val)
 318 {
 319         wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
 320 }
 321
 322 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
 323                                       struct i915_wa_list *wal)
 324 {
 325         wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
 326 }
 327
 328 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine,
 329                                       struct i915_wa_list *wal)
 330 {
 331         wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
 332 }
 333
 334 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
 335                                       struct i915_wa_list *wal)
 336 {
 337         wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
 338
 339         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 340         wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);
 341
 342         /* WaDisablePartialInstShootdown:bdw,chv */
 343         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
 344                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 345
 346         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 347          * workaround for a possible hang in the unlikely event a TLB
 348          * invalidation occurs during a PSD flush.
 349          */
 350         /* WaForceEnableNonCoherent:bdw,chv */
 351         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 352         wa_masked_en(wal, HDC_CHICKEN0,
 353                      HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 354                      HDC_FORCE_NON_COHERENT);
 355
 356         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 357          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 358          *  polygons in the same 8x4 pixel/sample area to be processed without
 359          *  stalling waiting for the earlier ones to write to Hierarchical Z
 360          *  buffer."
 361          *
 362          * This optimization is off by default for BDW and CHV; turn it on.
 363          */
 364         wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 365
 366         /* Wa4x4STCOptimizationDisable:bdw,chv */
 367         wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 368
 369         /*
 370          * BSpec recommends 8x4 when MSAA is used,
 371          * however in practice 16x4 seems fastest.
 372          *
 373          * Note that PS/WM thread counts depend on the WIZ hashing
 374          * disable bit, which we don't touch here, but it's good
 375          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 376          */
 377         wa_masked_field_set(wal, GEN7_GT_MODE,
 378                             GEN6_WIZ_HASHING_MASK,
 379                             GEN6_WIZ_HASHING_16x4);
 380 }
 381
 382 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
 383                                      struct i915_wa_list *wal)
 384 {
 385         struct drm_i915_private *i915 = engine->i915;
 386
 387         gen8_ctx_workarounds_init(engine, wal);
 388
 389         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 390         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 391
 392         /* WaDisableDopClockGating:bdw
 393          *
 394          * Also see the related UCGTCL1 write in bdw_init_clock_gating()
 395          * to disable EUTC clock gating.
 396          */
 397         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 398                          DOP_CLOCK_GATING_DISABLE);
 399
 400         wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
 401                          GEN8_SAMPLER_POWER_BYPASS_DIS);
 402
 403         wa_masked_en(wal, HDC_CHICKEN0,
 404                      /* WaForceContextSaveRestoreNonCoherent:bdw */
 405                      HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 406                      /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 407                      (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 408 }
 409
 410 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
 411                                      struct i915_wa_list *wal)
 412 {
 413         gen8_ctx_workarounds_init(engine, wal);
 414
 415         /* WaDisableThreadStallDopClockGating:chv */
 416         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 417
 418         /* Improve HiZ throughput on CHV. */
 419         wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 420 }
 421
 422 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
 423                                       struct i915_wa_list *wal)
 424 {
 425         struct drm_i915_private *i915 = engine->i915;
 426
 427         if (HAS_LLC(i915)) {
 428                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
 429                  *
 430                  * Must match Display Engine. See
 431                  * WaCompressedResourceDisplayNewHashMode.
 432                  */
 433                 wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 434                              GEN9_PBE_COMPRESSED_HASH_SELECTION);
 435                 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
 436                                  GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
 437         }
 438
 439         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
 440         /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
 441         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
 442                          FLOW_CONTROL_ENABLE |
 443                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 444
 445         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
 446         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
 447         wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
 448                          GEN9_ENABLE_YV12_BUGFIX |
 449                          GEN9_ENABLE_GPGPU_PREEMPTION);
 450
 451         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
 452         /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
 453         wa_masked_en(wal, CACHE_MODE_1,
 454                      GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 455                      GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 456
 457         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
 458         wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5,
 459                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 460
 461         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
 462         wa_masked_en(wal, HDC_CHICKEN0,
 463                      HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 464                      HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 465
 466         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 467          * both tied to WaForceContextSaveRestoreNonCoherent
 468          * in some hsds for skl. We keep the tie for all gen9. The
 469          * documentation is a bit hazy and so we want to get common behaviour,
 470          * even though there is no clear evidence we would need both on kbl/bxt.
 471          * This area has been source of system hangs so we play it safe
 472          * and mimic the skl regardless of what bspec says.
 473          *
 474          * Use Force Non-Coherent whenever executing a 3D context. This
 475          * is a workaround for a possible hang in the unlikely event
 476          * a TLB invalidation occurs during a PSD flush.
 477          */
 478
 479         /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
 480         wa_masked_en(wal, HDC_CHICKEN0,
 481                      HDC_FORCE_NON_COHERENT);
 482
 483         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
 484         if (IS_SKYLAKE(i915) ||
 485             IS_KABYLAKE(i915) ||
 486             IS_COFFEELAKE(i915) ||
 487             IS_COMETLAKE(i915))
 488                 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
 489                                  GEN8_SAMPLER_POWER_BYPASS_DIS);
 490
 491         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
 492         wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 493
 494         /*
 495          * Supporting preemption with fine-granularity requires changes in the
 496          * batch buffer programming. Since we can't break old userspace, we
 497          * need to set our default preemption level to safe value. Userspace is
 498          * still able to use more fine-grained preemption levels, since in
 499          * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
 500          * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
 501          * not real HW workarounds, but merely a way to start using preemption
 502          * while maintaining old contract with userspace.
 503          */
 504
 505         /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
 506         wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
 507
 508         /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
 509         wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
 510                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 511                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 512
 513         /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
 514         if (IS_GEN9_LP(i915))
 515                 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
 516 }
 517
 518 static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
 519                                 struct i915_wa_list *wal)
 520 {
 521         struct intel_gt *gt = engine->gt;
 522         u8 vals[3] = { 0, 0, 0 };
 523         unsigned int i;
 524
 525         for (i = 0; i < 3; i++) {
 526                 u8 ss;
 527
 528                 /*
 529                  * Only consider slices where one, and only one, subslice has 7
 530                  * EUs
 531                  */
 532                 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i]))
 533                         continue;
 534
 535                 /*
 536                  * subslice_7eu[i] != 0 (because of the check above) and
 537                  * ss_max == 4 (maximum number of subslices possible per slice)
 538                  *
 539                  * ->    0 <= ss <= 3;
 540                  */
 541                 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1;
 542                 vals[i] = 3 - ss;
 543         }
 544
 545         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
 546                 return;
 547
 548         /* Tune IZ hashing. See intel_device_info_runtime_init() */
 549         wa_masked_field_set(wal, GEN7_GT_MODE,
 550                             GEN9_IZ_HASHING_MASK(2) |
 551                             GEN9_IZ_HASHING_MASK(1) |
 552                             GEN9_IZ_HASHING_MASK(0),
 553                             GEN9_IZ_HASHING(2, vals[2]) |
 554                             GEN9_IZ_HASHING(1, vals[1]) |
 555                             GEN9_IZ_HASHING(0, vals[0]));
 556 }
 557
 558 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
 559                                      struct i915_wa_list *wal)
 560 {
 561         gen9_ctx_workarounds_init(engine, wal);
 562         skl_tune_iz_hashing(engine, wal);
 563 }
 564
 565 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
 566                                      struct i915_wa_list *wal)
 567 {
 568         gen9_ctx_workarounds_init(engine, wal);
 569
 570         /* WaDisableThreadStallDopClockGating:bxt */
 571         wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
 572                          STALL_DOP_GATING_DISABLE);
 573
 574         /* WaToEnableHwFixForPushConstHWBug:bxt */
 575         wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 576                      GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 577 }
 578
 579 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
 580                                      struct i915_wa_list *wal)
 581 {
 582         struct drm_i915_private *i915 = engine->i915;
 583
 584         gen9_ctx_workarounds_init(engine, wal);
 585
 586         /* WaToEnableHwFixForPushConstHWBug:kbl */
 587         if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
 588                 wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 589                              GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 590
 591         /* WaDisableSbeCacheDispatchPortSharing:kbl */
 592         wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
 593                          GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 594 }
 595
 596 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
 597                                      struct i915_wa_list *wal)
 598 {
 599         gen9_ctx_workarounds_init(engine, wal);
 600
 601         /* WaToEnableHwFixForPushConstHWBug:glk */
 602         wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 603                      GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 604 }
 605
 606 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
 607                                      struct i915_wa_list *wal)
 608 {
 609         gen9_ctx_workarounds_init(engine, wal);
 610
 611         /* WaToEnableHwFixForPushConstHWBug:cfl */
 612         wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
 613                      GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
 614
 615         /* WaDisableSbeCacheDispatchPortSharing:cfl */
 616         wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
 617                          GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 618 }
 619
 620 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 621                                      struct i915_wa_list *wal)
 622 {
 623         /* Wa_1406697149 (WaDisableBankHangMode:icl) */
 624         wa_write(wal,
 625                  GEN8_L3CNTLREG,
 626                  intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
 627                  GEN8_ERRDETBCTRL);
 628
 629         /* WaForceEnableNonCoherent:icl
 630          * This is not the same workaround as in early Gen9 platforms, where
 631          * lacking this could cause system hangs, but coherency performance
 632          * overhead is high and only a few compute workloads really need it
 633          * (the register is whitelisted in hardware now, so UMDs can opt in
 634          * for coherency if they have a good reason).
 635          */
 636         wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
 637
 638         /* WaEnableFloatBlendOptimization:icl */
 639         wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
 640                    _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
 641                    0 /* write-only, so skip validation */,
 642                    true);
 643
 644         /* WaDisableGPGPUMidThreadPreemption:icl */
 645         wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
 646                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 647                             GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 648
 649         /* allow headerless messages for preemptible GPGPU context */
 650         wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 651                          GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
 652
 653         /* Wa_1604278689:icl,ehl */
 654         wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
 655         wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER,
 656                          0, /* write-only register; skip validation */
 657                          0xFFFFFFFF);
 658
 659         /* Wa_1406306137:icl,ehl */
 660         wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
 661 }
 662
 663 /*
 664  * These settings aren't actually workarounds, but general tuning settings that
 665  * need to be programmed on dg2 platform.
 666  */
 667 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 668                                    struct i915_wa_list *wal)
 669 {
 670         wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
 671         wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
 672                              REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
 673         wa_mcr_add(wal,
 674                    XEHP_FF_MODE2,
 675                    FF_MODE2_TDS_TIMER_MASK,
 676                    FF_MODE2_TDS_TIMER_128,
 677                    0, false);
 678 }
 679
 680 /*
 681  * These settings aren't actually workarounds, but general tuning settings that
 682  * need to be programmed on several platforms.
 683  */
 684 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 685                                      struct i915_wa_list *wal)
 686 {
 687         /*
 688          * Although some platforms refer to it as Wa_1604555607, we need to
 689          * program it even on those that don't explicitly list that
 690          * workaround.
 691          *
 692          * Note that the programming of this register is further modified
 693          * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
 694          * Wa_1608008084 tells us the FF_MODE2 register will return the wrong
 695          * value when read. The default value for this register is zero for all
 696          * fields and there are no bit masks. So instead of doing a RMW we
 697          * should just write TDS timer value. For the same reason read
 698          * verification is ignored.
 699          */
 700         wa_add(wal,
 701                GEN12_FF_MODE2,
 702                FF_MODE2_TDS_TIMER_MASK,
 703                FF_MODE2_TDS_TIMER_128,
 704                0, false);
 705 }
 706
 707 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
 708                                        struct i915_wa_list *wal)
 709 {
 710         struct drm_i915_private *i915 = engine->i915;
 711
 712         gen12_ctx_gt_tuning_init(engine, wal);
 713
 714         /*
 715          * Wa_1409142259:tgl,dg1,adl-p
 716          * Wa_1409347922:tgl,dg1,adl-p
 717          * Wa_1409252684:tgl,dg1,adl-p
 718          * Wa_1409217633:tgl,dg1,adl-p
 719          * Wa_1409207793:tgl,dg1,adl-p
 720          * Wa_1409178076:tgl,dg1,adl-p
 721          * Wa_1408979724:tgl,dg1,adl-p
 722          * Wa_14010443199:tgl,rkl,dg1,adl-p
 723          * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p
 724          * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p
 725          */
 726         wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
 727                      GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 728
 729         /* WaDisableGPGPUMidThreadPreemption:gen12 */
 730         wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
 731                             GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 732                             GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 733
 734         /*
 735          * Wa_16011163337
 736          *
 737          * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due
 738          * to Wa_1608008084.
 739          */
 740         wa_add(wal,
 741                GEN12_FF_MODE2,
 742                FF_MODE2_GS_TIMER_MASK,
 743                FF_MODE2_GS_TIMER_224,
 744                0, false);
 745
 746         if (!IS_DG1(i915))
 747                 /* Wa_1806527549 */
 748                 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
 749 }
 750
 751 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
 752                                      struct i915_wa_list *wal)
 753 {
 754         gen12_ctx_workarounds_init(engine, wal);
 755
 756         /* Wa_1409044764 */
 757         wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3,
 758                       DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
 759
 760         /* Wa_22010493298 */
 761         wa_masked_en(wal, HIZ_CHICKEN,
 762                      DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
 763 }
 764
 765 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
 766                                      struct i915_wa_list *wal)
 767 {
 768         dg2_ctx_gt_tuning_init(engine, wal);
 769
 770         /* Wa_16011186671:dg2_g11 */
 771         if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
 772                 wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH);
 773                 wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE);
 774         }
 775
 776         if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
 777                 /* Wa_14010469329:dg2_g10 */
 778                 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
 779                                  XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
 780
 781                 /*
 782                  * Wa_22010465075:dg2_g10
 783                  * Wa_22010613112:dg2_g10
 784                  * Wa_14010698770:dg2_g10
 785                  */
 786                 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
 787                                  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
 788         }
 789
 790         /* Wa_16013271637:dg2 */
 791         wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
 792                          MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
 793
 794         /* Wa_14014947963:dg2 */
 795         if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
 796             IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
 797                 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
 798
 799         /* Wa_18018764978:dg2 */
 800         if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
 801             IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
 802                 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
 803
 804         /* Wa_15010599737:dg2 */
 805         wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
 806
 807         /* Wa_18019271663:dg2 */
 808         wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 809 }
 810
 811 static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
 812                                      struct i915_wa_list *wal)
 813 {
 814         struct drm_i915_private *i915 = engine->i915;
 815
 816         if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 817             IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
 818                 /* Wa_14014947963 */
 819                 wa_masked_field_set(wal, VF_PREEMPTION,
 820                                     PREEMPTION_VERTEX_COUNT, 0x4000);
 821
 822                 /* Wa_16013271637 */
 823                 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
 824                                  MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
 825
 826                 /* Wa_18019627453 */
 827                 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);
 828
 829                 /* Wa_18018764978 */
 830                 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
 831         }
 832
 833         /* Wa_18019271663 */
 834         wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 835 }
 836
 837 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
 838                                          struct i915_wa_list *wal)
 839 {
 840         /*
 841          * This is a "fake" workaround defined by software to ensure we
 842          * maintain reliable, backward-compatible behavior for userspace with
 843          * regards to how nested MI_BATCH_BUFFER_START commands are handled.
 844          *
 845          * The per-context setting of MI_MODE[12] determines whether the bits
 846          * of a nested MI_BATCH_BUFFER_START instruction should be interpreted
 847          * in the traditional manner or whether they should instead use a new
 848          * tgl+ meaning that breaks backward compatibility, but allows nesting
 849          * into 3rd-level batchbuffers.  When this new capability was first
 850          * added in TGL, it remained off by default unless a context
 851          * intentionally opted in to the new behavior.  However Xe_HPG now
 852          * flips this on by default and requires that we explicitly opt out if
 853          * we don't want the new behavior.
 854          *
 855          * From a SW perspective, we want to maintain the backward-compatible
 856          * behavior for userspace, so we'll apply a fake workaround to set it
 857          * back to the legacy behavior on platforms where the hardware default
 858          * is to break compatibility.  At the moment there is no Linux
 859          * userspace that utilizes third-level batchbuffers, so this will avoid
 860          * userspace from needing to make any changes.  using the legacy
 861          * meaning is the correct thing to do.  If/when we have userspace
 862          * consumers that want to utilize third-level batch nesting, we can
 863          * provide a context parameter to allow them to opt-in.
 864          */
 865         wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);
 866 }
 867
 868 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine,
 869                                    struct i915_wa_list *wal)
 870 {
 871         u8 mocs;
 872
 873         /*
 874          * Some blitter commands do not have a field for MOCS, those
 875          * commands will use MOCS index pointed by BLIT_CCTL.
 876          * BLIT_CCTL registers are needed to be programmed to un-cached.
 877          */
 878         if (engine->class == COPY_ENGINE_CLASS) {
 879                 mocs = engine->gt->mocs.uc_index;
 880                 wa_write_clr_set(wal,
 881                                  BLIT_CCTL(engine->mmio_base),
 882                                  BLIT_CCTL_MASK,
 883                                  BLIT_CCTL_MOCS(mocs, mocs));
 884         }
 885 }
 886
 887 /*
 888  * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround
 889  * defined by the hardware team, but it programming general context registers.
 890  * Adding those context register programming in context workaround
 891  * allow us to use the wa framework for proper application and validation.
 892  */
 893 static void
 894 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine,
 895                           struct i915_wa_list *wal)
 896 {
 897         if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
 898                 fakewa_disable_nestedbb_mode(engine, wal);
 899
 900         gen12_ctx_gt_mocs_init(engine, wal);
 901 }
 902
 903 static void
 904 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 905                            struct i915_wa_list *wal,
 906                            const char *name)
 907 {
 908         struct drm_i915_private *i915 = engine->i915;
 909
 910         wa_init_start(wal, engine->gt, name, engine->name);
 911
 912         /* Applies to all engines */
 913         /*
 914          * Fake workarounds are not the actual workaround but
 915          * programming of context registers using workaround framework.
 916          */
 917         if (GRAPHICS_VER(i915) >= 12)
 918                 gen12_ctx_gt_fake_wa_init(engine, wal);
 919
 920         if (engine->class != RENDER_CLASS)
 921                 goto done;
 922
 923         if (IS_METEORLAKE(i915))
 924                 mtl_ctx_workarounds_init(engine, wal);
 925         else if (IS_PONTEVECCHIO(i915))
 926                 ; /* noop; none at this time */
 927         else if (IS_DG2(i915))
 928                 dg2_ctx_workarounds_init(engine, wal);
 929         else if (IS_XEHPSDV(i915))
 930                 ; /* noop; none at this time */
 931         else if (IS_DG1(i915))
 932                 dg1_ctx_workarounds_init(engine, wal);
 933         else if (GRAPHICS_VER(i915) == 12)
 934                 gen12_ctx_workarounds_init(engine, wal);
 935         else if (GRAPHICS_VER(i915) == 11)
 936                 icl_ctx_workarounds_init(engine, wal);
 937         else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
 938                 cfl_ctx_workarounds_init(engine, wal);
 939         else if (IS_GEMINILAKE(i915))
 940                 glk_ctx_workarounds_init(engine, wal);
 941         else if (IS_KABYLAKE(i915))
 942                 kbl_ctx_workarounds_init(engine, wal);
 943         else if (IS_BROXTON(i915))
 944                 bxt_ctx_workarounds_init(engine, wal);
 945         else if (IS_SKYLAKE(i915))
 946                 skl_ctx_workarounds_init(engine, wal);
 947         else if (IS_CHERRYVIEW(i915))
 948                 chv_ctx_workarounds_init(engine, wal);
 949         else if (IS_BROADWELL(i915))
 950                 bdw_ctx_workarounds_init(engine, wal);
 951         else if (GRAPHICS_VER(i915) == 7)
 952                 gen7_ctx_workarounds_init(engine, wal);
 953         else if (GRAPHICS_VER(i915) == 6)
 954                 gen6_ctx_workarounds_init(engine, wal);
 955         else if (GRAPHICS_VER(i915) < 8)
 956                 ;
 957         else
 958                 MISSING_CASE(GRAPHICS_VER(i915));
 959
 960 done:
 961         wa_init_finish(wal);
 962 }
 963
 964 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
 965 {
 966         __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
 967 }
 968
 969 int intel_engine_emit_ctx_wa(struct i915_request *rq)
 970 {
 971         struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
 972         struct i915_wa *wa;
 973         unsigned int i;
 974         u32 *cs;
 975         int ret;
 976
 977         if (wal->count == 0)
 978                 return 0;
 979
 980         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
 981         if (ret)
 982                 return ret;
 983
 984         cs = intel_ring_begin(rq, (wal->count * 2 + 2));
 985         if (IS_ERR(cs))
 986                 return PTR_ERR(cs);
 987
 988         *cs++ = MI_LOAD_REGISTER_IMM(wal->count);
 989         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
 990                 *cs++ = i915_mmio_reg_offset(wa->reg);
 991                 *cs++ = wa->set;
 992         }
 993         *cs++ = MI_NOOP;
 994
 995         intel_ring_advance(rq, cs);
 996
 997         ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
 998         if (ret)
 999                 return ret;
1000
1001         return 0;
1002 }
1003
1004 static void
1005 gen4_gt_workarounds_init(struct intel_gt *gt,
1006                          struct i915_wa_list *wal)
1007 {
1008         /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
1009         wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
1010 }
1011
1012 static void
1013 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1014 {
1015         gen4_gt_workarounds_init(gt, wal);
1016
1017         /* WaDisableRenderCachePipelinedFlush:g4x,ilk */
1018         wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
1019 }
1020
1021 static void
1022 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1023 {
1024         g4x_gt_workarounds_init(gt, wal);
1025
1026         wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
1027 }
1028
1029 static void
1030 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1031 {
1032 }
1033
1034 static void
1035 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1036 {
1037         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
1038         wa_masked_dis(wal,
1039                       GEN7_COMMON_SLICE_CHICKEN1,
1040                       GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
1041
1042         /* WaApplyL3ControlAndL3ChickenMode:ivb */
1043         wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
1044         wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
1045
1046         /* WaForceL3Serialization:ivb */
1047         wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
1048 }
1049
1050 static void
1051 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1052 {
1053         /* WaForceL3Serialization:vlv */
1054         wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
1055
1056         /*
1057          * WaIncreaseL3CreditsForVLVB0:vlv
1058          * This is the hardware default actually.
1059          */
1060         wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
1061 }
1062
1063 static void
1064 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1065 {
1066         /* L3 caching of data atomics doesn't work -- disable it. */
1067         wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
1068
1069         wa_add(wal,
1070                HSW_ROW_CHICKEN3, 0,
1071                _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
1072                0 /* XXX does this reg exist? */, true);
1073
1074         /* WaVSRefCountFullforceMissDisable:hsw */
1075         wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
1076 }
1077
1078 static void
1079 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
1080 {
1081         const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
1082         unsigned int slice, subslice;
1083         u32 mcr, mcr_mask;
1084
1085         GEM_BUG_ON(GRAPHICS_VER(i915) != 9);
1086
1087         /*
1088          * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml
1089          * Before any MMIO read into slice/subslice specific registers, MCR
1090          * packet control register needs to be programmed to point to any
1091          * enabled s/ss pair. Otherwise, incorrect values will be returned.
1092          * This means each subsequent MMIO read will be forwarded to an
1093          * specific s/ss combination, but this is OK since these registers
1094          * are consistent across s/ss in almost all cases. In the rare
1095          * occasions, such as INSTDONE, where this value is dependent
1096          * on s/ss combo, the read should be done with read_subslice_reg.
1097          */
1098         slice = ffs(sseu->slice_mask) - 1;
1099         GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
1100         subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
1101         GEM_BUG_ON(!subslice);
1102         subslice--;
1103
1104         /*
1105          * We use GEN8_MCR..() macros to calculate the |mcr| value for
1106          * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads
1107          */
1108         mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1109         mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
1110
1111         drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr);
1112
1113         wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
1114 }
1115
1116 static void
1117 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1118 {
1119         struct drm_i915_private *i915 = gt->i915;
1120
1121         /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */
1122         gen9_wa_init_mcr(i915, wal);
1123
1124         /* WaDisableKillLogic:bxt,skl,kbl */
1125         if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
1126                 wa_write_or(wal,
1127                             GAM_ECOCHK,
1128                             ECOCHK_DIS_TLB);
1129
1130         if (HAS_LLC(i915)) {
1131                 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
1132                  *
1133                  * Must match Display Engine. See
1134                  * WaCompressedResourceDisplayNewHashMode.
1135                  */
1136                 wa_write_or(wal,
1137                             MMCD_MISC_CTRL,
1138                             MMCD_PCLA | MMCD_HOTSPOT_EN);
1139         }
1140
1141         /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
1142         wa_write_or(wal,
1143                     GAM_ECOCHK,
1144                     BDW_DISABLE_HDC_INVALIDATION);
1145 }
1146
1147 static void
1148 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1149 {
1150         gen9_gt_workarounds_init(gt, wal);
1151
1152         /* WaDisableGafsUnitClkGating:skl */
1153         wa_write_or(wal,
1154                     GEN7_UCGCTL4,
1155                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1156
1157         /* WaInPlaceDecompressionHang:skl */
1158         if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
1159                 wa_write_or(wal,
1160                             GEN9_GAMT_ECO_REG_RW_IA,
1161                             GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1162 }
1163
1164 static void
1165 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1166 {
1167         gen9_gt_workarounds_init(gt, wal);
1168
1169         /* WaDisableDynamicCreditSharing:kbl */
1170         if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
1171                 wa_write_or(wal,
1172                             GAMT_CHKN_BIT_REG,
1173                             GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1174
1175         /* WaDisableGafsUnitClkGating:kbl */
1176         wa_write_or(wal,
1177                     GEN7_UCGCTL4,
1178                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1179
1180         /* WaInPlaceDecompressionHang:kbl */
1181         wa_write_or(wal,
1182                     GEN9_GAMT_ECO_REG_RW_IA,
1183                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1184 }
1185
1186 static void
1187 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1188 {
1189         gen9_gt_workarounds_init(gt, wal);
1190 }
1191
1192 static void
1193 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1194 {
1195         gen9_gt_workarounds_init(gt, wal);
1196
1197         /* WaDisableGafsUnitClkGating:cfl */
1198         wa_write_or(wal,
1199                     GEN7_UCGCTL4,
1200                     GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1201
1202         /* WaInPlaceDecompressionHang:cfl */
1203         wa_write_or(wal,
1204                     GEN9_GAMT_ECO_REG_RW_IA,
1205                     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1206 }
1207
1208 static void __set_mcr_steering(struct i915_wa_list *wal,
1209                                i915_reg_t steering_reg,
1210                                unsigned int slice, unsigned int subslice)
1211 {
1212         u32 mcr, mcr_mask;
1213
1214         mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
1215         mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
1216
1217         wa_write_clr_set(wal, steering_reg, mcr_mask, mcr);
1218 }
1219
1220 static void debug_dump_steering(struct intel_gt *gt)
1221 {
1222         struct drm_printer p = drm_debug_printer("MCR Steering:");
1223
1224         if (drm_debug_enabled(DRM_UT_DRIVER))
1225                 intel_gt_mcr_report_steering(&p, gt, false);
1226 }
1227
1228 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal,
1229                          unsigned int slice, unsigned int subslice)
1230 {
1231         __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice);
1232
1233         gt->default_steering.groupid = slice;
1234         gt->default_steering.instanceid = subslice;
1235
1236         debug_dump_steering(gt);
1237 }
1238
1239 static void
1240 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1241 {
1242         const struct sseu_dev_info *sseu = &gt->info.sseu;
1243         unsigned int subslice;
1244
1245         GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
1246         GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
1247
1248         /*
1249          * Although a platform may have subslices, we need to always steer
1250          * reads to the lowest instance that isn't fused off.  When Render
1251          * Power Gating is enabled, grabbing forcewake will only power up a
1252          * single subslice (the "minconfig") if there isn't a real workload
1253          * that needs to be run; this means that if we steer register reads to
1254          * one of the higher subslices, we run the risk of reading back 0's or
1255          * random garbage.
1256          */
1257         subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
1258
1259         /*
1260          * If the subslice we picked above also steers us to a valid L3 bank,
1261          * then we can just rely on the default steering and won't need to
1262          * worry about explicitly re-steering L3BANK reads later.
1263          */
1264         if (gt->info.l3bank_mask & BIT(subslice))
1265                 gt->steering_table[L3BANK] = NULL;
1266
1267         __add_mcr_wa(gt, wal, 0, subslice);
1268 }
1269
1270 static void
1271 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1272 {
1273         const struct sseu_dev_info *sseu = &gt->info.sseu;
1274         unsigned long slice, subslice = 0, slice_mask = 0;
1275         u32 lncf_mask = 0;
1276         int i;
1277
1278         /*
1279          * On Xe_HP the steering increases in complexity. There are now several
1280          * more units that require steering and we're not guaranteed to be able
1281          * to find a common setting for all of them. These are:
1282          * - GSLICE (fusable)
1283          * - DSS (sub-unit within gslice; fusable)
1284          * - L3 Bank (fusable)
1285          * - MSLICE (fusable)
1286          * - LNCF (sub-unit within mslice; always present if mslice is present)
1287          *
1288          * We'll do our default/implicit steering based on GSLICE (in the
1289          * sliceid field) and DSS (in the subsliceid field).  If we can
1290          * find overlap between the valid MSLICE and/or LNCF values with
1291          * a suitable GSLICE, then we can just re-use the default value and
1292          * skip and explicit steering at runtime.
1293          *
1294          * We only need to look for overlap between GSLICE/MSLICE/LNCF to find
1295          * a valid sliceid value.  DSS steering is the only type of steering
1296          * that utilizes the 'subsliceid' bits.
1297          *
1298          * Also note that, even though the steering domain is called "GSlice"
1299          * and it is encoded in the register using the gslice format, the spec
1300          * says that the combined (geometry | compute) fuse should be used to
1301          * select the steering.
1302          */
1303
1304         /* Find the potential gslice candidates */
1305         slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
1306                                                        GEN_DSS_PER_GSLICE);
1307
1308         /*
1309          * Find the potential LNCF candidates.  Either LNCF within a valid
1310          * mslice is fine.
1311          */
1312         for_each_set_bit(i, &gt->info.mslice_mask, GEN12_MAX_MSLICES)
1313                 lncf_mask |= (0x3 << (i * 2));
1314
1315         /*
1316          * Are there any sliceid values that work for both GSLICE and LNCF
1317          * steering?
1318          */
1319         if (slice_mask & lncf_mask) {
1320                 slice_mask &= lncf_mask;
1321                 gt->steering_table[LNCF] = NULL;
1322         }
1323
1324         /* How about sliceid values that also work for MSLICE steering? */
1325         if (slice_mask & gt->info.mslice_mask) {
1326                 slice_mask &= gt->info.mslice_mask;
1327                 gt->steering_table[MSLICE] = NULL;
1328         }
1329
1330         if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0))
1331                 gt->steering_table[GAM] = NULL;
1332
1333         slice = __ffs(slice_mask);
1334         subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
1335                 GEN_DSS_PER_GSLICE;
1336
1337         __add_mcr_wa(gt, wal, slice, subslice);
1338
1339         /*
1340          * SQIDI ranges are special because they use different steering
1341          * registers than everything else we work with.  On XeHP SDV and
1342          * DG2-G10, any value in the steering registers will work fine since
1343          * all instances are present, but DG2-G11 only has SQIDI instances at
1344          * ID's 2 and 3, so we need to steer to one of those.  For simplicity
1345          * we'll just steer to a hardcoded "2" since that value will work
1346          * everywhere.
1347          */
1348         __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2);
1349         __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2);
1350
1351         /*
1352          * On DG2, GAM registers have a dedicated steering control register
1353          * and must always be programmed to a hardcoded groupid of "1."
1354          */
1355         if (IS_DG2(gt->i915))
1356                 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0);
1357 }
1358
1359 static void
1360 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1361 {
1362         unsigned int dss;
1363
1364         /*
1365          * Setup implicit steering for COMPUTE and DSS ranges to the first
1366          * non-fused-off DSS.  All other types of MCR registers will be
1367          * explicitly steered.
1368          */
1369         dss = intel_sseu_find_first_xehp_dss(&gt->info.sseu, 0, 0);
1370         __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE);
1371 }
1372
1373 static void
1374 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1375 {
1376         struct drm_i915_private *i915 = gt->i915;
1377
1378         icl_wa_init_mcr(gt, wal);
1379
1380         /* WaModifyGamTlbPartitioning:icl */
1381         wa_write_clr_set(wal,
1382                          GEN11_GACB_PERF_CTRL,
1383                          GEN11_HASH_CTRL_MASK,
1384                          GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
1385
1386         /* Wa_1405766107:icl
1387          * Formerly known as WaCL2SFHalfMaxAlloc
1388          */
1389         wa_write_or(wal,
1390                     GEN11_LSN_UNSLCVC,
1391                     GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
1392                     GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
1393
1394         /* Wa_220166154:icl
1395          * Formerly known as WaDisCtxReload
1396          */
1397         wa_write_or(wal,
1398                     GEN8_GAMW_ECO_DEV_RW_IA,
1399                     GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
1400
1401         /* Wa_1406463099:icl
1402          * Formerly known as WaGamTlbPendError
1403          */
1404         wa_write_or(wal,
1405                     GAMT_CHKN_BIT_REG,
1406                     GAMT_CHKN_DISABLE_L3_COH_PIPE);
1407
1408         /*
1409          * Wa_1408615072:icl,ehl  (vsunit)
1410          * Wa_1407596294:icl,ehl  (hsunit)
1411          */
1412         wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1413                     VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
1414
1415         /* Wa_1407352427:icl,ehl */
1416         wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
1417                     PSDUNIT_CLKGATE_DIS);
1418
1419         /* Wa_1406680159:icl,ehl */
1420         wa_mcr_write_or(wal,
1421                         GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
1422                         GWUNIT_CLKGATE_DIS);
1423
1424         /* Wa_1607087056:icl,ehl,jsl */
1425         if (IS_ICELAKE(i915) ||
1426             IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
1427                 wa_write_or(wal,
1428                             GEN11_SLICE_UNIT_LEVEL_CLKGATE,
1429                             L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
1430
1431         /*
1432          * This is not a documented workaround, but rather an optimization
1433          * to reduce sampler power.
1434          */
1435         wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
1436 }
1437
1438 /*
1439  * Though there are per-engine instances of these registers,
1440  * they retain their value through engine resets and should
1441  * only be provided on the GT workaround list rather than
1442  * the engine-specific workaround list.
1443  */
1444 static void
1445 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal)
1446 {
1447         struct intel_engine_cs *engine;
1448         int id;
1449
1450         for_each_engine(engine, gt, id) {
1451                 if (engine->class != VIDEO_DECODE_CLASS ||
1452                     (engine->instance % 2))
1453                         continue;
1454
1455                 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base),
1456                             IECPUNIT_CLKGATE_DIS);
1457         }
1458 }
1459
1460 static void
1461 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1462 {
1463         icl_wa_init_mcr(gt, wal);
1464
1465         /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */
1466         wa_14011060649(gt, wal);
1467
1468         /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
1469         wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
1470 }
1471
1472 static void
1473 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1474 {
1475         struct drm_i915_private *i915 = gt->i915;
1476
1477         gen12_gt_workarounds_init(gt, wal);
1478
1479         /* Wa_1409420604:dg1 */
1480         if (IS_DG1(i915))
1481                 wa_mcr_write_or(wal,
1482                                 SUBSLICE_UNIT_LEVEL_CLKGATE2,
1483                                 CPSSUNIT_CLKGATE_DIS);
1484
1485         /* Wa_1408615072:dg1 */
1486         /* Empirical testing shows this register is unaffected by engine reset. */
1487         if (IS_DG1(i915))
1488                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
1489                             VSUNIT_CLKGATE_DIS_TGL);
1490 }
1491
1492 static void
1493 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1494 {
1495         struct drm_i915_private *i915 = gt->i915;
1496
1497         xehp_init_mcr(gt, wal);
1498
1499         /* Wa_1409757795:xehpsdv */
1500         wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB);
1501
1502         /* Wa_16011155590:xehpsdv */
1503         if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
1504                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1505                             TSGUNIT_CLKGATE_DIS);
1506
1507         /* Wa_14011780169:xehpsdv */
1508         if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) {
1509                 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
1510                             GAMTLBVDBOX7_CLKGATE_DIS |
1511                             GAMTLBVDBOX6_CLKGATE_DIS |
1512                             GAMTLBVDBOX5_CLKGATE_DIS |
1513                             GAMTLBVDBOX4_CLKGATE_DIS |
1514                             GAMTLBVDBOX3_CLKGATE_DIS |
1515                             GAMTLBVDBOX2_CLKGATE_DIS |
1516                             GAMTLBVDBOX1_CLKGATE_DIS |
1517                             GAMTLBVDBOX0_CLKGATE_DIS |
1518                             GAMTLBKCR_CLKGATE_DIS |
1519                             GAMTLBGUC_CLKGATE_DIS |
1520                             GAMTLBBLT_CLKGATE_DIS);
1521                 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS |
1522                             GAMTLBGFXA1_CLKGATE_DIS |
1523                             GAMTLBCOMPA0_CLKGATE_DIS |
1524                             GAMTLBCOMPA1_CLKGATE_DIS |
1525                             GAMTLBCOMPB0_CLKGATE_DIS |
1526                             GAMTLBCOMPB1_CLKGATE_DIS |
1527                             GAMTLBCOMPC0_CLKGATE_DIS |
1528                             GAMTLBCOMPC1_CLKGATE_DIS |
1529                             GAMTLBCOMPD0_CLKGATE_DIS |
1530                             GAMTLBCOMPD1_CLKGATE_DIS |
1531                             GAMTLBMERT_CLKGATE_DIS   |
1532                             GAMTLBVEBOX3_CLKGATE_DIS |
1533                             GAMTLBVEBOX2_CLKGATE_DIS |
1534                             GAMTLBVEBOX1_CLKGATE_DIS |
1535                             GAMTLBVEBOX0_CLKGATE_DIS);
1536         }
1537
1538         /* Wa_16012725990:xehpsdv */
1539         if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER))
1540                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS);
1541
1542         /* Wa_14011060649:xehpsdv */
1543         wa_14011060649(gt, wal);
1544
1545         /* Wa_14012362059:xehpsdv */
1546         wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
1547
1548         /* Wa_14014368820:xehpsdv */
1549         wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
1550                         INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
1551 }
1552
1553 static void
1554 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1555 {
1556         struct intel_engine_cs *engine;
1557         int id;
1558
1559         xehp_init_mcr(gt, wal);
1560
1561         /* Wa_14011060649:dg2 */
1562         wa_14011060649(gt, wal);
1563
1564         /*
1565          * Although there are per-engine instances of these registers,
1566          * they technically exist outside the engine itself and are not
1567          * impacted by engine resets.  Furthermore, they're part of the
1568          * GuC blacklist so trying to treat them as engine workarounds
1569          * will result in GuC initialization failure and a wedged GPU.
1570          */
1571         for_each_engine(engine, gt, id) {
1572                 if (engine->class != VIDEO_DECODE_CLASS)
1573                         continue;
1574
1575                 /* Wa_16010515920:dg2_g10 */
1576                 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
1577                         wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base),
1578                                     ALNUNIT_CLKGATE_DIS);
1579         }
1580
1581         if (IS_DG2_G10(gt->i915)) {
1582                 /* Wa_22010523718:dg2 */
1583                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1584                             CG3DDISCFEG_CLKGATE_DIS);
1585
1586                 /* Wa_14011006942:dg2 */
1587                 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
1588                                 DSS_ROUTER_CLKGATE_DIS);
1589         }
1590
1591         if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0) ||
1592             IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) {
1593                 /* Wa_14012362059:dg2 */
1594                 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
1595         }
1596
1597         if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
1598                 /* Wa_14010948348:dg2_g10 */
1599                 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS);
1600
1601                 /* Wa_14011037102:dg2_g10 */
1602                 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
1603
1604                 /* Wa_14011371254:dg2_g10 */
1605                 wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
1606
1607                 /* Wa_14011431319:dg2_g10 */
1608                 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
1609                             GAMTLBVDBOX7_CLKGATE_DIS |
1610                             GAMTLBVDBOX6_CLKGATE_DIS |
1611                             GAMTLBVDBOX5_CLKGATE_DIS |
1612                             GAMTLBVDBOX4_CLKGATE_DIS |
1613                             GAMTLBVDBOX3_CLKGATE_DIS |
1614                             GAMTLBVDBOX2_CLKGATE_DIS |
1615                             GAMTLBVDBOX1_CLKGATE_DIS |
1616                             GAMTLBVDBOX0_CLKGATE_DIS |
1617                             GAMTLBKCR_CLKGATE_DIS |
1618                             GAMTLBGUC_CLKGATE_DIS |
1619                             GAMTLBBLT_CLKGATE_DIS);
1620                 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS |
1621                             GAMTLBGFXA1_CLKGATE_DIS |
1622                             GAMTLBCOMPA0_CLKGATE_DIS |
1623                             GAMTLBCOMPA1_CLKGATE_DIS |
1624                             GAMTLBCOMPB0_CLKGATE_DIS |
1625                             GAMTLBCOMPB1_CLKGATE_DIS |
1626                             GAMTLBCOMPC0_CLKGATE_DIS |
1627                             GAMTLBCOMPC1_CLKGATE_DIS |
1628                             GAMTLBCOMPD0_CLKGATE_DIS |
1629                             GAMTLBCOMPD1_CLKGATE_DIS |
1630                             GAMTLBMERT_CLKGATE_DIS   |
1631                             GAMTLBVEBOX3_CLKGATE_DIS |
1632                             GAMTLBVEBOX2_CLKGATE_DIS |
1633                             GAMTLBVEBOX1_CLKGATE_DIS |
1634                             GAMTLBVEBOX0_CLKGATE_DIS);
1635
1636                 /* Wa_14010569222:dg2_g10 */
1637                 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1638                             GAMEDIA_CLKGATE_DIS);
1639
1640                 /* Wa_14011028019:dg2_g10 */
1641                 wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);
1642
1643                 /* Wa_14010680813:dg2_g10 */
1644                 wa_mcr_write_or(wal, XEHP_GAMSTLB_CTRL,
1645                                 CONTROL_BLOCK_CLKGATE_DIS |
1646                                 EGRESS_BLOCK_CLKGATE_DIS |
1647                                 TAG_BLOCK_CLKGATE_DIS);
1648         }
1649
1650         /* Wa_14014830051:dg2 */
1651         wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
1652
1653         /*
1654          * The following are not actually "workarounds" but rather
1655          * recommended tuning settings documented in the bspec's
1656          * performance guide section.
1657          */
1658         wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
1659
1660         /* Wa_14015795083 */
1661         wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
1662
1663         /* Wa_18018781329 */
1664         wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1665         wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1666         wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1667         wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
1668
1669         /* Wa_1509235366:dg2 */
1670         wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
1671                         INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
1672 }
1673
1674 static void
1675 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1676 {
1677         pvc_init_mcr(gt, wal);
1678
1679         /* Wa_14015795083 */
1680         wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
1681
1682         /* Wa_18018781329 */
1683         wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1684         wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1685         wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1686         wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
1687 }
1688
1689 static void
1690 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1691 {
1692         if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
1693             IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
1694                 /* Wa_14014830051 */
1695                 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
1696
1697                 /* Wa_18018781329 */
1698                 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1699                 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1700         }
1701
1702         /*
1703          * Unlike older platforms, we no longer setup implicit steering here;
1704          * all MCR accesses are explicitly steered.
1705          */
1706         debug_dump_steering(gt);
1707 }
1708
1709 static void
1710 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1711 {
1712         if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0)) {
1713                 /*
1714                  * Wa_18018781329
1715                  *
1716                  * Note that although these registers are MCR on the primary
1717                  * GT, the media GT's versions are regular singleton registers.
1718                  */
1719                 wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);
1720                 wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1721                 wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
1722         }
1723
1724         debug_dump_steering(gt);
1725 }
1726
1727 static void
1728 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
1729 {
1730         struct drm_i915_private *i915 = gt->i915;
1731
1732         if (gt->type == GT_MEDIA) {
1733                 if (MEDIA_VER(i915) >= 13)
1734                         xelpmp_gt_workarounds_init(gt, wal);
1735                 else
1736                         MISSING_CASE(MEDIA_VER(i915));
1737
1738                 return;
1739         }
1740
1741         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
1742                 xelpg_gt_workarounds_init(gt, wal);
1743         else if (IS_PONTEVECCHIO(i915))
1744                 pvc_gt_workarounds_init(gt, wal);
1745         else if (IS_DG2(i915))
1746                 dg2_gt_workarounds_init(gt, wal);
1747         else if (IS_XEHPSDV(i915))
1748                 xehpsdv_gt_workarounds_init(gt, wal);
1749         else if (IS_DG1(i915))
1750                 dg1_gt_workarounds_init(gt, wal);
1751         else if (GRAPHICS_VER(i915) == 12)
1752                 gen12_gt_workarounds_init(gt, wal);
1753         else if (GRAPHICS_VER(i915) == 11)
1754                 icl_gt_workarounds_init(gt, wal);
1755         else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
1756                 cfl_gt_workarounds_init(gt, wal);
1757         else if (IS_GEMINILAKE(i915))
1758                 glk_gt_workarounds_init(gt, wal);
1759         else if (IS_KABYLAKE(i915))
1760                 kbl_gt_workarounds_init(gt, wal);
1761         else if (IS_BROXTON(i915))
1762                 gen9_gt_workarounds_init(gt, wal);
1763         else if (IS_SKYLAKE(i915))
1764                 skl_gt_workarounds_init(gt, wal);
1765         else if (IS_HASWELL(i915))
1766                 hsw_gt_workarounds_init(gt, wal);
1767         else if (IS_VALLEYVIEW(i915))
1768                 vlv_gt_workarounds_init(gt, wal);
1769         else if (IS_IVYBRIDGE(i915))
1770                 ivb_gt_workarounds_init(gt, wal);
1771         else if (GRAPHICS_VER(i915) == 6)
1772                 snb_gt_workarounds_init(gt, wal);
1773         else if (GRAPHICS_VER(i915) == 5)
1774                 ilk_gt_workarounds_init(gt, wal);
1775         else if (IS_G4X(i915))
1776                 g4x_gt_workarounds_init(gt, wal);
1777         else if (GRAPHICS_VER(i915) == 4)
1778                 gen4_gt_workarounds_init(gt, wal);
1779         else if (GRAPHICS_VER(i915) <= 8)
1780                 ;
1781         else
1782                 MISSING_CASE(GRAPHICS_VER(i915));
1783 }
1784
1785 void intel_gt_init_workarounds(struct intel_gt *gt)
1786 {
1787         struct i915_wa_list *wal = &gt->wa_list;
1788
1789         wa_init_start(wal, gt, "GT", "global");
1790         gt_init_workarounds(gt, wal);
1791         wa_init_finish(wal);
1792 }
1793
1794 static enum forcewake_domains
1795 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
1796 {
1797         enum forcewake_domains fw = 0;
1798         struct i915_wa *wa;
1799         unsigned int i;
1800
1801         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1802                 fw |= intel_uncore_forcewake_for_reg(uncore,
1803                                                      wa->reg,
1804                                                      FW_REG_READ |
1805                                                      FW_REG_WRITE);
1806
1807         return fw;
1808 }
1809
1810 static bool
1811 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur,
1812           const char *name, const char *from)
1813 {
1814         if ((cur ^ wa->set) & wa->read) {
1815                 drm_err(&gt->i915->drm,
1816                         "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n",
1817                         name, from, i915_mmio_reg_offset(wa->reg),
1818                         cur, cur & wa->read, wa->set & wa->read);
1819
1820                 return false;
1821         }
1822
1823         return true;
1824 }
1825
1826 static void wa_list_apply(const struct i915_wa_list *wal)
1827 {
1828         struct intel_gt *gt = wal->gt;
1829         struct intel_uncore *uncore = gt->uncore;
1830         enum forcewake_domains fw;
1831         unsigned long flags;
1832         struct i915_wa *wa;
1833         unsigned int i;
1834
1835         if (!wal->count)
1836                 return;
1837
1838         fw = wal_get_fw_for_rmw(uncore, wal);
1839
1840         intel_gt_mcr_lock(gt, &flags);
1841         spin_lock(&uncore->lock);
1842         intel_uncore_forcewake_get__locked(uncore, fw);
1843
1844         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1845                 u32 val, old = 0;
1846
1847                 /* open-coded rmw due to steering */
1848                 if (wa->clr)
1849                         old = wa->is_mcr ?
1850                                 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
1851                                 intel_uncore_read_fw(uncore, wa->reg);
1852                 val = (old & ~wa->clr) | wa->set;
1853                 if (val != old || !wa->clr) {
1854                         if (wa->is_mcr)
1855                                 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val);
1856                         else
1857                                 intel_uncore_write_fw(uncore, wa->reg, val);
1858                 }
1859
1860                 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
1861                         u32 val = wa->is_mcr ?
1862                                 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
1863                                 intel_uncore_read_fw(uncore, wa->reg);
1864
1865                         wa_verify(gt, wa, val, wal->name, "application");
1866                 }
1867         }
1868
1869         intel_uncore_forcewake_put__locked(uncore, fw);
1870         spin_unlock(&uncore->lock);
1871         intel_gt_mcr_unlock(gt, flags);
1872 }
1873
1874 void intel_gt_apply_workarounds(struct intel_gt *gt)
1875 {
1876         wa_list_apply(&gt->wa_list);
1877 }
1878
1879 static bool wa_list_verify(struct intel_gt *gt,
1880                            const struct i915_wa_list *wal,
1881                            const char *from)
1882 {
1883         struct intel_uncore *uncore = gt->uncore;
1884         struct i915_wa *wa;
1885         enum forcewake_domains fw;
1886         unsigned long flags;
1887         unsigned int i;
1888         bool ok = true;
1889
1890         fw = wal_get_fw_for_rmw(uncore, wal);
1891
1892         intel_gt_mcr_lock(gt, &flags);
1893         spin_lock(&uncore->lock);
1894         intel_uncore_forcewake_get__locked(uncore, fw);
1895
1896         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1897                 ok &= wa_verify(wal->gt, wa, wa->is_mcr ?
1898                                 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
1899                                 intel_uncore_read_fw(uncore, wa->reg),
1900                                 wal->name, from);
1901
1902         intel_uncore_forcewake_put__locked(uncore, fw);
1903         spin_unlock(&uncore->lock);
1904         intel_gt_mcr_unlock(gt, flags);
1905
1906         return ok;
1907 }
1908
1909 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
1910 {
1911         return wa_list_verify(gt, &gt->wa_list, from);
1912 }
1913
1914 __maybe_unused
1915 static bool is_nonpriv_flags_valid(u32 flags)
1916 {
1917         /* Check only valid flag bits are set */
1918         if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
1919                 return false;
1920
1921         /* NB: Only 3 out of 4 enum values are valid for access field */
1922         if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
1923             RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
1924                 return false;
1925
1926         return true;
1927 }
1928
1929 static void
1930 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1931 {
1932         struct i915_wa wa = {
1933                 .reg = reg
1934         };
1935
1936         if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1937                 return;
1938
1939         if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1940                 return;
1941
1942         wa.reg.reg |= flags;
1943         _wa_add(wal, &wa);
1944 }
1945
1946 static void
1947 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags)
1948 {
1949         struct i915_wa wa = {
1950                 .mcr_reg = reg,
1951                 .is_mcr = 1,
1952         };
1953
1954         if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1955                 return;
1956
1957         if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1958                 return;
1959
1960         wa.mcr_reg.reg |= flags;
1961         _wa_add(wal, &wa);
1962 }
1963
1964 static void
1965 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1966 {
1967         whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1968 }
1969
1970 static void
1971 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg)
1972 {
1973         whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1974 }
1975
1976 static void gen9_whitelist_build(struct i915_wa_list *w)
1977 {
1978         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1979         whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
1980
1981         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1982         whitelist_reg(w, GEN8_CS_CHICKEN1);
1983
1984         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1985         whitelist_reg(w, GEN8_HDC_CHICKEN1);
1986
1987         /* WaSendPushConstantsFromMMIO:skl,bxt */
1988         whitelist_reg(w, COMMON_SLICE_CHICKEN2);
1989 }
1990
1991 static void skl_whitelist_build(struct intel_engine_cs *engine)
1992 {
1993         struct i915_wa_list *w = &engine->whitelist;
1994
1995         if (engine->class != RENDER_CLASS)
1996                 return;
1997
1998         gen9_whitelist_build(w);
1999
2000         /* WaDisableLSQCROPERFforOCL:skl */
2001         whitelist_mcr_reg(w, GEN8_L3SQCREG4);
2002 }
2003
2004 static void bxt_whitelist_build(struct intel_engine_cs *engine)
2005 {
2006         if (engine->class != RENDER_CLASS)
2007                 return;
2008
2009         gen9_whitelist_build(&engine->whitelist);
2010 }
2011
2012 static void kbl_whitelist_build(struct intel_engine_cs *engine)
2013 {
2014         struct i915_wa_list *w = &engine->whitelist;
2015
2016         if (engine->class != RENDER_CLASS)
2017                 return;
2018
2019         gen9_whitelist_build(w);
2020
2021         /* WaDisableLSQCROPERFforOCL:kbl */
2022         whitelist_mcr_reg(w, GEN8_L3SQCREG4);
2023 }
2024
2025 static void glk_whitelist_build(struct intel_engine_cs *engine)
2026 {
2027         struct i915_wa_list *w = &engine->whitelist;
2028
2029         if (engine->class != RENDER_CLASS)
2030                 return;
2031
2032         gen9_whitelist_build(w);
2033
2034         /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
2035         whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
2036 }
2037
2038 static void cfl_whitelist_build(struct intel_engine_cs *engine)
2039 {
2040         struct i915_wa_list *w = &engine->whitelist;
2041
2042         if (engine->class != RENDER_CLASS)
2043                 return;
2044
2045         gen9_whitelist_build(w);
2046
2047         /*
2048          * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
2049          *
2050          * This covers 4 register which are next to one another :
2051          *   - PS_INVOCATION_COUNT
2052          *   - PS_INVOCATION_COUNT_UDW
2053          *   - PS_DEPTH_COUNT
2054          *   - PS_DEPTH_COUNT_UDW
2055          */
2056         whitelist_reg_ext(w, PS_INVOCATION_COUNT,
2057                           RING_FORCE_TO_NONPRIV_ACCESS_RD |
2058                           RING_FORCE_TO_NONPRIV_RANGE_4);
2059 }
2060
2061 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine)
2062 {
2063         struct i915_wa_list *w = &engine->whitelist;
2064
2065         if (engine->class != RENDER_CLASS)
2066                 whitelist_reg_ext(w,
2067                                   RING_CTX_TIMESTAMP(engine->mmio_base),
2068                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
2069 }
2070
2071 static void cml_whitelist_build(struct intel_engine_cs *engine)
2072 {
2073         allow_read_ctx_timestamp(engine);
2074
2075         cfl_whitelist_build(engine);
2076 }
2077
2078 static void icl_whitelist_build(struct intel_engine_cs *engine)
2079 {
2080         struct i915_wa_list *w = &engine->whitelist;
2081
2082         allow_read_ctx_timestamp(engine);
2083
2084         switch (engine->class) {
2085         case RENDER_CLASS:
2086                 /* WaAllowUMDToModifyHalfSliceChicken7:icl */
2087                 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7);
2088
2089                 /* WaAllowUMDToModifySamplerMode:icl */
2090                 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE);
2091
2092                 /* WaEnableStateCacheRedirectToCS:icl */
2093                 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
2094
2095                 /*
2096                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
2097                  *
2098                  * This covers 4 register which are next to one another :
2099                  *   - PS_INVOCATION_COUNT
2100                  *   - PS_INVOCATION_COUNT_UDW
2101                  *   - PS_DEPTH_COUNT
2102                  *   - PS_DEPTH_COUNT_UDW
2103                  */
2104                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
2105                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
2106                                   RING_FORCE_TO_NONPRIV_RANGE_4);
2107                 break;
2108
2109         case VIDEO_DECODE_CLASS:
2110                 /* hucStatusRegOffset */
2111                 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
2112                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
2113                 /* hucUKernelHdrInfoRegOffset */
2114                 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
2115                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
2116                 /* hucStatus2RegOffset */
2117                 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
2118                                   RING_FORCE_TO_NONPRIV_ACCESS_RD);
2119                 break;
2120
2121         default:
2122                 break;
2123         }
2124 }
2125
2126 static void tgl_whitelist_build(struct intel_engine_cs *engine)
2127 {
2128         struct i915_wa_list *w = &engine->whitelist;
2129
2130         allow_read_ctx_timestamp(engine);
2131
2132         switch (engine->class) {
2133         case RENDER_CLASS:
2134                 /*
2135                  * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
2136                  * Wa_1408556865:tgl
2137                  *
2138                  * This covers 4 registers which are next to one another :
2139                  *   - PS_INVOCATION_COUNT
2140                  *   - PS_INVOCATION_COUNT_UDW
2141                  *   - PS_DEPTH_COUNT
2142                  *   - PS_DEPTH_COUNT_UDW
2143                  */
2144                 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
2145                                   RING_FORCE_TO_NONPRIV_ACCESS_RD |
2146                                   RING_FORCE_TO_NONPRIV_RANGE_4);
2147
2148                 /*
2149                  * Wa_1808121037:tgl
2150                  * Wa_14012131227:dg1
2151                  * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p
2152                  */
2153                 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
2154
2155                 /* Wa_1806527549:tgl */
2156                 whitelist_reg(w, HIZ_CHICKEN);
2157                 break;
2158         default:
2159                 break;
2160         }
2161 }
2162
2163 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
2164 {
2165         allow_read_ctx_timestamp(engine);
2166 }
2167
2168 static void dg2_whitelist_build(struct intel_engine_cs *engine)
2169 {
2170         struct i915_wa_list *w = &engine->whitelist;
2171
2172         allow_read_ctx_timestamp(engine);
2173
2174         switch (engine->class) {
2175         case RENDER_CLASS:
2176                 /*
2177                  * Wa_1507100340:dg2_g10
2178                  *
2179                  * This covers 4 registers which are next to one another :
2180                  *   - PS_INVOCATION_COUNT
2181                  *   - PS_INVOCATION_COUNT_UDW
2182                  *   - PS_DEPTH_COUNT
2183                  *   - PS_DEPTH_COUNT_UDW
2184                  */
2185                 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0))
2186                         whitelist_reg_ext(w, PS_INVOCATION_COUNT,
2187                                           RING_FORCE_TO_NONPRIV_ACCESS_RD |
2188                                           RING_FORCE_TO_NONPRIV_RANGE_4);
2189
2190                 break;
2191         case COMPUTE_CLASS:
2192                 /* Wa_16011157294:dg2_g10 */
2193                 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0))
2194                         whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
2195                 break;
2196         default:
2197                 break;
2198         }
2199 }
2200
2201 static void blacklist_trtt(struct intel_engine_cs *engine)
2202 {
2203         struct i915_wa_list *w = &engine->whitelist;
2204
2205         /*
2206          * Prevent read/write access to [0x4400, 0x4600) which covers
2207          * the TRTT range across all engines. Note that normally userspace
2208          * cannot access the other engines' trtt control, but for simplicity
2209          * we cover the entire range on each engine.
2210          */
2211         whitelist_reg_ext(w, _MMIO(0x4400),
2212                           RING_FORCE_TO_NONPRIV_DENY |
2213                           RING_FORCE_TO_NONPRIV_RANGE_64);
2214         whitelist_reg_ext(w, _MMIO(0x4500),
2215                           RING_FORCE_TO_NONPRIV_DENY |
2216                           RING_FORCE_TO_NONPRIV_RANGE_64);
2217 }
2218
2219 static void pvc_whitelist_build(struct intel_engine_cs *engine)
2220 {
2221         allow_read_ctx_timestamp(engine);
2222
2223         /* Wa_16014440446:pvc */
2224         blacklist_trtt(engine);
2225 }
2226
2227 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
2228 {
2229         struct drm_i915_private *i915 = engine->i915;
2230         struct i915_wa_list *w = &engine->whitelist;
2231
2232         wa_init_start(w, engine->gt, "whitelist", engine->name);
2233
2234         if (IS_METEORLAKE(i915))
2235                 ; /* noop; none at this time */
2236         else if (IS_PONTEVECCHIO(i915))
2237                 pvc_whitelist_build(engine);
2238         else if (IS_DG2(i915))
2239                 dg2_whitelist_build(engine);
2240         else if (IS_XEHPSDV(i915))
2241                 xehpsdv_whitelist_build(engine);
2242         else if (GRAPHICS_VER(i915) == 12)
2243                 tgl_whitelist_build(engine);
2244         else if (GRAPHICS_VER(i915) == 11)
2245                 icl_whitelist_build(engine);
2246         else if (IS_COMETLAKE(i915))
2247                 cml_whitelist_build(engine);
2248         else if (IS_COFFEELAKE(i915))
2249                 cfl_whitelist_build(engine);
2250         else if (IS_GEMINILAKE(i915))
2251                 glk_whitelist_build(engine);
2252         else if (IS_KABYLAKE(i915))
2253                 kbl_whitelist_build(engine);
2254         else if (IS_BROXTON(i915))
2255                 bxt_whitelist_build(engine);
2256         else if (IS_SKYLAKE(i915))
2257                 skl_whitelist_build(engine);
2258         else if (GRAPHICS_VER(i915) <= 8)
2259                 ;
2260         else
2261                 MISSING_CASE(GRAPHICS_VER(i915));
2262
2263         wa_init_finish(w);
2264 }
2265
2266 void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
2267 {
2268         const struct i915_wa_list *wal = &engine->whitelist;
2269         struct intel_uncore *uncore = engine->uncore;
2270         const u32 base = engine->mmio_base;
2271         struct i915_wa *wa;
2272         unsigned int i;
2273
2274         if (!wal->count)
2275                 return;
2276
2277         for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
2278                 intel_uncore_write(uncore,
2279                                    RING_FORCE_TO_NONPRIV(base, i),
2280                                    i915_mmio_reg_offset(wa->reg));
2281
2282         /* And clear the rest just in case of garbage */
2283         for (; i < RING_MAX_NONPRIV_SLOTS; i++)
2284                 intel_uncore_write(uncore,
2285                                    RING_FORCE_TO_NONPRIV(base, i),
2286                                    i915_mmio_reg_offset(RING_NOPID(base)));
2287 }
2288
2289 /*
2290  * engine_fake_wa_init(), a place holder to program the registers
2291  * which are not part of an official workaround defined by the
2292  * hardware team.
2293  * Adding programming of those register inside workaround will
2294  * allow utilizing wa framework to proper application and verification.
2295  */
2296 static void
2297 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2298 {
2299         u8 mocs_w, mocs_r;
2300
2301         /*
2302          * RING_CMD_CCTL specifies the default MOCS entry that will be used
2303          * by the command streamer when executing commands that don't have
2304          * a way to explicitly specify a MOCS setting.  The default should
2305          * usually reference whichever MOCS entry corresponds to uncached
2306          * behavior, although use of a WB cached entry is recommended by the
2307          * spec in certain circumstances on specific platforms.
2308          */
2309         if (GRAPHICS_VER(engine->i915) >= 12) {
2310                 mocs_r = engine->gt->mocs.uc_index;
2311                 mocs_w = engine->gt->mocs.uc_index;
2312
2313                 if (HAS_L3_CCS_READ(engine->i915) &&
2314                     engine->class == COMPUTE_CLASS) {
2315                         mocs_r = engine->gt->mocs.wb_index;
2316
2317                         /*
2318                          * Even on the few platforms where MOCS 0 is a
2319                          * legitimate table entry, it's never the correct
2320                          * setting to use here; we can assume the MOCS init
2321                          * just forgot to initialize wb_index.
2322                          */
2323                         drm_WARN_ON(&engine->i915->drm, mocs_r == 0);
2324                 }
2325
2326                 wa_masked_field_set(wal,
2327                                     RING_CMD_CCTL(engine->mmio_base),
2328                                     CMD_CCTL_MOCS_MASK,
2329                                     CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r));
2330         }
2331 }
2332
2333 static bool needs_wa_1308578152(struct intel_engine_cs *engine)
2334 {
2335         return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >=
2336                 GEN_DSS_PER_GSLICE;
2337 }
2338
2339 static void
2340 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2341 {
2342         struct drm_i915_private *i915 = engine->i915;
2343
2344         if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2345             IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
2346                 /* Wa_22014600077 */
2347                 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
2348                                  ENABLE_EU_COUNT_FOR_TDL_FLUSH);
2349         }
2350
2351         if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2352             IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
2353             IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
2354             IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
2355                 /* Wa_1509727124 */
2356                 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
2357                                  SC_DISABLE_POWER_OPTIMIZATION_EBB);
2358         }
2359
2360         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
2361             IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
2362             IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
2363                 /* Wa_22012856258 */
2364                 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
2365                                  GEN12_DISABLE_READ_SUPPRESSION);
2366         }
2367
2368         if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
2369                 /* Wa_14013392000:dg2_g11 */
2370                 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
2371         }
2372
2373         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
2374             IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
2375                 /* Wa_14012419201:dg2 */
2376                 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4,
2377                                  GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX);
2378         }
2379
2380         /* Wa_1308578152:dg2_g10 when first gslice is fused off */
2381         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) &&
2382             needs_wa_1308578152(engine)) {
2383                 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON,
2384                               GEN12_REPLAY_MODE_GRANULARITY);
2385         }
2386
2387         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
2388             IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
2389                 /*
2390                  * Wa_22010960976:dg2
2391                  * Wa_14013347512:dg2
2392                  */
2393                 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0,
2394                                   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
2395         }
2396
2397         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
2398                 /*
2399                  * Wa_1608949956:dg2_g10
2400                  * Wa_14010198302:dg2_g10
2401                  */
2402                 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
2403                                  MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE);
2404         }
2405
2406         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
2407                 /* Wa_22010430635:dg2 */
2408                 wa_mcr_masked_en(wal,
2409                                  GEN9_ROW_CHICKEN4,
2410                                  GEN12_DISABLE_GRF_CLEAR);
2411
2412                 /* Wa_14010648519:dg2 */
2413                 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
2414         }
2415
2416         /* Wa_14013202645:dg2 */
2417         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
2418             IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0))
2419                 wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY);
2420
2421         /* Wa_22012532006:dg2 */
2422         if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) ||
2423             IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
2424                 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
2425                                  DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
2426
2427         if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
2428             IS_DG2_G10(i915)) {
2429                 /* Wa_22014600077:dg2 */
2430                 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
2431                            _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
2432                            0 /* Wa_14012342262 write-only reg, so skip verification */,
2433                            true);
2434         }
2435
2436         if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
2437             IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2438                 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
2439                 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
2440
2441                 /*
2442                  * Wa_1407928979:tgl A*
2443                  * Wa_18011464164:tgl[B0+],dg1[B0+]
2444                  * Wa_22010931296:tgl[B0+],dg1[B0+]
2445                  * Wa_14010919138:rkl,dg1,adl-s,adl-p
2446                  */
2447                 wa_write_or(wal, GEN7_FF_THREAD_MODE,
2448                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
2449         }
2450
2451         if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) ||
2452             IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2453                 /*
2454                  * Wa_1606700617:tgl,dg1,adl-p
2455                  * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
2456                  * Wa_14010826681:tgl,dg1,rkl,adl-p
2457                  * Wa_18019627453:dg2
2458                  */
2459                 wa_masked_en(wal,
2460                              GEN9_CS_DEBUG_MODE1,
2461                              FF_DOP_CLOCK_GATE_DISABLE);
2462         }
2463
2464         if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
2465             IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2466                 /* Wa_1409804808 */
2467                 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
2468                                  GEN12_PUSH_CONST_DEREF_HOLD_DIS);
2469
2470                 /* Wa_14010229206 */
2471                 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
2472         }
2473
2474         if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
2475                 /*
2476                  * Wa_1607297627
2477                  *
2478                  * On TGL and RKL there are multiple entries for this WA in the
2479                  * BSpec; some indicate this is an A0-only WA, others indicate
2480                  * it applies to all steppings so we trust the "all steppings."
2481                  */
2482                 wa_masked_en(wal,
2483                              RING_PSMI_CTL(RENDER_RING_BASE),
2484                              GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
2485                              GEN8_RC_SEMA_IDLE_MSG_DISABLE);
2486         }
2487
2488         if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) ||
2489             IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
2490                 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
2491                 wa_mcr_masked_en(wal,
2492                                  GEN10_SAMPLER_MODE,
2493                                  ENABLE_SMALLPL);
2494         }
2495
2496         if (GRAPHICS_VER(i915) == 11) {
2497                 /* This is not an Wa. Enable for better image quality */
2498                 wa_masked_en(wal,
2499                              _3D_CHICKEN3,
2500                              _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
2501
2502                 /*
2503                  * Wa_1405543622:icl
2504                  * Formerly known as WaGAPZPriorityScheme
2505                  */
2506                 wa_write_or(wal,
2507                             GEN8_GARBCNTL,
2508                             GEN11_ARBITRATION_PRIO_ORDER_MASK);
2509
2510                 /*
2511                  * Wa_1604223664:icl
2512                  * Formerly known as WaL3BankAddressHashing
2513                  */
2514                 wa_write_clr_set(wal,
2515                                  GEN8_GARBCNTL,
2516                                  GEN11_HASH_CTRL_EXCL_MASK,
2517                                  GEN11_HASH_CTRL_EXCL_BIT0);
2518                 wa_write_clr_set(wal,
2519                                  GEN11_GLBLINVL,
2520                                  GEN11_BANK_HASH_ADDR_EXCL_MASK,
2521                                  GEN11_BANK_HASH_ADDR_EXCL_BIT0);
2522
2523                 /*
2524                  * Wa_1405733216:icl
2525                  * Formerly known as WaDisableCleanEvicts
2526                  */
2527                 wa_mcr_write_or(wal,
2528                                 GEN8_L3SQCREG4,
2529                                 GEN11_LQSC_CLEAN_EVICT_DISABLE);
2530
2531                 /* Wa_1606682166:icl */
2532                 wa_write_or(wal,
2533                             GEN7_SARCHKMD,
2534                             GEN7_DISABLE_SAMPLER_PREFETCH);
2535
2536                 /* Wa_1409178092:icl */
2537                 wa_mcr_write_clr_set(wal,
2538                                      GEN11_SCRATCH2,
2539                                      GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
2540                                      0);
2541
2542                 /* WaEnable32PlaneMode:icl */
2543                 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
2544                              GEN11_ENABLE_32_PLANE_MODE);
2545
2546                 /*
2547                  * Wa_1408767742:icl[a2..forever],ehl[all]
2548                  * Wa_1605460711:icl[a0..c0]
2549                  */
2550                 wa_write_or(wal,
2551                             GEN7_FF_THREAD_MODE,
2552                             GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
2553
2554                 /* Wa_22010271021 */
2555                 wa_masked_en(wal,
2556                              GEN9_CS_DEBUG_MODE1,
2557                              FF_DOP_CLOCK_GATE_DISABLE);
2558         }
2559
2560         /*
2561          * Intel platforms that support fine-grained preemption (i.e., gen9 and
2562          * beyond) allow the kernel-mode driver to choose between two different
2563          * options for controlling preemption granularity and behavior.
2564          *
2565          * Option 1 (hardware default):
2566          *   Preemption settings are controlled in a global manner via
2567          *   kernel-only register CS_DEBUG_MODE1 (0x20EC).  Any granularity
2568          *   and settings chosen by the kernel-mode driver will apply to all
2569          *   userspace clients.
2570          *
2571          * Option 2:
2572          *   Preemption settings are controlled on a per-context basis via
2573          *   register CS_CHICKEN1 (0x2580).  CS_CHICKEN1 is saved/restored on
2574          *   context switch and is writable by userspace (e.g., via
2575          *   MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer)
2576          *   which allows different userspace drivers/clients to select
2577          *   different settings, or to change those settings on the fly in
2578          *   response to runtime needs.  This option was known by name
2579          *   "FtrPerCtxtPreemptionGranularityControl" at one time, although
2580          *   that name is somewhat misleading as other non-granularity
2581          *   preemption settings are also impacted by this decision.
2582          *
2583          * On Linux, our policy has always been to let userspace drivers
2584          * control preemption granularity/settings (Option 2).  This was
2585          * originally mandatory on gen9 to prevent ABI breakage (old gen9
2586          * userspace developed before object-level preemption was enabled would
2587          * not behave well if i915 were to go with Option 1 and enable that
2588          * preemption in a global manner).  On gen9 each context would have
2589          * object-level preemption disabled by default (see
2590          * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but
2591          * userspace drivers could opt-in to object-level preemption as they
2592          * saw fit.  For post-gen9 platforms, we continue to utilize Option 2;
2593          * even though it is no longer necessary for ABI compatibility when
2594          * enabling a new platform, it does ensure that userspace will be able
2595          * to implement any workarounds that show up requiring temporary
2596          * adjustments to preemption behavior at runtime.
2597          *
2598          * Notes/Workarounds:
2599          *  - Wa_14015141709:  On DG2 and early steppings of MTL,
2600          *      CS_CHICKEN1[0] does not disable object-level preemption as
2601          *      it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been
2602          *      using Option 1).  Effectively this means userspace is unable
2603          *      to disable object-level preemption on these platforms/steppings
2604          *      despite the setting here.
2605          *
2606          *  - Wa_16013994831:  May require that userspace program
2607          *      CS_CHICKEN1[10] when certain runtime conditions are true.
2608          *      Userspace requires Option 2 to be in effect for their update of
2609          *      CS_CHICKEN1[10] to be effective.
2610          *
2611          * Other workarounds may appear in the future that will also require
2612          * Option 2 behavior to allow proper userspace implementation.
2613          */
2614         if (GRAPHICS_VER(i915) >= 9)
2615                 wa_masked_en(wal,
2616                              GEN7_FF_SLICE_CS_CHICKEN1,
2617                              GEN9_FFSC_PERCTX_PREEMPT_CTRL);
2618
2619         if (IS_SKYLAKE(i915) ||
2620             IS_KABYLAKE(i915) ||
2621             IS_COFFEELAKE(i915) ||
2622             IS_COMETLAKE(i915)) {
2623                 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
2624                 wa_write_or(wal,
2625                             GEN8_GARBCNTL,
2626                             GEN9_GAPS_TSV_CREDIT_DISABLE);
2627         }
2628
2629         if (IS_BROXTON(i915)) {
2630                 /* WaDisablePooledEuLoadBalancingFix:bxt */
2631                 wa_masked_en(wal,
2632                              FF_SLICE_CS_CHICKEN2,
2633                              GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
2634         }
2635
2636         if (GRAPHICS_VER(i915) == 9) {
2637                 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
2638                 wa_masked_en(wal,
2639                              GEN9_CSFE_CHICKEN1_RCS,
2640                              GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
2641
2642                 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
2643                 wa_mcr_write_or(wal,
2644                                 BDW_SCRATCH1,
2645                                 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
2646
2647                 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
2648                 if (IS_GEN9_LP(i915))
2649                         wa_mcr_write_clr_set(wal,
2650                                              GEN8_L3SQCREG1,
2651                                              L3_PRIO_CREDITS_MASK,
2652                                              L3_GENERAL_PRIO_CREDITS(62) |
2653                                              L3_HIGH_PRIO_CREDITS(2));
2654
2655                 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
2656                 wa_mcr_write_or(wal,
2657                                 GEN8_L3SQCREG4,
2658                                 GEN8_LQSC_FLUSH_COHERENT_LINES);
2659
2660                 /* Disable atomics in L3 to prevent unrecoverable hangs */
2661                 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
2662                                  GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
2663                 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4,
2664                                      GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
2665                 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1,
2666                                      EVICTION_PERF_FIX_ENABLE, 0);
2667         }
2668
2669         if (IS_HASWELL(i915)) {
2670                 /* WaSampleCChickenBitEnable:hsw */
2671                 wa_masked_en(wal,
2672                              HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
2673
2674                 wa_masked_dis(wal,
2675                               CACHE_MODE_0_GEN7,
2676                               /* enable HiZ Raw Stall Optimization */
2677                               HIZ_RAW_STALL_OPT_DISABLE);
2678         }
2679
2680         if (IS_VALLEYVIEW(i915)) {
2681                 /* WaDisableEarlyCull:vlv */
2682                 wa_masked_en(wal,
2683                              _3D_CHICKEN3,
2684                              _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
2685
2686                 /*
2687                  * WaVSThreadDispatchOverride:ivb,vlv
2688                  *
2689                  * This actually overrides the dispatch
2690                  * mode for all thread types.
2691                  */
2692                 wa_write_clr_set(wal,
2693                                  GEN7_FF_THREAD_MODE,
2694                                  GEN7_FF_SCHED_MASK,
2695                                  GEN7_FF_TS_SCHED_HW |
2696                                  GEN7_FF_VS_SCHED_HW |
2697                                  GEN7_FF_DS_SCHED_HW);
2698
2699                 /* WaPsdDispatchEnable:vlv */
2700                 /* WaDisablePSDDualDispatchEnable:vlv */
2701                 wa_masked_en(wal,
2702                              GEN7_HALF_SLICE_CHICKEN1,
2703                              GEN7_MAX_PS_THREAD_DEP |
2704                              GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
2705         }
2706
2707         if (IS_IVYBRIDGE(i915)) {
2708                 /* WaDisableEarlyCull:ivb */
2709                 wa_masked_en(wal,
2710                              _3D_CHICKEN3,
2711                              _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
2712
2713                 if (0) { /* causes HiZ corruption on ivb:gt1 */
2714                         /* enable HiZ Raw Stall Optimization */
2715                         wa_masked_dis(wal,
2716                                       CACHE_MODE_0_GEN7,
2717                                       HIZ_RAW_STALL_OPT_DISABLE);
2718                 }
2719
2720                 /*
2721                  * WaVSThreadDispatchOverride:ivb,vlv
2722                  *
2723                  * This actually overrides the dispatch
2724                  * mode for all thread types.
2725                  */
2726                 wa_write_clr_set(wal,
2727                                  GEN7_FF_THREAD_MODE,
2728                                  GEN7_FF_SCHED_MASK,
2729                                  GEN7_FF_TS_SCHED_HW |
2730                                  GEN7_FF_VS_SCHED_HW |
2731                                  GEN7_FF_DS_SCHED_HW);
2732
2733                 /* WaDisablePSDDualDispatchEnable:ivb */
2734                 if (IS_IVB_GT1(i915))
2735                         wa_masked_en(wal,
2736                                      GEN7_HALF_SLICE_CHICKEN1,
2737                                      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
2738         }
2739
2740         if (GRAPHICS_VER(i915) == 7) {
2741                 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
2742                 wa_masked_en(wal,
2743                              RING_MODE_GEN7(RENDER_RING_BASE),
2744                              GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
2745
2746                 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
2747                 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
2748
2749                 /*
2750                  * BSpec says this must be set, even though
2751                  * WaDisable4x2SubspanOptimization:ivb,hsw
2752                  * WaDisable4x2SubspanOptimization isn't listed for VLV.
2753                  */
2754                 wa_masked_en(wal,
2755                              CACHE_MODE_1,
2756                              PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
2757
2758                 /*
2759                  * BSpec recommends 8x4 when MSAA is used,
2760                  * however in practice 16x4 seems fastest.
2761                  *
2762                  * Note that PS/WM thread counts depend on the WIZ hashing
2763                  * disable bit, which we don't touch here, but it's good
2764                  * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
2765                  */
2766                 wa_masked_field_set(wal,
2767                                     GEN7_GT_MODE,
2768                                     GEN6_WIZ_HASHING_MASK,
2769                                     GEN6_WIZ_HASHING_16x4);
2770         }
2771
2772         if (IS_GRAPHICS_VER(i915, 6, 7))
2773                 /*
2774                  * We need to disable the AsyncFlip performance optimisations in
2775                  * order to use MI_WAIT_FOR_EVENT within the CS. It should
2776                  * already be programmed to '1' on all products.
2777                  *
2778                  * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
2779                  */
2780                 wa_masked_en(wal,
2781                              RING_MI_MODE(RENDER_RING_BASE),
2782                              ASYNC_FLIP_PERF_DISABLE);
2783
2784         if (GRAPHICS_VER(i915) == 6) {
2785                 /*
2786                  * Required for the hardware to program scanline values for
2787                  * waiting
2788                  * WaEnableFlushTlbInvalidationMode:snb
2789                  */
2790                 wa_masked_en(wal,
2791                              GFX_MODE,
2792                              GFX_TLB_INVALIDATE_EXPLICIT);
2793
2794                 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
2795                 wa_masked_en(wal,
2796                              _3D_CHICKEN,
2797                              _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
2798
2799                 wa_masked_en(wal,
2800                              _3D_CHICKEN3,
2801                              /* WaStripsFansDisableFastClipPerformanceFix:snb */
2802                              _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
2803                              /*
2804                               * Bspec says:
2805                               * "This bit must be set if 3DSTATE_CLIP clip mode is set
2806                               * to normal and 3DSTATE_SF number of SF output attributes
2807                               * is more than 16."
2808                               */
2809                              _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
2810
2811                 /*
2812                  * BSpec recommends 8x4 when MSAA is used,
2813                  * however in practice 16x4 seems fastest.
2814                  *
2815                  * Note that PS/WM thread counts depend on the WIZ hashing
2816                  * disable bit, which we don't touch here, but it's good
2817                  * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
2818                  */
2819                 wa_masked_field_set(wal,
2820                                     GEN6_GT_MODE,
2821                                     GEN6_WIZ_HASHING_MASK,
2822                                     GEN6_WIZ_HASHING_16x4);
2823
2824                 /* WaDisable_RenderCache_OperationalFlush:snb */
2825                 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
2826
2827                 /*
2828                  * From the Sandybridge PRM, volume 1 part 3, page 24:
2829                  * "If this bit is set, STCunit will have LRA as replacement
2830                  *  policy. [...] This bit must be reset. LRA replacement
2831                  *  policy is not supported."
2832                  */
2833                 wa_masked_dis(wal,
2834                               CACHE_MODE_0,
2835                               CM0_STC_EVICT_DISABLE_LRA_SNB);
2836         }
2837
2838         if (IS_GRAPHICS_VER(i915, 4, 6))
2839                 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
2840                 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),
2841                        0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
2842                        /* XXX bit doesn't stick on Broadwater */
2843                        IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true);
2844
2845         if (GRAPHICS_VER(i915) == 4)
2846                 /*
2847                  * Disable CONSTANT_BUFFER before it is loaded from the context
2848                  * image. For as it is loaded, it is executed and the stored
2849                  * address may no longer be valid, leading to a GPU hang.
2850                  *
2851                  * This imposes the requirement that userspace reload their
2852                  * CONSTANT_BUFFER on every batch, fortunately a requirement
2853                  * they are already accustomed to from before contexts were
2854                  * enabled.
2855                  */
2856                 wa_add(wal, ECOSKPD(RENDER_RING_BASE),
2857                        0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
2858                        0 /* XXX bit doesn't stick on Broadwater */,
2859                        true);
2860 }
2861
2862 static void
2863 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2864 {
2865         struct drm_i915_private *i915 = engine->i915;
2866
2867         /* WaKBLVECSSemaphoreWaitPoll:kbl */
2868         if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
2869                 wa_write(wal,
2870                          RING_SEMA_WAIT_POLL(engine->mmio_base),
2871                          1);
2872         }
2873 }
2874
2875 static void
2876 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2877 {
2878         if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) {
2879                 /* Wa_14014999345:pvc */
2880                 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
2881         }
2882 }
2883
2884 /*
2885  * The bspec performance guide has recommended MMIO tuning settings.  These
2886  * aren't truly "workarounds" but we want to program them with the same
2887  * workaround infrastructure to ensure that they're automatically added to
2888  * the GuC save/restore lists, re-applied at the right times, and checked for
2889  * any conflicting programming requested by real workarounds.
2890  *
2891  * Programming settings should be added here only if their registers are not
2892  * part of an engine's register state context.  If a register is part of a
2893  * context, then any tuning settings should be programmed in an appropriate
2894  * function invoked by __intel_engine_init_ctx_wa().
2895  */
2896 static void
2897 add_render_compute_tuning_settings(struct drm_i915_private *i915,
2898                                    struct i915_wa_list *wal)
2899 {
2900         if (IS_PONTEVECCHIO(i915)) {
2901                 wa_mcr_write(wal, XEHPC_L3SCRUB,
2902                              SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
2903                 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
2904         }
2905
2906         if (IS_DG2(i915)) {
2907                 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
2908                 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
2909         }
2910
2911         /*
2912          * This tuning setting proves beneficial only on ATS-M designs; the
2913          * default "age based" setting is optimal on regular DG2 and other
2914          * platforms.
2915          */
2916         if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
2917                 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
2918                                         THREAD_EX_ARB_MODE_RR_AFTER_DEP);
2919
2920         if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
2921                 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
2922 }
2923
2924 /*
2925  * The workarounds in this function apply to shared registers in
2926  * the general render reset domain that aren't tied to a
2927  * specific engine.  Since all render+compute engines get reset
2928  * together, and the contents of these registers are lost during
2929  * the shared render domain reset, we'll define such workarounds
2930  * here and then add them to just a single RCS or CCS engine's
2931  * workaround list (whichever engine has the XXXX flag).
2932  */
2933 static void
2934 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2935 {
2936         struct drm_i915_private *i915 = engine->i915;
2937
2938         add_render_compute_tuning_settings(i915, wal);
2939
2940         if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2941             IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
2942             IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
2943             IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
2944                 /* Wa_22013037850 */
2945                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
2946                                 DISABLE_128B_EVICTION_COMMAND_UDW);
2947         }
2948
2949         if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2950             IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
2951             IS_PONTEVECCHIO(i915) ||
2952             IS_DG2(i915)) {
2953                 /* Wa_22014226127 */
2954                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
2955         }
2956
2957         if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
2958             IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
2959             IS_DG2(i915)) {
2960                 /* Wa_18017747507 */
2961                 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
2962         }
2963
2964         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
2965             IS_DG2_G11(i915)) {
2966                 /*
2967                  * Wa_22012826095:dg2
2968                  * Wa_22013059131:dg2
2969                  */
2970                 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
2971                                      MAXREQS_PER_BANK,
2972                                      REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
2973
2974                 /* Wa_22013059131:dg2 */
2975                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
2976                                 FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
2977         }
2978
2979         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
2980                 /*
2981                  * Wa_14010918519:dg2_g10
2982                  *
2983                  * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping,
2984                  * so ignoring verification.
2985                  */
2986                 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
2987                            FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
2988                            0, false);
2989         }
2990
2991         if (IS_PONTEVECCHIO(i915)) {
2992                 /* Wa_16016694945 */
2993                 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
2994         }
2995
2996         if (IS_XEHPSDV(i915)) {
2997                 /* Wa_1409954639 */
2998                 wa_mcr_masked_en(wal,
2999                                  GEN8_ROW_CHICKEN,
3000                                  SYSTOLIC_DOP_CLOCK_GATING_DIS);
3001
3002                 /* Wa_1607196519 */
3003                 wa_mcr_masked_en(wal,
3004                                  GEN9_ROW_CHICKEN4,
3005                                  GEN12_DISABLE_GRF_CLEAR);
3006
3007                 /* Wa_14010670810:xehpsdv */
3008                 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
3009
3010                 /* Wa_14010449647:xehpsdv */
3011                 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
3012                                  GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
3013
3014                 /* Wa_18011725039:xehpsdv */
3015                 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
3016                         wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
3017                         wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
3018                 }
3019         }
3020
3021         if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) {
3022                 /* Wa_14015227452:dg2,pvc */
3023                 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
3024
3025                 /* Wa_16015675438:dg2,pvc */
3026                 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
3027         }
3028
3029         if (IS_DG2(i915)) {
3030                 /*
3031                  * Wa_16011620976:dg2_g11
3032                  * Wa_22015475538:dg2
3033                  */
3034                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
3035         }
3036
3037         if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915))
3038                 /*
3039                  * Wa_22012654132
3040                  *
3041                  * Note that register 0xE420 is write-only and cannot be read
3042                  * back for verification on DG2 (due to Wa_14012342262), so
3043                  * we need to explicitly skip the readback.
3044                  */
3045                 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
3046                            _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
3047                            0 /* write-only, so skip validation */,
3048                            true);
3049 }
3050
3051 static void
3052 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
3053 {
3054         if (GRAPHICS_VER(engine->i915) < 4)
3055                 return;
3056
3057         engine_fake_wa_init(engine, wal);
3058
3059         /*
3060          * These are common workarounds that just need to applied
3061          * to a single RCS/CCS engine's workaround list since
3062          * they're reset as part of the general render domain reset.
3063          */
3064         if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
3065                 general_render_compute_wa_init(engine, wal);
3066
3067         if (engine->class == COMPUTE_CLASS)
3068                 ccs_engine_wa_init(engine, wal);
3069         else if (engine->class == RENDER_CLASS)
3070                 rcs_engine_wa_init(engine, wal);
3071         else
3072                 xcs_engine_wa_init(engine, wal);
3073 }
3074
3075 void intel_engine_init_workarounds(struct intel_engine_cs *engine)
3076 {
3077         struct i915_wa_list *wal = &engine->wa_list;
3078
3079         wa_init_start(wal, engine->gt, "engine", engine->name);
3080         engine_init_workarounds(engine, wal);
3081         wa_init_finish(wal);
3082 }
3083
3084 void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
3085 {
3086         wa_list_apply(&engine->wa_list);
3087 }
3088
3089 static const struct i915_range mcr_ranges_gen8[] = {
3090         { .start = 0x5500, .end = 0x55ff },
3091         { .start = 0x7000, .end = 0x7fff },
3092         { .start = 0x9400, .end = 0x97ff },
3093         { .start = 0xb000, .end = 0xb3ff },
3094         { .start = 0xe000, .end = 0xe7ff },
3095         {},
3096 };
3097
3098 static const struct i915_range mcr_ranges_gen12[] = {
3099         { .start =  0x8150, .end =  0x815f },
3100         { .start =  0x9520, .end =  0x955f },
3101         { .start =  0xb100, .end =  0xb3ff },
3102         { .start =  0xde80, .end =  0xe8ff },
3103         { .start = 0x24a00, .end = 0x24a7f },
3104         {},
3105 };
3106
3107 static const struct i915_range mcr_ranges_xehp[] = {
3108         { .start =  0x4000, .end =  0x4aff },
3109         { .start =  0x5200, .end =  0x52ff },
3110         { .start =  0x5400, .end =  0x7fff },
3111         { .start =  0x8140, .end =  0x815f },
3112         { .start =  0x8c80, .end =  0x8dff },
3113         { .start =  0x94d0, .end =  0x955f },
3114         { .start =  0x9680, .end =  0x96ff },
3115         { .start =  0xb000, .end =  0xb3ff },
3116         { .start =  0xc800, .end =  0xcfff },
3117         { .start =  0xd800, .end =  0xd8ff },
3118         { .start =  0xdc00, .end =  0xffff },
3119         { .start = 0x17000, .end = 0x17fff },
3120         { .start = 0x24a00, .end = 0x24a7f },
3121         {},
3122 };
3123
3124 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
3125 {
3126         const struct i915_range *mcr_ranges;
3127         int i;
3128
3129         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
3130                 mcr_ranges = mcr_ranges_xehp;
3131         else if (GRAPHICS_VER(i915) >= 12)
3132                 mcr_ranges = mcr_ranges_gen12;
3133         else if (GRAPHICS_VER(i915) >= 8)
3134                 mcr_ranges = mcr_ranges_gen8;
3135         else
3136                 return false;
3137
3138         /*
3139          * Registers in these ranges are affected by the MCR selector
3140          * which only controls CPU initiated MMIO. Routing does not
3141          * work for CS access so we cannot verify them on this path.
3142          */
3143         for (i = 0; mcr_ranges[i].start; i++)
3144                 if (offset >= mcr_ranges[i].start &&
3145                     offset <= mcr_ranges[i].end)
3146                         return true;
3147
3148         return false;
3149 }
3150
3151 static int
3152 wa_list_srm(struct i915_request *rq,
3153             const struct i915_wa_list *wal,
3154             struct i915_vma *vma)
3155 {
3156         struct drm_i915_private *i915 = rq->engine->i915;
3157         unsigned int i, count = 0;
3158         const struct i915_wa *wa;
3159         u32 srm, *cs;
3160
3161         srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
3162         if (GRAPHICS_VER(i915) >= 8)
3163                 srm++;
3164
3165         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3166                 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
3167                         count++;
3168         }
3169
3170         cs = intel_ring_begin(rq, 4 * count);
3171         if (IS_ERR(cs))
3172                 return PTR_ERR(cs);
3173
3174         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3175                 u32 offset = i915_mmio_reg_offset(wa->reg);
3176
3177                 if (mcr_range(i915, offset))
3178                         continue;
3179
3180                 *cs++ = srm;
3181                 *cs++ = offset;
3182                 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
3183                 *cs++ = 0;
3184         }
3185         intel_ring_advance(rq, cs);
3186
3187         return 0;
3188 }
3189
3190 static int engine_wa_list_verify(struct intel_context *ce,
3191                                  const struct i915_wa_list * const wal,
3192                                  const char *from)
3193 {
3194         const struct i915_wa *wa;
3195         struct i915_request *rq;
3196         struct i915_vma *vma;
3197         struct i915_gem_ww_ctx ww;
3198         unsigned int i;
3199         u32 *results;
3200         int err;
3201
3202         if (!wal->count)
3203                 return 0;
3204
3205         vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm,
3206                                            wal->count * sizeof(u32));
3207         if (IS_ERR(vma))
3208                 return PTR_ERR(vma);
3209
3210         intel_engine_pm_get(ce->engine);
3211         i915_gem_ww_ctx_init(&ww, false);
3212 retry:
3213         err = i915_gem_object_lock(vma->obj, &ww);
3214         if (err == 0)
3215                 err = intel_context_pin_ww(ce, &ww);
3216         if (err)
3217                 goto err_pm;
3218
3219         err = i915_vma_pin_ww(vma, &ww, 0, 0,
3220                            i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
3221         if (err)
3222                 goto err_unpin;
3223
3224         rq = i915_request_create(ce);
3225         if (IS_ERR(rq)) {
3226                 err = PTR_ERR(rq);
3227                 goto err_vma;
3228         }
3229
3230         err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
3231         if (err == 0)
3232                 err = wa_list_srm(rq, wal, vma);
3233
3234         i915_request_get(rq);
3235         if (err)
3236                 i915_request_set_error_once(rq, err);
3237         i915_request_add(rq);
3238
3239         if (err)
3240                 goto err_rq;
3241
3242         if (i915_request_wait(rq, 0, HZ / 5) < 0) {
3243                 err = -ETIME;
3244                 goto err_rq;
3245         }
3246
3247         results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
3248         if (IS_ERR(results)) {
3249                 err = PTR_ERR(results);
3250                 goto err_rq;
3251         }
3252
3253         err = 0;
3254         for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3255                 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg)))
3256                         continue;
3257
3258                 if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
3259                         err = -ENXIO;
3260         }
3261
3262         i915_gem_object_unpin_map(vma->obj);
3263
3264 err_rq:
3265         i915_request_put(rq);
3266 err_vma:
3267         i915_vma_unpin(vma);
3268 err_unpin:
3269         intel_context_unpin(ce);
3270 err_pm:
3271         if (err == -EDEADLK) {
3272                 err = i915_gem_ww_ctx_backoff(&ww);
3273                 if (!err)
3274                         goto retry;
3275         }
3276         i915_gem_ww_ctx_fini(&ww);
3277         intel_engine_pm_put(ce->engine);
3278         i915_vma_put(vma);
3279         return err;
3280 }
3281
3282 int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
3283                                     const char *from)
3284 {
3285         return engine_wa_list_verify(engine->kernel_context,
3286                                      &engine->wa_list,
3287                                      from);
3288 }
3289
3290 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3291 #include "selftest_workarounds.c"
3292 #endif