drivers/gpu/drm/i915/display/skl_universal_plane.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <drm/drm_atomic_helper.h>
   7 #include <drm/drm_blend.h>
   8 #include <drm/drm_damage_helper.h>
   9 #include <drm/drm_fourcc.h>
  10
  11 #include "i915_drv.h"
  12 #include "i915_reg.h"
  13 #include "intel_atomic_plane.h"
  14 #include "intel_de.h"
  15 #include "intel_display_irq.h"
  16 #include "intel_display_types.h"
  17 #include "intel_fb.h"
  18 #include "intel_fbc.h"
  19 #include "intel_psr.h"
  20 #include "skl_scaler.h"
  21 #include "skl_universal_plane.h"
  22 #include "skl_watermark.h"
  23 #include "gt/intel_gt.h"
  24 #include "pxp/intel_pxp.h"
  25
  26 static const u32 skl_plane_formats[] = {
  27         DRM_FORMAT_C8,
  28         DRM_FORMAT_RGB565,
  29         DRM_FORMAT_XRGB8888,
  30         DRM_FORMAT_XBGR8888,
  31         DRM_FORMAT_ARGB8888,
  32         DRM_FORMAT_ABGR8888,
  33         DRM_FORMAT_XRGB2101010,
  34         DRM_FORMAT_XBGR2101010,
  35         DRM_FORMAT_XRGB16161616F,
  36         DRM_FORMAT_XBGR16161616F,
  37         DRM_FORMAT_YUYV,
  38         DRM_FORMAT_YVYU,
  39         DRM_FORMAT_UYVY,
  40         DRM_FORMAT_VYUY,
  41         DRM_FORMAT_XYUV8888,
  42 };
  43
  44 static const u32 skl_planar_formats[] = {
  45         DRM_FORMAT_C8,
  46         DRM_FORMAT_RGB565,
  47         DRM_FORMAT_XRGB8888,
  48         DRM_FORMAT_XBGR8888,
  49         DRM_FORMAT_ARGB8888,
  50         DRM_FORMAT_ABGR8888,
  51         DRM_FORMAT_XRGB2101010,
  52         DRM_FORMAT_XBGR2101010,
  53         DRM_FORMAT_XRGB16161616F,
  54         DRM_FORMAT_XBGR16161616F,
  55         DRM_FORMAT_YUYV,
  56         DRM_FORMAT_YVYU,
  57         DRM_FORMAT_UYVY,
  58         DRM_FORMAT_VYUY,
  59         DRM_FORMAT_NV12,
  60         DRM_FORMAT_XYUV8888,
  61 };
  62
  63 static const u32 glk_planar_formats[] = {
  64         DRM_FORMAT_C8,
  65         DRM_FORMAT_RGB565,
  66         DRM_FORMAT_XRGB8888,
  67         DRM_FORMAT_XBGR8888,
  68         DRM_FORMAT_ARGB8888,
  69         DRM_FORMAT_ABGR8888,
  70         DRM_FORMAT_XRGB2101010,
  71         DRM_FORMAT_XBGR2101010,
  72         DRM_FORMAT_XRGB16161616F,
  73         DRM_FORMAT_XBGR16161616F,
  74         DRM_FORMAT_YUYV,
  75         DRM_FORMAT_YVYU,
  76         DRM_FORMAT_UYVY,
  77         DRM_FORMAT_VYUY,
  78         DRM_FORMAT_NV12,
  79         DRM_FORMAT_XYUV8888,
  80         DRM_FORMAT_P010,
  81         DRM_FORMAT_P012,
  82         DRM_FORMAT_P016,
  83 };
  84
  85 static const u32 icl_sdr_y_plane_formats[] = {
  86         DRM_FORMAT_C8,
  87         DRM_FORMAT_RGB565,
  88         DRM_FORMAT_XRGB8888,
  89         DRM_FORMAT_XBGR8888,
  90         DRM_FORMAT_ARGB8888,
  91         DRM_FORMAT_ABGR8888,
  92         DRM_FORMAT_XRGB2101010,
  93         DRM_FORMAT_XBGR2101010,
  94         DRM_FORMAT_ARGB2101010,
  95         DRM_FORMAT_ABGR2101010,
  96         DRM_FORMAT_YUYV,
  97         DRM_FORMAT_YVYU,
  98         DRM_FORMAT_UYVY,
  99         DRM_FORMAT_VYUY,
 100         DRM_FORMAT_Y210,
 101         DRM_FORMAT_Y212,
 102         DRM_FORMAT_Y216,
 103         DRM_FORMAT_XYUV8888,
 104         DRM_FORMAT_XVYU2101010,
 105         DRM_FORMAT_XVYU12_16161616,
 106         DRM_FORMAT_XVYU16161616,
 107 };
 108
 109 static const u32 icl_sdr_uv_plane_formats[] = {
 110         DRM_FORMAT_C8,
 111         DRM_FORMAT_RGB565,
 112         DRM_FORMAT_XRGB8888,
 113         DRM_FORMAT_XBGR8888,
 114         DRM_FORMAT_ARGB8888,
 115         DRM_FORMAT_ABGR8888,
 116         DRM_FORMAT_XRGB2101010,
 117         DRM_FORMAT_XBGR2101010,
 118         DRM_FORMAT_ARGB2101010,
 119         DRM_FORMAT_ABGR2101010,
 120         DRM_FORMAT_YUYV,
 121         DRM_FORMAT_YVYU,
 122         DRM_FORMAT_UYVY,
 123         DRM_FORMAT_VYUY,
 124         DRM_FORMAT_NV12,
 125         DRM_FORMAT_P010,
 126         DRM_FORMAT_P012,
 127         DRM_FORMAT_P016,
 128         DRM_FORMAT_Y210,
 129         DRM_FORMAT_Y212,
 130         DRM_FORMAT_Y216,
 131         DRM_FORMAT_XYUV8888,
 132         DRM_FORMAT_XVYU2101010,
 133         DRM_FORMAT_XVYU12_16161616,
 134         DRM_FORMAT_XVYU16161616,
 135 };
 136
 137 static const u32 icl_hdr_plane_formats[] = {
 138         DRM_FORMAT_C8,
 139         DRM_FORMAT_RGB565,
 140         DRM_FORMAT_XRGB8888,
 141         DRM_FORMAT_XBGR8888,
 142         DRM_FORMAT_ARGB8888,
 143         DRM_FORMAT_ABGR8888,
 144         DRM_FORMAT_XRGB2101010,
 145         DRM_FORMAT_XBGR2101010,
 146         DRM_FORMAT_ARGB2101010,
 147         DRM_FORMAT_ABGR2101010,
 148         DRM_FORMAT_XRGB16161616F,
 149         DRM_FORMAT_XBGR16161616F,
 150         DRM_FORMAT_ARGB16161616F,
 151         DRM_FORMAT_ABGR16161616F,
 152         DRM_FORMAT_YUYV,
 153         DRM_FORMAT_YVYU,
 154         DRM_FORMAT_UYVY,
 155         DRM_FORMAT_VYUY,
 156         DRM_FORMAT_NV12,
 157         DRM_FORMAT_P010,
 158         DRM_FORMAT_P012,
 159         DRM_FORMAT_P016,
 160         DRM_FORMAT_Y210,
 161         DRM_FORMAT_Y212,
 162         DRM_FORMAT_Y216,
 163         DRM_FORMAT_XYUV8888,
 164         DRM_FORMAT_XVYU2101010,
 165         DRM_FORMAT_XVYU12_16161616,
 166         DRM_FORMAT_XVYU16161616,
 167 };
 168
 169 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 170 {
 171         switch (format) {
 172         case PLANE_CTL_FORMAT_RGB_565:
 173                 return DRM_FORMAT_RGB565;
 174         case PLANE_CTL_FORMAT_NV12:
 175                 return DRM_FORMAT_NV12;
 176         case PLANE_CTL_FORMAT_XYUV:
 177                 return DRM_FORMAT_XYUV8888;
 178         case PLANE_CTL_FORMAT_P010:
 179                 return DRM_FORMAT_P010;
 180         case PLANE_CTL_FORMAT_P012:
 181                 return DRM_FORMAT_P012;
 182         case PLANE_CTL_FORMAT_P016:
 183                 return DRM_FORMAT_P016;
 184         case PLANE_CTL_FORMAT_Y210:
 185                 return DRM_FORMAT_Y210;
 186         case PLANE_CTL_FORMAT_Y212:
 187                 return DRM_FORMAT_Y212;
 188         case PLANE_CTL_FORMAT_Y216:
 189                 return DRM_FORMAT_Y216;
 190         case PLANE_CTL_FORMAT_Y410:
 191                 return DRM_FORMAT_XVYU2101010;
 192         case PLANE_CTL_FORMAT_Y412:
 193                 return DRM_FORMAT_XVYU12_16161616;
 194         case PLANE_CTL_FORMAT_Y416:
 195                 return DRM_FORMAT_XVYU16161616;
 196         default:
 197         case PLANE_CTL_FORMAT_XRGB_8888:
 198                 if (rgb_order) {
 199                         if (alpha)
 200                                 return DRM_FORMAT_ABGR8888;
 201                         else
 202                                 return DRM_FORMAT_XBGR8888;
 203                 } else {
 204                         if (alpha)
 205                                 return DRM_FORMAT_ARGB8888;
 206                         else
 207                                 return DRM_FORMAT_XRGB8888;
 208                 }
 209         case PLANE_CTL_FORMAT_XRGB_2101010:
 210                 if (rgb_order) {
 211                         if (alpha)
 212                                 return DRM_FORMAT_ABGR2101010;
 213                         else
 214                                 return DRM_FORMAT_XBGR2101010;
 215                 } else {
 216                         if (alpha)
 217                                 return DRM_FORMAT_ARGB2101010;
 218                         else
 219                                 return DRM_FORMAT_XRGB2101010;
 220                 }
 221         case PLANE_CTL_FORMAT_XRGB_16161616F:
 222                 if (rgb_order) {
 223                         if (alpha)
 224                                 return DRM_FORMAT_ABGR16161616F;
 225                         else
 226                                 return DRM_FORMAT_XBGR16161616F;
 227                 } else {
 228                         if (alpha)
 229                                 return DRM_FORMAT_ARGB16161616F;
 230                         else
 231                                 return DRM_FORMAT_XRGB16161616F;
 232                 }
 233         }
 234 }
 235
 236 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
 237 {
 238         if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
 239                 return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
 240         else
 241                 return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
 242 }
 243
 244 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
 245                          enum plane_id plane_id)
 246 {
 247         return DISPLAY_VER(dev_priv) >= 11 &&
 248                 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
 249 }
 250
 251 u8 icl_hdr_plane_mask(void)
 252 {
 253         return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
 254 }
 255
 256 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
 257 {
 258         return DISPLAY_VER(dev_priv) >= 11 &&
 259                 icl_hdr_plane_mask() & BIT(plane_id);
 260 }
 261
 262 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 263                                const struct intel_plane_state *plane_state)
 264 {
 265         unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
 266
 267         /* two pixels per clock */
 268         return DIV_ROUND_UP(pixel_rate, 2);
 269 }
 270
 271 static void
 272 glk_plane_ratio(const struct intel_plane_state *plane_state,
 273                 unsigned int *num, unsigned int *den)
 274 {
 275         const struct drm_framebuffer *fb = plane_state->hw.fb;
 276
 277         if (fb->format->cpp[0] == 8) {
 278                 *num = 10;
 279                 *den = 8;
 280         } else {
 281                 *num = 1;
 282                 *den = 1;
 283         }
 284 }
 285
 286 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 287                                const struct intel_plane_state *plane_state)
 288 {
 289         unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
 290         unsigned int num, den;
 291
 292         glk_plane_ratio(plane_state, &num, &den);
 293
 294         /* two pixels per clock */
 295         return DIV_ROUND_UP(pixel_rate * num, 2 * den);
 296 }
 297
 298 static void
 299 skl_plane_ratio(const struct intel_plane_state *plane_state,
 300                 unsigned int *num, unsigned int *den)
 301 {
 302         const struct drm_framebuffer *fb = plane_state->hw.fb;
 303
 304         if (fb->format->cpp[0] == 8) {
 305                 *num = 9;
 306                 *den = 8;
 307         } else {
 308                 *num = 1;
 309                 *den = 1;
 310         }
 311 }
 312
 313 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 314                                const struct intel_plane_state *plane_state)
 315 {
 316         unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
 317         unsigned int num, den;
 318
 319         skl_plane_ratio(plane_state, &num, &den);
 320
 321         return DIV_ROUND_UP(pixel_rate * num, den);
 322 }
 323
 324 static int skl_plane_max_width(const struct drm_framebuffer *fb,
 325                                int color_plane,
 326                                unsigned int rotation)
 327 {
 328         int cpp = fb->format->cpp[color_plane];
 329
 330         switch (fb->modifier) {
 331         case DRM_FORMAT_MOD_LINEAR:
 332         case I915_FORMAT_MOD_X_TILED:
 333                 /*
 334                  * Validated limit is 4k, but has 5k should
 335                  * work apart from the following features:
 336                  * - Ytile (already limited to 4k)
 337                  * - FP16 (already limited to 4k)
 338                  * - render compression (already limited to 4k)
 339                  * - KVMR sprite and cursor (don't care)
 340                  * - horizontal panning (TODO verify this)
 341                  * - pipe and plane scaling (TODO verify this)
 342                  */
 343                 if (cpp == 8)
 344                         return 4096;
 345                 else
 346                         return 5120;
 347         case I915_FORMAT_MOD_Y_TILED_CCS:
 348         case I915_FORMAT_MOD_Yf_TILED_CCS:
 349         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 350                 /* FIXME AUX plane? */
 351         case I915_FORMAT_MOD_Y_TILED:
 352         case I915_FORMAT_MOD_Yf_TILED:
 353                 if (cpp == 8)
 354                         return 2048;
 355                 else
 356                         return 4096;
 357         default:
 358                 MISSING_CASE(fb->modifier);
 359                 return 2048;
 360         }
 361 }
 362
 363 static int glk_plane_max_width(const struct drm_framebuffer *fb,
 364                                int color_plane,
 365                                unsigned int rotation)
 366 {
 367         int cpp = fb->format->cpp[color_plane];
 368
 369         switch (fb->modifier) {
 370         case DRM_FORMAT_MOD_LINEAR:
 371         case I915_FORMAT_MOD_X_TILED:
 372                 if (cpp == 8)
 373                         return 4096;
 374                 else
 375                         return 5120;
 376         case I915_FORMAT_MOD_Y_TILED_CCS:
 377         case I915_FORMAT_MOD_Yf_TILED_CCS:
 378                 /* FIXME AUX plane? */
 379         case I915_FORMAT_MOD_Y_TILED:
 380         case I915_FORMAT_MOD_Yf_TILED:
 381                 if (cpp == 8)
 382                         return 2048;
 383                 else
 384                         return 5120;
 385         default:
 386                 MISSING_CASE(fb->modifier);
 387                 return 2048;
 388         }
 389 }
 390
 391 static int icl_plane_min_width(const struct drm_framebuffer *fb,
 392                                int color_plane,
 393                                unsigned int rotation)
 394 {
 395         /* Wa_14011264657, Wa_14011050563: gen11+ */
 396         switch (fb->format->format) {
 397         case DRM_FORMAT_C8:
 398                 return 18;
 399         case DRM_FORMAT_RGB565:
 400                 return 10;
 401         case DRM_FORMAT_XRGB8888:
 402         case DRM_FORMAT_XBGR8888:
 403         case DRM_FORMAT_ARGB8888:
 404         case DRM_FORMAT_ABGR8888:
 405         case DRM_FORMAT_XRGB2101010:
 406         case DRM_FORMAT_XBGR2101010:
 407         case DRM_FORMAT_ARGB2101010:
 408         case DRM_FORMAT_ABGR2101010:
 409         case DRM_FORMAT_XVYU2101010:
 410         case DRM_FORMAT_Y212:
 411         case DRM_FORMAT_Y216:
 412                 return 6;
 413         case DRM_FORMAT_NV12:
 414                 return 20;
 415         case DRM_FORMAT_P010:
 416         case DRM_FORMAT_P012:
 417         case DRM_FORMAT_P016:
 418                 return 12;
 419         case DRM_FORMAT_XRGB16161616F:
 420         case DRM_FORMAT_XBGR16161616F:
 421         case DRM_FORMAT_ARGB16161616F:
 422         case DRM_FORMAT_ABGR16161616F:
 423         case DRM_FORMAT_XVYU12_16161616:
 424         case DRM_FORMAT_XVYU16161616:
 425                 return 4;
 426         default:
 427                 return 1;
 428         }
 429 }
 430
 431 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
 432                                    int color_plane,
 433                                    unsigned int rotation)
 434 {
 435         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 436                 return 4096;
 437         else
 438                 return 5120;
 439 }
 440
 441 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
 442                                    int color_plane,
 443                                    unsigned int rotation)
 444 {
 445         return 5120;
 446 }
 447
 448 static int skl_plane_max_height(const struct drm_framebuffer *fb,
 449                                 int color_plane,
 450                                 unsigned int rotation)
 451 {
 452         return 4096;
 453 }
 454
 455 static int icl_plane_max_height(const struct drm_framebuffer *fb,
 456                                 int color_plane,
 457                                 unsigned int rotation)
 458 {
 459         return 4320;
 460 }
 461
 462 static unsigned int
 463 skl_plane_max_stride(struct intel_plane *plane,
 464                      u32 pixel_format, u64 modifier,
 465                      unsigned int rotation)
 466 {
 467         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 468         const struct drm_format_info *info = drm_format_info(pixel_format);
 469         int cpp = info->cpp[0];
 470         int max_horizontal_pixels = 8192;
 471         int max_stride_bytes;
 472
 473         if (DISPLAY_VER(i915) >= 13) {
 474                 /*
 475                  * The stride in bytes must not exceed of the size
 476                  * of 128K bytes. For pixel formats of 64bpp will allow
 477                  * for a 16K pixel surface.
 478                  */
 479                 max_stride_bytes = 131072;
 480                 if (cpp == 8)
 481                         max_horizontal_pixels = 16384;
 482                 else
 483                         max_horizontal_pixels = 65536;
 484         } else {
 485                 /*
 486                  * "The stride in bytes must not exceed the
 487                  * of the size of 8K pixels and 32K bytes."
 488                  */
 489                 max_stride_bytes = 32768;
 490         }
 491
 492         if (drm_rotation_90_or_270(rotation))
 493                 return min(max_horizontal_pixels, max_stride_bytes / cpp);
 494         else
 495                 return min(max_horizontal_pixels * cpp, max_stride_bytes);
 496 }
 497
 498
 499 /* Preoffset values for YUV to RGB Conversion */
 500 #define PREOFF_YUV_TO_RGB_HI            0x1800
 501 #define PREOFF_YUV_TO_RGB_ME            0x0000
 502 #define PREOFF_YUV_TO_RGB_LO            0x1800
 503
 504 #define  ROFF(x)          (((x) & 0xffff) << 16)
 505 #define  GOFF(x)          (((x) & 0xffff) << 0)
 506 #define  BOFF(x)          (((x) & 0xffff) << 16)
 507
 508 /*
 509  * Programs the input color space conversion stage for ICL HDR planes.
 510  * Note that it is assumed that this stage always happens after YUV
 511  * range correction. Thus, the input to this stage is assumed to be
 512  * in full-range YCbCr.
 513  */
 514 static void
 515 icl_program_input_csc(struct intel_plane *plane,
 516                       const struct intel_crtc_state *crtc_state,
 517                       const struct intel_plane_state *plane_state)
 518 {
 519         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 520         enum pipe pipe = plane->pipe;
 521         enum plane_id plane_id = plane->id;
 522
 523         static const u16 input_csc_matrix[][9] = {
 524                 /*
 525                  * BT.601 full range YCbCr -> full range RGB
 526                  * The matrix required is :
 527                  * [1.000, 0.000, 1.371,
 528                  *  1.000, -0.336, -0.698,
 529                  *  1.000, 1.732, 0.0000]
 530                  */
 531                 [DRM_COLOR_YCBCR_BT601] = {
 532                         0x7AF8, 0x7800, 0x0,
 533                         0x8B28, 0x7800, 0x9AC0,
 534                         0x0, 0x7800, 0x7DD8,
 535                 },
 536                 /*
 537                  * BT.709 full range YCbCr -> full range RGB
 538                  * The matrix required is :
 539                  * [1.000, 0.000, 1.574,
 540                  *  1.000, -0.187, -0.468,
 541                  *  1.000, 1.855, 0.0000]
 542                  */
 543                 [DRM_COLOR_YCBCR_BT709] = {
 544                         0x7C98, 0x7800, 0x0,
 545                         0x9EF8, 0x7800, 0xAC00,
 546                         0x0, 0x7800,  0x7ED8,
 547                 },
 548                 /*
 549                  * BT.2020 full range YCbCr -> full range RGB
 550                  * The matrix required is :
 551                  * [1.000, 0.000, 1.474,
 552                  *  1.000, -0.1645, -0.5713,
 553                  *  1.000, 1.8814, 0.0000]
 554                  */
 555                 [DRM_COLOR_YCBCR_BT2020] = {
 556                         0x7BC8, 0x7800, 0x0,
 557                         0x8928, 0x7800, 0xAA88,
 558                         0x0, 0x7800, 0x7F10,
 559                 },
 560         };
 561         const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];
 562
 563         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
 564                           ROFF(csc[0]) | GOFF(csc[1]));
 565         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),
 566                           BOFF(csc[2]));
 567         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),
 568                           ROFF(csc[3]) | GOFF(csc[4]));
 569         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),
 570                           BOFF(csc[5]));
 571         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),
 572                           ROFF(csc[6]) | GOFF(csc[7]));
 573         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),
 574                           BOFF(csc[8]));
 575
 576         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
 577                           PREOFF_YUV_TO_RGB_HI);
 578         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
 579                           PREOFF_YUV_TO_RGB_ME);
 580         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
 581                           PREOFF_YUV_TO_RGB_LO);
 582         intel_de_write_fw(dev_priv,
 583                           PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
 584         intel_de_write_fw(dev_priv,
 585                           PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
 586         intel_de_write_fw(dev_priv,
 587                           PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
 588 }
 589
 590 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 591                                           int color_plane, unsigned int rotation)
 592 {
 593         /*
 594          * The stride is either expressed as a multiple of 64 bytes chunks for
 595          * linear buffers or in number of tiles for tiled buffers.
 596          */
 597         if (is_surface_linear(fb, color_plane))
 598                 return 64;
 599         else if (drm_rotation_90_or_270(rotation))
 600                 return intel_tile_height(fb, color_plane);
 601         else
 602                 return intel_tile_width_bytes(fb, color_plane);
 603 }
 604
 605 static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 606                             int color_plane)
 607 {
 608         const struct drm_framebuffer *fb = plane_state->hw.fb;
 609         unsigned int rotation = plane_state->hw.rotation;
 610         u32 stride = plane_state->view.color_plane[color_plane].scanout_stride;
 611
 612         if (color_plane >= fb->format->num_planes)
 613                 return 0;
 614
 615         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
 616 }
 617
 618 static void
 619 skl_plane_disable_arm(struct intel_plane *plane,
 620                       const struct intel_crtc_state *crtc_state)
 621 {
 622         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 623         enum plane_id plane_id = plane->id;
 624         enum pipe pipe = plane->pipe;
 625
 626         skl_write_plane_wm(plane, crtc_state);
 627
 628         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
 629         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
 630 }
 631
 632 static void
 633 icl_plane_disable_arm(struct intel_plane *plane,
 634                       const struct intel_crtc_state *crtc_state)
 635 {
 636         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 637         enum plane_id plane_id = plane->id;
 638         enum pipe pipe = plane->pipe;
 639
 640         if (icl_is_hdr_plane(dev_priv, plane_id))
 641                 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
 642
 643         skl_write_plane_wm(plane, crtc_state);
 644
 645         intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state);
 646         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
 647         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
 648 }
 649
 650 static bool
 651 skl_plane_get_hw_state(struct intel_plane *plane,
 652                        enum pipe *pipe)
 653 {
 654         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 655         enum intel_display_power_domain power_domain;
 656         enum plane_id plane_id = plane->id;
 657         intel_wakeref_t wakeref;
 658         bool ret;
 659
 660         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 661         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 662         if (!wakeref)
 663                 return false;
 664
 665         ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
 666
 667         *pipe = plane->pipe;
 668
 669         intel_display_power_put(dev_priv, power_domain, wakeref);
 670
 671         return ret;
 672 }
 673
 674 static u32 skl_plane_ctl_format(u32 pixel_format)
 675 {
 676         switch (pixel_format) {
 677         case DRM_FORMAT_C8:
 678                 return PLANE_CTL_FORMAT_INDEXED;
 679         case DRM_FORMAT_RGB565:
 680                 return PLANE_CTL_FORMAT_RGB_565;
 681         case DRM_FORMAT_XBGR8888:
 682         case DRM_FORMAT_ABGR8888:
 683                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
 684         case DRM_FORMAT_XRGB8888:
 685         case DRM_FORMAT_ARGB8888:
 686                 return PLANE_CTL_FORMAT_XRGB_8888;
 687         case DRM_FORMAT_XBGR2101010:
 688         case DRM_FORMAT_ABGR2101010:
 689                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
 690         case DRM_FORMAT_XRGB2101010:
 691         case DRM_FORMAT_ARGB2101010:
 692                 return PLANE_CTL_FORMAT_XRGB_2101010;
 693         case DRM_FORMAT_XBGR16161616F:
 694         case DRM_FORMAT_ABGR16161616F:
 695                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
 696         case DRM_FORMAT_XRGB16161616F:
 697         case DRM_FORMAT_ARGB16161616F:
 698                 return PLANE_CTL_FORMAT_XRGB_16161616F;
 699         case DRM_FORMAT_XYUV8888:
 700                 return PLANE_CTL_FORMAT_XYUV;
 701         case DRM_FORMAT_YUYV:
 702                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
 703         case DRM_FORMAT_YVYU:
 704                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
 705         case DRM_FORMAT_UYVY:
 706                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
 707         case DRM_FORMAT_VYUY:
 708                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
 709         case DRM_FORMAT_NV12:
 710                 return PLANE_CTL_FORMAT_NV12;
 711         case DRM_FORMAT_P010:
 712                 return PLANE_CTL_FORMAT_P010;
 713         case DRM_FORMAT_P012:
 714                 return PLANE_CTL_FORMAT_P012;
 715         case DRM_FORMAT_P016:
 716                 return PLANE_CTL_FORMAT_P016;
 717         case DRM_FORMAT_Y210:
 718                 return PLANE_CTL_FORMAT_Y210;
 719         case DRM_FORMAT_Y212:
 720                 return PLANE_CTL_FORMAT_Y212;
 721         case DRM_FORMAT_Y216:
 722                 return PLANE_CTL_FORMAT_Y216;
 723         case DRM_FORMAT_XVYU2101010:
 724                 return PLANE_CTL_FORMAT_Y410;
 725         case DRM_FORMAT_XVYU12_16161616:
 726                 return PLANE_CTL_FORMAT_Y412;
 727         case DRM_FORMAT_XVYU16161616:
 728                 return PLANE_CTL_FORMAT_Y416;
 729         default:
 730                 MISSING_CASE(pixel_format);
 731         }
 732
 733         return 0;
 734 }
 735
 736 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
 737 {
 738         if (!plane_state->hw.fb->format->has_alpha)
 739                 return PLANE_CTL_ALPHA_DISABLE;
 740
 741         switch (plane_state->hw.pixel_blend_mode) {
 742         case DRM_MODE_BLEND_PIXEL_NONE:
 743                 return PLANE_CTL_ALPHA_DISABLE;
 744         case DRM_MODE_BLEND_PREMULTI:
 745                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
 746         case DRM_MODE_BLEND_COVERAGE:
 747                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
 748         default:
 749                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
 750                 return PLANE_CTL_ALPHA_DISABLE;
 751         }
 752 }
 753
 754 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
 755 {
 756         if (!plane_state->hw.fb->format->has_alpha)
 757                 return PLANE_COLOR_ALPHA_DISABLE;
 758
 759         switch (plane_state->hw.pixel_blend_mode) {
 760         case DRM_MODE_BLEND_PIXEL_NONE:
 761                 return PLANE_COLOR_ALPHA_DISABLE;
 762         case DRM_MODE_BLEND_PREMULTI:
 763                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
 764         case DRM_MODE_BLEND_COVERAGE:
 765                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
 766         default:
 767                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
 768                 return PLANE_COLOR_ALPHA_DISABLE;
 769         }
 770 }
 771
 772 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 773 {
 774         switch (fb_modifier) {
 775         case DRM_FORMAT_MOD_LINEAR:
 776                 break;
 777         case I915_FORMAT_MOD_X_TILED:
 778                 return PLANE_CTL_TILED_X;
 779         case I915_FORMAT_MOD_Y_TILED:
 780                 return PLANE_CTL_TILED_Y;
 781         case I915_FORMAT_MOD_4_TILED:
 782                 return PLANE_CTL_TILED_4;
 783         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
 784                 return PLANE_CTL_TILED_4 |
 785                         PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 786                         PLANE_CTL_CLEAR_COLOR_DISABLE;
 787         case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 788                 return PLANE_CTL_TILED_4 |
 789                         PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
 790                         PLANE_CTL_CLEAR_COLOR_DISABLE;
 791         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 792                 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 793         case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
 794                 return PLANE_CTL_TILED_4 |
 795                         PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 796                         PLANE_CTL_CLEAR_COLOR_DISABLE;
 797         case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
 798                 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 799         case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
 800                 return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 801         case I915_FORMAT_MOD_Y_TILED_CCS:
 802         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 803                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 804         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 805                 return PLANE_CTL_TILED_Y |
 806                        PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 807                        PLANE_CTL_CLEAR_COLOR_DISABLE;
 808         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 809                 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 810         case I915_FORMAT_MOD_Yf_TILED:
 811                 return PLANE_CTL_TILED_YF;
 812         case I915_FORMAT_MOD_Yf_TILED_CCS:
 813                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 814         default:
 815                 MISSING_CASE(fb_modifier);
 816         }
 817
 818         return 0;
 819 }
 820
 821 static u32 skl_plane_ctl_rotate(unsigned int rotate)
 822 {
 823         switch (rotate) {
 824         case DRM_MODE_ROTATE_0:
 825                 break;
 826         /*
 827          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
 828          * while i915 HW rotation is clockwise, thats why this swapping.
 829          */
 830         case DRM_MODE_ROTATE_90:
 831                 return PLANE_CTL_ROTATE_270;
 832         case DRM_MODE_ROTATE_180:
 833                 return PLANE_CTL_ROTATE_180;
 834         case DRM_MODE_ROTATE_270:
 835                 return PLANE_CTL_ROTATE_90;
 836         default:
 837                 MISSING_CASE(rotate);
 838         }
 839
 840         return 0;
 841 }
 842
 843 static u32 icl_plane_ctl_flip(unsigned int reflect)
 844 {
 845         switch (reflect) {
 846         case 0:
 847                 break;
 848         case DRM_MODE_REFLECT_X:
 849                 return PLANE_CTL_FLIP_HORIZONTAL;
 850         case DRM_MODE_REFLECT_Y:
 851         default:
 852                 MISSING_CASE(reflect);
 853         }
 854
 855         return 0;
 856 }
 857
 858 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)
 859 {
 860         const struct drm_framebuffer *fb = plane_state->hw.fb;
 861
 862         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
 863                 switch (fb->format->cpp[0]) {
 864                 case 2:
 865                         return PLANE_CTL_ARB_SLOTS(1);
 866                 default:
 867                         return PLANE_CTL_ARB_SLOTS(0);
 868                 }
 869         } else {
 870                 switch (fb->format->cpp[0]) {
 871                 case 8:
 872                         return PLANE_CTL_ARB_SLOTS(3);
 873                 case 4:
 874                         return PLANE_CTL_ARB_SLOTS(1);
 875                 default:
 876                         return PLANE_CTL_ARB_SLOTS(0);
 877                 }
 878         }
 879 }
 880
 881 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 882 {
 883         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 884         u32 plane_ctl = 0;
 885
 886         if (DISPLAY_VER(dev_priv) >= 10)
 887                 return plane_ctl;
 888
 889         if (crtc_state->gamma_enable)
 890                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
 891
 892         if (crtc_state->csc_enable)
 893                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 894
 895         return plane_ctl;
 896 }
 897
 898 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 899                          const struct intel_plane_state *plane_state)
 900 {
 901         struct drm_i915_private *dev_priv =
 902                 to_i915(plane_state->uapi.plane->dev);
 903         const struct drm_framebuffer *fb = plane_state->hw.fb;
 904         unsigned int rotation = plane_state->hw.rotation;
 905         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 906         u32 plane_ctl;
 907
 908         plane_ctl = PLANE_CTL_ENABLE;
 909
 910         if (DISPLAY_VER(dev_priv) < 10) {
 911                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
 912                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
 913
 914                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
 915                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
 916
 917                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 918                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
 919         }
 920
 921         plane_ctl |= skl_plane_ctl_format(fb->format->format);
 922         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
 923         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
 924
 925         if (DISPLAY_VER(dev_priv) >= 11)
 926                 plane_ctl |= icl_plane_ctl_flip(rotation &
 927                                                 DRM_MODE_REFLECT_MASK);
 928
 929         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 930                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 931         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 932                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 933
 934         /* Wa_22012358565:adl-p */
 935         if (DISPLAY_VER(dev_priv) == 13)
 936                 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
 937
 938         return plane_ctl;
 939 }
 940
 941 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
 942 {
 943         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 944         u32 plane_color_ctl = 0;
 945
 946         if (DISPLAY_VER(dev_priv) >= 11)
 947                 return plane_color_ctl;
 948
 949         if (crtc_state->gamma_enable)
 950                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
 951
 952         if (crtc_state->csc_enable)
 953                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
 954
 955         return plane_color_ctl;
 956 }
 957
 958 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 959                                const struct intel_plane_state *plane_state)
 960 {
 961         struct drm_i915_private *dev_priv =
 962                 to_i915(plane_state->uapi.plane->dev);
 963         const struct drm_framebuffer *fb = plane_state->hw.fb;
 964         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 965         u32 plane_color_ctl = 0;
 966
 967         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
 968         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 969
 970         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
 971                 switch (plane_state->hw.color_encoding) {
 972                 case DRM_COLOR_YCBCR_BT709:
 973                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 974                         break;
 975                 case DRM_COLOR_YCBCR_BT2020:
 976                         plane_color_ctl |=
 977                                 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
 978                         break;
 979                 default:
 980                         plane_color_ctl |=
 981                                 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
 982                 }
 983                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 984                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
 985         } else if (fb->format->is_yuv) {
 986                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
 987                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 988                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
 989         }
 990
 991         if (plane_state->force_black)
 992                 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
 993
 994         return plane_color_ctl;
 995 }
 996
 997 static u32 skl_surf_address(const struct intel_plane_state *plane_state,
 998                             int color_plane)
 999 {
1000         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1001         const struct drm_framebuffer *fb = plane_state->hw.fb;
1002         u32 offset = plane_state->view.color_plane[color_plane].offset;
1003
1004         if (intel_fb_uses_dpt(fb)) {
1005                 /*
1006                  * The DPT object contains only one vma, so the VMA's offset
1007                  * within the DPT is always 0.
1008                  */
1009                 drm_WARN_ON(&i915->drm, plane_state->dpt_vma->node.start);
1010                 drm_WARN_ON(&i915->drm, offset & 0x1fffff);
1011                 return offset >> 9;
1012         } else {
1013                 drm_WARN_ON(&i915->drm, offset & 0xfff);
1014                 return offset;
1015         }
1016 }
1017
1018 static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
1019                           int color_plane)
1020 {
1021         u32 plane_surf;
1022
1023         plane_surf = intel_plane_ggtt_offset(plane_state) +
1024                 skl_surf_address(plane_state, color_plane);
1025
1026         if (plane_state->decrypt)
1027                 plane_surf |= PLANE_SURF_DECRYPT;
1028
1029         return plane_surf;
1030 }
1031
1032 static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
1033                               int color_plane)
1034 {
1035         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1036         const struct drm_framebuffer *fb = plane_state->hw.fb;
1037         int aux_plane = skl_main_to_aux_plane(fb, color_plane);
1038         u32 aux_dist;
1039
1040         if (!aux_plane)
1041                 return 0;
1042
1043         aux_dist = skl_surf_address(plane_state, aux_plane) -
1044                 skl_surf_address(plane_state, color_plane);
1045
1046         if (DISPLAY_VER(i915) < 12)
1047                 aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
1048
1049         return aux_dist;
1050 }
1051
1052 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
1053 {
1054         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1055
1056         return key->min_value;
1057 }
1058
1059 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
1060 {
1061         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1062         u8 alpha = plane_state->hw.alpha >> 8;
1063
1064         return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
1065 }
1066
1067 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
1068 {
1069         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1070         u8 alpha = plane_state->hw.alpha >> 8;
1071         u32 keymsk;
1072
1073         keymsk = key->channel_mask & 0x7ffffff;
1074         if (alpha < 0xff)
1075                 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
1076
1077         return keymsk;
1078 }
1079
1080 static void icl_plane_csc_load_black(struct intel_plane *plane)
1081 {
1082         struct drm_i915_private *i915 = to_i915(plane->base.dev);
1083         enum plane_id plane_id = plane->id;
1084         enum pipe pipe = plane->pipe;
1085
1086         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);
1087         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);
1088
1089         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);
1090         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);
1091
1092         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);
1093         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);
1094
1095         intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);
1096         intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);
1097         intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);
1098
1099         intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);
1100         intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);
1101         intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
1102 }
1103
1104 static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
1105 {
1106         /* Program the UV plane on planar master */
1107         if (plane_state->planar_linked_plane && !plane_state->planar_slave)
1108                 return 1;
1109         else
1110                 return 0;
1111 }
1112
1113 static void
1114 skl_plane_update_noarm(struct intel_plane *plane,
1115                        const struct intel_crtc_state *crtc_state,
1116                        const struct intel_plane_state *plane_state)
1117 {
1118         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1119         enum plane_id plane_id = plane->id;
1120         enum pipe pipe = plane->pipe;
1121         u32 stride = skl_plane_stride(plane_state, 0);
1122         int crtc_x = plane_state->uapi.dst.x1;
1123         int crtc_y = plane_state->uapi.dst.y1;
1124         u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1125         u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1126
1127         /* The scaler will handle the output position */
1128         if (plane_state->scaler_id >= 0) {
1129                 crtc_x = 0;
1130                 crtc_y = 0;
1131         }
1132
1133         intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
1134                           PLANE_STRIDE_(stride));
1135         intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
1136                           PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
1137         intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
1138                           PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
1139
1140         skl_write_plane_wm(plane, crtc_state);
1141 }
1142
1143 static void
1144 skl_plane_update_arm(struct intel_plane *plane,
1145                      const struct intel_crtc_state *crtc_state,
1146                      const struct intel_plane_state *plane_state)
1147 {
1148         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1149         enum plane_id plane_id = plane->id;
1150         enum pipe pipe = plane->pipe;
1151         u32 x = plane_state->view.color_plane[0].x;
1152         u32 y = plane_state->view.color_plane[0].y;
1153         u32 plane_ctl, plane_color_ctl = 0;
1154
1155         plane_ctl = plane_state->ctl |
1156                 skl_plane_ctl_crtc(crtc_state);
1157
1158         if (DISPLAY_VER(dev_priv) >= 10)
1159                 plane_color_ctl = plane_state->color_ctl |
1160                         glk_plane_color_ctl_crtc(crtc_state);
1161
1162         intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
1163         intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
1164         intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
1165
1166         intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
1167                           PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
1168
1169         intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
1170                           skl_plane_aux_dist(plane_state, 0));
1171
1172         intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
1173                           PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
1174                           PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
1175
1176         if (DISPLAY_VER(dev_priv) >= 10)
1177                 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
1178
1179         /*
1180          * Enable the scaler before the plane so that we don't
1181          * get a catastrophic underrun even if the two operations
1182          * end up happening in two different frames.
1183          *
1184          * TODO: split into noarm+arm pair
1185          */
1186         if (plane_state->scaler_id >= 0)
1187                 skl_program_plane_scaler(plane, crtc_state, plane_state);
1188
1189         /*
1190          * The control register self-arms if the plane was previously
1191          * disabled. Try to make the plane enable atomic by writing
1192          * the control register just before the surface register.
1193          */
1194         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1195         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1196                           skl_plane_surf(plane_state, 0));
1197 }
1198
1199 static void
1200 icl_plane_update_noarm(struct intel_plane *plane,
1201                        const struct intel_crtc_state *crtc_state,
1202                        const struct intel_plane_state *plane_state)
1203 {
1204         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1205         enum plane_id plane_id = plane->id;
1206         enum pipe pipe = plane->pipe;
1207         int color_plane = icl_plane_color_plane(plane_state);
1208         u32 stride = skl_plane_stride(plane_state, color_plane);
1209         const struct drm_framebuffer *fb = plane_state->hw.fb;
1210         int crtc_x = plane_state->uapi.dst.x1;
1211         int crtc_y = plane_state->uapi.dst.y1;
1212         int x = plane_state->view.color_plane[color_plane].x;
1213         int y = plane_state->view.color_plane[color_plane].y;
1214         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1215         int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1216         u32 plane_color_ctl;
1217
1218         plane_color_ctl = plane_state->color_ctl |
1219                 glk_plane_color_ctl_crtc(crtc_state);
1220
1221         /* The scaler will handle the output position */
1222         if (plane_state->scaler_id >= 0) {
1223                 crtc_x = 0;
1224                 crtc_y = 0;
1225         }
1226
1227         intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
1228                           PLANE_STRIDE_(stride));
1229         intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
1230                           PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
1231         intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
1232                           PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
1233
1234         intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
1235         intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
1236         intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
1237
1238         intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
1239                           PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
1240
1241         if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
1242                 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
1243                                   lower_32_bits(plane_state->ccval));
1244                 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1),
1245                                   upper_32_bits(plane_state->ccval));
1246         }
1247
1248         /* FLAT CCS doesn't need to program AUX_DIST */
1249         if (!HAS_FLAT_CCS(dev_priv))
1250                 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
1251                                   skl_plane_aux_dist(plane_state, color_plane));
1252
1253         if (icl_is_hdr_plane(dev_priv, plane_id))
1254                 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
1255                                   plane_state->cus_ctl);
1256
1257         intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
1258
1259         if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
1260                 icl_program_input_csc(plane, crtc_state, plane_state);
1261
1262         skl_write_plane_wm(plane, crtc_state);
1263
1264         /*
1265          * FIXME: pxp session invalidation can hit any time even at time of commit
1266          * or after the commit, display content will be garbage.
1267          */
1268         if (plane_state->force_black)
1269                 icl_plane_csc_load_black(plane);
1270
1271         intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane);
1272 }
1273
1274 static void
1275 icl_plane_update_arm(struct intel_plane *plane,
1276                      const struct intel_crtc_state *crtc_state,
1277                      const struct intel_plane_state *plane_state)
1278 {
1279         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1280         enum plane_id plane_id = plane->id;
1281         enum pipe pipe = plane->pipe;
1282         int color_plane = icl_plane_color_plane(plane_state);
1283         u32 plane_ctl;
1284
1285         plane_ctl = plane_state->ctl |
1286                 skl_plane_ctl_crtc(crtc_state);
1287
1288         /*
1289          * Enable the scaler before the plane so that we don't
1290          * get a catastrophic underrun even if the two operations
1291          * end up happening in two different frames.
1292          *
1293          * TODO: split into noarm+arm pair
1294          */
1295         if (plane_state->scaler_id >= 0)
1296                 skl_program_plane_scaler(plane, crtc_state, plane_state);
1297
1298         intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state, plane_state);
1299
1300         /*
1301          * The control register self-arms if the plane was previously
1302          * disabled. Try to make the plane enable atomic by writing
1303          * the control register just before the surface register.
1304          */
1305         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1306         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1307                           skl_plane_surf(plane_state, color_plane));
1308 }
1309
1310 static void
1311 skl_plane_async_flip(struct intel_plane *plane,
1312                      const struct intel_crtc_state *crtc_state,
1313                      const struct intel_plane_state *plane_state,
1314                      bool async_flip)
1315 {
1316         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1317         enum plane_id plane_id = plane->id;
1318         enum pipe pipe = plane->pipe;
1319         u32 plane_ctl = plane_state->ctl;
1320
1321         plane_ctl |= skl_plane_ctl_crtc(crtc_state);
1322
1323         if (async_flip)
1324                 plane_ctl |= PLANE_CTL_ASYNC_FLIP;
1325
1326         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1327         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1328                           skl_plane_surf(plane_state, 0));
1329 }
1330
1331 static bool intel_format_is_p01x(u32 format)
1332 {
1333         switch (format) {
1334         case DRM_FORMAT_P010:
1335         case DRM_FORMAT_P012:
1336         case DRM_FORMAT_P016:
1337                 return true;
1338         default:
1339                 return false;
1340         }
1341 }
1342
1343 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1344                               const struct intel_plane_state *plane_state)
1345 {
1346         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1347         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1348         const struct drm_framebuffer *fb = plane_state->hw.fb;
1349         unsigned int rotation = plane_state->hw.rotation;
1350
1351         if (!fb)
1352                 return 0;
1353
1354         if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1355             intel_fb_is_ccs_modifier(fb->modifier)) {
1356                 drm_dbg_kms(&dev_priv->drm,
1357                             "RC support only with 0/180 degree rotation (%x)\n",
1358                             rotation);
1359                 return -EINVAL;
1360         }
1361
1362         if (rotation & DRM_MODE_REFLECT_X &&
1363             fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1364                 drm_dbg_kms(&dev_priv->drm,
1365                             "horizontal flip is not supported with linear surface formats\n");
1366                 return -EINVAL;
1367         }
1368
1369         if (drm_rotation_90_or_270(rotation)) {
1370                 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) {
1371                         drm_dbg_kms(&dev_priv->drm,
1372                                     "Y/Yf tiling required for 90/270!\n");
1373                         return -EINVAL;
1374                 }
1375
1376                 /*
1377                  * 90/270 is not allowed with RGB64 16:16:16:16 and
1378                  * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
1379                  */
1380                 switch (fb->format->format) {
1381                 case DRM_FORMAT_RGB565:
1382                         if (DISPLAY_VER(dev_priv) >= 11)
1383                                 break;
1384                         fallthrough;
1385                 case DRM_FORMAT_C8:
1386                 case DRM_FORMAT_XRGB16161616F:
1387                 case DRM_FORMAT_XBGR16161616F:
1388                 case DRM_FORMAT_ARGB16161616F:
1389                 case DRM_FORMAT_ABGR16161616F:
1390                 case DRM_FORMAT_Y210:
1391                 case DRM_FORMAT_Y212:
1392                 case DRM_FORMAT_Y216:
1393                 case DRM_FORMAT_XVYU12_16161616:
1394                 case DRM_FORMAT_XVYU16161616:
1395                         drm_dbg_kms(&dev_priv->drm,
1396                                     "Unsupported pixel format %p4cc for 90/270!\n",
1397                                     &fb->format->format);
1398                         return -EINVAL;
1399                 default:
1400                         break;
1401                 }
1402         }
1403
1404         /* Y-tiling is not supported in IF-ID Interlace mode */
1405         if (crtc_state->hw.enable &&
1406             crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1407             fb->modifier != DRM_FORMAT_MOD_LINEAR &&
1408             fb->modifier != I915_FORMAT_MOD_X_TILED) {
1409                 drm_dbg_kms(&dev_priv->drm,
1410                             "Y/Yf tiling not supported in IF-ID mode\n");
1411                 return -EINVAL;
1412         }
1413
1414         /* Wa_1606054188:tgl,adl-s */
1415         if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
1416             plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
1417             intel_format_is_p01x(fb->format->format)) {
1418                 drm_dbg_kms(&dev_priv->drm,
1419                             "Source color keying not supported with P01x formats\n");
1420                 return -EINVAL;
1421         }
1422
1423         return 0;
1424 }
1425
1426 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1427                                            const struct intel_plane_state *plane_state)
1428 {
1429         struct drm_i915_private *dev_priv =
1430                 to_i915(plane_state->uapi.plane->dev);
1431         int crtc_x = plane_state->uapi.dst.x1;
1432         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
1433         int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
1434
1435         /*
1436          * Display WA #1175: glk
1437          * Planes other than the cursor may cause FIFO underflow and display
1438          * corruption if starting less than 4 pixels from the right edge of
1439          * the screen.
1440          * Besides the above WA fix the similar problem, where planes other
1441          * than the cursor ending less than 4 pixels from the left edge of the
1442          * screen may cause FIFO underflow and display corruption.
1443          */
1444         if (DISPLAY_VER(dev_priv) == 10 &&
1445             (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1446                 drm_dbg_kms(&dev_priv->drm,
1447                             "requested plane X %s position %d invalid (valid range %d-%d)\n",
1448                             crtc_x + crtc_w < 4 ? "end" : "start",
1449                             crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1450                             4, pipe_src_w - 4);
1451                 return -ERANGE;
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
1458 {
1459         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1460         const struct drm_framebuffer *fb = plane_state->hw.fb;
1461         unsigned int rotation = plane_state->hw.rotation;
1462         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1463
1464         /* Display WA #1106 */
1465         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1466             src_w & 3 &&
1467             (rotation == DRM_MODE_ROTATE_270 ||
1468              rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
1469                 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n");
1470                 return -EINVAL;
1471         }
1472
1473         return 0;
1474 }
1475
1476 static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
1477                                const struct drm_framebuffer *fb)
1478 {
1479         /*
1480          * We don't yet know the final source width nor
1481          * whether we can use the HQ scaler mode. Assume
1482          * the best case.
1483          * FIXME need to properly check this later.
1484          */
1485         if (DISPLAY_VER(dev_priv) >= 10 ||
1486             !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
1487                 return 0x30000 - 1;
1488         else
1489                 return 0x20000 - 1;
1490 }
1491
1492 static int intel_plane_min_width(struct intel_plane *plane,
1493                                  const struct drm_framebuffer *fb,
1494                                  int color_plane,
1495                                  unsigned int rotation)
1496 {
1497         if (plane->min_width)
1498                 return plane->min_width(fb, color_plane, rotation);
1499         else
1500                 return 1;
1501 }
1502
1503 static int intel_plane_max_width(struct intel_plane *plane,
1504                                  const struct drm_framebuffer *fb,
1505                                  int color_plane,
1506                                  unsigned int rotation)
1507 {
1508         if (plane->max_width)
1509                 return plane->max_width(fb, color_plane, rotation);
1510         else
1511                 return INT_MAX;
1512 }
1513
1514 static int intel_plane_max_height(struct intel_plane *plane,
1515                                   const struct drm_framebuffer *fb,
1516                                   int color_plane,
1517                                   unsigned int rotation)
1518 {
1519         if (plane->max_height)
1520                 return plane->max_height(fb, color_plane, rotation);
1521         else
1522                 return INT_MAX;
1523 }
1524
1525 static bool
1526 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
1527                                int main_x, int main_y, u32 main_offset,
1528                                int ccs_plane)
1529 {
1530         const struct drm_framebuffer *fb = plane_state->hw.fb;
1531         int aux_x = plane_state->view.color_plane[ccs_plane].x;
1532         int aux_y = plane_state->view.color_plane[ccs_plane].y;
1533         u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
1534         u32 alignment = intel_surf_alignment(fb, ccs_plane);
1535         int hsub;
1536         int vsub;
1537
1538         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1539         while (aux_offset >= main_offset && aux_y <= main_y) {
1540                 int x, y;
1541
1542                 if (aux_x == main_x && aux_y == main_y)
1543                         break;
1544
1545                 if (aux_offset == 0)
1546                         break;
1547
1548                 x = aux_x / hsub;
1549                 y = aux_y / vsub;
1550                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
1551                                                                plane_state,
1552                                                                ccs_plane,
1553                                                                aux_offset,
1554                                                                aux_offset -
1555                                                                 alignment);
1556                 aux_x = x * hsub + aux_x % hsub;
1557                 aux_y = y * vsub + aux_y % vsub;
1558         }
1559
1560         if (aux_x != main_x || aux_y != main_y)
1561                 return false;
1562
1563         plane_state->view.color_plane[ccs_plane].offset = aux_offset;
1564         plane_state->view.color_plane[ccs_plane].x = aux_x;
1565         plane_state->view.color_plane[ccs_plane].y = aux_y;
1566
1567         return true;
1568 }
1569
1570
1571 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
1572                                  int *x, int *y, u32 *offset)
1573 {
1574         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1575         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1576         const struct drm_framebuffer *fb = plane_state->hw.fb;
1577         const int aux_plane = skl_main_to_aux_plane(fb, 0);
1578         const u32 aux_offset = plane_state->view.color_plane[aux_plane].offset;
1579         const u32 alignment = intel_surf_alignment(fb, 0);
1580         const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1581
1582         intel_add_fb_offsets(x, y, plane_state, 0);
1583         *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
1584         if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
1585                 return -EINVAL;
1586
1587         /*
1588          * AUX surface offset is specified as the distance from the
1589          * main surface offset, and it must be non-negative. Make
1590          * sure that is what we will get.
1591          */
1592         if (aux_plane && *offset > aux_offset)
1593                 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1594                                                             *offset,
1595                                                             aux_offset & ~(alignment - 1));
1596
1597         /*
1598          * When using an X-tiled surface, the plane blows up
1599          * if the x offset + width exceed the stride.
1600          *
1601          * TODO: linear and Y-tiled seem fine, Yf untested,
1602          */
1603         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
1604                 int cpp = fb->format->cpp[0];
1605
1606                 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) {
1607                         if (*offset == 0) {
1608                                 drm_dbg_kms(&dev_priv->drm,
1609                                             "Unable to find suitable display surface offset due to X-tiling\n");
1610                                 return -EINVAL;
1611                         }
1612
1613                         *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1614                                                                     *offset,
1615                                                                     *offset - alignment);
1616                 }
1617         }
1618
1619         return 0;
1620 }
1621
1622 static int skl_check_main_surface(struct intel_plane_state *plane_state)
1623 {
1624         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1625         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1626         const struct drm_framebuffer *fb = plane_state->hw.fb;
1627         const unsigned int rotation = plane_state->hw.rotation;
1628         int x = plane_state->uapi.src.x1 >> 16;
1629         int y = plane_state->uapi.src.y1 >> 16;
1630         const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1631         const int h = drm_rect_height(&plane_state->uapi.src) >> 16;
1632         const int min_width = intel_plane_min_width(plane, fb, 0, rotation);
1633         const int max_width = intel_plane_max_width(plane, fb, 0, rotation);
1634         const int max_height = intel_plane_max_height(plane, fb, 0, rotation);
1635         const int aux_plane = skl_main_to_aux_plane(fb, 0);
1636         const u32 alignment = intel_surf_alignment(fb, 0);
1637         u32 offset;
1638         int ret;
1639
1640         if (w > max_width || w < min_width || h > max_height || h < 1) {
1641                 drm_dbg_kms(&dev_priv->drm,
1642                             "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
1643                             w, h, min_width, max_width, max_height);
1644                 return -EINVAL;
1645         }
1646
1647         ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
1648         if (ret)
1649                 return ret;
1650
1651         /*
1652          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
1653          * they match with the main surface x/y offsets. On DG2
1654          * there's no aux plane on fb so skip this checking.
1655          */
1656         if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) {
1657                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
1658                                                        offset, aux_plane)) {
1659                         if (offset == 0)
1660                                 break;
1661
1662                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
1663                                                                    offset, offset - alignment);
1664                 }
1665
1666                 if (x != plane_state->view.color_plane[aux_plane].x ||
1667                     y != plane_state->view.color_plane[aux_plane].y) {
1668                         drm_dbg_kms(&dev_priv->drm,
1669                                     "Unable to find suitable display surface offset due to CCS\n");
1670                         return -EINVAL;
1671                 }
1672         }
1673
1674         if (DISPLAY_VER(dev_priv) >= 13)
1675                 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535);
1676         else
1677                 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
1678
1679         plane_state->view.color_plane[0].offset = offset;
1680         plane_state->view.color_plane[0].x = x;
1681         plane_state->view.color_plane[0].y = y;
1682
1683         /*
1684          * Put the final coordinates back so that the src
1685          * coordinate checks will see the right values.
1686          */
1687         drm_rect_translate_to(&plane_state->uapi.src,
1688                               x << 16, y << 16);
1689
1690         return 0;
1691 }
1692
1693 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
1694 {
1695         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1696         struct drm_i915_private *i915 = to_i915(plane->base.dev);
1697         const struct drm_framebuffer *fb = plane_state->hw.fb;
1698         unsigned int rotation = plane_state->hw.rotation;
1699         int uv_plane = 1;
1700         int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ?
1701                         skl_main_to_aux_plane(fb, uv_plane) : 0;
1702         int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
1703         int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
1704         int x = plane_state->uapi.src.x1 >> 17;
1705         int y = plane_state->uapi.src.y1 >> 17;
1706         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
1707         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
1708         u32 offset;
1709
1710         /* FIXME not quite sure how/if these apply to the chroma plane */
1711         if (w > max_width || h > max_height) {
1712                 drm_dbg_kms(&i915->drm,
1713                             "CbCr source size %dx%d too big (limit %dx%d)\n",
1714                             w, h, max_width, max_height);
1715                 return -EINVAL;
1716         }
1717
1718         intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
1719         offset = intel_plane_compute_aligned_offset(&x, &y,
1720                                                     plane_state, uv_plane);
1721
1722         if (ccs_plane) {
1723                 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
1724                 u32 alignment = intel_surf_alignment(fb, uv_plane);
1725
1726                 if (offset > aux_offset)
1727                         offset = intel_plane_adjust_aligned_offset(&x, &y,
1728                                                                    plane_state,
1729                                                                    uv_plane,
1730                                                                    offset,
1731                                                                    aux_offset & ~(alignment - 1));
1732
1733                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
1734                                                        offset, ccs_plane)) {
1735                         if (offset == 0)
1736                                 break;
1737
1738                         offset = intel_plane_adjust_aligned_offset(&x, &y,
1739                                                                    plane_state,
1740                                                                    uv_plane,
1741                                                                    offset, offset - alignment);
1742                 }
1743
1744                 if (x != plane_state->view.color_plane[ccs_plane].x ||
1745                     y != plane_state->view.color_plane[ccs_plane].y) {
1746                         drm_dbg_kms(&i915->drm,
1747                                     "Unable to find suitable display surface offset due to CCS\n");
1748                         return -EINVAL;
1749                 }
1750         }
1751
1752         if (DISPLAY_VER(i915) >= 13)
1753                 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535);
1754         else
1755                 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
1756
1757         plane_state->view.color_plane[uv_plane].offset = offset;
1758         plane_state->view.color_plane[uv_plane].x = x;
1759         plane_state->view.color_plane[uv_plane].y = y;
1760
1761         return 0;
1762 }
1763
1764 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
1765 {
1766         const struct drm_framebuffer *fb = plane_state->hw.fb;
1767         int src_x = plane_state->uapi.src.x1 >> 16;
1768         int src_y = plane_state->uapi.src.y1 >> 16;
1769         u32 offset;
1770         int ccs_plane;
1771
1772         for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
1773                 int main_hsub, main_vsub;
1774                 int hsub, vsub;
1775                 int x, y;
1776
1777                 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))
1778                         continue;
1779
1780                 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
1781                                                skl_ccs_to_main_plane(fb, ccs_plane));
1782                 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1783
1784                 hsub *= main_hsub;
1785                 vsub *= main_vsub;
1786                 x = src_x / hsub;
1787                 y = src_y / vsub;
1788
1789                 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
1790
1791                 offset = intel_plane_compute_aligned_offset(&x, &y,
1792                                                             plane_state,
1793                                                             ccs_plane);
1794
1795                 plane_state->view.color_plane[ccs_plane].offset = offset;
1796                 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub;
1797                 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub;
1798         }
1799
1800         return 0;
1801 }
1802
1803 static int skl_check_plane_surface(struct intel_plane_state *plane_state)
1804 {
1805         const struct drm_framebuffer *fb = plane_state->hw.fb;
1806         int ret;
1807
1808         ret = intel_plane_compute_gtt(plane_state);
1809         if (ret)
1810                 return ret;
1811
1812         if (!plane_state->uapi.visible)
1813                 return 0;
1814
1815         /*
1816          * Handle the AUX surface first since the main surface setup depends on
1817          * it.
1818          */
1819         if (intel_fb_is_ccs_modifier(fb->modifier)) {
1820                 ret = skl_check_ccs_aux_surface(plane_state);
1821                 if (ret)
1822                         return ret;
1823         }
1824
1825         if (intel_format_info_is_yuv_semiplanar(fb->format,
1826                                                 fb->modifier)) {
1827                 ret = skl_check_nv12_aux_surface(plane_state);
1828                 if (ret)
1829                         return ret;
1830         }
1831
1832         ret = skl_check_main_surface(plane_state);
1833         if (ret)
1834                 return ret;
1835
1836         return 0;
1837 }
1838
1839 static bool skl_fb_scalable(const struct drm_framebuffer *fb)
1840 {
1841         if (!fb)
1842                 return false;
1843
1844         switch (fb->format->format) {
1845         case DRM_FORMAT_C8:
1846                 return false;
1847         case DRM_FORMAT_XRGB16161616F:
1848         case DRM_FORMAT_ARGB16161616F:
1849         case DRM_FORMAT_XBGR16161616F:
1850         case DRM_FORMAT_ABGR16161616F:
1851                 return DISPLAY_VER(to_i915(fb->dev)) >= 11;
1852         default:
1853                 return true;
1854         }
1855 }
1856
1857 static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj)
1858 {
1859         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1860
1861         return intel_pxp_key_check(i915->pxp, obj, false) == 0;
1862 }
1863
1864 static bool pxp_is_borked(struct drm_i915_gem_object *obj)
1865 {
1866         return i915_gem_object_is_protected(obj) && !bo_has_valid_encryption(obj);
1867 }
1868
1869 static int skl_plane_check(struct intel_crtc_state *crtc_state,
1870                            struct intel_plane_state *plane_state)
1871 {
1872         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1873         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1874         const struct drm_framebuffer *fb = plane_state->hw.fb;
1875         int min_scale = DRM_PLANE_NO_SCALING;
1876         int max_scale = DRM_PLANE_NO_SCALING;
1877         int ret;
1878
1879         ret = skl_plane_check_fb(crtc_state, plane_state);
1880         if (ret)
1881                 return ret;
1882
1883         /* use scaler when colorkey is not required */
1884         if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
1885                 min_scale = 1;
1886                 max_scale = skl_plane_max_scale(dev_priv, fb);
1887         }
1888
1889         ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
1890                                                 min_scale, max_scale, true);
1891         if (ret)
1892                 return ret;
1893
1894         ret = skl_check_plane_surface(plane_state);
1895         if (ret)
1896                 return ret;
1897
1898         if (!plane_state->uapi.visible)
1899                 return 0;
1900
1901         ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1902         if (ret)
1903                 return ret;
1904
1905         ret = intel_plane_check_src_coordinates(plane_state);
1906         if (ret)
1907                 return ret;
1908
1909         ret = skl_plane_check_nv12_rotation(plane_state);
1910         if (ret)
1911                 return ret;
1912
1913         if (DISPLAY_VER(dev_priv) >= 11) {
1914                 plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb));
1915                 plane_state->force_black = pxp_is_borked(intel_fb_obj(fb));
1916         }
1917
1918         /* HW only has 8 bits pixel precision, disable plane if invisible */
1919         if (!(plane_state->hw.alpha >> 8))
1920                 plane_state->uapi.visible = false;
1921
1922         plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1923
1924         if (DISPLAY_VER(dev_priv) >= 10)
1925                 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1926                                                              plane_state);
1927
1928         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1929             icl_is_hdr_plane(dev_priv, plane->id))
1930                 /* Enable and use MPEG-2 chroma siting */
1931                 plane_state->cus_ctl = PLANE_CUS_ENABLE |
1932                         PLANE_CUS_HPHASE_0 |
1933                         PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
1934         else
1935                 plane_state->cus_ctl = 0;
1936
1937         return 0;
1938 }
1939
1940 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
1941 {
1942         return pipe - PIPE_A + INTEL_FBC_A;
1943 }
1944
1945 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
1946                               enum intel_fbc_id fbc_id, enum plane_id plane_id)
1947 {
1948         if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
1949                 return false;
1950
1951         return plane_id == PLANE_PRIMARY;
1952 }
1953
1954 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
1955                                        enum pipe pipe, enum plane_id plane_id)
1956 {
1957         enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
1958
1959         if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
1960                 return dev_priv->display.fbc[fbc_id];
1961         else
1962                 return NULL;
1963 }
1964
1965 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
1966                                  enum pipe pipe, enum plane_id plane_id)
1967 {
1968         /* Display WA #0870: skl, bxt */
1969         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
1970                 return false;
1971
1972         if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
1973                 return false;
1974
1975         if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
1976                 return false;
1977
1978         return true;
1979 }
1980
1981 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv,
1982                                         enum pipe pipe, enum plane_id plane_id,
1983                                         int *num_formats)
1984 {
1985         if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
1986                 *num_formats = ARRAY_SIZE(skl_planar_formats);
1987                 return skl_planar_formats;
1988         } else {
1989                 *num_formats = ARRAY_SIZE(skl_plane_formats);
1990                 return skl_plane_formats;
1991         }
1992 }
1993
1994 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv,
1995                                         enum pipe pipe, enum plane_id plane_id,
1996                                         int *num_formats)
1997 {
1998         if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
1999                 *num_formats = ARRAY_SIZE(glk_planar_formats);
2000                 return glk_planar_formats;
2001         } else {
2002                 *num_formats = ARRAY_SIZE(skl_plane_formats);
2003                 return skl_plane_formats;
2004         }
2005 }
2006
2007 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
2008                                         enum pipe pipe, enum plane_id plane_id,
2009                                         int *num_formats)
2010 {
2011         if (icl_is_hdr_plane(dev_priv, plane_id)) {
2012                 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
2013                 return icl_hdr_plane_formats;
2014         } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
2015                 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
2016                 return icl_sdr_y_plane_formats;
2017         } else {
2018                 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats);
2019                 return icl_sdr_uv_plane_formats;
2020         }
2021 }
2022
2023 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
2024                                            u32 format, u64 modifier)
2025 {
2026         struct intel_plane *plane = to_intel_plane(_plane);
2027
2028         if (!intel_fb_plane_supports_modifier(plane, modifier))
2029                 return false;
2030
2031         switch (format) {
2032         case DRM_FORMAT_XRGB8888:
2033         case DRM_FORMAT_XBGR8888:
2034         case DRM_FORMAT_ARGB8888:
2035         case DRM_FORMAT_ABGR8888:
2036                 if (intel_fb_is_ccs_modifier(modifier))
2037                         return true;
2038                 fallthrough;
2039         case DRM_FORMAT_RGB565:
2040         case DRM_FORMAT_XRGB2101010:
2041         case DRM_FORMAT_XBGR2101010:
2042         case DRM_FORMAT_ARGB2101010:
2043         case DRM_FORMAT_ABGR2101010:
2044         case DRM_FORMAT_YUYV:
2045         case DRM_FORMAT_YVYU:
2046         case DRM_FORMAT_UYVY:
2047         case DRM_FORMAT_VYUY:
2048         case DRM_FORMAT_NV12:
2049         case DRM_FORMAT_XYUV8888:
2050         case DRM_FORMAT_P010:
2051         case DRM_FORMAT_P012:
2052         case DRM_FORMAT_P016:
2053         case DRM_FORMAT_XVYU2101010:
2054                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
2055                         return true;
2056                 fallthrough;
2057         case DRM_FORMAT_C8:
2058         case DRM_FORMAT_XBGR16161616F:
2059         case DRM_FORMAT_ABGR16161616F:
2060         case DRM_FORMAT_XRGB16161616F:
2061         case DRM_FORMAT_ARGB16161616F:
2062         case DRM_FORMAT_Y210:
2063         case DRM_FORMAT_Y212:
2064         case DRM_FORMAT_Y216:
2065         case DRM_FORMAT_XVYU12_16161616:
2066         case DRM_FORMAT_XVYU16161616:
2067                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2068                     modifier == I915_FORMAT_MOD_X_TILED ||
2069                     modifier == I915_FORMAT_MOD_Y_TILED)
2070                         return true;
2071                 fallthrough;
2072         default:
2073                 return false;
2074         }
2075 }
2076
2077 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
2078                                              u32 format, u64 modifier)
2079 {
2080         struct intel_plane *plane = to_intel_plane(_plane);
2081
2082         if (!intel_fb_plane_supports_modifier(plane, modifier))
2083                 return false;
2084
2085         switch (format) {
2086         case DRM_FORMAT_XRGB8888:
2087         case DRM_FORMAT_XBGR8888:
2088         case DRM_FORMAT_ARGB8888:
2089         case DRM_FORMAT_ABGR8888:
2090                 if (intel_fb_is_ccs_modifier(modifier))
2091                         return true;
2092                 fallthrough;
2093         case DRM_FORMAT_YUYV:
2094         case DRM_FORMAT_YVYU:
2095         case DRM_FORMAT_UYVY:
2096         case DRM_FORMAT_VYUY:
2097         case DRM_FORMAT_NV12:
2098         case DRM_FORMAT_XYUV8888:
2099         case DRM_FORMAT_P010:
2100         case DRM_FORMAT_P012:
2101         case DRM_FORMAT_P016:
2102                 if (intel_fb_is_mc_ccs_modifier(modifier))
2103                         return true;
2104                 fallthrough;
2105         case DRM_FORMAT_RGB565:
2106         case DRM_FORMAT_XRGB2101010:
2107         case DRM_FORMAT_XBGR2101010:
2108         case DRM_FORMAT_ARGB2101010:
2109         case DRM_FORMAT_ABGR2101010:
2110         case DRM_FORMAT_XVYU2101010:
2111         case DRM_FORMAT_C8:
2112         case DRM_FORMAT_XBGR16161616F:
2113         case DRM_FORMAT_ABGR16161616F:
2114         case DRM_FORMAT_XRGB16161616F:
2115         case DRM_FORMAT_ARGB16161616F:
2116         case DRM_FORMAT_Y210:
2117         case DRM_FORMAT_Y212:
2118         case DRM_FORMAT_Y216:
2119         case DRM_FORMAT_XVYU12_16161616:
2120         case DRM_FORMAT_XVYU16161616:
2121                 if (!intel_fb_is_ccs_modifier(modifier))
2122                         return true;
2123                 fallthrough;
2124         default:
2125                 return false;
2126         }
2127 }
2128
2129 static const struct drm_plane_funcs skl_plane_funcs = {
2130         .update_plane = drm_atomic_helper_update_plane,
2131         .disable_plane = drm_atomic_helper_disable_plane,
2132         .destroy = intel_plane_destroy,
2133         .atomic_duplicate_state = intel_plane_duplicate_state,
2134         .atomic_destroy_state = intel_plane_destroy_state,
2135         .format_mod_supported = skl_plane_format_mod_supported,
2136 };
2137
2138 static const struct drm_plane_funcs gen12_plane_funcs = {
2139         .update_plane = drm_atomic_helper_update_plane,
2140         .disable_plane = drm_atomic_helper_disable_plane,
2141         .destroy = intel_plane_destroy,
2142         .atomic_duplicate_state = intel_plane_duplicate_state,
2143         .atomic_destroy_state = intel_plane_destroy_state,
2144         .format_mod_supported = gen12_plane_format_mod_supported,
2145 };
2146
2147 static void
2148 skl_plane_enable_flip_done(struct intel_plane *plane)
2149 {
2150         struct drm_i915_private *i915 = to_i915(plane->base.dev);
2151         enum pipe pipe = plane->pipe;
2152
2153         spin_lock_irq(&i915->irq_lock);
2154         bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2155         spin_unlock_irq(&i915->irq_lock);
2156 }
2157
2158 static void
2159 skl_plane_disable_flip_done(struct intel_plane *plane)
2160 {
2161         struct drm_i915_private *i915 = to_i915(plane->base.dev);
2162         enum pipe pipe = plane->pipe;
2163
2164         spin_lock_irq(&i915->irq_lock);
2165         bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2166         spin_unlock_irq(&i915->irq_lock);
2167 }
2168
2169 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
2170                                  enum pipe pipe, enum plane_id plane_id)
2171 {
2172         /* Wa_22011186057 */
2173         if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2174                 return false;
2175
2176         if (DISPLAY_VER(i915) >= 11)
2177                 return true;
2178
2179         if (IS_GEMINILAKE(i915))
2180                 return pipe != PIPE_C;
2181
2182         return pipe != PIPE_C &&
2183                 (plane_id == PLANE_PRIMARY ||
2184                  plane_id == PLANE_SPRITE0);
2185 }
2186
2187 static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
2188                                    enum plane_id plane_id)
2189 {
2190         if (DISPLAY_VER(i915) < 12)
2191                 return false;
2192
2193         /* Wa_14010477008 */
2194         if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
2195                 (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
2196                 return false;
2197
2198         /* Wa_22011186057 */
2199         if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2200                 return false;
2201
2202         /* Wa_14013215631 */
2203         if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
2204                 return false;
2205
2206         return plane_id < PLANE_SPRITE4;
2207 }
2208
2209 static u8 skl_get_plane_caps(struct drm_i915_private *i915,
2210                              enum pipe pipe, enum plane_id plane_id)
2211 {
2212         u8 caps = INTEL_PLANE_CAP_TILING_X;
2213
2214         if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915))
2215                 caps |= INTEL_PLANE_CAP_TILING_Y;
2216         if (DISPLAY_VER(i915) < 12)
2217                 caps |= INTEL_PLANE_CAP_TILING_Yf;
2218         if (HAS_4TILE(i915))
2219                 caps |= INTEL_PLANE_CAP_TILING_4;
2220
2221         if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
2222                 caps |= INTEL_PLANE_CAP_CCS_RC;
2223                 if (DISPLAY_VER(i915) >= 12)
2224                         caps |= INTEL_PLANE_CAP_CCS_RC_CC;
2225         }
2226
2227         if (gen12_plane_has_mc_ccs(i915, plane_id))
2228                 caps |= INTEL_PLANE_CAP_CCS_MC;
2229
2230         return caps;
2231 }
2232
2233 struct intel_plane *
2234 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2235                            enum pipe pipe, enum plane_id plane_id)
2236 {
2237         const struct drm_plane_funcs *plane_funcs;
2238         struct intel_plane *plane;
2239         enum drm_plane_type plane_type;
2240         unsigned int supported_rotations;
2241         unsigned int supported_csc;
2242         const u64 *modifiers;
2243         const u32 *formats;
2244         int num_formats;
2245         int ret;
2246
2247         plane = intel_plane_alloc();
2248         if (IS_ERR(plane))
2249                 return plane;
2250
2251         plane->pipe = pipe;
2252         plane->id = plane_id;
2253         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
2254
2255         intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane);
2256
2257         if (DISPLAY_VER(dev_priv) >= 11) {
2258                 plane->min_width = icl_plane_min_width;
2259                 if (icl_is_hdr_plane(dev_priv, plane_id))
2260                         plane->max_width = icl_hdr_plane_max_width;
2261                 else
2262                         plane->max_width = icl_sdr_plane_max_width;
2263                 plane->max_height = icl_plane_max_height;
2264                 plane->min_cdclk = icl_plane_min_cdclk;
2265         } else if (DISPLAY_VER(dev_priv) >= 10) {
2266                 plane->max_width = glk_plane_max_width;
2267                 plane->max_height = skl_plane_max_height;
2268                 plane->min_cdclk = glk_plane_min_cdclk;
2269         } else {
2270                 plane->max_width = skl_plane_max_width;
2271                 plane->max_height = skl_plane_max_height;
2272                 plane->min_cdclk = skl_plane_min_cdclk;
2273         }
2274
2275         plane->max_stride = skl_plane_max_stride;
2276         if (DISPLAY_VER(dev_priv) >= 11) {
2277                 plane->update_noarm = icl_plane_update_noarm;
2278                 plane->update_arm = icl_plane_update_arm;
2279                 plane->disable_arm = icl_plane_disable_arm;
2280         } else {
2281                 plane->update_noarm = skl_plane_update_noarm;
2282                 plane->update_arm = skl_plane_update_arm;
2283                 plane->disable_arm = skl_plane_disable_arm;
2284         }
2285         plane->get_hw_state = skl_plane_get_hw_state;
2286         plane->check_plane = skl_plane_check;
2287
2288         if (plane_id == PLANE_PRIMARY) {
2289                 plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv,
2290                                                                    9, 10);
2291                 plane->async_flip = skl_plane_async_flip;
2292                 plane->enable_flip_done = skl_plane_enable_flip_done;
2293                 plane->disable_flip_done = skl_plane_disable_flip_done;
2294         }
2295
2296         if (DISPLAY_VER(dev_priv) >= 11)
2297                 formats = icl_get_plane_formats(dev_priv, pipe,
2298                                                 plane_id, &num_formats);
2299         else if (DISPLAY_VER(dev_priv) >= 10)
2300                 formats = glk_get_plane_formats(dev_priv, pipe,
2301                                                 plane_id, &num_formats);
2302         else
2303                 formats = skl_get_plane_formats(dev_priv, pipe,
2304                                                 plane_id, &num_formats);
2305
2306         if (DISPLAY_VER(dev_priv) >= 12)
2307                 plane_funcs = &gen12_plane_funcs;
2308         else
2309                 plane_funcs = &skl_plane_funcs;
2310
2311         if (plane_id == PLANE_PRIMARY)
2312                 plane_type = DRM_PLANE_TYPE_PRIMARY;
2313         else
2314                 plane_type = DRM_PLANE_TYPE_OVERLAY;
2315
2316         modifiers = intel_fb_plane_get_modifiers(dev_priv,
2317                                                  skl_get_plane_caps(dev_priv, pipe, plane_id));
2318
2319         ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2320                                        0, plane_funcs,
2321                                        formats, num_formats, modifiers,
2322                                        plane_type,
2323                                        "plane %d%c", plane_id + 1,
2324                                        pipe_name(pipe));
2325
2326         kfree(modifiers);
2327
2328         if (ret)
2329                 goto fail;
2330
2331         if (DISPLAY_VER(dev_priv) >= 13)
2332                 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
2333         else
2334                 supported_rotations =
2335                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
2336                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
2337
2338         if (DISPLAY_VER(dev_priv) >= 11)
2339                 supported_rotations |= DRM_MODE_REFLECT_X;
2340
2341         drm_plane_create_rotation_property(&plane->base,
2342                                            DRM_MODE_ROTATE_0,
2343                                            supported_rotations);
2344
2345         supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
2346
2347         if (DISPLAY_VER(dev_priv) >= 10)
2348                 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
2349
2350         drm_plane_create_color_properties(&plane->base,
2351                                           supported_csc,
2352                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2353                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2354                                           DRM_COLOR_YCBCR_BT709,
2355                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
2356
2357         drm_plane_create_alpha_property(&plane->base);
2358         drm_plane_create_blend_mode_property(&plane->base,
2359                                              BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2360                                              BIT(DRM_MODE_BLEND_PREMULTI) |
2361                                              BIT(DRM_MODE_BLEND_COVERAGE));
2362
2363         drm_plane_create_zpos_immutable_property(&plane->base, plane_id);
2364
2365         if (DISPLAY_VER(dev_priv) >= 12)
2366                 drm_plane_enable_fb_damage_clips(&plane->base);
2367
2368         if (DISPLAY_VER(dev_priv) >= 11)
2369                 drm_plane_create_scaling_filter_property(&plane->base,
2370                                                 BIT(DRM_SCALING_FILTER_DEFAULT) |
2371                                                 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
2372
2373         intel_plane_helper_add(plane);
2374
2375         return plane;
2376
2377 fail:
2378         intel_plane_free(plane);
2379
2380         return ERR_PTR(ret);
2381 }
2382
2383 void
2384 skl_get_initial_plane_config(struct intel_crtc *crtc,
2385                              struct intel_initial_plane_config *plane_config)
2386 {
2387         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
2388         struct drm_device *dev = crtc->base.dev;
2389         struct drm_i915_private *dev_priv = to_i915(dev);
2390         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2391         enum plane_id plane_id = plane->id;
2392         enum pipe pipe;
2393         u32 val, base, offset, stride_mult, tiling, alpha;
2394         int fourcc, pixel_format;
2395         unsigned int aligned_height;
2396         struct drm_framebuffer *fb;
2397         struct intel_framebuffer *intel_fb;
2398         static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4);
2399
2400         if (!plane->get_hw_state(plane, &pipe))
2401                 return;
2402
2403         drm_WARN_ON(dev, pipe != crtc->pipe);
2404
2405         if (crtc_state->bigjoiner_pipes) {
2406                 drm_dbg_kms(&dev_priv->drm,
2407                             "Unsupported bigjoiner configuration for initial FB\n");
2408                 return;
2409         }
2410
2411         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2412         if (!intel_fb) {
2413                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
2414                 return;
2415         }
2416
2417         fb = &intel_fb->base;
2418
2419         fb->dev = dev;
2420
2421         val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
2422
2423         if (DISPLAY_VER(dev_priv) >= 11)
2424                 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
2425         else
2426                 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
2427
2428         if (DISPLAY_VER(dev_priv) >= 10) {
2429                 u32 color_ctl;
2430
2431                 color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
2432                 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
2433         } else {
2434                 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
2435         }
2436
2437         fourcc = skl_format_to_fourcc(pixel_format,
2438                                       val & PLANE_CTL_ORDER_RGBX, alpha);
2439         fb->format = drm_format_info(fourcc);
2440
2441         tiling = val & PLANE_CTL_TILED_MASK;
2442         switch (tiling) {
2443         case PLANE_CTL_TILED_LINEAR:
2444                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
2445                 break;
2446         case PLANE_CTL_TILED_X:
2447                 plane_config->tiling = I915_TILING_X;
2448                 fb->modifier = I915_FORMAT_MOD_X_TILED;
2449                 break;
2450         case PLANE_CTL_TILED_Y:
2451                 plane_config->tiling = I915_TILING_Y;
2452                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2453                         if (DISPLAY_VER(dev_priv) >= 14)
2454                                 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS;
2455                         else if (DISPLAY_VER(dev_priv) >= 12)
2456                                 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
2457                         else
2458                                 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
2459                 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
2460                         if (DISPLAY_VER(dev_priv) >= 14)
2461                                 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS;
2462                         else
2463                                 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
2464                 else
2465                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
2466                 break;
2467         case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
2468                 if (HAS_4TILE(dev_priv)) {
2469                         u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
2470                                       PLANE_CTL_CLEAR_COLOR_DISABLE;
2471
2472                         if ((val & rc_mask) == rc_mask)
2473                                 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
2474                         else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
2475                                 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
2476                         else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2477                                 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
2478                         else
2479                                 fb->modifier = I915_FORMAT_MOD_4_TILED;
2480                 } else {
2481                         if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2482                                 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
2483                         else
2484                                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
2485                 }
2486                 break;
2487         default:
2488                 MISSING_CASE(tiling);
2489                 goto error;
2490         }
2491
2492         if (!dev_priv->params.enable_dpt &&
2493             intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) {
2494                 drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n");
2495                 goto error;
2496         }
2497
2498         /*
2499          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
2500          * while i915 HW rotation is clockwise, thats why this swapping.
2501          */
2502         switch (val & PLANE_CTL_ROTATE_MASK) {
2503         case PLANE_CTL_ROTATE_0:
2504                 plane_config->rotation = DRM_MODE_ROTATE_0;
2505                 break;
2506         case PLANE_CTL_ROTATE_90:
2507                 plane_config->rotation = DRM_MODE_ROTATE_270;
2508                 break;
2509         case PLANE_CTL_ROTATE_180:
2510                 plane_config->rotation = DRM_MODE_ROTATE_180;
2511                 break;
2512         case PLANE_CTL_ROTATE_270:
2513                 plane_config->rotation = DRM_MODE_ROTATE_90;
2514                 break;
2515         }
2516
2517         if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
2518                 plane_config->rotation |= DRM_MODE_REFLECT_X;
2519
2520         /* 90/270 degree rotation would require extra work */
2521         if (drm_rotation_90_or_270(plane_config->rotation))
2522                 goto error;
2523
2524         base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
2525         plane_config->base = base;
2526
2527         offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
2528         drm_WARN_ON(&dev_priv->drm, offset != 0);
2529
2530         val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
2531         fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
2532         fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
2533
2534         val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
2535         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
2536
2537         fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
2538
2539         aligned_height = intel_fb_align_height(fb, 0, fb->height);
2540
2541         plane_config->size = fb->pitches[0] * aligned_height;
2542
2543         drm_dbg_kms(&dev_priv->drm,
2544                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
2545                     crtc->base.name, plane->base.name, fb->width, fb->height,
2546                     fb->format->cpp[0] * 8, base, fb->pitches[0],
2547                     plane_config->size);
2548
2549         plane_config->fb = intel_fb;
2550         return;
2551
2552 error:
2553         kfree(intel_fb);
2554 }