1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2022 Intel Corporation
6 #ifndef __INTEL_DISPLAY_CORE_H__
7 #define __INTEL_DISPLAY_CORE_H__
9 #include <linux/list.h>
10 #include <linux/llist.h>
11 #include <linux/mutex.h>
12 #include <linux/types.h>
13 #include <linux/wait.h>
14 #include <linux/workqueue.h>
16 #include <drm/drm_connector.h>
17 #include <drm/drm_modeset_lock.h>
19 #include "intel_cdclk.h"
20 #include "intel_display_device.h"
21 #include "intel_display_limits.h"
22 #include "intel_display_params.h"
23 #include "intel_display_power.h"
24 #include "intel_dpll_mgr.h"
25 #include "intel_fbc.h"
26 #include "intel_global_state.h"
27 #include "intel_gmbus.h"
28 #include "intel_opregion.h"
29 #include "intel_wm_types.h"
31 struct drm_i915_private;
33 struct drm_property_blob;
34 struct i915_audio_component;
35 struct i915_hdcp_arbiter;
36 struct intel_atomic_state;
37 struct intel_audio_funcs;
38 struct intel_cdclk_funcs;
39 struct intel_cdclk_vals;
40 struct intel_color_funcs;
42 struct intel_crtc_state;
44 struct intel_dpll_funcs;
45 struct intel_dpll_mgr;
47 struct intel_fdi_funcs;
48 struct intel_hotplug_funcs;
49 struct intel_initial_plane_config;
52 /* Amount of SAGV/QGV points, BSpec precisely defines this */
53 #define I915_NUM_QGV_POINTS 8
55 /* Amount of PSF GV points, BSpec precisely defines this */
56 #define I915_NUM_PSF_GV_POINTS 3
58 struct intel_display_funcs {
60 * Returns the active state of the crtc, and if the crtc is active,
61 * fills out the pipe-config with the hw state.
63 bool (*get_pipe_config)(struct intel_crtc *,
64 struct intel_crtc_state *);
65 void (*get_initial_plane_config)(struct intel_crtc *,
66 struct intel_initial_plane_config *);
67 void (*crtc_enable)(struct intel_atomic_state *state,
68 struct intel_crtc *crtc);
69 void (*crtc_disable)(struct intel_atomic_state *state,
70 struct intel_crtc *crtc);
71 void (*commit_modeset_enables)(struct intel_atomic_state *state);
74 /* functions used for watermark calcs for display. */
75 struct intel_wm_funcs {
76 /* update_wm is for legacy wm management */
77 void (*update_wm)(struct drm_i915_private *dev_priv);
78 int (*compute_pipe_wm)(struct intel_atomic_state *state,
79 struct intel_crtc *crtc);
80 int (*compute_intermediate_wm)(struct intel_atomic_state *state,
81 struct intel_crtc *crtc);
82 void (*initial_watermarks)(struct intel_atomic_state *state,
83 struct intel_crtc *crtc);
84 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
85 struct intel_crtc *crtc);
86 void (*optimize_watermarks)(struct intel_atomic_state *state,
87 struct intel_crtc *crtc);
88 int (*compute_global_watermarks)(struct intel_atomic_state *state);
89 void (*get_hw_state)(struct drm_i915_private *i915);
92 struct intel_audio_state {
93 struct intel_encoder *encoder;
94 u8 eld[MAX_ELD_BYTES];
98 /* hda/i915 audio component */
99 struct i915_audio_component *component;
100 bool component_registered;
101 /* mutex for audio/video sync */
106 /* current audio state for the audio component hooks */
107 struct intel_audio_state state[I915_MAX_TRANSCODERS];
109 /* necessary resource sharing with HDMI LPE audio driver. */
111 struct platform_device *platdev;
117 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
118 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
119 * dpll, because on some platforms plls share registers.
125 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
126 const struct intel_dpll_mgr *mgr;
134 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id.
139 struct intel_frontbuffer_tracking {
143 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
150 struct intel_hotplug {
151 struct delayed_work hotplug_work;
153 const u32 *hpd, *pch_hpd;
156 unsigned long last_jiffies;
161 HPD_MARK_DISABLED = 2
163 } stats[HPD_NUM_PINS];
166 struct delayed_work reenable_work;
170 struct work_struct dig_port_work;
172 struct work_struct poll_init_work;
175 unsigned int hpd_storm_threshold;
176 /* Whether or not to count short HPD IRQs in HPD storms */
177 u8 hpd_short_storm_enabled;
179 /* Last state reported by oob_hotplug_event for each encoder */
180 unsigned long oob_hotplug_last_state;
183 * if we get a HPD irq from DP and a HPD irq from non-DP
184 * the non-DP HPD could block the workqueue on a mode config
185 * mutex getting, that userspace may have taken. However
186 * userspace is waiting on the DP workqueue to run which is
187 * blocked behind the non-DP one.
189 struct workqueue_struct *dp_wq;
192 * Flag to track if long HPDs need not to be processed
194 * Some panels generate long HPDs while keep connected to the port.
195 * This can cause issues with CI tests results. In CI systems we
196 * don't expect to disconnect the panels and could ignore the long
197 * HPDs generated from the faulty panels. This flag can be used as
198 * cue to ignore the long HPDs and can be set / unset using debugfs.
200 bool ignore_long_hpd;
203 struct intel_vbt_data {
208 unsigned int int_tv_support:1;
209 unsigned int int_crt_support:1;
210 unsigned int lvds_use_ssc:1;
211 unsigned int int_lvds_support:1;
212 unsigned int display_clock_mode:1;
213 unsigned int fdi_rx_polarity_inverted:1;
215 enum drm_panel_orientation orientation;
217 bool override_afc_startup;
218 u8 override_afc_startup_val;
222 struct list_head display_devices;
223 struct list_head bdb_blocks;
225 struct sdvo_device_mapping {
237 * Raw watermark latency values:
238 * in 0.1us units for WM0,
239 * in 0.5us units for WM1+.
248 * Raw watermark memory latency values
249 * for SKL for all 8 levels
254 /* current hardware state */
256 struct ilk_wm_values hw;
257 struct vlv_wm_values vlv;
258 struct g4x_wm_values g4x;
264 * Should be held around atomic WM register writing; also
265 * protects * intel_crtc->wm.active and
266 * crtc_state->wm.need_postvbl_update.
268 struct mutex wm_mutex;
273 struct intel_display {
274 /* Display functions */
276 /* Top level crtc-ish functions */
277 const struct intel_display_funcs *display;
279 /* Display CDCLK functions */
280 const struct intel_cdclk_funcs *cdclk;
282 /* Display pll funcs */
283 const struct intel_dpll_funcs *dpll;
285 /* irq display functions */
286 const struct intel_hotplug_funcs *hotplug;
288 /* pm display functions */
289 const struct intel_wm_funcs *wm;
291 /* fdi display functions */
292 const struct intel_fdi_funcs *fdi;
294 /* Display internal color functions */
295 const struct intel_color_funcs *color;
297 /* Display internal audio functions */
298 const struct intel_audio_funcs *audio;
301 /* Grouping using anonymous structs. Keep sorted. */
302 struct intel_atomic_helper {
303 struct llist_head free_list;
304 struct work_struct free_work;
308 /* backlight registers and fields in struct intel_panel */
313 struct intel_global_obj obj;
315 struct intel_bw_info {
316 /* for each QGV point */
317 unsigned int deratedbw[I915_NUM_QGV_POINTS];
318 /* for each PSF GV point */
319 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
320 /* Peak BW for each QGV point */
321 unsigned int peakbw[I915_NUM_QGV_POINTS];
323 u8 num_psf_gv_points;
329 /* The current hardware cdclk configuration */
330 struct intel_cdclk_config hw;
332 /* cdclk, divider, and ratio table from bspec */
333 const struct intel_cdclk_vals *table;
335 struct intel_global_obj obj;
337 unsigned int max_cdclk_freq;
341 struct drm_property_blob *glk_linear_degamma_lut;
345 /* The current hardware dbuf configuration */
348 struct intel_global_obj obj;
353 * dkl.phy_lock protects against concurrent access of the
360 struct intel_dmc *dmc;
361 intel_wakeref_t wakeref;
365 /* VLV/CHV/BXT/GLK DSI MMIO register base address */
370 /* list of fbdev register on this device */
371 struct intel_fbdev *fbdev;
372 struct work_struct suspend_work;
376 unsigned int pll_freq;
381 struct list_head obj_list;
386 * Base address of where the gmbus and gpio blocks are located
387 * (either on PCH or on SoC for platforms without PCH).
392 * gmbus.mutex protects against concurrent usage of the single
393 * hw gmbus controller on different i2c buses.
397 struct intel_gmbus *bus[GMBUS_NUM_PINS];
399 wait_queue_head_t wait_queue;
403 struct i915_hdcp_arbiter *arbiter;
407 * HDCP message struct for allocation of memory which can be
408 * reused when sending message to gsc cs.
409 * this is only populated post Meteorlake
411 struct intel_hdcp_gsc_message *hdcp_message;
412 /* Mutex to protect the above hdcp related values. */
413 struct mutex hdcp_mutex;
418 * HTI (aka HDPORT) state read during initial hw readout. Most
419 * platforms don't have HTI, so this will just stay 0. Those
420 * that do will use this later to figure out which PLLs and PHYs
421 * are unavailable for driver usage.
427 /* Access with DISPLAY_INFO() */
428 const struct intel_display_device_info *__device_info;
430 /* Access with DISPLAY_RUNTIME_INFO() */
431 struct intel_display_runtime_info __runtime_info;
439 wait_queue_head_t waitqueue;
441 /* mutex to protect pmdemand programming sequence */
444 struct intel_global_obj obj;
448 struct i915_power_domains domains;
450 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
453 /* perform PHY state sanity checks? */
454 bool chv_phy_assert[2];
460 /* protects panel power sequencer state */
465 struct drm_property *broadcast_rgb;
466 struct drm_property *force_audio;
474 /* restore state for suspend/resume and display reset */
475 struct drm_atomic_state *modeset_state;
476 struct drm_modeset_acquire_ctx reset_ctx;
481 I915_SAGV_UNKNOWN = 0,
484 I915_SAGV_NOT_CONTROLLED
492 * DG2: Mask of PHYs that were not calibrated by the firmware
493 * and should not be used.
495 u8 phy_failed_calibration;
500 * Shadows for CHV DPLL_MD regs to keep the state
501 * checker somewhat working in the presence hardware
502 * crappiness (can't read out DPLL_MD for pipes B & C).
504 u32 chv_dpll_md[I915_MAX_PIPES];
509 /* ordered wq for modesets */
510 struct workqueue_struct *modeset;
512 /* unbound hipri wq for page flips/plane updates */
513 struct workqueue_struct *flip;
516 /* Grouping using named structs. Keep sorted. */
517 struct intel_audio audio;
518 struct intel_dpll dpll;
519 struct intel_fbc *fbc[I915_MAX_FBCS];
520 struct intel_frontbuffer_tracking fb_tracking;
521 struct intel_hotplug hotplug;
522 struct intel_opregion opregion;
523 struct intel_overlay *overlay;
524 struct intel_display_params params;
525 struct intel_vbt_data vbt;
529 #endif /* __INTEL_DISPLAY_CORE_H__ */