drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <acpi/video.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34 #include <linux/string_helpers.h>
  35 #include <linux/vga_switcheroo.h>
  36
  37 #include <drm/display/drm_dp_helper.h>
  38 #include <drm/drm_atomic.h>
  39 #include <drm/drm_atomic_helper.h>
  40 #include <drm/drm_atomic_uapi.h>
  41 #include <drm/drm_damage_helper.h>
  42 #include <drm/drm_edid.h>
  43 #include <drm/drm_fourcc.h>
  44 #include <drm/drm_privacy_screen_consumer.h>
  45 #include <drm/drm_probe_helper.h>
  46 #include <drm/drm_rect.h>
  47
  48 #include "display/intel_audio.h"
  49 #include "display/intel_crt.h"
  50 #include "display/intel_ddi.h"
  51 #include "display/intel_display_debugfs.h"
  52 #include "display/intel_display_power.h"
  53 #include "display/intel_dp.h"
  54 #include "display/intel_dp_mst.h"
  55 #include "display/intel_dpll.h"
  56 #include "display/intel_dpll_mgr.h"
  57 #include "display/intel_drrs.h"
  58 #include "display/intel_dsi.h"
  59 #include "display/intel_dvo.h"
  60 #include "display/intel_fb.h"
  61 #include "display/intel_gmbus.h"
  62 #include "display/intel_hdmi.h"
  63 #include "display/intel_lvds.h"
  64 #include "display/intel_sdvo.h"
  65 #include "display/intel_snps_phy.h"
  66 #include "display/intel_tv.h"
  67 #include "display/intel_vdsc.h"
  68 #include "display/intel_vrr.h"
  69
  70 #include "gem/i915_gem_lmem.h"
  71 #include "gem/i915_gem_object.h"
  72
  73 #include "gt/gen8_ppgtt.h"
  74
  75 #include "g4x_dp.h"
  76 #include "g4x_hdmi.h"
  77 #include "hsw_ips.h"
  78 #include "i915_drv.h"
  79 #include "i915_utils.h"
  80 #include "icl_dsi.h"
  81 #include "intel_acpi.h"
  82 #include "intel_atomic.h"
  83 #include "intel_atomic_plane.h"
  84 #include "intel_bw.h"
  85 #include "intel_cdclk.h"
  86 #include "intel_color.h"
  87 #include "intel_crtc.h"
  88 #include "intel_crtc_state_dump.h"
  89 #include "intel_de.h"
  90 #include "intel_display_types.h"
  91 #include "intel_dmc.h"
  92 #include "intel_dp_link_training.h"
  93 #include "intel_dpt.h"
  94 #include "intel_dsb.h"
  95 #include "intel_fbc.h"
  96 #include "intel_fbdev.h"
  97 #include "intel_fdi.h"
  98 #include "intel_fifo_underrun.h"
  99 #include "intel_frontbuffer.h"
 100 #include "intel_hdcp.h"
 101 #include "intel_hotplug.h"
 102 #include "intel_modeset_verify.h"
 103 #include "intel_modeset_setup.h"
 104 #include "intel_overlay.h"
 105 #include "intel_panel.h"
 106 #include "intel_pch_display.h"
 107 #include "intel_pch_refclk.h"
 108 #include "intel_pcode.h"
 109 #include "intel_pipe_crc.h"
 110 #include "intel_plane_initial.h"
 111 #include "intel_pm.h"
 112 #include "intel_pps.h"
 113 #include "intel_psr.h"
 114 #include "intel_quirks.h"
 115 #include "intel_sprite.h"
 116 #include "intel_tc.h"
 117 #include "intel_vga.h"
 118 #include "i9xx_plane.h"
 119 #include "skl_scaler.h"
 120 #include "skl_universal_plane.h"
 121 #include "skl_watermark.h"
 122 #include "vlv_dsi.h"
 123 #include "vlv_dsi_pll.h"
 124 #include "vlv_dsi_regs.h"
 125 #include "vlv_sideband.h"
 126
 127 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 128 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 129 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 130 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 131 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 132
 133 /**
 134  * intel_update_watermarks - update FIFO watermark values based on current modes
 135  * @dev_priv: i915 device
 136  *
 137  * Calculate watermark values for the various WM regs based on current mode
 138  * and plane configuration.
 139  *
 140  * There are several cases to deal with here:
 141  *   - normal (i.e. non-self-refresh)
 142  *   - self-refresh (SR) mode
 143  *   - lines are large relative to FIFO size (buffer can hold up to 2)
 144  *   - lines are small relative to FIFO size (buffer can hold more than 2
 145  *     lines), so need to account for TLB latency
 146  *
 147  *   The normal calculation is:
 148  *     watermark = dotclock * bytes per pixel * latency
 149  *   where latency is platform & configuration dependent (we assume pessimal
 150  *   values here).
 151  *
 152  *   The SR calculation is:
 153  *     watermark = (trunc(latency/line time)+1) * surface width *
 154  *       bytes per pixel
 155  *   where
 156  *     line time = htotal / dotclock
 157  *     surface width = hdisplay for normal plane and 64 for cursor
 158  *   and latency is assumed to be high, as above.
 159  *
 160  * The final value programmed to the register should always be rounded up,
 161  * and include an extra 2 entries to account for clock crossings.
 162  *
 163  * We don't use the sprite, so we can ignore that.  And on Crestline we have
 164  * to set the non-SR watermarks to 8.
 165  */
 166 void intel_update_watermarks(struct drm_i915_private *dev_priv)
 167 {
 168         if (dev_priv->display.funcs.wm->update_wm)
 169                 dev_priv->display.funcs.wm->update_wm(dev_priv);
 170 }
 171
 172 static int intel_compute_pipe_wm(struct intel_atomic_state *state,
 173                                  struct intel_crtc *crtc)
 174 {
 175         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 176         if (dev_priv->display.funcs.wm->compute_pipe_wm)
 177                 return dev_priv->display.funcs.wm->compute_pipe_wm(state, crtc);
 178         return 0;
 179 }
 180
 181 static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
 182                                          struct intel_crtc *crtc)
 183 {
 184         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 185         if (!dev_priv->display.funcs.wm->compute_intermediate_wm)
 186                 return 0;
 187         if (drm_WARN_ON(&dev_priv->drm,
 188                         !dev_priv->display.funcs.wm->compute_pipe_wm))
 189                 return 0;
 190         return dev_priv->display.funcs.wm->compute_intermediate_wm(state, crtc);
 191 }
 192
 193 static bool intel_initial_watermarks(struct intel_atomic_state *state,
 194                                      struct intel_crtc *crtc)
 195 {
 196         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 197         if (dev_priv->display.funcs.wm->initial_watermarks) {
 198                 dev_priv->display.funcs.wm->initial_watermarks(state, crtc);
 199                 return true;
 200         }
 201         return false;
 202 }
 203
 204 static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
 205                                            struct intel_crtc *crtc)
 206 {
 207         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 208         if (dev_priv->display.funcs.wm->atomic_update_watermarks)
 209                 dev_priv->display.funcs.wm->atomic_update_watermarks(state, crtc);
 210 }
 211
 212 static void intel_optimize_watermarks(struct intel_atomic_state *state,
 213                                       struct intel_crtc *crtc)
 214 {
 215         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 216         if (dev_priv->display.funcs.wm->optimize_watermarks)
 217                 dev_priv->display.funcs.wm->optimize_watermarks(state, crtc);
 218 }
 219
 220 static int intel_compute_global_watermarks(struct intel_atomic_state *state)
 221 {
 222         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 223         if (dev_priv->display.funcs.wm->compute_global_watermarks)
 224                 return dev_priv->display.funcs.wm->compute_global_watermarks(state);
 225         return 0;
 226 }
 227
 228 /* returns HPLL frequency in kHz */
 229 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 230 {
 231         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 232
 233         /* Obtain SKU information */
 234         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 235                 CCK_FUSE_HPLL_FREQ_MASK;
 236
 237         return vco_freq[hpll_freq] * 1000;
 238 }
 239
 240 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 241                       const char *name, u32 reg, int ref_freq)
 242 {
 243         u32 val;
 244         int divider;
 245
 246         val = vlv_cck_read(dev_priv, reg);
 247         divider = val & CCK_FREQUENCY_VALUES;
 248
 249         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 250                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 251                  "%s change in progress\n", name);
 252
 253         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 254 }
 255
 256 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 257                            const char *name, u32 reg)
 258 {
 259         int hpll;
 260
 261         vlv_cck_get(dev_priv);
 262
 263         if (dev_priv->hpll_freq == 0)
 264                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 265
 266         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 267
 268         vlv_cck_put(dev_priv);
 269
 270         return hpll;
 271 }
 272
 273 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 274 {
 275         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 276                 return;
 277
 278         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 279                                                       CCK_CZ_CLOCK_CONTROL);
 280
 281         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 282                 dev_priv->czclk_freq);
 283 }
 284
 285 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 286 {
 287         return (crtc_state->active_planes &
 288                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 289 }
 290
 291 /* WA Display #0827: Gen9:all */
 292 static void
 293 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 294 {
 295         if (enable)
 296                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 297                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 298         else
 299                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 300                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 301 }
 302
 303 /* Wa_2006604312:icl,ehl */
 304 static void
 305 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 306                        bool enable)
 307 {
 308         if (enable)
 309                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 310                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 311         else
 312                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 313                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 314 }
 315
 316 /* Wa_1604331009:icl,jsl,ehl */
 317 static void
 318 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 319                        bool enable)
 320 {
 321         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
 322                      enable ? CURSOR_GATING_DIS : 0);
 323 }
 324
 325 static bool
 326 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 327 {
 328         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 329 }
 330
 331 static bool
 332 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 333 {
 334         return crtc_state->sync_mode_slaves_mask != 0;
 335 }
 336
 337 bool
 338 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 339 {
 340         return is_trans_port_sync_master(crtc_state) ||
 341                 is_trans_port_sync_slave(crtc_state);
 342 }
 343
 344 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 345 {
 346         return ffs(crtc_state->bigjoiner_pipes) - 1;
 347 }
 348
 349 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 350 {
 351         if (crtc_state->bigjoiner_pipes)
 352                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 353         else
 354                 return 0;
 355 }
 356
 357 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 358 {
 359         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 360
 361         return crtc_state->bigjoiner_pipes &&
 362                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 363 }
 364
 365 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 366 {
 367         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 368
 369         return crtc_state->bigjoiner_pipes &&
 370                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 371 }
 372
 373 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 374 {
 375         return hweight8(crtc_state->bigjoiner_pipes);
 376 }
 377
 378 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 379 {
 380         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 381
 382         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 383                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 384         else
 385                 return to_intel_crtc(crtc_state->uapi.crtc);
 386 }
 387
 388 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
 389                                     enum pipe pipe)
 390 {
 391         i915_reg_t reg = PIPEDSL(pipe);
 392         u32 line1, line2;
 393
 394         line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
 395         msleep(5);
 396         line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
 397
 398         return line1 != line2;
 399 }
 400
 401 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
 402 {
 403         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 404         enum pipe pipe = crtc->pipe;
 405
 406         /* Wait for the display line to settle/start moving */
 407         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
 408                 drm_err(&dev_priv->drm,
 409                         "pipe %c scanline %s wait timed out\n",
 410                         pipe_name(pipe), str_on_off(state));
 411 }
 412
 413 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
 414 {
 415         wait_for_pipe_scanline_moving(crtc, false);
 416 }
 417
 418 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
 419 {
 420         wait_for_pipe_scanline_moving(crtc, true);
 421 }
 422
 423 static void
 424 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 425 {
 426         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 427         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 428
 429         if (DISPLAY_VER(dev_priv) >= 4) {
 430                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 431
 432                 /* Wait for the Pipe State to go off */
 433                 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
 434                                             PIPECONF_STATE_ENABLE, 100))
 435                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 436         } else {
 437                 intel_wait_for_pipe_scanline_stopped(crtc);
 438         }
 439 }
 440
 441 void assert_transcoder(struct drm_i915_private *dev_priv,
 442                        enum transcoder cpu_transcoder, bool state)
 443 {
 444         bool cur_state;
 445         enum intel_display_power_domain power_domain;
 446         intel_wakeref_t wakeref;
 447
 448         /* we keep both pipes enabled on 830 */
 449         if (IS_I830(dev_priv))
 450                 state = true;
 451
 452         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 453         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 454         if (wakeref) {
 455                 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
 456                 cur_state = !!(val & PIPECONF_ENABLE);
 457
 458                 intel_display_power_put(dev_priv, power_domain, wakeref);
 459         } else {
 460                 cur_state = false;
 461         }
 462
 463         I915_STATE_WARN(cur_state != state,
 464                         "transcoder %s assertion failure (expected %s, current %s)\n",
 465                         transcoder_name(cpu_transcoder),
 466                         str_on_off(state), str_on_off(cur_state));
 467 }
 468
 469 static void assert_plane(struct intel_plane *plane, bool state)
 470 {
 471         enum pipe pipe;
 472         bool cur_state;
 473
 474         cur_state = plane->get_hw_state(plane, &pipe);
 475
 476         I915_STATE_WARN(cur_state != state,
 477                         "%s assertion failure (expected %s, current %s)\n",
 478                         plane->base.name, str_on_off(state),
 479                         str_on_off(cur_state));
 480 }
 481
 482 #define assert_plane_enabled(p) assert_plane(p, true)
 483 #define assert_plane_disabled(p) assert_plane(p, false)
 484
 485 static void assert_planes_disabled(struct intel_crtc *crtc)
 486 {
 487         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 488         struct intel_plane *plane;
 489
 490         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 491                 assert_plane_disabled(plane);
 492 }
 493
 494 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 495                          struct intel_digital_port *dig_port,
 496                          unsigned int expected_mask)
 497 {
 498         u32 port_mask;
 499         i915_reg_t dpll_reg;
 500
 501         switch (dig_port->base.port) {
 502         default:
 503                 MISSING_CASE(dig_port->base.port);
 504                 fallthrough;
 505         case PORT_B:
 506                 port_mask = DPLL_PORTB_READY_MASK;
 507                 dpll_reg = DPLL(0);
 508                 break;
 509         case PORT_C:
 510                 port_mask = DPLL_PORTC_READY_MASK;
 511                 dpll_reg = DPLL(0);
 512                 expected_mask <<= 4;
 513                 break;
 514         case PORT_D:
 515                 port_mask = DPLL_PORTD_READY_MASK;
 516                 dpll_reg = DPIO_PHY_STATUS;
 517                 break;
 518         }
 519
 520         if (intel_de_wait_for_register(dev_priv, dpll_reg,
 521                                        port_mask, expected_mask, 1000))
 522                 drm_WARN(&dev_priv->drm, 1,
 523                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 524                          dig_port->base.base.base.id, dig_port->base.base.name,
 525                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 526                          expected_mask);
 527 }
 528
 529 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 530 {
 531         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 532         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 533         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 534         enum pipe pipe = crtc->pipe;
 535         i915_reg_t reg;
 536         u32 val;
 537
 538         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 539
 540         assert_planes_disabled(crtc);
 541
 542         /*
 543          * A pipe without a PLL won't actually be able to drive bits from
 544          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 545          * need the check.
 546          */
 547         if (HAS_GMCH(dev_priv)) {
 548                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 549                         assert_dsi_pll_enabled(dev_priv);
 550                 else
 551                         assert_pll_enabled(dev_priv, pipe);
 552         } else {
 553                 if (new_crtc_state->has_pch_encoder) {
 554                         /* if driving the PCH, we need FDI enabled */
 555                         assert_fdi_rx_pll_enabled(dev_priv,
 556                                                   intel_crtc_pch_transcoder(crtc));
 557                         assert_fdi_tx_pll_enabled(dev_priv,
 558                                                   (enum pipe) cpu_transcoder);
 559                 }
 560                 /* FIXME: assert CPU port conditions for SNB+ */
 561         }
 562
 563         /* Wa_22012358565:adl-p */
 564         if (DISPLAY_VER(dev_priv) == 13)
 565                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 566                              0, PIPE_ARB_USE_PROG_SLOTS);
 567
 568         reg = PIPECONF(cpu_transcoder);
 569         val = intel_de_read(dev_priv, reg);
 570         if (val & PIPECONF_ENABLE) {
 571                 /* we keep both pipes enabled on 830 */
 572                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 573                 return;
 574         }
 575
 576         intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
 577         intel_de_posting_read(dev_priv, reg);
 578
 579         /*
 580          * Until the pipe starts PIPEDSL reads will return a stale value,
 581          * which causes an apparent vblank timestamp jump when PIPEDSL
 582          * resets to its proper value. That also messes up the frame count
 583          * when it's derived from the timestamps. So let's wait for the
 584          * pipe to start properly before we call drm_crtc_vblank_on()
 585          */
 586         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 587                 intel_wait_for_pipe_scanline_moving(crtc);
 588 }
 589
 590 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 591 {
 592         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 593         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 594         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 595         enum pipe pipe = crtc->pipe;
 596         i915_reg_t reg;
 597         u32 val;
 598
 599         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 600
 601         /*
 602          * Make sure planes won't keep trying to pump pixels to us,
 603          * or we might hang the display.
 604          */
 605         assert_planes_disabled(crtc);
 606
 607         reg = PIPECONF(cpu_transcoder);
 608         val = intel_de_read(dev_priv, reg);
 609         if ((val & PIPECONF_ENABLE) == 0)
 610                 return;
 611
 612         /*
 613          * Double wide has implications for planes
 614          * so best keep it disabled when not needed.
 615          */
 616         if (old_crtc_state->double_wide)
 617                 val &= ~PIPECONF_DOUBLE_WIDE;
 618
 619         /* Don't disable pipe or pipe PLLs if needed */
 620         if (!IS_I830(dev_priv))
 621                 val &= ~PIPECONF_ENABLE;
 622
 623         if (DISPLAY_VER(dev_priv) >= 14)
 624                 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
 625                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 626         else if (DISPLAY_VER(dev_priv) >= 12)
 627                 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
 628                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 629
 630         intel_de_write(dev_priv, reg, val);
 631         if ((val & PIPECONF_ENABLE) == 0)
 632                 intel_wait_for_pipe_off(old_crtc_state);
 633 }
 634
 635 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 636 {
 637         unsigned int size = 0;
 638         int i;
 639
 640         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 641                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 642
 643         return size;
 644 }
 645
 646 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 647 {
 648         unsigned int size = 0;
 649         int i;
 650
 651         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 652                 unsigned int plane_size;
 653
 654                 if (rem_info->plane[i].linear)
 655                         plane_size = rem_info->plane[i].size;
 656                 else
 657                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 658
 659                 if (plane_size == 0)
 660                         continue;
 661
 662                 if (rem_info->plane_alignment)
 663                         size = ALIGN(size, rem_info->plane_alignment);
 664
 665                 size += plane_size;
 666         }
 667
 668         return size;
 669 }
 670
 671 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 672 {
 673         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 674         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 675
 676         return DISPLAY_VER(dev_priv) < 4 ||
 677                 (plane->fbc &&
 678                  plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
 679 }
 680
 681 /*
 682  * Convert the x/y offsets into a linear offset.
 683  * Only valid with 0/180 degree rotation, which is fine since linear
 684  * offset is only used with linear buffers on pre-hsw and tiled buffers
 685  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 686  */
 687 u32 intel_fb_xy_to_linear(int x, int y,
 688                           const struct intel_plane_state *state,
 689                           int color_plane)
 690 {
 691         const struct drm_framebuffer *fb = state->hw.fb;
 692         unsigned int cpp = fb->format->cpp[color_plane];
 693         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 694
 695         return y * pitch + x * cpp;
 696 }
 697
 698 /*
 699  * Add the x/y offsets derived from fb->offsets[] to the user
 700  * specified plane src x/y offsets. The resulting x/y offsets
 701  * specify the start of scanout from the beginning of the gtt mapping.
 702  */
 703 void intel_add_fb_offsets(int *x, int *y,
 704                           const struct intel_plane_state *state,
 705                           int color_plane)
 706
 707 {
 708         *x += state->view.color_plane[color_plane].x;
 709         *y += state->view.color_plane[color_plane].y;
 710 }
 711
 712 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 713                               u32 pixel_format, u64 modifier)
 714 {
 715         struct intel_crtc *crtc;
 716         struct intel_plane *plane;
 717
 718         if (!HAS_DISPLAY(dev_priv))
 719                 return 0;
 720
 721         /*
 722          * We assume the primary plane for pipe A has
 723          * the highest stride limits of them all,
 724          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 725          */
 726         crtc = intel_first_crtc(dev_priv);
 727         if (!crtc)
 728                 return 0;
 729
 730         plane = to_intel_plane(crtc->base.primary);
 731
 732         return plane->max_stride(plane, pixel_format, modifier,
 733                                  DRM_MODE_ROTATE_0);
 734 }
 735
 736 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 737                              struct intel_plane_state *plane_state,
 738                              bool visible)
 739 {
 740         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 741
 742         plane_state->uapi.visible = visible;
 743
 744         if (visible)
 745                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 746         else
 747                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 748 }
 749
 750 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 751 {
 752         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 753         struct drm_plane *plane;
 754
 755         /*
 756          * Active_planes aliases if multiple "primary" or cursor planes
 757          * have been used on the same (or wrong) pipe. plane_mask uses
 758          * unique ids, hence we can use that to reconstruct active_planes.
 759          */
 760         crtc_state->enabled_planes = 0;
 761         crtc_state->active_planes = 0;
 762
 763         drm_for_each_plane_mask(plane, &dev_priv->drm,
 764                                 crtc_state->uapi.plane_mask) {
 765                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 766                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 767         }
 768 }
 769
 770 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 771                                   struct intel_plane *plane)
 772 {
 773         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 774         struct intel_crtc_state *crtc_state =
 775                 to_intel_crtc_state(crtc->base.state);
 776         struct intel_plane_state *plane_state =
 777                 to_intel_plane_state(plane->base.state);
 778
 779         drm_dbg_kms(&dev_priv->drm,
 780                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 781                     plane->base.base.id, plane->base.name,
 782                     crtc->base.base.id, crtc->base.name);
 783
 784         intel_set_plane_visible(crtc_state, plane_state, false);
 785         intel_plane_fixup_bitmasks(crtc_state);
 786         crtc_state->data_rate[plane->id] = 0;
 787         crtc_state->data_rate_y[plane->id] = 0;
 788         crtc_state->rel_data_rate[plane->id] = 0;
 789         crtc_state->rel_data_rate_y[plane->id] = 0;
 790         crtc_state->min_cdclk[plane->id] = 0;
 791
 792         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 793             hsw_ips_disable(crtc_state)) {
 794                 crtc_state->ips_enabled = false;
 795                 intel_crtc_wait_for_next_vblank(crtc);
 796         }
 797
 798         /*
 799          * Vblank time updates from the shadow to live plane control register
 800          * are blocked if the memory self-refresh mode is active at that
 801          * moment. So to make sure the plane gets truly disabled, disable
 802          * first the self-refresh mode. The self-refresh enable bit in turn
 803          * will be checked/applied by the HW only at the next frame start
 804          * event which is after the vblank start event, so we need to have a
 805          * wait-for-vblank between disabling the plane and the pipe.
 806          */
 807         if (HAS_GMCH(dev_priv) &&
 808             intel_set_memory_cxsr(dev_priv, false))
 809                 intel_crtc_wait_for_next_vblank(crtc);
 810
 811         /*
 812          * Gen2 reports pipe underruns whenever all planes are disabled.
 813          * So disable underrun reporting before all the planes get disabled.
 814          */
 815         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 816                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 817
 818         intel_plane_disable_arm(plane, crtc_state);
 819         intel_crtc_wait_for_next_vblank(crtc);
 820 }
 821
 822 unsigned int
 823 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 824 {
 825         int x = 0, y = 0;
 826
 827         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 828                                           plane_state->view.color_plane[0].offset, 0);
 829
 830         return y;
 831 }
 832
 833 static int
 834 intel_display_commit_duplicated_state(struct intel_atomic_state *state,
 835                                       struct drm_modeset_acquire_ctx *ctx)
 836 {
 837         struct drm_i915_private *i915 = to_i915(state->base.dev);
 838         int ret;
 839
 840         ret = drm_atomic_helper_commit_duplicated_state(&state->base, ctx);
 841
 842         drm_WARN_ON(&i915->drm, ret == -EDEADLK);
 843
 844         return ret;
 845 }
 846
 847 static int
 848 __intel_display_resume(struct drm_i915_private *i915,
 849                        struct drm_atomic_state *state,
 850                        struct drm_modeset_acquire_ctx *ctx)
 851 {
 852         struct drm_crtc_state *crtc_state;
 853         struct drm_crtc *crtc;
 854         int i;
 855
 856         intel_modeset_setup_hw_state(i915, ctx);
 857         intel_vga_redisable(i915);
 858
 859         if (!state)
 860                 return 0;
 861
 862         /*
 863          * We've duplicated the state, pointers to the old state are invalid.
 864          *
 865          * Don't attempt to use the old state until we commit the duplicated state.
 866          */
 867         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 868                 /*
 869                  * Force recalculation even if we restore
 870                  * current state. With fast modeset this may not result
 871                  * in a modeset when the state is compatible.
 872                  */
 873                 crtc_state->mode_changed = true;
 874         }
 875
 876         /* ignore any reset values/BIOS leftovers in the WM registers */
 877         if (!HAS_GMCH(i915))
 878                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
 879
 880         return intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx);
 881 }
 882
 883 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
 884 {
 885         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
 886                 intel_has_gpu_reset(to_gt(dev_priv)));
 887 }
 888
 889 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
 890 {
 891         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
 892         struct drm_atomic_state *state;
 893         int ret;
 894
 895         if (!HAS_DISPLAY(dev_priv))
 896                 return;
 897
 898         /* reset doesn't touch the display */
 899         if (!dev_priv->params.force_reset_modeset_test &&
 900             !gpu_reset_clobbers_display(dev_priv))
 901                 return;
 902
 903         /* We have a modeset vs reset deadlock, defensively unbreak it. */
 904         set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);
 905         smp_mb__after_atomic();
 906         wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET);
 907
 908         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
 909                 drm_dbg_kms(&dev_priv->drm,
 910                             "Modeset potentially stuck, unbreaking through wedging\n");
 911                 intel_gt_set_wedged(to_gt(dev_priv));
 912         }
 913
 914         /*
 915          * Need mode_config.mutex so that we don't
 916          * trample ongoing ->detect() and whatnot.
 917          */
 918         mutex_lock(&dev_priv->drm.mode_config.mutex);
 919         drm_modeset_acquire_init(ctx, 0);
 920         while (1) {
 921                 ret = drm_modeset_lock_all_ctx(&dev_priv->drm, ctx);
 922                 if (ret != -EDEADLK)
 923                         break;
 924
 925                 drm_modeset_backoff(ctx);
 926         }
 927         /*
 928          * Disabling the crtcs gracefully seems nicer. Also the
 929          * g33 docs say we should at least disable all the planes.
 930          */
 931         state = drm_atomic_helper_duplicate_state(&dev_priv->drm, ctx);
 932         if (IS_ERR(state)) {
 933                 ret = PTR_ERR(state);
 934                 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
 935                         ret);
 936                 return;
 937         }
 938
 939         ret = drm_atomic_helper_disable_all(&dev_priv->drm, ctx);
 940         if (ret) {
 941                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
 942                         ret);
 943                 drm_atomic_state_put(state);
 944                 return;
 945         }
 946
 947         dev_priv->modeset_restore_state = state;
 948         state->acquire_ctx = ctx;
 949 }
 950
 951 void intel_display_finish_reset(struct drm_i915_private *i915)
 952 {
 953         struct drm_modeset_acquire_ctx *ctx = &i915->reset_ctx;
 954         struct drm_atomic_state *state;
 955         int ret;
 956
 957         if (!HAS_DISPLAY(i915))
 958                 return;
 959
 960         /* reset doesn't touch the display */
 961         if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))
 962                 return;
 963
 964         state = fetch_and_zero(&i915->modeset_restore_state);
 965         if (!state)
 966                 goto unlock;
 967
 968         /* reset doesn't touch the display */
 969         if (!gpu_reset_clobbers_display(i915)) {
 970                 /* for testing only restore the display */
 971                 ret = intel_display_commit_duplicated_state(to_intel_atomic_state(state), ctx);
 972                 if (ret)
 973                         drm_err(&i915->drm,
 974                                 "Restoring old state failed with %i\n", ret);
 975         } else {
 976                 /*
 977                  * The display has been reset as well,
 978                  * so need a full re-initialization.
 979                  */
 980                 intel_pps_unlock_regs_wa(i915);
 981                 intel_modeset_init_hw(i915);
 982                 intel_init_clock_gating(i915);
 983                 intel_hpd_init(i915);
 984
 985                 ret = __intel_display_resume(i915, state, ctx);
 986                 if (ret)
 987                         drm_err(&i915->drm,
 988                                 "Restoring old state failed with %i\n", ret);
 989
 990                 intel_hpd_poll_disable(i915);
 991         }
 992
 993         drm_atomic_state_put(state);
 994 unlock:
 995         drm_modeset_drop_locks(ctx);
 996         drm_modeset_acquire_fini(ctx);
 997         mutex_unlock(&i915->drm.mode_config.mutex);
 998
 999         clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags);
1000 }
1001
1002 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1005         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1006         enum pipe pipe = crtc->pipe;
1007         u32 tmp;
1008
1009         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
1010
1011         /*
1012          * Display WA #1153: icl
1013          * enable hardware to bypass the alpha math
1014          * and rounding for per-pixel values 00 and 0xff
1015          */
1016         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
1017         /*
1018          * Display WA # 1605353570: icl
1019          * Set the pixel rounding bit to 1 for allowing
1020          * passthrough of Frame buffer pixels unmodified
1021          * across pipe
1022          */
1023         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
1024
1025         /*
1026          * Underrun recovery must always be disabled on display 13+.
1027          * DG2 chicken bit meaning is inverted compared to other platforms.
1028          */
1029         if (IS_DG2(dev_priv))
1030                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
1031         else if (DISPLAY_VER(dev_priv) >= 13)
1032                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
1033
1034         /* Wa_14010547955:dg2 */
1035         if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
1036                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
1037
1038         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
1039 }
1040
1041 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
1042 {
1043         struct drm_crtc *crtc;
1044         bool cleanup_done;
1045
1046         drm_for_each_crtc(crtc, &dev_priv->drm) {
1047                 struct drm_crtc_commit *commit;
1048                 spin_lock(&crtc->commit_lock);
1049                 commit = list_first_entry_or_null(&crtc->commit_list,
1050                                                   struct drm_crtc_commit, commit_entry);
1051                 cleanup_done = commit ?
1052                         try_wait_for_completion(&commit->cleanup_done) : true;
1053                 spin_unlock(&crtc->commit_lock);
1054
1055                 if (cleanup_done)
1056                         continue;
1057
1058                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
1059
1060                 return true;
1061         }
1062
1063         return false;
1064 }
1065
1066 /*
1067  * Finds the encoder associated with the given CRTC. This can only be
1068  * used when we know that the CRTC isn't feeding multiple encoders!
1069  */
1070 struct intel_encoder *
1071 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
1072                            const struct intel_crtc_state *crtc_state)
1073 {
1074         const struct drm_connector_state *connector_state;
1075         const struct drm_connector *connector;
1076         struct intel_encoder *encoder = NULL;
1077         struct intel_crtc *master_crtc;
1078         int num_encoders = 0;
1079         int i;
1080
1081         master_crtc = intel_master_crtc(crtc_state);
1082
1083         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
1084                 if (connector_state->crtc != &master_crtc->base)
1085                         continue;
1086
1087                 encoder = to_intel_encoder(connector_state->best_encoder);
1088                 num_encoders++;
1089         }
1090
1091         drm_WARN(encoder->base.dev, num_encoders != 1,
1092                  "%d encoders for pipe %c\n",
1093                  num_encoders, pipe_name(master_crtc->pipe));
1094
1095         return encoder;
1096 }
1097
1098 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
1099                                enum pipe pipe)
1100 {
1101         i915_reg_t dslreg = PIPEDSL(pipe);
1102         u32 temp;
1103
1104         temp = intel_de_read(dev_priv, dslreg);
1105         udelay(500);
1106         if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
1107                 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
1108                         drm_err(&dev_priv->drm,
1109                                 "mode set failed: pipe %c stuck\n",
1110                                 pipe_name(pipe));
1111         }
1112 }
1113
1114 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
1115 {
1116         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1117         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1118         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
1119         enum pipe pipe = crtc->pipe;
1120         int width = drm_rect_width(dst);
1121         int height = drm_rect_height(dst);
1122         int x = dst->x1;
1123         int y = dst->y1;
1124
1125         if (!crtc_state->pch_pfit.enabled)
1126                 return;
1127
1128         /* Force use of hard-coded filter coefficients
1129          * as some pre-programmed values are broken,
1130          * e.g. x201.
1131          */
1132         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
1133                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
1134                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
1135         else
1136                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
1137                                   PF_FILTER_MED_3x3);
1138         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
1139         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
1140 }
1141
1142 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
1143 {
1144         if (crtc->overlay)
1145                 (void) intel_overlay_switch_off(crtc->overlay);
1146
1147         /* Let userspace switch the overlay on again. In most cases userspace
1148          * has to recompute where to put it anyway.
1149          */
1150 }
1151
1152 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
1153 {
1154         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1155
1156         if (!crtc_state->nv12_planes)
1157                 return false;
1158
1159         /* WA Display #0827: Gen9:all */
1160         if (DISPLAY_VER(dev_priv) == 9)
1161                 return true;
1162
1163         return false;
1164 }
1165
1166 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
1167 {
1168         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1169
1170         /* Wa_2006604312:icl,ehl */
1171         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
1172                 return true;
1173
1174         return false;
1175 }
1176
1177 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
1178 {
1179         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1180
1181         /* Wa_1604331009:icl,jsl,ehl */
1182         if (is_hdr_mode(crtc_state) &&
1183             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
1184             DISPLAY_VER(dev_priv) == 11)
1185                 return true;
1186
1187         return false;
1188 }
1189
1190 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
1191                                     enum pipe pipe, bool enable)
1192 {
1193         if (DISPLAY_VER(i915) == 9) {
1194                 /*
1195                  * "Plane N strech max must be programmed to 11b (x1)
1196                  *  when Async flips are enabled on that plane."
1197                  */
1198                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1199                              SKL_PLANE1_STRETCH_MAX_MASK,
1200                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
1201         } else {
1202                 /* Also needed on HSW/BDW albeit undocumented */
1203                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1204                              HSW_PRI_STRETCH_MAX_MASK,
1205                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
1206         }
1207 }
1208
1209 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
1210 {
1211         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1212
1213         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
1214                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
1215 }
1216
1217 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
1218                             const struct intel_crtc_state *new_crtc_state)
1219 {
1220         return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
1221                 new_crtc_state->active_planes;
1222 }
1223
1224 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
1225                              const struct intel_crtc_state *new_crtc_state)
1226 {
1227         return old_crtc_state->active_planes &&
1228                 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
1229 }
1230
1231 static void intel_post_plane_update(struct intel_atomic_state *state,
1232                                     struct intel_crtc *crtc)
1233 {
1234         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1235         const struct intel_crtc_state *old_crtc_state =
1236                 intel_atomic_get_old_crtc_state(state, crtc);
1237         const struct intel_crtc_state *new_crtc_state =
1238                 intel_atomic_get_new_crtc_state(state, crtc);
1239         enum pipe pipe = crtc->pipe;
1240
1241         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1242
1243         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1244                 intel_update_watermarks(dev_priv);
1245
1246         hsw_ips_post_update(state, crtc);
1247         intel_fbc_post_update(state, crtc);
1248
1249         if (needs_async_flip_vtd_wa(old_crtc_state) &&
1250             !needs_async_flip_vtd_wa(new_crtc_state))
1251                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
1252
1253         if (needs_nv12_wa(old_crtc_state) &&
1254             !needs_nv12_wa(new_crtc_state))
1255                 skl_wa_827(dev_priv, pipe, false);
1256
1257         if (needs_scalerclk_wa(old_crtc_state) &&
1258             !needs_scalerclk_wa(new_crtc_state))
1259                 icl_wa_scalerclkgating(dev_priv, pipe, false);
1260
1261         if (needs_cursorclk_wa(old_crtc_state) &&
1262             !needs_cursorclk_wa(new_crtc_state))
1263                 icl_wa_cursorclkgating(dev_priv, pipe, false);
1264 }
1265
1266 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1267                                         struct intel_crtc *crtc)
1268 {
1269         const struct intel_crtc_state *crtc_state =
1270                 intel_atomic_get_new_crtc_state(state, crtc);
1271         u8 update_planes = crtc_state->update_planes;
1272         const struct intel_plane_state *plane_state;
1273         struct intel_plane *plane;
1274         int i;
1275
1276         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1277                 if (plane->pipe == crtc->pipe &&
1278                     update_planes & BIT(plane->id))
1279                         plane->enable_flip_done(plane);
1280         }
1281 }
1282
1283 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1284                                          struct intel_crtc *crtc)
1285 {
1286         const struct intel_crtc_state *crtc_state =
1287                 intel_atomic_get_new_crtc_state(state, crtc);
1288         u8 update_planes = crtc_state->update_planes;
1289         const struct intel_plane_state *plane_state;
1290         struct intel_plane *plane;
1291         int i;
1292
1293         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1294                 if (plane->pipe == crtc->pipe &&
1295                     update_planes & BIT(plane->id))
1296                         plane->disable_flip_done(plane);
1297         }
1298 }
1299
1300 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1301                                              struct intel_crtc *crtc)
1302 {
1303         const struct intel_crtc_state *old_crtc_state =
1304                 intel_atomic_get_old_crtc_state(state, crtc);
1305         const struct intel_crtc_state *new_crtc_state =
1306                 intel_atomic_get_new_crtc_state(state, crtc);
1307         u8 update_planes = new_crtc_state->update_planes;
1308         const struct intel_plane_state *old_plane_state;
1309         struct intel_plane *plane;
1310         bool need_vbl_wait = false;
1311         int i;
1312
1313         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1314                 if (plane->need_async_flip_disable_wa &&
1315                     plane->pipe == crtc->pipe &&
1316                     update_planes & BIT(plane->id)) {
1317                         /*
1318                          * Apart from the async flip bit we want to
1319                          * preserve the old state for the plane.
1320                          */
1321                         plane->async_flip(plane, old_crtc_state,
1322                                           old_plane_state, false);
1323                         need_vbl_wait = true;
1324                 }
1325         }
1326
1327         if (need_vbl_wait)
1328                 intel_crtc_wait_for_next_vblank(crtc);
1329 }
1330
1331 static void intel_pre_plane_update(struct intel_atomic_state *state,
1332                                    struct intel_crtc *crtc)
1333 {
1334         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1335         const struct intel_crtc_state *old_crtc_state =
1336                 intel_atomic_get_old_crtc_state(state, crtc);
1337         const struct intel_crtc_state *new_crtc_state =
1338                 intel_atomic_get_new_crtc_state(state, crtc);
1339         enum pipe pipe = crtc->pipe;
1340
1341         intel_drrs_deactivate(old_crtc_state);
1342
1343         intel_psr_pre_plane_update(state, crtc);
1344
1345         if (hsw_ips_pre_update(state, crtc))
1346                 intel_crtc_wait_for_next_vblank(crtc);
1347
1348         if (intel_fbc_pre_update(state, crtc))
1349                 intel_crtc_wait_for_next_vblank(crtc);
1350
1351         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1352             needs_async_flip_vtd_wa(new_crtc_state))
1353                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1354
1355         /* Display WA 827 */
1356         if (!needs_nv12_wa(old_crtc_state) &&
1357             needs_nv12_wa(new_crtc_state))
1358                 skl_wa_827(dev_priv, pipe, true);
1359
1360         /* Wa_2006604312:icl,ehl */
1361         if (!needs_scalerclk_wa(old_crtc_state) &&
1362             needs_scalerclk_wa(new_crtc_state))
1363                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1364
1365         /* Wa_1604331009:icl,jsl,ehl */
1366         if (!needs_cursorclk_wa(old_crtc_state) &&
1367             needs_cursorclk_wa(new_crtc_state))
1368                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1369
1370         /*
1371          * Vblank time updates from the shadow to live plane control register
1372          * are blocked if the memory self-refresh mode is active at that
1373          * moment. So to make sure the plane gets truly disabled, disable
1374          * first the self-refresh mode. The self-refresh enable bit in turn
1375          * will be checked/applied by the HW only at the next frame start
1376          * event which is after the vblank start event, so we need to have a
1377          * wait-for-vblank between disabling the plane and the pipe.
1378          */
1379         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1380             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1381                 intel_crtc_wait_for_next_vblank(crtc);
1382
1383         /*
1384          * IVB workaround: must disable low power watermarks for at least
1385          * one frame before enabling scaling.  LP watermarks can be re-enabled
1386          * when scaling is disabled.
1387          *
1388          * WaCxSRDisabledForSpriteScaling:ivb
1389          */
1390         if (old_crtc_state->hw.active &&
1391             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1392                 intel_crtc_wait_for_next_vblank(crtc);
1393
1394         /*
1395          * If we're doing a modeset we don't need to do any
1396          * pre-vblank watermark programming here.
1397          */
1398         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1399                 /*
1400                  * For platforms that support atomic watermarks, program the
1401                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1402                  * will be the intermediate values that are safe for both pre- and
1403                  * post- vblank; when vblank happens, the 'active' values will be set
1404                  * to the final 'target' values and we'll do this again to get the
1405                  * optimal watermarks.  For gen9+ platforms, the values we program here
1406                  * will be the final target values which will get automatically latched
1407                  * at vblank time; no further programming will be necessary.
1408                  *
1409                  * If a platform hasn't been transitioned to atomic watermarks yet,
1410                  * we'll continue to update watermarks the old way, if flags tell
1411                  * us to.
1412                  */
1413                 if (!intel_initial_watermarks(state, crtc))
1414                         if (new_crtc_state->update_wm_pre)
1415                                 intel_update_watermarks(dev_priv);
1416         }
1417
1418         /*
1419          * Gen2 reports pipe underruns whenever all planes are disabled.
1420          * So disable underrun reporting before all the planes get disabled.
1421          *
1422          * We do this after .initial_watermarks() so that we have a
1423          * chance of catching underruns with the intermediate watermarks
1424          * vs. the old plane configuration.
1425          */
1426         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1427                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1428
1429         /*
1430          * WA for platforms where async address update enable bit
1431          * is double buffered and only latched at start of vblank.
1432          */
1433         if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
1434                 intel_crtc_async_flip_disable_wa(state, crtc);
1435 }
1436
1437 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1438                                       struct intel_crtc *crtc)
1439 {
1440         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1441         const struct intel_crtc_state *new_crtc_state =
1442                 intel_atomic_get_new_crtc_state(state, crtc);
1443         unsigned int update_mask = new_crtc_state->update_planes;
1444         const struct intel_plane_state *old_plane_state;
1445         struct intel_plane *plane;
1446         unsigned fb_bits = 0;
1447         int i;
1448
1449         intel_crtc_dpms_overlay_disable(crtc);
1450
1451         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1452                 if (crtc->pipe != plane->pipe ||
1453                     !(update_mask & BIT(plane->id)))
1454                         continue;
1455
1456                 intel_plane_disable_arm(plane, new_crtc_state);
1457
1458                 if (old_plane_state->uapi.visible)
1459                         fb_bits |= plane->frontbuffer_bit;
1460         }
1461
1462         intel_frontbuffer_flip(dev_priv, fb_bits);
1463 }
1464
1465 /*
1466  * intel_connector_primary_encoder - get the primary encoder for a connector
1467  * @connector: connector for which to return the encoder
1468  *
1469  * Returns the primary encoder for a connector. There is a 1:1 mapping from
1470  * all connectors to their encoder, except for DP-MST connectors which have
1471  * both a virtual and a primary encoder. These DP-MST primary encoders can be
1472  * pointed to by as many DP-MST connectors as there are pipes.
1473  */
1474 static struct intel_encoder *
1475 intel_connector_primary_encoder(struct intel_connector *connector)
1476 {
1477         struct intel_encoder *encoder;
1478
1479         if (connector->mst_port)
1480                 return &dp_to_dig_port(connector->mst_port)->base;
1481
1482         encoder = intel_attached_encoder(connector);
1483         drm_WARN_ON(connector->base.dev, !encoder);
1484
1485         return encoder;
1486 }
1487
1488 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1489 {
1490         struct drm_i915_private *i915 = to_i915(state->base.dev);
1491         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1492         struct intel_crtc *crtc;
1493         struct drm_connector_state *new_conn_state;
1494         struct drm_connector *connector;
1495         int i;
1496
1497         /*
1498          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1499          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1500          */
1501         if (i915->display.dpll.mgr) {
1502                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1503                         if (intel_crtc_needs_modeset(new_crtc_state))
1504                                 continue;
1505
1506                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1507                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1508                 }
1509         }
1510
1511         if (!state->modeset)
1512                 return;
1513
1514         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
1515                                         i) {
1516                 struct intel_connector *intel_connector;
1517                 struct intel_encoder *encoder;
1518                 struct intel_crtc *crtc;
1519
1520                 if (!intel_connector_needs_modeset(state, connector))
1521                         continue;
1522
1523                 intel_connector = to_intel_connector(connector);
1524                 encoder = intel_connector_primary_encoder(intel_connector);
1525                 if (!encoder->update_prepare)
1526                         continue;
1527
1528                 crtc = new_conn_state->crtc ?
1529                         to_intel_crtc(new_conn_state->crtc) : NULL;
1530                 encoder->update_prepare(state, encoder, crtc);
1531         }
1532 }
1533
1534 static void intel_encoders_update_complete(struct intel_atomic_state *state)
1535 {
1536         struct drm_connector_state *new_conn_state;
1537         struct drm_connector *connector;
1538         int i;
1539
1540         if (!state->modeset)
1541                 return;
1542
1543         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
1544                                         i) {
1545                 struct intel_connector *intel_connector;
1546                 struct intel_encoder *encoder;
1547                 struct intel_crtc *crtc;
1548
1549                 if (!intel_connector_needs_modeset(state, connector))
1550                         continue;
1551
1552                 intel_connector = to_intel_connector(connector);
1553                 encoder = intel_connector_primary_encoder(intel_connector);
1554                 if (!encoder->update_complete)
1555                         continue;
1556
1557                 crtc = new_conn_state->crtc ?
1558                         to_intel_crtc(new_conn_state->crtc) : NULL;
1559                 encoder->update_complete(state, encoder, crtc);
1560         }
1561 }
1562
1563 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1564                                           struct intel_crtc *crtc)
1565 {
1566         const struct intel_crtc_state *crtc_state =
1567                 intel_atomic_get_new_crtc_state(state, crtc);
1568         const struct drm_connector_state *conn_state;
1569         struct drm_connector *conn;
1570         int i;
1571
1572         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1573                 struct intel_encoder *encoder =
1574                         to_intel_encoder(conn_state->best_encoder);
1575
1576                 if (conn_state->crtc != &crtc->base)
1577                         continue;
1578
1579                 if (encoder->pre_pll_enable)
1580                         encoder->pre_pll_enable(state, encoder,
1581                                                 crtc_state, conn_state);
1582         }
1583 }
1584
1585 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1586                                       struct intel_crtc *crtc)
1587 {
1588         const struct intel_crtc_state *crtc_state =
1589                 intel_atomic_get_new_crtc_state(state, crtc);
1590         const struct drm_connector_state *conn_state;
1591         struct drm_connector *conn;
1592         int i;
1593
1594         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1595                 struct intel_encoder *encoder =
1596                         to_intel_encoder(conn_state->best_encoder);
1597
1598                 if (conn_state->crtc != &crtc->base)
1599                         continue;
1600
1601                 if (encoder->pre_enable)
1602                         encoder->pre_enable(state, encoder,
1603                                             crtc_state, conn_state);
1604         }
1605 }
1606
1607 static void intel_encoders_enable(struct intel_atomic_state *state,
1608                                   struct intel_crtc *crtc)
1609 {
1610         const struct intel_crtc_state *crtc_state =
1611                 intel_atomic_get_new_crtc_state(state, crtc);
1612         const struct drm_connector_state *conn_state;
1613         struct drm_connector *conn;
1614         int i;
1615
1616         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1617                 struct intel_encoder *encoder =
1618                         to_intel_encoder(conn_state->best_encoder);
1619
1620                 if (conn_state->crtc != &crtc->base)
1621                         continue;
1622
1623                 if (encoder->enable)
1624                         encoder->enable(state, encoder,
1625                                         crtc_state, conn_state);
1626                 intel_opregion_notify_encoder(encoder, true);
1627         }
1628 }
1629
1630 static void intel_encoders_disable(struct intel_atomic_state *state,
1631                                    struct intel_crtc *crtc)
1632 {
1633         const struct intel_crtc_state *old_crtc_state =
1634                 intel_atomic_get_old_crtc_state(state, crtc);
1635         const struct drm_connector_state *old_conn_state;
1636         struct drm_connector *conn;
1637         int i;
1638
1639         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1640                 struct intel_encoder *encoder =
1641                         to_intel_encoder(old_conn_state->best_encoder);
1642
1643                 if (old_conn_state->crtc != &crtc->base)
1644                         continue;
1645
1646                 intel_opregion_notify_encoder(encoder, false);
1647                 if (encoder->disable)
1648                         encoder->disable(state, encoder,
1649                                          old_crtc_state, old_conn_state);
1650         }
1651 }
1652
1653 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1654                                         struct intel_crtc *crtc)
1655 {
1656         const struct intel_crtc_state *old_crtc_state =
1657                 intel_atomic_get_old_crtc_state(state, crtc);
1658         const struct drm_connector_state *old_conn_state;
1659         struct drm_connector *conn;
1660         int i;
1661
1662         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1663                 struct intel_encoder *encoder =
1664                         to_intel_encoder(old_conn_state->best_encoder);
1665
1666                 if (old_conn_state->crtc != &crtc->base)
1667                         continue;
1668
1669                 if (encoder->post_disable)
1670                         encoder->post_disable(state, encoder,
1671                                               old_crtc_state, old_conn_state);
1672         }
1673 }
1674
1675 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1676                                             struct intel_crtc *crtc)
1677 {
1678         const struct intel_crtc_state *old_crtc_state =
1679                 intel_atomic_get_old_crtc_state(state, crtc);
1680         const struct drm_connector_state *old_conn_state;
1681         struct drm_connector *conn;
1682         int i;
1683
1684         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1685                 struct intel_encoder *encoder =
1686                         to_intel_encoder(old_conn_state->best_encoder);
1687
1688                 if (old_conn_state->crtc != &crtc->base)
1689                         continue;
1690
1691                 if (encoder->post_pll_disable)
1692                         encoder->post_pll_disable(state, encoder,
1693                                                   old_crtc_state, old_conn_state);
1694         }
1695 }
1696
1697 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1698                                        struct intel_crtc *crtc)
1699 {
1700         const struct intel_crtc_state *crtc_state =
1701                 intel_atomic_get_new_crtc_state(state, crtc);
1702         const struct drm_connector_state *conn_state;
1703         struct drm_connector *conn;
1704         int i;
1705
1706         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1707                 struct intel_encoder *encoder =
1708                         to_intel_encoder(conn_state->best_encoder);
1709
1710                 if (conn_state->crtc != &crtc->base)
1711                         continue;
1712
1713                 if (encoder->update_pipe)
1714                         encoder->update_pipe(state, encoder,
1715                                              crtc_state, conn_state);
1716         }
1717 }
1718
1719 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1720 {
1721         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1722         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1723
1724         plane->disable_arm(plane, crtc_state);
1725 }
1726
1727 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1728 {
1729         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1730         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1731
1732         if (crtc_state->has_pch_encoder) {
1733                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1734                                                &crtc_state->fdi_m_n);
1735         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1736                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1737                                                &crtc_state->dp_m_n);
1738                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1739                                                &crtc_state->dp_m2_n2);
1740         }
1741
1742         intel_set_transcoder_timings(crtc_state);
1743
1744         ilk_set_pipeconf(crtc_state);
1745 }
1746
1747 static void ilk_crtc_enable(struct intel_atomic_state *state,
1748                             struct intel_crtc *crtc)
1749 {
1750         const struct intel_crtc_state *new_crtc_state =
1751                 intel_atomic_get_new_crtc_state(state, crtc);
1752         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1753         enum pipe pipe = crtc->pipe;
1754
1755         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1756                 return;
1757
1758         /*
1759          * Sometimes spurious CPU pipe underruns happen during FDI
1760          * training, at least with VGA+HDMI cloning. Suppress them.
1761          *
1762          * On ILK we get an occasional spurious CPU pipe underruns
1763          * between eDP port A enable and vdd enable. Also PCH port
1764          * enable seems to result in the occasional CPU pipe underrun.
1765          *
1766          * Spurious PCH underruns also occur during PCH enabling.
1767          */
1768         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1769         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1770
1771         ilk_configure_cpu_transcoder(new_crtc_state);
1772
1773         intel_set_pipe_src_size(new_crtc_state);
1774
1775         crtc->active = true;
1776
1777         intel_encoders_pre_enable(state, crtc);
1778
1779         if (new_crtc_state->has_pch_encoder) {
1780                 ilk_pch_pre_enable(state, crtc);
1781         } else {
1782                 assert_fdi_tx_disabled(dev_priv, pipe);
1783                 assert_fdi_rx_disabled(dev_priv, pipe);
1784         }
1785
1786         ilk_pfit_enable(new_crtc_state);
1787
1788         /*
1789          * On ILK+ LUT must be loaded before the pipe is running but with
1790          * clocks enabled
1791          */
1792         intel_color_load_luts(new_crtc_state);
1793         intel_color_commit_noarm(new_crtc_state);
1794         intel_color_commit_arm(new_crtc_state);
1795         /* update DSPCNTR to configure gamma for pipe bottom color */
1796         intel_disable_primary_plane(new_crtc_state);
1797
1798         intel_initial_watermarks(state, crtc);
1799         intel_enable_transcoder(new_crtc_state);
1800
1801         if (new_crtc_state->has_pch_encoder)
1802                 ilk_pch_enable(state, crtc);
1803
1804         intel_crtc_vblank_on(new_crtc_state);
1805
1806         intel_encoders_enable(state, crtc);
1807
1808         if (HAS_PCH_CPT(dev_priv))
1809                 cpt_verify_modeset(dev_priv, pipe);
1810
1811         /*
1812          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1813          * And a second vblank wait is needed at least on ILK with
1814          * some interlaced HDMI modes. Let's do the double wait always
1815          * in case there are more corner cases we don't know about.
1816          */
1817         if (new_crtc_state->has_pch_encoder) {
1818                 intel_crtc_wait_for_next_vblank(crtc);
1819                 intel_crtc_wait_for_next_vblank(crtc);
1820         }
1821         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1822         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1823 }
1824
1825 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1826                                             enum pipe pipe, bool apply)
1827 {
1828         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1829         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1830
1831         if (apply)
1832                 val |= mask;
1833         else
1834                 val &= ~mask;
1835
1836         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1837 }
1838
1839 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1840 {
1841         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1842         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1843
1844         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1845                        HSW_LINETIME(crtc_state->linetime) |
1846                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1847 }
1848
1849 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1850 {
1851         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1852         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1853         enum transcoder transcoder = crtc_state->cpu_transcoder;
1854         i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
1855                          CHICKEN_TRANS(transcoder);
1856         u32 val;
1857
1858         val = intel_de_read(dev_priv, reg);
1859         val &= ~HSW_FRAME_START_DELAY_MASK;
1860         val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
1861         intel_de_write(dev_priv, reg, val);
1862 }
1863
1864 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1865                                          const struct intel_crtc_state *crtc_state)
1866 {
1867         struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1868
1869         /*
1870          * Enable sequence steps 1-7 on bigjoiner master
1871          */
1872         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1873                 intel_encoders_pre_pll_enable(state, master_crtc);
1874
1875         if (crtc_state->shared_dpll)
1876                 intel_enable_shared_dpll(crtc_state);
1877
1878         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1879                 intel_encoders_pre_enable(state, master_crtc);
1880 }
1881
1882 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1883 {
1884         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1885         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1886         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1887
1888         if (crtc_state->has_pch_encoder) {
1889                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1890                                                &crtc_state->fdi_m_n);
1891         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1892                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1893                                                &crtc_state->dp_m_n);
1894                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1895                                                &crtc_state->dp_m2_n2);
1896         }
1897
1898         intel_set_transcoder_timings(crtc_state);
1899
1900         if (cpu_transcoder != TRANSCODER_EDP)
1901                 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
1902                                crtc_state->pixel_multiplier - 1);
1903
1904         hsw_set_frame_start_delay(crtc_state);
1905
1906         hsw_set_transconf(crtc_state);
1907 }
1908
1909 static void hsw_crtc_enable(struct intel_atomic_state *state,
1910                             struct intel_crtc *crtc)
1911 {
1912         const struct intel_crtc_state *new_crtc_state =
1913                 intel_atomic_get_new_crtc_state(state, crtc);
1914         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1915         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1916         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1917         bool psl_clkgate_wa;
1918
1919         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1920                 return;
1921
1922         if (!new_crtc_state->bigjoiner_pipes) {
1923                 intel_encoders_pre_pll_enable(state, crtc);
1924
1925                 if (new_crtc_state->shared_dpll)
1926                         intel_enable_shared_dpll(new_crtc_state);
1927
1928                 intel_encoders_pre_enable(state, crtc);
1929         } else {
1930                 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1931         }
1932
1933         intel_dsc_enable(new_crtc_state);
1934
1935         if (DISPLAY_VER(dev_priv) >= 13)
1936                 intel_uncompressed_joiner_enable(new_crtc_state);
1937
1938         intel_set_pipe_src_size(new_crtc_state);
1939         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1940                 bdw_set_pipemisc(new_crtc_state);
1941
1942         if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1943             !transcoder_is_dsi(cpu_transcoder))
1944                 hsw_configure_cpu_transcoder(new_crtc_state);
1945
1946         crtc->active = true;
1947
1948         /* Display WA #1180: WaDisableScalarClockGating: glk */
1949         psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1950                 new_crtc_state->pch_pfit.enabled;
1951         if (psl_clkgate_wa)
1952                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1953
1954         if (DISPLAY_VER(dev_priv) >= 9)
1955                 skl_pfit_enable(new_crtc_state);
1956         else
1957                 ilk_pfit_enable(new_crtc_state);
1958
1959         /*
1960          * On ILK+ LUT must be loaded before the pipe is running but with
1961          * clocks enabled
1962          */
1963         intel_color_load_luts(new_crtc_state);
1964         intel_color_commit_noarm(new_crtc_state);
1965         intel_color_commit_arm(new_crtc_state);
1966         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1967         if (DISPLAY_VER(dev_priv) < 9)
1968                 intel_disable_primary_plane(new_crtc_state);
1969
1970         hsw_set_linetime_wm(new_crtc_state);
1971
1972         if (DISPLAY_VER(dev_priv) >= 11)
1973                 icl_set_pipe_chicken(new_crtc_state);
1974
1975         intel_initial_watermarks(state, crtc);
1976
1977         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1978                 intel_crtc_vblank_on(new_crtc_state);
1979
1980         intel_encoders_enable(state, crtc);
1981
1982         if (psl_clkgate_wa) {
1983                 intel_crtc_wait_for_next_vblank(crtc);
1984                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1985         }
1986
1987         /* If we change the relative order between pipe/planes enabling, we need
1988          * to change the workaround. */
1989         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1990         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1991                 struct intel_crtc *wa_crtc;
1992
1993                 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1994
1995                 intel_crtc_wait_for_next_vblank(wa_crtc);
1996                 intel_crtc_wait_for_next_vblank(wa_crtc);
1997         }
1998 }
1999
2000 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2001 {
2002         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2003         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2004         enum pipe pipe = crtc->pipe;
2005
2006         /* To avoid upsetting the power well on haswell only disable the pfit if
2007          * it's in use. The hw state code will make sure we get this right. */
2008         if (!old_crtc_state->pch_pfit.enabled)
2009                 return;
2010
2011         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
2012         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
2013         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
2014 }
2015
2016 static void ilk_crtc_disable(struct intel_atomic_state *state,
2017                              struct intel_crtc *crtc)
2018 {
2019         const struct intel_crtc_state *old_crtc_state =
2020                 intel_atomic_get_old_crtc_state(state, crtc);
2021         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2022         enum pipe pipe = crtc->pipe;
2023
2024         /*
2025          * Sometimes spurious CPU pipe underruns happen when the
2026          * pipe is already disabled, but FDI RX/TX is still enabled.
2027          * Happens at least with VGA+HDMI cloning. Suppress them.
2028          */
2029         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2030         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
2031
2032         intel_encoders_disable(state, crtc);
2033
2034         intel_crtc_vblank_off(old_crtc_state);
2035
2036         intel_disable_transcoder(old_crtc_state);
2037
2038         ilk_pfit_disable(old_crtc_state);
2039
2040         if (old_crtc_state->has_pch_encoder)
2041                 ilk_pch_disable(state, crtc);
2042
2043         intel_encoders_post_disable(state, crtc);
2044
2045         if (old_crtc_state->has_pch_encoder)
2046                 ilk_pch_post_disable(state, crtc);
2047
2048         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2049         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
2050 }
2051
2052 static void hsw_crtc_disable(struct intel_atomic_state *state,
2053                              struct intel_crtc *crtc)
2054 {
2055         const struct intel_crtc_state *old_crtc_state =
2056                 intel_atomic_get_old_crtc_state(state, crtc);
2057
2058         /*
2059          * FIXME collapse everything to one hook.
2060          * Need care with mst->ddi interactions.
2061          */
2062         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
2063                 intel_encoders_disable(state, crtc);
2064                 intel_encoders_post_disable(state, crtc);
2065         }
2066 }
2067
2068 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
2069 {
2070         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2071         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2072
2073         if (!crtc_state->gmch_pfit.control)
2074                 return;
2075
2076         /*
2077          * The panel fitter should only be adjusted whilst the pipe is disabled,
2078          * according to register description and PRM.
2079          */
2080         drm_WARN_ON(&dev_priv->drm,
2081                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
2082         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2083
2084         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
2085                        crtc_state->gmch_pfit.pgm_ratios);
2086         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
2087
2088         /* Border color in case we don't scale up to the full screen. Black by
2089          * default, change to something else for debugging. */
2090         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
2091 }
2092
2093 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
2094 {
2095         if (phy == PHY_NONE)
2096                 return false;
2097         else if (IS_ALDERLAKE_S(dev_priv))
2098                 return phy <= PHY_E;
2099         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
2100                 return phy <= PHY_D;
2101         else if (IS_JSL_EHL(dev_priv))
2102                 return phy <= PHY_C;
2103         else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
2104                 return phy <= PHY_B;
2105         else
2106                 /*
2107                  * DG2 outputs labelled as "combo PHY" in the bspec use
2108                  * SNPS PHYs with completely different programming,
2109                  * hence we always return false here.
2110                  */
2111                 return false;
2112 }
2113
2114 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
2115 {
2116         if (IS_DG2(dev_priv))
2117                 /* DG2's "TC1" output uses a SNPS PHY */
2118                 return false;
2119         else if (IS_ALDERLAKE_P(dev_priv))
2120                 return phy >= PHY_F && phy <= PHY_I;
2121         else if (IS_TIGERLAKE(dev_priv))
2122                 return phy >= PHY_D && phy <= PHY_I;
2123         else if (IS_ICELAKE(dev_priv))
2124                 return phy >= PHY_C && phy <= PHY_F;
2125         else
2126                 return false;
2127 }
2128
2129 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
2130 {
2131         if (phy == PHY_NONE)
2132                 return false;
2133         else if (IS_DG2(dev_priv))
2134                 /*
2135                  * All four "combo" ports and the TC1 port (PHY E) use
2136                  * Synopsis PHYs.
2137                  */
2138                 return phy <= PHY_E;
2139
2140         return false;
2141 }
2142
2143 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
2144 {
2145         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
2146                 return PHY_D + port - PORT_D_XELPD;
2147         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
2148                 return PHY_F + port - PORT_TC1;
2149         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
2150                 return PHY_B + port - PORT_TC1;
2151         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
2152                 return PHY_C + port - PORT_TC1;
2153         else if (IS_JSL_EHL(i915) && port == PORT_D)
2154                 return PHY_A;
2155
2156         return PHY_A + port - PORT_A;
2157 }
2158
2159 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
2160 {
2161         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
2162                 return TC_PORT_NONE;
2163
2164         if (DISPLAY_VER(dev_priv) >= 12)
2165                 return TC_PORT_1 + port - PORT_TC1;
2166         else
2167                 return TC_PORT_1 + port - PORT_C;
2168 }
2169
2170 enum intel_display_power_domain
2171 intel_aux_power_domain(struct intel_digital_port *dig_port)
2172 {
2173         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
2174
2175         if (intel_tc_port_in_tbt_alt_mode(dig_port))
2176                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
2177
2178         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
2179 }
2180
2181 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2182                                    struct intel_power_domain_mask *mask)
2183 {
2184         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2185         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2186         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2187         struct drm_encoder *encoder;
2188         enum pipe pipe = crtc->pipe;
2189
2190         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
2191
2192         if (!crtc_state->hw.active)
2193                 return;
2194
2195         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
2196         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
2197         if (crtc_state->pch_pfit.enabled ||
2198             crtc_state->pch_pfit.force_thru)
2199                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
2200
2201         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
2202                                   crtc_state->uapi.encoder_mask) {
2203                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2204
2205                 set_bit(intel_encoder->power_domain, mask->bits);
2206         }
2207
2208         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2209                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
2210
2211         if (crtc_state->shared_dpll)
2212                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
2213
2214         if (crtc_state->dsc.compression_enable)
2215                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
2216 }
2217
2218 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2219                                           struct intel_power_domain_mask *old_domains)
2220 {
2221         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2222         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2223         enum intel_display_power_domain domain;
2224         struct intel_power_domain_mask domains, new_domains;
2225
2226         get_crtc_power_domains(crtc_state, &domains);
2227
2228         bitmap_andnot(new_domains.bits,
2229                       domains.bits,
2230                       crtc->enabled_power_domains.mask.bits,
2231                       POWER_DOMAIN_NUM);
2232         bitmap_andnot(old_domains->bits,
2233                       crtc->enabled_power_domains.mask.bits,
2234                       domains.bits,
2235                       POWER_DOMAIN_NUM);
2236
2237         for_each_power_domain(domain, &new_domains)
2238                 intel_display_power_get_in_set(dev_priv,
2239                                                &crtc->enabled_power_domains,
2240                                                domain);
2241 }
2242
2243 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2244                                           struct intel_power_domain_mask *domains)
2245 {
2246         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
2247                                             &crtc->enabled_power_domains,
2248                                             domains);
2249 }
2250
2251 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2252 {
2253         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2254         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2255
2256         if (intel_crtc_has_dp_encoder(crtc_state)) {
2257                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2258                                                &crtc_state->dp_m_n);
2259                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2260                                                &crtc_state->dp_m2_n2);
2261         }
2262
2263         intel_set_transcoder_timings(crtc_state);
2264
2265         i9xx_set_pipeconf(crtc_state);
2266 }
2267
2268 static void valleyview_crtc_enable(struct intel_atomic_state *state,
2269                                    struct intel_crtc *crtc)
2270 {
2271         const struct intel_crtc_state *new_crtc_state =
2272                 intel_atomic_get_new_crtc_state(state, crtc);
2273         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2274         enum pipe pipe = crtc->pipe;
2275
2276         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2277                 return;
2278
2279         i9xx_configure_cpu_transcoder(new_crtc_state);
2280
2281         intel_set_pipe_src_size(new_crtc_state);
2282
2283         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2284                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
2285                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
2286         }
2287
2288         crtc->active = true;
2289
2290         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2291
2292         intel_encoders_pre_pll_enable(state, crtc);
2293
2294         if (IS_CHERRYVIEW(dev_priv))
2295                 chv_enable_pll(new_crtc_state);
2296         else
2297                 vlv_enable_pll(new_crtc_state);
2298
2299         intel_encoders_pre_enable(state, crtc);
2300
2301         i9xx_pfit_enable(new_crtc_state);
2302
2303         intel_color_load_luts(new_crtc_state);
2304         intel_color_commit_noarm(new_crtc_state);
2305         intel_color_commit_arm(new_crtc_state);
2306         /* update DSPCNTR to configure gamma for pipe bottom color */
2307         intel_disable_primary_plane(new_crtc_state);
2308
2309         intel_initial_watermarks(state, crtc);
2310         intel_enable_transcoder(new_crtc_state);
2311
2312         intel_crtc_vblank_on(new_crtc_state);
2313
2314         intel_encoders_enable(state, crtc);
2315 }
2316
2317 static void i9xx_crtc_enable(struct intel_atomic_state *state,
2318                              struct intel_crtc *crtc)
2319 {
2320         const struct intel_crtc_state *new_crtc_state =
2321                 intel_atomic_get_new_crtc_state(state, crtc);
2322         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2323         enum pipe pipe = crtc->pipe;
2324
2325         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2326                 return;
2327
2328         i9xx_configure_cpu_transcoder(new_crtc_state);
2329
2330         intel_set_pipe_src_size(new_crtc_state);
2331
2332         crtc->active = true;
2333
2334         if (DISPLAY_VER(dev_priv) != 2)
2335                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2336
2337         intel_encoders_pre_enable(state, crtc);
2338
2339         i9xx_enable_pll(new_crtc_state);
2340
2341         i9xx_pfit_enable(new_crtc_state);
2342
2343         intel_color_load_luts(new_crtc_state);
2344         intel_color_commit_noarm(new_crtc_state);
2345         intel_color_commit_arm(new_crtc_state);
2346         /* update DSPCNTR to configure gamma for pipe bottom color */
2347         intel_disable_primary_plane(new_crtc_state);
2348
2349         if (!intel_initial_watermarks(state, crtc))
2350                 intel_update_watermarks(dev_priv);
2351         intel_enable_transcoder(new_crtc_state);
2352
2353         intel_crtc_vblank_on(new_crtc_state);
2354
2355         intel_encoders_enable(state, crtc);
2356
2357         /* prevents spurious underruns */
2358         if (DISPLAY_VER(dev_priv) == 2)
2359                 intel_crtc_wait_for_next_vblank(crtc);
2360 }
2361
2362 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2363 {
2364         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2365         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2366
2367         if (!old_crtc_state->gmch_pfit.control)
2368                 return;
2369
2370         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2371
2372         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2373                     intel_de_read(dev_priv, PFIT_CONTROL));
2374         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2375 }
2376
2377 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2378                               struct intel_crtc *crtc)
2379 {
2380         struct intel_crtc_state *old_crtc_state =
2381                 intel_atomic_get_old_crtc_state(state, crtc);
2382         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2383         enum pipe pipe = crtc->pipe;
2384
2385         /*
2386          * On gen2 planes are double buffered but the pipe isn't, so we must
2387          * wait for planes to fully turn off before disabling the pipe.
2388          */
2389         if (DISPLAY_VER(dev_priv) == 2)
2390                 intel_crtc_wait_for_next_vblank(crtc);
2391
2392         intel_encoders_disable(state, crtc);
2393
2394         intel_crtc_vblank_off(old_crtc_state);
2395
2396         intel_disable_transcoder(old_crtc_state);
2397
2398         i9xx_pfit_disable(old_crtc_state);
2399
2400         intel_encoders_post_disable(state, crtc);
2401
2402         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2403                 if (IS_CHERRYVIEW(dev_priv))
2404                         chv_disable_pll(dev_priv, pipe);
2405                 else if (IS_VALLEYVIEW(dev_priv))
2406                         vlv_disable_pll(dev_priv, pipe);
2407                 else
2408                         i9xx_disable_pll(old_crtc_state);
2409         }
2410
2411         intel_encoders_post_pll_disable(state, crtc);
2412
2413         if (DISPLAY_VER(dev_priv) != 2)
2414                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2415
2416         if (!dev_priv->display.funcs.wm->initial_watermarks)
2417                 intel_update_watermarks(dev_priv);
2418
2419         /* clock the pipe down to 640x480@60 to potentially save power */
2420         if (IS_I830(dev_priv))
2421                 i830_enable_pipe(dev_priv, pipe);
2422 }
2423
2424
2425 /*
2426  * turn all crtc's off, but do not adjust state
2427  * This has to be paired with a call to intel_modeset_setup_hw_state.
2428  */
2429 int intel_display_suspend(struct drm_device *dev)
2430 {
2431         struct drm_i915_private *dev_priv = to_i915(dev);
2432         struct drm_atomic_state *state;
2433         int ret;
2434
2435         if (!HAS_DISPLAY(dev_priv))
2436                 return 0;
2437
2438         state = drm_atomic_helper_suspend(dev);
2439         ret = PTR_ERR_OR_ZERO(state);
2440         if (ret)
2441                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2442                         ret);
2443         else
2444                 dev_priv->modeset_restore_state = state;
2445         return ret;
2446 }
2447
2448 void intel_encoder_destroy(struct drm_encoder *encoder)
2449 {
2450         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2451
2452         drm_encoder_cleanup(encoder);
2453         kfree(intel_encoder);
2454 }
2455
2456 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2457 {
2458         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2459
2460         /* GDG double wide on either pipe, otherwise pipe A only */
2461         return DISPLAY_VER(dev_priv) < 4 &&
2462                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2463 }
2464
2465 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2466 {
2467         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2468         struct drm_rect src;
2469
2470         /*
2471          * We only use IF-ID interlacing. If we ever use
2472          * PF-ID we'll need to adjust the pixel_rate here.
2473          */
2474
2475         if (!crtc_state->pch_pfit.enabled)
2476                 return pixel_rate;
2477
2478         drm_rect_init(&src, 0, 0,
2479                       drm_rect_width(&crtc_state->pipe_src) << 16,
2480                       drm_rect_height(&crtc_state->pipe_src) << 16);
2481
2482         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2483                                    pixel_rate);
2484 }
2485
2486 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2487                                          const struct drm_display_mode *timings)
2488 {
2489         mode->hdisplay = timings->crtc_hdisplay;
2490         mode->htotal = timings->crtc_htotal;
2491         mode->hsync_start = timings->crtc_hsync_start;
2492         mode->hsync_end = timings->crtc_hsync_end;
2493
2494         mode->vdisplay = timings->crtc_vdisplay;
2495         mode->vtotal = timings->crtc_vtotal;
2496         mode->vsync_start = timings->crtc_vsync_start;
2497         mode->vsync_end = timings->crtc_vsync_end;
2498
2499         mode->flags = timings->flags;
2500         mode->type = DRM_MODE_TYPE_DRIVER;
2501
2502         mode->clock = timings->crtc_clock;
2503
2504         drm_mode_set_name(mode);
2505 }
2506
2507 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2508 {
2509         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2510
2511         if (HAS_GMCH(dev_priv))
2512                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2513                 crtc_state->pixel_rate =
2514                         crtc_state->hw.pipe_mode.crtc_clock;
2515         else
2516                 crtc_state->pixel_rate =
2517                         ilk_pipe_pixel_rate(crtc_state);
2518 }
2519
2520 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2521                                            struct drm_display_mode *mode)
2522 {
2523         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2524
2525         if (num_pipes < 2)
2526                 return;
2527
2528         mode->crtc_clock /= num_pipes;
2529         mode->crtc_hdisplay /= num_pipes;
2530         mode->crtc_hblank_start /= num_pipes;
2531         mode->crtc_hblank_end /= num_pipes;
2532         mode->crtc_hsync_start /= num_pipes;
2533         mode->crtc_hsync_end /= num_pipes;
2534         mode->crtc_htotal /= num_pipes;
2535 }
2536
2537 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2538                                           struct drm_display_mode *mode)
2539 {
2540         int overlap = crtc_state->splitter.pixel_overlap;
2541         int n = crtc_state->splitter.link_count;
2542
2543         if (!crtc_state->splitter.enable)
2544                 return;
2545
2546         /*
2547          * eDP MSO uses segment timings from EDID for transcoder
2548          * timings, but full mode for everything else.
2549          *
2550          * h_full = (h_segment - pixel_overlap) * link_count
2551          */
2552         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2553         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2554         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2555         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2556         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2557         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2558         mode->crtc_clock *= n;
2559 }
2560
2561 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2562 {
2563         struct drm_display_mode *mode = &crtc_state->hw.mode;
2564         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2565         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2566
2567         /*
2568          * Start with the adjusted_mode crtc timings, which
2569          * have been filled with the transcoder timings.
2570          */
2571         drm_mode_copy(pipe_mode, adjusted_mode);
2572
2573         /* Expand MSO per-segment transcoder timings to full */
2574         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2575
2576         /*
2577          * We want the full numbers in adjusted_mode normal timings,
2578          * adjusted_mode crtc timings are left with the raw transcoder
2579          * timings.
2580          */
2581         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2582
2583         /* Populate the "user" mode with full numbers */
2584         drm_mode_copy(mode, pipe_mode);
2585         intel_mode_from_crtc_timings(mode, mode);
2586         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2587                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2588         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2589
2590         /* Derive per-pipe timings in case bigjoiner is used */
2591         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2592         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2593
2594         intel_crtc_compute_pixel_rate(crtc_state);
2595 }
2596
2597 void intel_encoder_get_config(struct intel_encoder *encoder,
2598                               struct intel_crtc_state *crtc_state)
2599 {
2600         encoder->get_config(encoder, crtc_state);
2601
2602         intel_crtc_readout_derived_state(crtc_state);
2603 }
2604
2605 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2606 {
2607         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2608         int width, height;
2609
2610         if (num_pipes < 2)
2611                 return;
2612
2613         width = drm_rect_width(&crtc_state->pipe_src);
2614         height = drm_rect_height(&crtc_state->pipe_src);
2615
2616         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2617                       width / num_pipes, height);
2618 }
2619
2620 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2621 {
2622         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2623         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2624
2625         intel_bigjoiner_compute_pipe_src(crtc_state);
2626
2627         /*
2628          * Pipe horizontal size must be even in:
2629          * - DVO ganged mode
2630          * - LVDS dual channel mode
2631          * - Double wide pipe
2632          */
2633         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2634                 if (crtc_state->double_wide) {
2635                         drm_dbg_kms(&i915->drm,
2636                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2637                                     crtc->base.base.id, crtc->base.name);
2638                         return -EINVAL;
2639                 }
2640
2641                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2642                     intel_is_dual_link_lvds(i915)) {
2643                         drm_dbg_kms(&i915->drm,
2644                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2645                                     crtc->base.base.id, crtc->base.name);
2646                         return -EINVAL;
2647                 }
2648         }
2649
2650         return 0;
2651 }
2652
2653 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2654 {
2655         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2656         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2657         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2658         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2659         int clock_limit = i915->max_dotclk_freq;
2660
2661         /*
2662          * Start with the adjusted_mode crtc timings, which
2663          * have been filled with the transcoder timings.
2664          */
2665         drm_mode_copy(pipe_mode, adjusted_mode);
2666
2667         /* Expand MSO per-segment transcoder timings to full */
2668         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2669
2670         /* Derive per-pipe timings in case bigjoiner is used */
2671         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2672         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2673
2674         if (DISPLAY_VER(i915) < 4) {
2675                 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2676
2677                 /*
2678                  * Enable double wide mode when the dot clock
2679                  * is > 90% of the (display) core speed.
2680                  */
2681                 if (intel_crtc_supports_double_wide(crtc) &&
2682                     pipe_mode->crtc_clock > clock_limit) {
2683                         clock_limit = i915->max_dotclk_freq;
2684                         crtc_state->double_wide = true;
2685                 }
2686         }
2687
2688         if (pipe_mode->crtc_clock > clock_limit) {
2689                 drm_dbg_kms(&i915->drm,
2690                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2691                             crtc->base.base.id, crtc->base.name,
2692                             pipe_mode->crtc_clock, clock_limit,
2693                             str_yes_no(crtc_state->double_wide));
2694                 return -EINVAL;
2695         }
2696
2697         return 0;
2698 }
2699
2700 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2701                                      struct intel_crtc *crtc)
2702 {
2703         struct intel_crtc_state *crtc_state =
2704                 intel_atomic_get_new_crtc_state(state, crtc);
2705         int ret;
2706
2707         ret = intel_dpll_crtc_compute_clock(state, crtc);
2708         if (ret)
2709                 return ret;
2710
2711         ret = intel_crtc_compute_pipe_src(crtc_state);
2712         if (ret)
2713                 return ret;
2714
2715         ret = intel_crtc_compute_pipe_mode(crtc_state);
2716         if (ret)
2717                 return ret;
2718
2719         intel_crtc_compute_pixel_rate(crtc_state);
2720
2721         if (crtc_state->has_pch_encoder)
2722                 return ilk_fdi_compute_config(crtc, crtc_state);
2723
2724         return 0;
2725 }
2726
2727 static void
2728 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2729 {
2730         while (*num > DATA_LINK_M_N_MASK ||
2731                *den > DATA_LINK_M_N_MASK) {
2732                 *num >>= 1;
2733                 *den >>= 1;
2734         }
2735 }
2736
2737 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2738                         u32 m, u32 n, u32 constant_n)
2739 {
2740         if (constant_n)
2741                 *ret_n = constant_n;
2742         else
2743                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2744
2745         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2746         intel_reduce_m_n_ratio(ret_m, ret_n);
2747 }
2748
2749 void
2750 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2751                        int pixel_clock, int link_clock,
2752                        struct intel_link_m_n *m_n,
2753                        bool fec_enable)
2754 {
2755         u32 data_clock = bits_per_pixel * pixel_clock;
2756
2757         if (fec_enable)
2758                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
2759
2760         /*
2761          * Windows/BIOS uses fixed M/N values always. Follow suit.
2762          *
2763          * Also several DP dongles in particular seem to be fussy
2764          * about too large link M/N values. Presumably the 20bit
2765          * value used by Windows/BIOS is acceptable to everyone.
2766          */
2767         m_n->tu = 64;
2768         compute_m_n(&m_n->data_m, &m_n->data_n,
2769                     data_clock, link_clock * nlanes * 8,
2770                     0x8000000);
2771
2772         compute_m_n(&m_n->link_m, &m_n->link_n,
2773                     pixel_clock, link_clock,
2774                     0x80000);
2775 }
2776
2777 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2778 {
2779         /*
2780          * There may be no VBT; and if the BIOS enabled SSC we can
2781          * just keep using it to avoid unnecessary flicker.  Whereas if the
2782          * BIOS isn't using it, don't assume it will work even if the VBT
2783          * indicates as much.
2784          */
2785         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2786                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2787                                                        PCH_DREF_CONTROL) &
2788                         DREF_SSC1_ENABLE;
2789
2790                 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2791                         drm_dbg_kms(&dev_priv->drm,
2792                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2793                                     str_enabled_disabled(bios_lvds_use_ssc),
2794                                     str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2795                         dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2796                 }
2797         }
2798 }
2799
2800 void intel_zero_m_n(struct intel_link_m_n *m_n)
2801 {
2802         /* corresponds to 0 register value */
2803         memset(m_n, 0, sizeof(*m_n));
2804         m_n->tu = 1;
2805 }
2806
2807 void intel_set_m_n(struct drm_i915_private *i915,
2808                    const struct intel_link_m_n *m_n,
2809                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2810                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2811 {
2812         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2813         intel_de_write(i915, data_n_reg, m_n->data_n);
2814         intel_de_write(i915, link_m_reg, m_n->link_m);
2815         /*
2816          * On BDW+ writing LINK_N arms the double buffered update
2817          * of all the M/N registers, so it must be written last.
2818          */
2819         intel_de_write(i915, link_n_reg, m_n->link_n);
2820 }
2821
2822 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2823                                     enum transcoder transcoder)
2824 {
2825         if (IS_HASWELL(dev_priv))
2826                 return transcoder == TRANSCODER_EDP;
2827
2828         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2829 }
2830
2831 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2832                                     enum transcoder transcoder,
2833                                     const struct intel_link_m_n *m_n)
2834 {
2835         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2836         enum pipe pipe = crtc->pipe;
2837
2838         if (DISPLAY_VER(dev_priv) >= 5)
2839                 intel_set_m_n(dev_priv, m_n,
2840                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2841                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2842         else
2843                 intel_set_m_n(dev_priv, m_n,
2844                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2845                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2846 }
2847
2848 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2849                                     enum transcoder transcoder,
2850                                     const struct intel_link_m_n *m_n)
2851 {
2852         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2853
2854         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2855                 return;
2856
2857         intel_set_m_n(dev_priv, m_n,
2858                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2859                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2860 }
2861
2862 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2863 {
2864         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2865         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2866         enum pipe pipe = crtc->pipe;
2867         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2868         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2869         u32 crtc_vtotal, crtc_vblank_end;
2870         int vsyncshift = 0;
2871
2872         /* We need to be careful not to changed the adjusted mode, for otherwise
2873          * the hw state checker will get angry at the mismatch. */
2874         crtc_vtotal = adjusted_mode->crtc_vtotal;
2875         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2876
2877         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2878                 /* the chip adds 2 halflines automatically */
2879                 crtc_vtotal -= 1;
2880                 crtc_vblank_end -= 1;
2881
2882                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2883                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2884                 else
2885                         vsyncshift = adjusted_mode->crtc_hsync_start -
2886                                 adjusted_mode->crtc_htotal / 2;
2887                 if (vsyncshift < 0)
2888                         vsyncshift += adjusted_mode->crtc_htotal;
2889         }
2890
2891         if (DISPLAY_VER(dev_priv) > 3)
2892                 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
2893                                vsyncshift);
2894
2895         intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
2896                        (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
2897         intel_de_write(dev_priv, HBLANK(cpu_transcoder),
2898                        (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
2899         intel_de_write(dev_priv, HSYNC(cpu_transcoder),
2900                        (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
2901
2902         intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
2903                        (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
2904         intel_de_write(dev_priv, VBLANK(cpu_transcoder),
2905                        (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
2906         intel_de_write(dev_priv, VSYNC(cpu_transcoder),
2907                        (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
2908
2909         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2910          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2911          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2912          * bits. */
2913         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2914             (pipe == PIPE_B || pipe == PIPE_C))
2915                 intel_de_write(dev_priv, VTOTAL(pipe),
2916                                intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
2917
2918 }
2919
2920 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2921 {
2922         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2923         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2924         int width = drm_rect_width(&crtc_state->pipe_src);
2925         int height = drm_rect_height(&crtc_state->pipe_src);
2926         enum pipe pipe = crtc->pipe;
2927
2928         /* pipesrc controls the size that is scaled from, which should
2929          * always be the user's requested size.
2930          */
2931         intel_de_write(dev_priv, PIPESRC(pipe),
2932                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2933 }
2934
2935 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2936 {
2937         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2938         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2939
2940         if (DISPLAY_VER(dev_priv) == 2)
2941                 return false;
2942
2943         if (DISPLAY_VER(dev_priv) >= 9 ||
2944             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2945                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
2946         else
2947                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
2948 }
2949
2950 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2951                                          struct intel_crtc_state *pipe_config)
2952 {
2953         struct drm_device *dev = crtc->base.dev;
2954         struct drm_i915_private *dev_priv = to_i915(dev);
2955         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2956         u32 tmp;
2957
2958         tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
2959         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
2960         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
2961
2962         if (!transcoder_is_dsi(cpu_transcoder)) {
2963                 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
2964                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
2965                                                         (tmp & 0xffff) + 1;
2966                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
2967                                                 ((tmp >> 16) & 0xffff) + 1;
2968         }
2969         tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
2970         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
2971         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
2972
2973         tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
2974         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
2975         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
2976
2977         if (!transcoder_is_dsi(cpu_transcoder)) {
2978                 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
2979                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
2980                                                         (tmp & 0xffff) + 1;
2981                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
2982                                                 ((tmp >> 16) & 0xffff) + 1;
2983         }
2984         tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
2985         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
2986         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
2987
2988         if (intel_pipe_is_interlaced(pipe_config)) {
2989                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
2990                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
2991                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
2992         }
2993 }
2994
2995 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2996 {
2997         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2998         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2999         enum pipe master_pipe, pipe = crtc->pipe;
3000         int width;
3001
3002         if (num_pipes < 2)
3003                 return;
3004
3005         master_pipe = bigjoiner_master_pipe(crtc_state);
3006         width = drm_rect_width(&crtc_state->pipe_src);
3007
3008         drm_rect_translate_to(&crtc_state->pipe_src,
3009                               (pipe - master_pipe) * width, 0);
3010 }
3011
3012 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
3013                                     struct intel_crtc_state *pipe_config)
3014 {
3015         struct drm_device *dev = crtc->base.dev;
3016         struct drm_i915_private *dev_priv = to_i915(dev);
3017         u32 tmp;
3018
3019         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
3020
3021         drm_rect_init(&pipe_config->pipe_src, 0, 0,
3022                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
3023                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
3024
3025         intel_bigjoiner_adjust_pipe_src(pipe_config);
3026 }
3027
3028 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
3029 {
3030         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3031         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3032         u32 pipeconf = 0;
3033
3034         /*
3035          * - We keep both pipes enabled on 830
3036          * - During modeset the pipe is still disabled and must remain so
3037          * - During fastset the pipe is already enabled and must remain so
3038          */
3039         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
3040                 pipeconf |= PIPECONF_ENABLE;
3041
3042         if (crtc_state->double_wide)
3043                 pipeconf |= PIPECONF_DOUBLE_WIDE;
3044
3045         /* only g4x and later have fancy bpc/dither controls */
3046         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3047             IS_CHERRYVIEW(dev_priv)) {
3048                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
3049                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
3050                         pipeconf |= PIPECONF_DITHER_EN |
3051                                     PIPECONF_DITHER_TYPE_SP;
3052
3053                 switch (crtc_state->pipe_bpp) {
3054                 default:
3055                         /* Case prevented by intel_choose_pipe_bpp_dither. */
3056                         MISSING_CASE(crtc_state->pipe_bpp);
3057                         fallthrough;
3058                 case 18:
3059                         pipeconf |= PIPECONF_BPC_6;
3060                         break;
3061                 case 24:
3062                         pipeconf |= PIPECONF_BPC_8;
3063                         break;
3064                 case 30:
3065                         pipeconf |= PIPECONF_BPC_10;
3066                         break;
3067                 }
3068         }
3069
3070         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3071                 if (DISPLAY_VER(dev_priv) < 4 ||
3072                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3073                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3074                 else
3075                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
3076         } else {
3077                 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
3078         }
3079
3080         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3081              crtc_state->limited_color_range)
3082                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
3083
3084         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
3085
3086         pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3087
3088         intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
3089         intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
3090 }
3091
3092 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
3093 {
3094         if (IS_I830(dev_priv))
3095                 return false;
3096
3097         return DISPLAY_VER(dev_priv) >= 4 ||
3098                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
3099 }
3100
3101 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
3102 {
3103         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3104         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3105         u32 tmp;
3106
3107         if (!i9xx_has_pfit(dev_priv))
3108                 return;
3109
3110         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
3111         if (!(tmp & PFIT_ENABLE))
3112                 return;
3113
3114         /* Check whether the pfit is attached to our pipe. */
3115         if (DISPLAY_VER(dev_priv) < 4) {
3116                 if (crtc->pipe != PIPE_B)
3117                         return;
3118         } else {
3119                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
3120                         return;
3121         }
3122
3123         crtc_state->gmch_pfit.control = tmp;
3124         crtc_state->gmch_pfit.pgm_ratios =
3125                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
3126 }
3127
3128 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
3129                                struct intel_crtc_state *pipe_config)
3130 {
3131         struct drm_device *dev = crtc->base.dev;
3132         struct drm_i915_private *dev_priv = to_i915(dev);
3133         enum pipe pipe = crtc->pipe;
3134         struct dpll clock;
3135         u32 mdiv;
3136         int refclk = 100000;
3137
3138         /* In case of DSI, DPLL will not be used */
3139         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
3140                 return;
3141
3142         vlv_dpio_get(dev_priv);
3143         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
3144         vlv_dpio_put(dev_priv);
3145
3146         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
3147         clock.m2 = mdiv & DPIO_M2DIV_MASK;
3148         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
3149         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
3150         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
3151
3152         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
3153 }
3154
3155 static void chv_crtc_clock_get(struct intel_crtc *crtc,
3156                                struct intel_crtc_state *pipe_config)
3157 {
3158         struct drm_device *dev = crtc->base.dev;
3159         struct drm_i915_private *dev_priv = to_i915(dev);
3160         enum pipe pipe = crtc->pipe;
3161         enum dpio_channel port = vlv_pipe_to_channel(pipe);
3162         struct dpll clock;
3163         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
3164         int refclk = 100000;
3165
3166         /* In case of DSI, DPLL will not be used */
3167         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
3168                 return;
3169
3170         vlv_dpio_get(dev_priv);
3171         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
3172         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
3173         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
3174         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
3175         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
3176         vlv_dpio_put(dev_priv);
3177
3178         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
3179         clock.m2 = (pll_dw0 & 0xff) << 22;
3180         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
3181                 clock.m2 |= pll_dw2 & 0x3fffff;
3182         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
3183         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
3184         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
3185
3186         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
3187 }
3188
3189 static enum intel_output_format
3190 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
3191 {
3192         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3193         u32 tmp;
3194
3195         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
3196
3197         if (tmp & PIPEMISC_YUV420_ENABLE) {
3198                 /* We support 4:2:0 in full blend mode only */
3199                 drm_WARN_ON(&dev_priv->drm,
3200                             (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
3201
3202                 return INTEL_OUTPUT_FORMAT_YCBCR420;
3203         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
3204                 return INTEL_OUTPUT_FORMAT_YCBCR444;
3205         } else {
3206                 return INTEL_OUTPUT_FORMAT_RGB;
3207         }
3208 }
3209
3210 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
3211 {
3212         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3213         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3214         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3215         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3216         u32 tmp;
3217
3218         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
3219
3220         if (tmp & DISP_PIPE_GAMMA_ENABLE)
3221                 crtc_state->gamma_enable = true;
3222
3223         if (!HAS_GMCH(dev_priv) &&
3224             tmp & DISP_PIPE_CSC_ENABLE)
3225                 crtc_state->csc_enable = true;
3226 }
3227
3228 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3229                                  struct intel_crtc_state *pipe_config)
3230 {
3231         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3232         enum intel_display_power_domain power_domain;
3233         intel_wakeref_t wakeref;
3234         u32 tmp;
3235         bool ret;
3236
3237         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3238         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3239         if (!wakeref)
3240                 return false;
3241
3242         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3243         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3244         pipe_config->shared_dpll = NULL;
3245
3246         ret = false;
3247
3248         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
3249         if (!(tmp & PIPECONF_ENABLE))
3250                 goto out;
3251
3252         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3253             IS_CHERRYVIEW(dev_priv)) {
3254                 switch (tmp & PIPECONF_BPC_MASK) {
3255                 case PIPECONF_BPC_6:
3256                         pipe_config->pipe_bpp = 18;
3257                         break;
3258                 case PIPECONF_BPC_8:
3259                         pipe_config->pipe_bpp = 24;
3260                         break;
3261                 case PIPECONF_BPC_10:
3262                         pipe_config->pipe_bpp = 30;
3263                         break;
3264                 default:
3265                         MISSING_CASE(tmp);
3266                         break;
3267                 }
3268         }
3269
3270         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3271             (tmp & PIPECONF_COLOR_RANGE_SELECT))
3272                 pipe_config->limited_color_range = true;
3273
3274         pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
3275
3276         pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
3277
3278         if (IS_CHERRYVIEW(dev_priv))
3279                 pipe_config->cgm_mode = intel_de_read(dev_priv,
3280                                                       CGM_PIPE_MODE(crtc->pipe));
3281
3282         i9xx_get_pipe_color_config(pipe_config);
3283         intel_color_get_config(pipe_config);
3284
3285         if (DISPLAY_VER(dev_priv) < 4)
3286                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
3287
3288         intel_get_transcoder_timings(crtc, pipe_config);
3289         intel_get_pipe_src_size(crtc, pipe_config);
3290
3291         i9xx_get_pfit_config(pipe_config);
3292
3293         if (DISPLAY_VER(dev_priv) >= 4) {
3294                 /* No way to read it out on pipes B and C */
3295                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
3296                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
3297                 else
3298                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
3299                 pipe_config->pixel_multiplier =
3300                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3301                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3302                 pipe_config->dpll_hw_state.dpll_md = tmp;
3303         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3304                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3305                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
3306                 pipe_config->pixel_multiplier =
3307                         ((tmp & SDVO_MULTIPLIER_MASK)
3308                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3309         } else {
3310                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3311                  * port and will be fixed up in the encoder->get_config
3312                  * function. */
3313                 pipe_config->pixel_multiplier = 1;
3314         }
3315         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
3316                                                         DPLL(crtc->pipe));
3317         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
3318                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
3319                                                                FP0(crtc->pipe));
3320                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
3321                                                                FP1(crtc->pipe));
3322         } else {
3323                 /* Mask out read-only status bits. */
3324                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
3325                                                      DPLL_PORTC_READY_MASK |
3326                                                      DPLL_PORTB_READY_MASK);
3327         }
3328
3329         if (IS_CHERRYVIEW(dev_priv))
3330                 chv_crtc_clock_get(crtc, pipe_config);
3331         else if (IS_VALLEYVIEW(dev_priv))
3332                 vlv_crtc_clock_get(crtc, pipe_config);
3333         else
3334                 i9xx_crtc_clock_get(crtc, pipe_config);
3335
3336         /*
3337          * Normally the dotclock is filled in by the encoder .get_config()
3338          * but in case the pipe is enabled w/o any ports we need a sane
3339          * default.
3340          */
3341         pipe_config->hw.adjusted_mode.crtc_clock =
3342                 pipe_config->port_clock / pipe_config->pixel_multiplier;
3343
3344         ret = true;
3345
3346 out:
3347         intel_display_power_put(dev_priv, power_domain, wakeref);
3348
3349         return ret;
3350 }
3351
3352 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3353 {
3354         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3355         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3356         enum pipe pipe = crtc->pipe;
3357         u32 val = 0;
3358
3359         /*
3360          * - During modeset the pipe is still disabled and must remain so
3361          * - During fastset the pipe is already enabled and must remain so
3362          */
3363         if (!intel_crtc_needs_modeset(crtc_state))
3364                 val |= PIPECONF_ENABLE;
3365
3366         switch (crtc_state->pipe_bpp) {
3367         default:
3368                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3369                 MISSING_CASE(crtc_state->pipe_bpp);
3370                 fallthrough;
3371         case 18:
3372                 val |= PIPECONF_BPC_6;
3373                 break;
3374         case 24:
3375                 val |= PIPECONF_BPC_8;
3376                 break;
3377         case 30:
3378                 val |= PIPECONF_BPC_10;
3379                 break;
3380         case 36:
3381                 val |= PIPECONF_BPC_12;
3382                 break;
3383         }
3384
3385         if (crtc_state->dither)
3386                 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
3387
3388         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3389                 val |= PIPECONF_INTERLACE_IF_ID_ILK;
3390         else
3391                 val |= PIPECONF_INTERLACE_PF_PD_ILK;
3392
3393         /*
3394          * This would end up with an odd purple hue over
3395          * the entire display. Make sure we don't do it.
3396          */
3397         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3398                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3399
3400         if (crtc_state->limited_color_range &&
3401             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3402                 val |= PIPECONF_COLOR_RANGE_SELECT;
3403
3404         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3405                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
3406
3407         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
3408
3409         val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3410         val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3411
3412         intel_de_write(dev_priv, PIPECONF(pipe), val);
3413         intel_de_posting_read(dev_priv, PIPECONF(pipe));
3414 }
3415
3416 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3417 {
3418         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3419         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3420         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3421         u32 val = 0;
3422
3423         /*
3424          * - During modeset the pipe is still disabled and must remain so
3425          * - During fastset the pipe is already enabled and must remain so
3426          */
3427         if (!intel_crtc_needs_modeset(crtc_state))
3428                 val |= PIPECONF_ENABLE;
3429
3430         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3431                 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
3432
3433         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3434                 val |= PIPECONF_INTERLACE_IF_ID_ILK;
3435         else
3436                 val |= PIPECONF_INTERLACE_PF_PD_ILK;
3437
3438         if (IS_HASWELL(dev_priv) &&
3439             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3440                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
3441
3442         intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
3443         intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
3444 }
3445
3446 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
3447 {
3448         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3450         u32 val = 0;
3451
3452         switch (crtc_state->pipe_bpp) {
3453         case 18:
3454                 val |= PIPEMISC_BPC_6;
3455                 break;
3456         case 24:
3457                 val |= PIPEMISC_BPC_8;
3458                 break;
3459         case 30:
3460                 val |= PIPEMISC_BPC_10;
3461                 break;
3462         case 36:
3463                 /* Port output 12BPC defined for ADLP+ */
3464                 if (DISPLAY_VER(dev_priv) > 12)
3465                         val |= PIPEMISC_BPC_12_ADLP;
3466                 break;
3467         default:
3468                 MISSING_CASE(crtc_state->pipe_bpp);
3469                 break;
3470         }
3471
3472         if (crtc_state->dither)
3473                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
3474
3475         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3476             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3477                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
3478
3479         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3480                 val |= PIPEMISC_YUV420_ENABLE |
3481                         PIPEMISC_YUV420_MODE_FULL_BLEND;
3482
3483         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3484                 val |= PIPEMISC_HDR_MODE_PRECISION;
3485
3486         if (DISPLAY_VER(dev_priv) >= 12)
3487                 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
3488
3489         intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
3490 }
3491
3492 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
3493 {
3494         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3495         u32 tmp;
3496
3497         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
3498
3499         switch (tmp & PIPEMISC_BPC_MASK) {
3500         case PIPEMISC_BPC_6:
3501                 return 18;
3502         case PIPEMISC_BPC_8:
3503                 return 24;
3504         case PIPEMISC_BPC_10:
3505                 return 30;
3506         /*
3507          * PORT OUTPUT 12 BPC defined for ADLP+.
3508          *
3509          * TODO:
3510          * For previous platforms with DSI interface, bits 5:7
3511          * are used for storing pipe_bpp irrespective of dithering.
3512          * Since the value of 12 BPC is not defined for these bits
3513          * on older platforms, need to find a workaround for 12 BPC
3514          * MIPI DSI HW readout.
3515          */
3516         case PIPEMISC_BPC_12_ADLP:
3517                 if (DISPLAY_VER(dev_priv) > 12)
3518                         return 36;
3519                 fallthrough;
3520         default:
3521                 MISSING_CASE(tmp);
3522                 return 0;
3523         }
3524 }
3525
3526 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3527 {
3528         /*
3529          * Account for spread spectrum to avoid
3530          * oversubscribing the link. Max center spread
3531          * is 2.5%; use 5% for safety's sake.
3532          */
3533         u32 bps = target_clock * bpp * 21 / 20;
3534         return DIV_ROUND_UP(bps, link_bw * 8);
3535 }
3536
3537 void intel_get_m_n(struct drm_i915_private *i915,
3538                    struct intel_link_m_n *m_n,
3539                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3540                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3541 {
3542         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3543         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3544         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3545         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3546         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3547 }
3548
3549 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3550                                     enum transcoder transcoder,
3551                                     struct intel_link_m_n *m_n)
3552 {
3553         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3554         enum pipe pipe = crtc->pipe;
3555
3556         if (DISPLAY_VER(dev_priv) >= 5)
3557                 intel_get_m_n(dev_priv, m_n,
3558                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3559                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3560         else
3561                 intel_get_m_n(dev_priv, m_n,
3562                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3563                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3564 }
3565
3566 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3567                                     enum transcoder transcoder,
3568                                     struct intel_link_m_n *m_n)
3569 {
3570         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3571
3572         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3573                 return;
3574
3575         intel_get_m_n(dev_priv, m_n,
3576                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3577                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3578 }
3579
3580 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
3581                                   u32 pos, u32 size)
3582 {
3583         drm_rect_init(&crtc_state->pch_pfit.dst,
3584                       pos >> 16, pos & 0xffff,
3585                       size >> 16, size & 0xffff);
3586 }
3587
3588 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
3589 {
3590         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3591         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3592         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
3593         int id = -1;
3594         int i;
3595
3596         /* find scaler attached to this pipe */
3597         for (i = 0; i < crtc->num_scalers; i++) {
3598                 u32 ctl, pos, size;
3599
3600                 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
3601                 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
3602                         continue;
3603
3604                 id = i;
3605                 crtc_state->pch_pfit.enabled = true;
3606
3607                 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
3608                 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
3609
3610                 ilk_get_pfit_pos_size(crtc_state, pos, size);
3611
3612                 scaler_state->scalers[i].in_use = true;
3613                 break;
3614         }
3615
3616         scaler_state->scaler_id = id;
3617         if (id >= 0)
3618                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
3619         else
3620                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
3621 }
3622
3623 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3624 {
3625         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3626         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3627         u32 ctl, pos, size;
3628
3629         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3630         if ((ctl & PF_ENABLE) == 0)
3631                 return;
3632
3633         crtc_state->pch_pfit.enabled = true;
3634
3635         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3636         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3637
3638         ilk_get_pfit_pos_size(crtc_state, pos, size);
3639
3640         /*
3641          * We currently do not free assignements of panel fitters on
3642          * ivb/hsw (since we don't use the higher upscaling modes which
3643          * differentiates them) so just WARN about this case for now.
3644          */
3645         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
3646                     (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
3647 }
3648
3649 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3650                                 struct intel_crtc_state *pipe_config)
3651 {
3652         struct drm_device *dev = crtc->base.dev;
3653         struct drm_i915_private *dev_priv = to_i915(dev);
3654         enum intel_display_power_domain power_domain;
3655         intel_wakeref_t wakeref;
3656         u32 tmp;
3657         bool ret;
3658
3659         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3660         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3661         if (!wakeref)
3662                 return false;
3663
3664         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3665         pipe_config->shared_dpll = NULL;
3666
3667         ret = false;
3668         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
3669         if (!(tmp & PIPECONF_ENABLE))
3670                 goto out;
3671
3672         switch (tmp & PIPECONF_BPC_MASK) {
3673         case PIPECONF_BPC_6:
3674                 pipe_config->pipe_bpp = 18;
3675                 break;
3676         case PIPECONF_BPC_8:
3677                 pipe_config->pipe_bpp = 24;
3678                 break;
3679         case PIPECONF_BPC_10:
3680                 pipe_config->pipe_bpp = 30;
3681                 break;
3682         case PIPECONF_BPC_12:
3683                 pipe_config->pipe_bpp = 36;
3684                 break;
3685         default:
3686                 break;
3687         }
3688
3689         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
3690                 pipe_config->limited_color_range = true;
3691
3692         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
3693         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
3694         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
3695                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3696                 break;
3697         default:
3698                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3699                 break;
3700         }
3701
3702         pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
3703
3704         pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
3705
3706         pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp);
3707
3708         pipe_config->csc_mode = intel_de_read(dev_priv,
3709                                               PIPE_CSC_MODE(crtc->pipe));
3710
3711         i9xx_get_pipe_color_config(pipe_config);
3712         intel_color_get_config(pipe_config);
3713
3714         pipe_config->pixel_multiplier = 1;
3715
3716         ilk_pch_get_config(pipe_config);
3717
3718         intel_get_transcoder_timings(crtc, pipe_config);
3719         intel_get_pipe_src_size(crtc, pipe_config);
3720
3721         ilk_get_pfit_config(pipe_config);
3722
3723         ret = true;
3724
3725 out:
3726         intel_display_power_put(dev_priv, power_domain, wakeref);
3727
3728         return ret;
3729 }
3730
3731 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3732 {
3733         if (DISPLAY_VER(i915) >= 12)
3734                 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3735         else if (DISPLAY_VER(i915) >= 11)
3736                 return BIT(PIPE_B) | BIT(PIPE_C);
3737         else
3738                 return 0;
3739 }
3740
3741 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3742                                            enum transcoder cpu_transcoder)
3743 {
3744         enum intel_display_power_domain power_domain;
3745         intel_wakeref_t wakeref;
3746         u32 tmp = 0;
3747
3748         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3749
3750         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3751                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3752
3753         return tmp & TRANS_DDI_FUNC_ENABLE;
3754 }
3755
3756 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3757                                     u8 *master_pipes, u8 *slave_pipes)
3758 {
3759         struct intel_crtc *crtc;
3760
3761         *master_pipes = 0;
3762         *slave_pipes = 0;
3763
3764         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3765                                          bigjoiner_pipes(dev_priv)) {
3766                 enum intel_display_power_domain power_domain;
3767                 enum pipe pipe = crtc->pipe;
3768                 intel_wakeref_t wakeref;
3769
3770                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3771                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3772                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3773
3774                         if (!(tmp & BIG_JOINER_ENABLE))
3775                                 continue;
3776
3777                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3778                                 *master_pipes |= BIT(pipe);
3779                         else
3780                                 *slave_pipes |= BIT(pipe);
3781                 }
3782
3783                 if (DISPLAY_VER(dev_priv) < 13)
3784                         continue;
3785
3786                 power_domain = POWER_DOMAIN_PIPE(pipe);
3787                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3788                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3789
3790                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3791                                 *master_pipes |= BIT(pipe);
3792                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3793                                 *slave_pipes |= BIT(pipe);
3794                 }
3795         }
3796
3797         /* Bigjoiner pipes should always be consecutive master and slave */
3798         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3799                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3800                  *master_pipes, *slave_pipes);
3801 }
3802
3803 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3804 {
3805         if ((slave_pipes & BIT(pipe)) == 0)
3806                 return pipe;
3807
3808         /* ignore everything above our pipe */
3809         master_pipes &= ~GENMASK(7, pipe);
3810
3811         /* highest remaining bit should be our master pipe */
3812         return fls(master_pipes) - 1;
3813 }
3814
3815 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3816 {
3817         enum pipe master_pipe, next_master_pipe;
3818
3819         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3820
3821         if ((master_pipes & BIT(master_pipe)) == 0)
3822                 return 0;
3823
3824         /* ignore our master pipe and everything below it */
3825         master_pipes &= ~GENMASK(master_pipe, 0);
3826         /* make sure a high bit is set for the ffs() */
3827         master_pipes |= BIT(7);
3828         /* lowest remaining bit should be the next master pipe */
3829         next_master_pipe = ffs(master_pipes) - 1;
3830
3831         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3832 }
3833
3834 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3835 {
3836         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3837
3838         if (DISPLAY_VER(i915) >= 11)
3839                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3840
3841         return panel_transcoder_mask;
3842 }
3843
3844 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3845 {
3846         struct drm_device *dev = crtc->base.dev;
3847         struct drm_i915_private *dev_priv = to_i915(dev);
3848         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3849         enum transcoder cpu_transcoder;
3850         u8 master_pipes, slave_pipes;
3851         u8 enabled_transcoders = 0;
3852
3853         /*
3854          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3855          * consistency and less surprising code; it's in always on power).
3856          */
3857         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3858                                        panel_transcoder_mask) {
3859                 enum intel_display_power_domain power_domain;
3860                 intel_wakeref_t wakeref;
3861                 enum pipe trans_pipe;
3862                 u32 tmp = 0;
3863
3864                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3865                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3866                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3867
3868                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3869                         continue;
3870
3871                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3872                 default:
3873                         drm_WARN(dev, 1,
3874                                  "unknown pipe linked to transcoder %s\n",
3875                                  transcoder_name(cpu_transcoder));
3876                         fallthrough;
3877                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3878                 case TRANS_DDI_EDP_INPUT_A_ON:
3879                         trans_pipe = PIPE_A;
3880                         break;
3881                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3882                         trans_pipe = PIPE_B;
3883                         break;
3884                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3885                         trans_pipe = PIPE_C;
3886                         break;
3887                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3888                         trans_pipe = PIPE_D;
3889                         break;
3890                 }
3891
3892                 if (trans_pipe == crtc->pipe)
3893                         enabled_transcoders |= BIT(cpu_transcoder);
3894         }
3895
3896         /* single pipe or bigjoiner master */
3897         cpu_transcoder = (enum transcoder) crtc->pipe;
3898         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3899                 enabled_transcoders |= BIT(cpu_transcoder);
3900
3901         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3902         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3903         if (slave_pipes & BIT(crtc->pipe)) {
3904                 cpu_transcoder = (enum transcoder)
3905                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3906                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3907                         enabled_transcoders |= BIT(cpu_transcoder);
3908         }
3909
3910         return enabled_transcoders;
3911 }
3912
3913 static bool has_edp_transcoders(u8 enabled_transcoders)
3914 {
3915         return enabled_transcoders & BIT(TRANSCODER_EDP);
3916 }
3917
3918 static bool has_dsi_transcoders(u8 enabled_transcoders)
3919 {
3920         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3921                                       BIT(TRANSCODER_DSI_1));
3922 }
3923
3924 static bool has_pipe_transcoders(u8 enabled_transcoders)
3925 {
3926         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3927                                        BIT(TRANSCODER_DSI_0) |
3928                                        BIT(TRANSCODER_DSI_1));
3929 }
3930
3931 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3932                                        u8 enabled_transcoders)
3933 {
3934         /* Only one type of transcoder please */
3935         drm_WARN_ON(&i915->drm,
3936                     has_edp_transcoders(enabled_transcoders) +
3937                     has_dsi_transcoders(enabled_transcoders) +
3938                     has_pipe_transcoders(enabled_transcoders) > 1);
3939
3940         /* Only DSI transcoders can be ganged */
3941         drm_WARN_ON(&i915->drm,
3942                     !has_dsi_transcoders(enabled_transcoders) &&
3943                     !is_power_of_2(enabled_transcoders));
3944 }
3945
3946 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3947                                      struct intel_crtc_state *pipe_config,
3948                                      struct intel_display_power_domain_set *power_domain_set)
3949 {
3950         struct drm_device *dev = crtc->base.dev;
3951         struct drm_i915_private *dev_priv = to_i915(dev);
3952         unsigned long enabled_transcoders;
3953         u32 tmp;
3954
3955         enabled_transcoders = hsw_enabled_transcoders(crtc);
3956         if (!enabled_transcoders)
3957                 return false;
3958
3959         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3960
3961         /*
3962          * With the exception of DSI we should only ever have
3963          * a single enabled transcoder. With DSI let's just
3964          * pick the first one.
3965          */
3966         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3967
3968         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3969                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3970                 return false;
3971
3972         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3973                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3974
3975                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3976                         pipe_config->pch_pfit.force_thru = true;
3977         }
3978
3979         tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
3980
3981         return tmp & PIPECONF_ENABLE;
3982 }
3983
3984 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3985                                          struct intel_crtc_state *pipe_config,
3986                                          struct intel_display_power_domain_set *power_domain_set)
3987 {
3988         struct drm_device *dev = crtc->base.dev;
3989         struct drm_i915_private *dev_priv = to_i915(dev);
3990         enum transcoder cpu_transcoder;
3991         enum port port;
3992         u32 tmp;
3993
3994         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3995                 if (port == PORT_A)
3996                         cpu_transcoder = TRANSCODER_DSI_A;
3997                 else
3998                         cpu_transcoder = TRANSCODER_DSI_C;
3999
4000                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
4001                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
4002                         continue;
4003
4004                 /*
4005                  * The PLL needs to be enabled with a valid divider
4006                  * configuration, otherwise accessing DSI registers will hang
4007                  * the machine. See BSpec North Display Engine
4008                  * registers/MIPI[BXT]. We can break out here early, since we
4009                  * need the same DSI PLL to be enabled for both DSI ports.
4010                  */
4011                 if (!bxt_dsi_pll_is_enabled(dev_priv))
4012                         break;
4013
4014                 /* XXX: this works for video mode only */
4015                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
4016                 if (!(tmp & DPI_ENABLE))
4017                         continue;
4018
4019                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
4020                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
4021                         continue;
4022
4023                 pipe_config->cpu_transcoder = cpu_transcoder;
4024                 break;
4025         }
4026
4027         return transcoder_is_dsi(pipe_config->cpu_transcoder);
4028 }
4029
4030 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
4031 {
4032         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4033         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4034         u8 master_pipes, slave_pipes;
4035         enum pipe pipe = crtc->pipe;
4036
4037         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
4038
4039         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
4040                 return;
4041
4042         crtc_state->bigjoiner_pipes =
4043                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
4044                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
4045 }
4046
4047 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
4048                                 struct intel_crtc_state *pipe_config)
4049 {
4050         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4051         struct intel_display_power_domain_set power_domain_set = { };
4052         bool active;
4053         u32 tmp;
4054
4055         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
4056                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
4057                 return false;
4058
4059         pipe_config->shared_dpll = NULL;
4060
4061         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
4062
4063         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4064             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
4065                 drm_WARN_ON(&dev_priv->drm, active);
4066                 active = true;
4067         }
4068
4069         if (!active)
4070                 goto out;
4071
4072         intel_dsc_get_config(pipe_config);
4073         intel_bigjoiner_get_config(pipe_config);
4074
4075         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
4076             DISPLAY_VER(dev_priv) >= 11)
4077                 intel_get_transcoder_timings(crtc, pipe_config);
4078
4079         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
4080                 intel_vrr_get_config(crtc, pipe_config);
4081
4082         intel_get_pipe_src_size(crtc, pipe_config);
4083
4084         if (IS_HASWELL(dev_priv)) {
4085                 u32 tmp = intel_de_read(dev_priv,
4086                                         PIPECONF(pipe_config->cpu_transcoder));
4087
4088                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
4089                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
4090                 else
4091                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
4092         } else {
4093                 pipe_config->output_format =
4094                         bdw_get_pipemisc_output_format(crtc);
4095         }
4096
4097         pipe_config->gamma_mode = intel_de_read(dev_priv,
4098                                                 GAMMA_MODE(crtc->pipe));
4099
4100         pipe_config->csc_mode = intel_de_read(dev_priv,
4101                                               PIPE_CSC_MODE(crtc->pipe));
4102
4103         if (DISPLAY_VER(dev_priv) >= 9) {
4104                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
4105
4106                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
4107                         pipe_config->gamma_enable = true;
4108
4109                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
4110                         pipe_config->csc_enable = true;
4111         } else {
4112                 i9xx_get_pipe_color_config(pipe_config);
4113         }
4114
4115         intel_color_get_config(pipe_config);
4116
4117         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
4118         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
4119         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
4120                 pipe_config->ips_linetime =
4121                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
4122
4123         if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
4124                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
4125                 if (DISPLAY_VER(dev_priv) >= 9)
4126                         skl_get_pfit_config(pipe_config);
4127                 else
4128                         ilk_get_pfit_config(pipe_config);
4129         }
4130
4131         hsw_ips_get_config(pipe_config);
4132
4133         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
4134             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4135                 pipe_config->pixel_multiplier =
4136                         intel_de_read(dev_priv,
4137                                       PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
4138         } else {
4139                 pipe_config->pixel_multiplier = 1;
4140         }
4141
4142         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4143                 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ?
4144                                     MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
4145                                     CHICKEN_TRANS(pipe_config->cpu_transcoder));
4146
4147                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
4148         } else {
4149                 /* no idea if this is correct */
4150                 pipe_config->framestart_delay = 1;
4151         }
4152
4153 out:
4154         intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
4155
4156         return active;
4157 }
4158
4159 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
4160 {
4161         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4162         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4163
4164         if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
4165                 return false;
4166
4167         crtc_state->hw.active = true;
4168
4169         intel_crtc_readout_derived_state(crtc_state);
4170
4171         return true;
4172 }
4173
4174 /* VESA 640x480x72Hz mode to set on the pipe */
4175 static const struct drm_display_mode load_detect_mode = {
4176         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4177                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4178 };
4179
4180 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
4181                                         struct drm_crtc *crtc)
4182 {
4183         struct drm_plane *plane;
4184         struct drm_plane_state *plane_state;
4185         int ret, i;
4186
4187         ret = drm_atomic_add_affected_planes(state, crtc);
4188         if (ret)
4189                 return ret;
4190
4191         for_each_new_plane_in_state(state, plane, plane_state, i) {
4192                 if (plane_state->crtc != crtc)
4193                         continue;
4194
4195                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
4196                 if (ret)
4197                         return ret;
4198
4199                 drm_atomic_set_fb_for_plane(plane_state, NULL);
4200         }
4201
4202         return 0;
4203 }
4204
4205 int intel_get_load_detect_pipe(struct drm_connector *connector,
4206                                struct intel_load_detect_pipe *old,
4207                                struct drm_modeset_acquire_ctx *ctx)
4208 {
4209         struct intel_encoder *encoder =
4210                 intel_attached_encoder(to_intel_connector(connector));
4211         struct intel_crtc *possible_crtc;
4212         struct intel_crtc *crtc = NULL;
4213         struct drm_device *dev = encoder->base.dev;
4214         struct drm_i915_private *dev_priv = to_i915(dev);
4215         struct drm_mode_config *config = &dev->mode_config;
4216         struct drm_atomic_state *state = NULL, *restore_state = NULL;
4217         struct drm_connector_state *connector_state;
4218         struct intel_crtc_state *crtc_state;
4219         int ret;
4220
4221         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4222                     connector->base.id, connector->name,
4223                     encoder->base.base.id, encoder->base.name);
4224
4225         old->restore_state = NULL;
4226
4227         drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
4228
4229         /*
4230          * Algorithm gets a little messy:
4231          *
4232          *   - if the connector already has an assigned crtc, use it (but make
4233          *     sure it's on first)
4234          *
4235          *   - try to find the first unused crtc that can drive this connector,
4236          *     and use that if we find one
4237          */
4238
4239         /* See if we already have a CRTC for this connector */
4240         if (connector->state->crtc) {
4241                 crtc = to_intel_crtc(connector->state->crtc);
4242
4243                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4244                 if (ret)
4245                         goto fail;
4246
4247                 /* Make sure the crtc and connector are running */
4248                 goto found;
4249         }
4250
4251         /* Find an unused one (if possible) */
4252         for_each_intel_crtc(dev, possible_crtc) {
4253                 if (!(encoder->base.possible_crtcs &
4254                       drm_crtc_mask(&possible_crtc->base)))
4255                         continue;
4256
4257                 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);
4258                 if (ret)
4259                         goto fail;
4260
4261                 if (possible_crtc->base.state->enable) {
4262                         drm_modeset_unlock(&possible_crtc->base.mutex);
4263                         continue;
4264                 }
4265
4266                 crtc = possible_crtc;
4267                 break;
4268         }
4269
4270         /*
4271          * If we didn't find an unused CRTC, don't use any.
4272          */
4273         if (!crtc) {
4274                 drm_dbg_kms(&dev_priv->drm,
4275                             "no pipe available for load-detect\n");
4276                 ret = -ENODEV;
4277                 goto fail;
4278         }
4279
4280 found:
4281         state = drm_atomic_state_alloc(dev);
4282         restore_state = drm_atomic_state_alloc(dev);
4283         if (!state || !restore_state) {
4284                 ret = -ENOMEM;
4285                 goto fail;
4286         }
4287
4288         state->acquire_ctx = ctx;
4289         restore_state->acquire_ctx = ctx;
4290
4291         connector_state = drm_atomic_get_connector_state(state, connector);
4292         if (IS_ERR(connector_state)) {
4293                 ret = PTR_ERR(connector_state);
4294                 goto fail;
4295         }
4296
4297         ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);
4298         if (ret)
4299                 goto fail;
4300
4301         crtc_state = intel_atomic_get_crtc_state(state, crtc);
4302         if (IS_ERR(crtc_state)) {
4303                 ret = PTR_ERR(crtc_state);
4304                 goto fail;
4305         }
4306
4307         crtc_state->uapi.active = true;
4308
4309         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
4310                                            &load_detect_mode);
4311         if (ret)
4312                 goto fail;
4313
4314         ret = intel_modeset_disable_planes(state, &crtc->base);
4315         if (ret)
4316                 goto fail;
4317
4318         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
4319         if (!ret)
4320                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base));
4321         if (!ret)
4322                 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);
4323         if (ret) {
4324                 drm_dbg_kms(&dev_priv->drm,
4325                             "Failed to create a copy of old state to restore: %i\n",
4326                             ret);
4327                 goto fail;
4328         }
4329
4330         ret = drm_atomic_commit(state);
4331         if (ret) {
4332                 drm_dbg_kms(&dev_priv->drm,
4333                             "failed to set mode on load-detect pipe\n");
4334                 goto fail;
4335         }
4336
4337         old->restore_state = restore_state;
4338         drm_atomic_state_put(state);
4339
4340         /* let the connector get through one full cycle before testing */
4341         intel_crtc_wait_for_next_vblank(crtc);
4342
4343         return true;
4344
4345 fail:
4346         if (state) {
4347                 drm_atomic_state_put(state);
4348                 state = NULL;
4349         }
4350         if (restore_state) {
4351                 drm_atomic_state_put(restore_state);
4352                 restore_state = NULL;
4353         }
4354
4355         if (ret == -EDEADLK)
4356                 return ret;
4357
4358         return false;
4359 }
4360
4361 void intel_release_load_detect_pipe(struct drm_connector *connector,
4362                                     struct intel_load_detect_pipe *old,
4363                                     struct drm_modeset_acquire_ctx *ctx)
4364 {
4365         struct intel_encoder *intel_encoder =
4366                 intel_attached_encoder(to_intel_connector(connector));
4367         struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
4368         struct drm_encoder *encoder = &intel_encoder->base;
4369         struct drm_atomic_state *state = old->restore_state;
4370         int ret;
4371
4372         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4373                     connector->base.id, connector->name,
4374                     encoder->base.id, encoder->name);
4375
4376         if (!state)
4377                 return;
4378
4379         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4380         if (ret)
4381                 drm_dbg_kms(&i915->drm,
4382                             "Couldn't release load detect pipe: %i\n", ret);
4383         drm_atomic_state_put(state);
4384 }
4385
4386 static int i9xx_pll_refclk(struct drm_device *dev,
4387                            const struct intel_crtc_state *pipe_config)
4388 {
4389         struct drm_i915_private *dev_priv = to_i915(dev);
4390         u32 dpll = pipe_config->dpll_hw_state.dpll;
4391
4392         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
4393                 return dev_priv->display.vbt.lvds_ssc_freq;
4394         else if (HAS_PCH_SPLIT(dev_priv))
4395                 return 120000;
4396         else if (DISPLAY_VER(dev_priv) != 2)
4397                 return 96000;
4398         else
4399                 return 48000;
4400 }
4401
4402 /* Returns the clock of the currently programmed mode of the given pipe. */
4403 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
4404                          struct intel_crtc_state *pipe_config)
4405 {
4406         struct drm_device *dev = crtc->base.dev;
4407         struct drm_i915_private *dev_priv = to_i915(dev);
4408         u32 dpll = pipe_config->dpll_hw_state.dpll;
4409         u32 fp;
4410         struct dpll clock;
4411         int port_clock;
4412         int refclk = i9xx_pll_refclk(dev, pipe_config);
4413
4414         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4415                 fp = pipe_config->dpll_hw_state.fp0;
4416         else
4417                 fp = pipe_config->dpll_hw_state.fp1;
4418
4419         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4420         if (IS_PINEVIEW(dev_priv)) {
4421                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4422                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4423         } else {
4424                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4425                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4426         }
4427
4428         if (DISPLAY_VER(dev_priv) != 2) {
4429                 if (IS_PINEVIEW(dev_priv))
4430                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4431                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4432                 else
4433                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4434                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4435
4436                 switch (dpll & DPLL_MODE_MASK) {
4437                 case DPLLB_MODE_DAC_SERIAL:
4438                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4439                                 5 : 10;
4440                         break;
4441                 case DPLLB_MODE_LVDS:
4442                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4443                                 7 : 14;
4444                         break;
4445                 default:
4446                         drm_dbg_kms(&dev_priv->drm,
4447                                     "Unknown DPLL mode %08x in programmed "
4448                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
4449                         return;
4450                 }
4451
4452                 if (IS_PINEVIEW(dev_priv))
4453                         port_clock = pnv_calc_dpll_params(refclk, &clock);
4454                 else
4455                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
4456         } else {
4457                 enum pipe lvds_pipe;
4458
4459                 if (IS_I85X(dev_priv) &&
4460                     intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
4461                     lvds_pipe == crtc->pipe) {
4462                         u32 lvds = intel_de_read(dev_priv, LVDS);
4463
4464                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4465                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4466
4467                         if (lvds & LVDS_CLKB_POWER_UP)
4468                                 clock.p2 = 7;
4469                         else
4470                                 clock.p2 = 14;
4471                 } else {
4472                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4473                                 clock.p1 = 2;
4474                         else {
4475                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4476                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4477                         }
4478                         if (dpll & PLL_P2_DIVIDE_BY_4)
4479                                 clock.p2 = 4;
4480                         else
4481                                 clock.p2 = 2;
4482                 }
4483
4484                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
4485         }
4486
4487         /*
4488          * This value includes pixel_multiplier. We will use
4489          * port_clock to compute adjusted_mode.crtc_clock in the
4490          * encoder's get_config() function.
4491          */
4492         pipe_config->port_clock = port_clock;
4493 }
4494
4495 int intel_dotclock_calculate(int link_freq,
4496                              const struct intel_link_m_n *m_n)
4497 {
4498         /*
4499          * The calculation for the data clock is:
4500          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4501          * But we want to avoid losing precison if possible, so:
4502          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4503          *
4504          * and the link clock is simpler:
4505          * link_clock = (m * link_clock) / n
4506          */
4507
4508         if (!m_n->link_n)
4509                 return 0;
4510
4511         return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq),
4512                                 m_n->link_n);
4513 }
4514
4515 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
4516 {
4517         int dotclock;
4518
4519         if (intel_crtc_has_dp_encoder(pipe_config))
4520                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
4521                                                     &pipe_config->dp_m_n);
4522         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
4523                 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
4524                                              pipe_config->pipe_bpp);
4525         else
4526                 dotclock = pipe_config->port_clock;
4527
4528         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
4529             !intel_crtc_has_dp_encoder(pipe_config))
4530                 dotclock *= 2;
4531
4532         if (pipe_config->pixel_multiplier)
4533                 dotclock /= pipe_config->pixel_multiplier;
4534
4535         return dotclock;
4536 }
4537
4538 /* Returns the currently programmed mode of the given encoder. */
4539 struct drm_display_mode *
4540 intel_encoder_current_mode(struct intel_encoder *encoder)
4541 {
4542         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4543         struct intel_crtc_state *crtc_state;
4544         struct drm_display_mode *mode;
4545         struct intel_crtc *crtc;
4546         enum pipe pipe;
4547
4548         if (!encoder->get_hw_state(encoder, &pipe))
4549                 return NULL;
4550
4551         crtc = intel_crtc_for_pipe(dev_priv, pipe);
4552
4553         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4554         if (!mode)
4555                 return NULL;
4556
4557         crtc_state = intel_crtc_state_alloc(crtc);
4558         if (!crtc_state) {
4559                 kfree(mode);
4560                 return NULL;
4561         }
4562
4563         if (!intel_crtc_get_pipe_config(crtc_state)) {
4564                 kfree(crtc_state);
4565                 kfree(mode);
4566                 return NULL;
4567         }
4568
4569         intel_encoder_get_config(encoder, crtc_state);
4570
4571         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4572
4573         kfree(crtc_state);
4574
4575         return mode;
4576 }
4577
4578 static bool encoders_cloneable(const struct intel_encoder *a,
4579                                const struct intel_encoder *b)
4580 {
4581         /* masks could be asymmetric, so check both ways */
4582         return a == b || (a->cloneable & BIT(b->type) &&
4583                           b->cloneable & BIT(a->type));
4584 }
4585
4586 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4587                                          struct intel_crtc *crtc,
4588                                          struct intel_encoder *encoder)
4589 {
4590         struct intel_encoder *source_encoder;
4591         struct drm_connector *connector;
4592         struct drm_connector_state *connector_state;
4593         int i;
4594
4595         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4596                 if (connector_state->crtc != &crtc->base)
4597                         continue;
4598
4599                 source_encoder =
4600                         to_intel_encoder(connector_state->best_encoder);
4601                 if (!encoders_cloneable(encoder, source_encoder))
4602                         return false;
4603         }
4604
4605         return true;
4606 }
4607
4608 static int icl_add_linked_planes(struct intel_atomic_state *state)
4609 {
4610         struct intel_plane *plane, *linked;
4611         struct intel_plane_state *plane_state, *linked_plane_state;
4612         int i;
4613
4614         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4615                 linked = plane_state->planar_linked_plane;
4616
4617                 if (!linked)
4618                         continue;
4619
4620                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4621                 if (IS_ERR(linked_plane_state))
4622                         return PTR_ERR(linked_plane_state);
4623
4624                 drm_WARN_ON(state->base.dev,
4625                             linked_plane_state->planar_linked_plane != plane);
4626                 drm_WARN_ON(state->base.dev,
4627                             linked_plane_state->planar_slave == plane_state->planar_slave);
4628         }
4629
4630         return 0;
4631 }
4632
4633 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4634 {
4635         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4636         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4637         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4638         struct intel_plane *plane, *linked;
4639         struct intel_plane_state *plane_state;
4640         int i;
4641
4642         if (DISPLAY_VER(dev_priv) < 11)
4643                 return 0;
4644
4645         /*
4646          * Destroy all old plane links and make the slave plane invisible
4647          * in the crtc_state->active_planes mask.
4648          */
4649         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4650                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4651                         continue;
4652
4653                 plane_state->planar_linked_plane = NULL;
4654                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4655                         crtc_state->enabled_planes &= ~BIT(plane->id);
4656                         crtc_state->active_planes &= ~BIT(plane->id);
4657                         crtc_state->update_planes |= BIT(plane->id);
4658                         crtc_state->data_rate[plane->id] = 0;
4659                         crtc_state->rel_data_rate[plane->id] = 0;
4660                 }
4661
4662                 plane_state->planar_slave = false;
4663         }
4664
4665         if (!crtc_state->nv12_planes)
4666                 return 0;
4667
4668         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4669                 struct intel_plane_state *linked_state = NULL;
4670
4671                 if (plane->pipe != crtc->pipe ||
4672                     !(crtc_state->nv12_planes & BIT(plane->id)))
4673                         continue;
4674
4675                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4676                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4677                                 continue;
4678
4679                         if (crtc_state->active_planes & BIT(linked->id))
4680                                 continue;
4681
4682                         linked_state = intel_atomic_get_plane_state(state, linked);
4683                         if (IS_ERR(linked_state))
4684                                 return PTR_ERR(linked_state);
4685
4686                         break;
4687                 }
4688
4689                 if (!linked_state) {
4690                         drm_dbg_kms(&dev_priv->drm,
4691                                     "Need %d free Y planes for planar YUV\n",
4692                                     hweight8(crtc_state->nv12_planes));
4693
4694                         return -EINVAL;
4695                 }
4696
4697                 plane_state->planar_linked_plane = linked;
4698
4699                 linked_state->planar_slave = true;
4700                 linked_state->planar_linked_plane = plane;
4701                 crtc_state->enabled_planes |= BIT(linked->id);
4702                 crtc_state->active_planes |= BIT(linked->id);
4703                 crtc_state->update_planes |= BIT(linked->id);
4704                 crtc_state->data_rate[linked->id] =
4705                         crtc_state->data_rate_y[plane->id];
4706                 crtc_state->rel_data_rate[linked->id] =
4707                         crtc_state->rel_data_rate_y[plane->id];
4708                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4709                             linked->base.name, plane->base.name);
4710
4711                 /* Copy parameters to slave plane */
4712                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4713                 linked_state->color_ctl = plane_state->color_ctl;
4714                 linked_state->view = plane_state->view;
4715                 linked_state->decrypt = plane_state->decrypt;
4716
4717                 intel_plane_copy_hw_state(linked_state, plane_state);
4718                 linked_state->uapi.src = plane_state->uapi.src;
4719                 linked_state->uapi.dst = plane_state->uapi.dst;
4720
4721                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4722                         if (linked->id == PLANE_SPRITE5)
4723                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4724                         else if (linked->id == PLANE_SPRITE4)
4725                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4726                         else if (linked->id == PLANE_SPRITE3)
4727                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4728                         else if (linked->id == PLANE_SPRITE2)
4729                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4730                         else
4731                                 MISSING_CASE(linked->id);
4732                 }
4733         }
4734
4735         return 0;
4736 }
4737
4738 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4739 {
4740         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4741         struct intel_atomic_state *state =
4742                 to_intel_atomic_state(new_crtc_state->uapi.state);
4743         const struct intel_crtc_state *old_crtc_state =
4744                 intel_atomic_get_old_crtc_state(state, crtc);
4745
4746         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4747 }
4748
4749 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4750 {
4751         const struct drm_display_mode *pipe_mode =
4752                 &crtc_state->hw.pipe_mode;
4753         int linetime_wm;
4754
4755         if (!crtc_state->hw.enable)
4756                 return 0;
4757
4758         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4759                                         pipe_mode->crtc_clock);
4760
4761         return min(linetime_wm, 0x1ff);
4762 }
4763
4764 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4765                                const struct intel_cdclk_state *cdclk_state)
4766 {
4767         const struct drm_display_mode *pipe_mode =
4768                 &crtc_state->hw.pipe_mode;
4769         int linetime_wm;
4770
4771         if (!crtc_state->hw.enable)
4772                 return 0;
4773
4774         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4775                                         cdclk_state->logical.cdclk);
4776
4777         return min(linetime_wm, 0x1ff);
4778 }
4779
4780 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4781 {
4782         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4783         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4784         const struct drm_display_mode *pipe_mode =
4785                 &crtc_state->hw.pipe_mode;
4786         int linetime_wm;
4787
4788         if (!crtc_state->hw.enable)
4789                 return 0;
4790
4791         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4792                                    crtc_state->pixel_rate);
4793
4794         /* Display WA #1135: BXT:ALL GLK:ALL */
4795         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4796             skl_watermark_ipc_enabled(dev_priv))
4797                 linetime_wm /= 2;
4798
4799         return min(linetime_wm, 0x1ff);
4800 }
4801
4802 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4803                                    struct intel_crtc *crtc)
4804 {
4805         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4806         struct intel_crtc_state *crtc_state =
4807                 intel_atomic_get_new_crtc_state(state, crtc);
4808         const struct intel_cdclk_state *cdclk_state;
4809
4810         if (DISPLAY_VER(dev_priv) >= 9)
4811                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4812         else
4813                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4814
4815         if (!hsw_crtc_supports_ips(crtc))
4816                 return 0;
4817
4818         cdclk_state = intel_atomic_get_cdclk_state(state);
4819         if (IS_ERR(cdclk_state))
4820                 return PTR_ERR(cdclk_state);
4821
4822         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4823                                                        cdclk_state);
4824
4825         return 0;
4826 }
4827
4828 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4829                                    struct intel_crtc *crtc)
4830 {
4831         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4832         struct intel_crtc_state *crtc_state =
4833                 intel_atomic_get_new_crtc_state(state, crtc);
4834         int ret;
4835
4836         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4837             intel_crtc_needs_modeset(crtc_state) &&
4838             !crtc_state->hw.active)
4839                 crtc_state->update_wm_post = true;
4840
4841         if (intel_crtc_needs_modeset(crtc_state)) {
4842                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4843                 if (ret)
4844                         return ret;
4845         }
4846
4847         /*
4848          * May need to update pipe gamma enable bits
4849          * when C8 planes are getting enabled/disabled.
4850          */
4851         if (c8_planes_changed(crtc_state))
4852                 crtc_state->uapi.color_mgmt_changed = true;
4853
4854         if (intel_crtc_needs_color_update(crtc_state)) {
4855                 ret = intel_color_check(crtc_state);
4856                 if (ret)
4857                         return ret;
4858         }
4859
4860         ret = intel_compute_pipe_wm(state, crtc);
4861         if (ret) {
4862                 drm_dbg_kms(&dev_priv->drm,
4863                             "Target pipe watermarks are invalid\n");
4864                 return ret;
4865         }
4866
4867         /*
4868          * Calculate 'intermediate' watermarks that satisfy both the
4869          * old state and the new state.  We can program these
4870          * immediately.
4871          */
4872         ret = intel_compute_intermediate_wm(state, crtc);
4873         if (ret) {
4874                 drm_dbg_kms(&dev_priv->drm,
4875                             "No valid intermediate pipe watermarks are possible\n");
4876                 return ret;
4877         }
4878
4879         if (DISPLAY_VER(dev_priv) >= 9) {
4880                 if (intel_crtc_needs_modeset(crtc_state) ||
4881                     intel_crtc_needs_fastset(crtc_state)) {
4882                         ret = skl_update_scaler_crtc(crtc_state);
4883                         if (ret)
4884                                 return ret;
4885                 }
4886
4887                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4888                 if (ret)
4889                         return ret;
4890         }
4891
4892         if (HAS_IPS(dev_priv)) {
4893                 ret = hsw_ips_compute_config(state, crtc);
4894                 if (ret)
4895                         return ret;
4896         }
4897
4898         if (DISPLAY_VER(dev_priv) >= 9 ||
4899             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4900                 ret = hsw_compute_linetime_wm(state, crtc);
4901                 if (ret)
4902                         return ret;
4903
4904         }
4905
4906         ret = intel_psr2_sel_fetch_update(state, crtc);
4907         if (ret)
4908                 return ret;
4909
4910         return 0;
4911 }
4912
4913 static int
4914 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4915                       struct intel_crtc_state *crtc_state)
4916 {
4917         struct drm_connector *connector = conn_state->connector;
4918         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4919         const struct drm_display_info *info = &connector->display_info;
4920         int bpp;
4921
4922         switch (conn_state->max_bpc) {
4923         case 6 ... 7:
4924                 bpp = 6 * 3;
4925                 break;
4926         case 8 ... 9:
4927                 bpp = 8 * 3;
4928                 break;
4929         case 10 ... 11:
4930                 bpp = 10 * 3;
4931                 break;
4932         case 12 ... 16:
4933                 bpp = 12 * 3;
4934                 break;
4935         default:
4936                 MISSING_CASE(conn_state->max_bpc);
4937                 return -EINVAL;
4938         }
4939
4940         if (bpp < crtc_state->pipe_bpp) {
4941                 drm_dbg_kms(&i915->drm,
4942                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4943                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4944                             connector->base.id, connector->name,
4945                             bpp, 3 * info->bpc,
4946                             3 * conn_state->max_requested_bpc,
4947                             crtc_state->pipe_bpp);
4948
4949                 crtc_state->pipe_bpp = bpp;
4950         }
4951
4952         return 0;
4953 }
4954
4955 static int
4956 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4957                           struct intel_crtc *crtc)
4958 {
4959         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4960         struct intel_crtc_state *crtc_state =
4961                 intel_atomic_get_new_crtc_state(state, crtc);
4962         struct drm_connector *connector;
4963         struct drm_connector_state *connector_state;
4964         int bpp, i;
4965
4966         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4967             IS_CHERRYVIEW(dev_priv)))
4968                 bpp = 10*3;
4969         else if (DISPLAY_VER(dev_priv) >= 5)
4970                 bpp = 12*3;
4971         else
4972                 bpp = 8*3;
4973
4974         crtc_state->pipe_bpp = bpp;
4975
4976         /* Clamp display bpp to connector max bpp */
4977         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4978                 int ret;
4979
4980                 if (connector_state->crtc != &crtc->base)
4981                         continue;
4982
4983                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4984                 if (ret)
4985                         return ret;
4986         }
4987
4988         return 0;
4989 }
4990
4991 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4992 {
4993         struct drm_device *dev = state->base.dev;
4994         struct drm_connector *connector;
4995         struct drm_connector_list_iter conn_iter;
4996         unsigned int used_ports = 0;
4997         unsigned int used_mst_ports = 0;
4998         bool ret = true;
4999
5000         /*
5001          * We're going to peek into connector->state,
5002          * hence connection_mutex must be held.
5003          */
5004         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
5005
5006         /*
5007          * Walk the connector list instead of the encoder
5008          * list to detect the problem on ddi platforms
5009          * where there's just one encoder per digital port.
5010          */
5011         drm_connector_list_iter_begin(dev, &conn_iter);
5012         drm_for_each_connector_iter(connector, &conn_iter) {
5013                 struct drm_connector_state *connector_state;
5014                 struct intel_encoder *encoder;
5015
5016                 connector_state =
5017                         drm_atomic_get_new_connector_state(&state->base,
5018                                                            connector);
5019                 if (!connector_state)
5020                         connector_state = connector->state;
5021
5022                 if (!connector_state->best_encoder)
5023                         continue;
5024
5025                 encoder = to_intel_encoder(connector_state->best_encoder);
5026
5027                 drm_WARN_ON(dev, !connector_state->crtc);
5028
5029                 switch (encoder->type) {
5030                 case INTEL_OUTPUT_DDI:
5031                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
5032                                 break;
5033                         fallthrough;
5034                 case INTEL_OUTPUT_DP:
5035                 case INTEL_OUTPUT_HDMI:
5036                 case INTEL_OUTPUT_EDP:
5037                         /* the same port mustn't appear more than once */
5038                         if (used_ports & BIT(encoder->port))
5039                                 ret = false;
5040
5041                         used_ports |= BIT(encoder->port);
5042                         break;
5043                 case INTEL_OUTPUT_DP_MST:
5044                         used_mst_ports |=
5045                                 1 << encoder->port;
5046                         break;
5047                 default:
5048                         break;
5049                 }
5050         }
5051         drm_connector_list_iter_end(&conn_iter);
5052
5053         /* can't mix MST and SST/HDMI on the same port */
5054         if (used_ports & used_mst_ports)
5055                 return false;
5056
5057         return ret;
5058 }
5059
5060 static void
5061 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
5062                                            struct intel_crtc *crtc)
5063 {
5064         struct intel_crtc_state *crtc_state =
5065                 intel_atomic_get_new_crtc_state(state, crtc);
5066
5067         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
5068
5069         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
5070                                   crtc_state->uapi.degamma_lut);
5071         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
5072                                   crtc_state->uapi.gamma_lut);
5073         drm_property_replace_blob(&crtc_state->hw.ctm,
5074                                   crtc_state->uapi.ctm);
5075 }
5076
5077 static void
5078 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
5079                                          struct intel_crtc *crtc)
5080 {
5081         struct intel_crtc_state *crtc_state =
5082                 intel_atomic_get_new_crtc_state(state, crtc);
5083
5084         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
5085
5086         crtc_state->hw.enable = crtc_state->uapi.enable;
5087         crtc_state->hw.active = crtc_state->uapi.active;
5088         drm_mode_copy(&crtc_state->hw.mode,
5089                       &crtc_state->uapi.mode);
5090         drm_mode_copy(&crtc_state->hw.adjusted_mode,
5091                       &crtc_state->uapi.adjusted_mode);
5092         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
5093
5094         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
5095 }
5096
5097 static void
5098 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
5099                                     struct intel_crtc *slave_crtc)
5100 {
5101         struct intel_crtc_state *slave_crtc_state =
5102                 intel_atomic_get_new_crtc_state(state, slave_crtc);
5103         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
5104         const struct intel_crtc_state *master_crtc_state =
5105                 intel_atomic_get_new_crtc_state(state, master_crtc);
5106
5107         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
5108                                   master_crtc_state->hw.degamma_lut);
5109         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
5110                                   master_crtc_state->hw.gamma_lut);
5111         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
5112                                   master_crtc_state->hw.ctm);
5113
5114         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
5115 }
5116
5117 static int
5118 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
5119                                   struct intel_crtc *slave_crtc)
5120 {
5121         struct intel_crtc_state *slave_crtc_state =
5122                 intel_atomic_get_new_crtc_state(state, slave_crtc);
5123         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
5124         const struct intel_crtc_state *master_crtc_state =
5125                 intel_atomic_get_new_crtc_state(state, master_crtc);
5126         struct intel_crtc_state *saved_state;
5127
5128         WARN_ON(master_crtc_state->bigjoiner_pipes !=
5129                 slave_crtc_state->bigjoiner_pipes);
5130
5131         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
5132         if (!saved_state)
5133                 return -ENOMEM;
5134
5135         /* preserve some things from the slave's original crtc state */
5136         saved_state->uapi = slave_crtc_state->uapi;
5137         saved_state->scaler_state = slave_crtc_state->scaler_state;
5138         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
5139         saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
5140         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
5141
5142         intel_crtc_free_hw_state(slave_crtc_state);
5143         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
5144         kfree(saved_state);
5145
5146         /* Re-init hw state */
5147         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
5148         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
5149         slave_crtc_state->hw.active = master_crtc_state->hw.active;
5150         drm_mode_copy(&slave_crtc_state->hw.mode,
5151                       &master_crtc_state->hw.mode);
5152         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
5153                       &master_crtc_state->hw.pipe_mode);
5154         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
5155                       &master_crtc_state->hw.adjusted_mode);
5156         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
5157
5158         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
5159
5160         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
5161         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
5162         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
5163
5164         WARN_ON(master_crtc_state->bigjoiner_pipes !=
5165                 slave_crtc_state->bigjoiner_pipes);
5166
5167         return 0;
5168 }
5169
5170 static int
5171 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
5172                                  struct intel_crtc *crtc)
5173 {
5174         struct intel_crtc_state *crtc_state =
5175                 intel_atomic_get_new_crtc_state(state, crtc);
5176         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5177         struct intel_crtc_state *saved_state;
5178
5179         saved_state = intel_crtc_state_alloc(crtc);
5180         if (!saved_state)
5181                 return -ENOMEM;
5182
5183         /* free the old crtc_state->hw members */
5184         intel_crtc_free_hw_state(crtc_state);
5185
5186         /* FIXME: before the switch to atomic started, a new pipe_config was
5187          * kzalloc'd. Code that depends on any field being zero should be
5188          * fixed, so that the crtc_state can be safely duplicated. For now,
5189          * only fields that are know to not cause problems are preserved. */
5190
5191         saved_state->uapi = crtc_state->uapi;
5192         saved_state->scaler_state = crtc_state->scaler_state;
5193         saved_state->shared_dpll = crtc_state->shared_dpll;
5194         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
5195         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
5196                sizeof(saved_state->icl_port_dplls));
5197         saved_state->crc_enabled = crtc_state->crc_enabled;
5198         if (IS_G4X(dev_priv) ||
5199             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5200                 saved_state->wm = crtc_state->wm;
5201
5202         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
5203         kfree(saved_state);
5204
5205         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
5206
5207         return 0;
5208 }
5209
5210 static int
5211 intel_modeset_pipe_config(struct intel_atomic_state *state,
5212                           struct intel_crtc *crtc)
5213 {
5214         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5215         struct intel_crtc_state *crtc_state =
5216                 intel_atomic_get_new_crtc_state(state, crtc);
5217         struct drm_connector *connector;
5218         struct drm_connector_state *connector_state;
5219         int pipe_src_w, pipe_src_h;
5220         int base_bpp, ret, i;
5221         bool retry = true;
5222
5223         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
5224
5225         crtc_state->framestart_delay = 1;
5226
5227         /*
5228          * Sanitize sync polarity flags based on requested ones. If neither
5229          * positive or negative polarity is requested, treat this as meaning
5230          * negative polarity.
5231          */
5232         if (!(crtc_state->hw.adjusted_mode.flags &
5233               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
5234                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
5235
5236         if (!(crtc_state->hw.adjusted_mode.flags &
5237               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
5238                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
5239
5240         ret = compute_baseline_pipe_bpp(state, crtc);
5241         if (ret)
5242                 return ret;
5243
5244         base_bpp = crtc_state->pipe_bpp;
5245
5246         /*
5247          * Determine the real pipe dimensions. Note that stereo modes can
5248          * increase the actual pipe size due to the frame doubling and
5249          * insertion of additional space for blanks between the frame. This
5250          * is stored in the crtc timings. We use the requested mode to do this
5251          * computation to clearly distinguish it from the adjusted mode, which
5252          * can be changed by the connectors in the below retry loop.
5253          */
5254         drm_mode_get_hv_timing(&crtc_state->hw.mode,
5255                                &pipe_src_w, &pipe_src_h);
5256         drm_rect_init(&crtc_state->pipe_src, 0, 0,
5257                       pipe_src_w, pipe_src_h);
5258
5259         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5260                 struct intel_encoder *encoder =
5261                         to_intel_encoder(connector_state->best_encoder);
5262
5263                 if (connector_state->crtc != &crtc->base)
5264                         continue;
5265
5266                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
5267                         drm_dbg_kms(&i915->drm,
5268                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
5269                                     encoder->base.base.id, encoder->base.name);
5270                         return -EINVAL;
5271                 }
5272
5273                 /*
5274                  * Determine output_types before calling the .compute_config()
5275                  * hooks so that the hooks can use this information safely.
5276                  */
5277                 if (encoder->compute_output_type)
5278                         crtc_state->output_types |=
5279                                 BIT(encoder->compute_output_type(encoder, crtc_state,
5280                                                                  connector_state));
5281                 else
5282                         crtc_state->output_types |= BIT(encoder->type);
5283         }
5284
5285 encoder_retry:
5286         /* Ensure the port clock defaults are reset when retrying. */
5287         crtc_state->port_clock = 0;
5288         crtc_state->pixel_multiplier = 1;
5289
5290         /* Fill in default crtc timings, allow encoders to overwrite them. */
5291         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
5292                               CRTC_STEREO_DOUBLE);
5293
5294         /* Pass our mode to the connectors and the CRTC to give them a chance to
5295          * adjust it according to limitations or connector properties, and also
5296          * a chance to reject the mode entirely.
5297          */
5298         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5299                 struct intel_encoder *encoder =
5300                         to_intel_encoder(connector_state->best_encoder);
5301
5302                 if (connector_state->crtc != &crtc->base)
5303                         continue;
5304
5305                 ret = encoder->compute_config(encoder, crtc_state,
5306                                               connector_state);
5307                 if (ret == -EDEADLK)
5308                         return ret;
5309                 if (ret < 0) {
5310                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
5311                                     encoder->base.base.id, encoder->base.name, ret);
5312                         return ret;
5313                 }
5314         }
5315
5316         /* Set default port clock if not overwritten by the encoder. Needs to be
5317          * done afterwards in case the encoder adjusts the mode. */
5318         if (!crtc_state->port_clock)
5319                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
5320                         * crtc_state->pixel_multiplier;
5321
5322         ret = intel_crtc_compute_config(state, crtc);
5323         if (ret == -EDEADLK)
5324                 return ret;
5325         if (ret == -EAGAIN) {
5326                 if (drm_WARN(&i915->drm, !retry,
5327                              "[CRTC:%d:%s] loop in pipe configuration computation\n",
5328                              crtc->base.base.id, crtc->base.name))
5329                         return -EINVAL;
5330
5331                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
5332                             crtc->base.base.id, crtc->base.name);
5333                 retry = false;
5334                 goto encoder_retry;
5335         }
5336         if (ret < 0) {
5337                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
5338                             crtc->base.base.id, crtc->base.name, ret);
5339                 return ret;
5340         }
5341
5342         /* Dithering seems to not pass-through bits correctly when it should, so
5343          * only enable it on 6bpc panels and when its not a compliance
5344          * test requesting 6bpc video pattern.
5345          */
5346         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
5347                 !crtc_state->dither_force_disable;
5348         drm_dbg_kms(&i915->drm,
5349                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
5350                     crtc->base.base.id, crtc->base.name,
5351                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
5352
5353         return 0;
5354 }
5355
5356 static int
5357 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
5358                                struct intel_crtc *crtc)
5359 {
5360         struct intel_crtc_state *crtc_state =
5361                 intel_atomic_get_new_crtc_state(state, crtc);
5362         struct drm_connector_state *conn_state;
5363         struct drm_connector *connector;
5364         int i;
5365
5366         intel_bigjoiner_adjust_pipe_src(crtc_state);
5367
5368         for_each_new_connector_in_state(&state->base, connector,
5369                                         conn_state, i) {
5370                 struct intel_encoder *encoder =
5371                         to_intel_encoder(conn_state->best_encoder);
5372                 int ret;
5373
5374                 if (conn_state->crtc != &crtc->base ||
5375                     !encoder->compute_config_late)
5376                         continue;
5377
5378                 ret = encoder->compute_config_late(encoder, crtc_state,
5379                                                    conn_state);
5380                 if (ret)
5381                         return ret;
5382         }
5383
5384         return 0;
5385 }
5386
5387 bool intel_fuzzy_clock_check(int clock1, int clock2)
5388 {
5389         int diff;
5390
5391         if (clock1 == clock2)
5392                 return true;
5393
5394         if (!clock1 || !clock2)
5395                 return false;
5396
5397         diff = abs(clock1 - clock2);
5398
5399         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
5400                 return true;
5401
5402         return false;
5403 }
5404
5405 static bool
5406 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
5407                        const struct intel_link_m_n *m2_n2)
5408 {
5409         return m_n->tu == m2_n2->tu &&
5410                 m_n->data_m == m2_n2->data_m &&
5411                 m_n->data_n == m2_n2->data_n &&
5412                 m_n->link_m == m2_n2->link_m &&
5413                 m_n->link_n == m2_n2->link_n;
5414 }
5415
5416 static bool
5417 intel_compare_infoframe(const union hdmi_infoframe *a,
5418                         const union hdmi_infoframe *b)
5419 {
5420         return memcmp(a, b, sizeof(*a)) == 0;
5421 }
5422
5423 static bool
5424 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
5425                          const struct drm_dp_vsc_sdp *b)
5426 {
5427         return memcmp(a, b, sizeof(*a)) == 0;
5428 }
5429
5430 static void
5431 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
5432                                bool fastset, const char *name,
5433                                const union hdmi_infoframe *a,
5434                                const union hdmi_infoframe *b)
5435 {
5436         if (fastset) {
5437                 if (!drm_debug_enabled(DRM_UT_KMS))
5438                         return;
5439
5440                 drm_dbg_kms(&dev_priv->drm,
5441                             "fastset mismatch in %s infoframe\n", name);
5442                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5443                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
5444                 drm_dbg_kms(&dev_priv->drm, "found:\n");
5445                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
5446         } else {
5447                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
5448                 drm_err(&dev_priv->drm, "expected:\n");
5449                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
5450                 drm_err(&dev_priv->drm, "found:\n");
5451                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
5452         }
5453 }
5454
5455 static void
5456 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
5457                                 bool fastset, const char *name,
5458                                 const struct drm_dp_vsc_sdp *a,
5459                                 const struct drm_dp_vsc_sdp *b)
5460 {
5461         if (fastset) {
5462                 if (!drm_debug_enabled(DRM_UT_KMS))
5463                         return;
5464
5465                 drm_dbg_kms(&dev_priv->drm,
5466                             "fastset mismatch in %s dp sdp\n", name);
5467                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5468                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
5469                 drm_dbg_kms(&dev_priv->drm, "found:\n");
5470                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
5471         } else {
5472                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
5473                 drm_err(&dev_priv->drm, "expected:\n");
5474                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
5475                 drm_err(&dev_priv->drm, "found:\n");
5476                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
5477         }
5478 }
5479
5480 static void __printf(4, 5)
5481 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
5482                      const char *name, const char *format, ...)
5483 {
5484         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5485         struct va_format vaf;
5486         va_list args;
5487
5488         va_start(args, format);
5489         vaf.fmt = format;
5490         vaf.va = &args;
5491
5492         if (fastset)
5493                 drm_dbg_kms(&i915->drm,
5494                             "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
5495                             crtc->base.base.id, crtc->base.name, name, &vaf);
5496         else
5497                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
5498                         crtc->base.base.id, crtc->base.name, name, &vaf);
5499
5500         va_end(args);
5501 }
5502
5503 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
5504 {
5505         if (dev_priv->params.fastboot != -1)
5506                 return dev_priv->params.fastboot;
5507
5508         /* Enable fastboot by default on Skylake and newer */
5509         if (DISPLAY_VER(dev_priv) >= 9)
5510                 return true;
5511
5512         /* Enable fastboot by default on VLV and CHV */
5513         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5514                 return true;
5515
5516         /* Disabled by default on all others */
5517         return false;
5518 }
5519
5520 bool
5521 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5522                           const struct intel_crtc_state *pipe_config,
5523                           bool fastset)
5524 {
5525         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5526         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5527         bool ret = true;
5528         u32 bp_gamma = 0;
5529         bool fixup_inherited = fastset &&
5530                 current_config->inherited && !pipe_config->inherited;
5531
5532         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5533                 drm_dbg_kms(&dev_priv->drm,
5534                             "initial modeset and fastboot not set\n");
5535                 ret = false;
5536         }
5537
5538 #define PIPE_CONF_CHECK_X(name) do { \
5539         if (current_config->name != pipe_config->name) { \
5540                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5541                                      "(expected 0x%08x, found 0x%08x)", \
5542                                      current_config->name, \
5543                                      pipe_config->name); \
5544                 ret = false; \
5545         } \
5546 } while (0)
5547
5548 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5549         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5550                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5551                                      "(expected 0x%08x, found 0x%08x)", \
5552                                      current_config->name & (mask), \
5553                                      pipe_config->name & (mask)); \
5554                 ret = false; \
5555         } \
5556 } while (0)
5557
5558 #define PIPE_CONF_CHECK_I(name) do { \
5559         if (current_config->name != pipe_config->name) { \
5560                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5561                                      "(expected %i, found %i)", \
5562                                      current_config->name, \
5563                                      pipe_config->name); \
5564                 ret = false; \
5565         } \
5566 } while (0)
5567
5568 #define PIPE_CONF_CHECK_BOOL(name) do { \
5569         if (current_config->name != pipe_config->name) { \
5570                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
5571                                      "(expected %s, found %s)", \
5572                                      str_yes_no(current_config->name), \
5573                                      str_yes_no(pipe_config->name)); \
5574                 ret = false; \
5575         } \
5576 } while (0)
5577
5578 /*
5579  * Checks state where we only read out the enabling, but not the entire
5580  * state itself (like full infoframes or ELD for audio). These states
5581  * require a full modeset on bootup to fix up.
5582  */
5583 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5584         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5585                 PIPE_CONF_CHECK_BOOL(name); \
5586         } else { \
5587                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5588                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5589                                      str_yes_no(current_config->name), \
5590                                      str_yes_no(pipe_config->name)); \
5591                 ret = false; \
5592         } \
5593 } while (0)
5594
5595 #define PIPE_CONF_CHECK_P(name) do { \
5596         if (current_config->name != pipe_config->name) { \
5597                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5598                                      "(expected %p, found %p)", \
5599                                      current_config->name, \
5600                                      pipe_config->name); \
5601                 ret = false; \
5602         } \
5603 } while (0)
5604
5605 #define PIPE_CONF_CHECK_M_N(name) do { \
5606         if (!intel_compare_link_m_n(&current_config->name, \
5607                                     &pipe_config->name)) { \
5608                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5609                                      "(expected tu %i data %i/%i link %i/%i, " \
5610                                      "found tu %i, data %i/%i link %i/%i)", \
5611                                      current_config->name.tu, \
5612                                      current_config->name.data_m, \
5613                                      current_config->name.data_n, \
5614                                      current_config->name.link_m, \
5615                                      current_config->name.link_n, \
5616                                      pipe_config->name.tu, \
5617                                      pipe_config->name.data_m, \
5618                                      pipe_config->name.data_n, \
5619                                      pipe_config->name.link_m, \
5620                                      pipe_config->name.link_n); \
5621                 ret = false; \
5622         } \
5623 } while (0)
5624
5625 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5626         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5627         PIPE_CONF_CHECK_I(name.crtc_htotal); \
5628         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5629         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5630         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5631         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5632         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5633         PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5634         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5635         PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5636         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5637         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5638 } while (0)
5639
5640 #define PIPE_CONF_CHECK_RECT(name) do { \
5641         PIPE_CONF_CHECK_I(name.x1); \
5642         PIPE_CONF_CHECK_I(name.x2); \
5643         PIPE_CONF_CHECK_I(name.y1); \
5644         PIPE_CONF_CHECK_I(name.y2); \
5645 } while (0)
5646
5647 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5648         if ((current_config->name ^ pipe_config->name) & (mask)) { \
5649                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5650                                      "(%x) (expected %i, found %i)", \
5651                                      (mask), \
5652                                      current_config->name & (mask), \
5653                                      pipe_config->name & (mask)); \
5654                 ret = false; \
5655         } \
5656 } while (0)
5657
5658 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5659         if (!intel_compare_infoframe(&current_config->infoframes.name, \
5660                                      &pipe_config->infoframes.name)) { \
5661                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5662                                                &current_config->infoframes.name, \
5663                                                &pipe_config->infoframes.name); \
5664                 ret = false; \
5665         } \
5666 } while (0)
5667
5668 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5669         if (!current_config->has_psr && !pipe_config->has_psr && \
5670             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5671                                       &pipe_config->infoframes.name)) { \
5672                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5673                                                 &current_config->infoframes.name, \
5674                                                 &pipe_config->infoframes.name); \
5675                 ret = false; \
5676         } \
5677 } while (0)
5678
5679 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
5680         if (current_config->name1 != pipe_config->name1) { \
5681                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
5682                                 "(expected %i, found %i, won't compare lut values)", \
5683                                 current_config->name1, \
5684                                 pipe_config->name1); \
5685                 ret = false;\
5686         } else { \
5687                 if (!intel_color_lut_equal(current_config->name2, \
5688                                         pipe_config->name2, pipe_config->name1, \
5689                                         bit_precision)) { \
5690                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
5691                                         "hw_state doesn't match sw_state"); \
5692                         ret = false; \
5693                 } \
5694         } \
5695 } while (0)
5696
5697 #define PIPE_CONF_QUIRK(quirk) \
5698         ((current_config->quirks | pipe_config->quirks) & (quirk))
5699
5700         PIPE_CONF_CHECK_I(hw.enable);
5701         PIPE_CONF_CHECK_I(hw.active);
5702
5703         PIPE_CONF_CHECK_I(cpu_transcoder);
5704         PIPE_CONF_CHECK_I(mst_master_transcoder);
5705
5706         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5707         PIPE_CONF_CHECK_I(fdi_lanes);
5708         PIPE_CONF_CHECK_M_N(fdi_m_n);
5709
5710         PIPE_CONF_CHECK_I(lane_count);
5711         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5712
5713         if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5714                 if (!fastset || !pipe_config->seamless_m_n)
5715                         PIPE_CONF_CHECK_M_N(dp_m_n);
5716         } else {
5717                 PIPE_CONF_CHECK_M_N(dp_m_n);
5718                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5719         }
5720
5721         PIPE_CONF_CHECK_X(output_types);
5722
5723         PIPE_CONF_CHECK_I(framestart_delay);
5724         PIPE_CONF_CHECK_I(msa_timing_delay);
5725
5726         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5727         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5728
5729         PIPE_CONF_CHECK_I(pixel_multiplier);
5730
5731         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5732                               DRM_MODE_FLAG_INTERLACE);
5733
5734         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5735                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5736                                       DRM_MODE_FLAG_PHSYNC);
5737                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5738                                       DRM_MODE_FLAG_NHSYNC);
5739                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5740                                       DRM_MODE_FLAG_PVSYNC);
5741                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5742                                       DRM_MODE_FLAG_NVSYNC);
5743         }
5744
5745         PIPE_CONF_CHECK_I(output_format);
5746         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5747         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5748             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5749                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5750
5751         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5752         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5753         PIPE_CONF_CHECK_BOOL(has_infoframe);
5754         PIPE_CONF_CHECK_BOOL(fec_enable);
5755
5756         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5757
5758         PIPE_CONF_CHECK_X(gmch_pfit.control);
5759         /* pfit ratios are autocomputed by the hw on gen4+ */
5760         if (DISPLAY_VER(dev_priv) < 4)
5761                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5762         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5763
5764         /*
5765          * Changing the EDP transcoder input mux
5766          * (A_ONOFF vs. A_ON) requires a full modeset.
5767          */
5768         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5769
5770         if (!fastset) {
5771                 PIPE_CONF_CHECK_RECT(pipe_src);
5772
5773                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5774                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5775
5776                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5777                 PIPE_CONF_CHECK_I(pixel_rate);
5778
5779                 PIPE_CONF_CHECK_X(gamma_mode);
5780                 if (IS_CHERRYVIEW(dev_priv))
5781                         PIPE_CONF_CHECK_X(cgm_mode);
5782                 else
5783                         PIPE_CONF_CHECK_X(csc_mode);
5784                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5785                 PIPE_CONF_CHECK_BOOL(csc_enable);
5786
5787                 PIPE_CONF_CHECK_I(linetime);
5788                 PIPE_CONF_CHECK_I(ips_linetime);
5789
5790                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
5791                 if (bp_gamma)
5792                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, post_csc_lut, bp_gamma);
5793
5794                 if (current_config->active_planes) {
5795                         PIPE_CONF_CHECK_BOOL(has_psr);
5796                         PIPE_CONF_CHECK_BOOL(has_psr2);
5797                         PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5798                         PIPE_CONF_CHECK_I(dc3co_exitline);
5799                 }
5800         }
5801
5802         PIPE_CONF_CHECK_BOOL(double_wide);
5803
5804         if (dev_priv->display.dpll.mgr) {
5805                 PIPE_CONF_CHECK_P(shared_dpll);
5806
5807                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5808                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5809                 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5810                 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5811                 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5812                 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5813                 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5814                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5815                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5816                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5817                 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5818                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5819                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5820                 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5821                 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5822                 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5823                 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5824                 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5825                 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5826                 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5827                 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5828                 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5829                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5830                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5831                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5832                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5833                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5834                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5835                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5836                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5837                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5838                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5839         }
5840
5841         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5842         PIPE_CONF_CHECK_X(dsi_pll.div);
5843
5844         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5845                 PIPE_CONF_CHECK_I(pipe_bpp);
5846
5847         if (!fastset || !pipe_config->seamless_m_n) {
5848                 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5849                 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5850         }
5851         PIPE_CONF_CHECK_I(port_clock);
5852
5853         PIPE_CONF_CHECK_I(min_voltage_level);
5854
5855         if (current_config->has_psr || pipe_config->has_psr)
5856                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5857                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5858         else
5859                 PIPE_CONF_CHECK_X(infoframes.enable);
5860
5861         PIPE_CONF_CHECK_X(infoframes.gcp);
5862         PIPE_CONF_CHECK_INFOFRAME(avi);
5863         PIPE_CONF_CHECK_INFOFRAME(spd);
5864         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5865         PIPE_CONF_CHECK_INFOFRAME(drm);
5866         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5867
5868         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5869         PIPE_CONF_CHECK_I(master_transcoder);
5870         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5871
5872         PIPE_CONF_CHECK_I(dsc.compression_enable);
5873         PIPE_CONF_CHECK_I(dsc.dsc_split);
5874         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5875
5876         PIPE_CONF_CHECK_BOOL(splitter.enable);
5877         PIPE_CONF_CHECK_I(splitter.link_count);
5878         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5879
5880         PIPE_CONF_CHECK_BOOL(vrr.enable);
5881         PIPE_CONF_CHECK_I(vrr.vmin);
5882         PIPE_CONF_CHECK_I(vrr.vmax);
5883         PIPE_CONF_CHECK_I(vrr.flipline);
5884         PIPE_CONF_CHECK_I(vrr.pipeline_full);
5885         PIPE_CONF_CHECK_I(vrr.guardband);
5886
5887 #undef PIPE_CONF_CHECK_X
5888 #undef PIPE_CONF_CHECK_I
5889 #undef PIPE_CONF_CHECK_BOOL
5890 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5891 #undef PIPE_CONF_CHECK_P
5892 #undef PIPE_CONF_CHECK_FLAGS
5893 #undef PIPE_CONF_CHECK_COLOR_LUT
5894 #undef PIPE_CONF_CHECK_TIMINGS
5895 #undef PIPE_CONF_CHECK_RECT
5896 #undef PIPE_CONF_QUIRK
5897
5898         return ret;
5899 }
5900
5901 static void
5902 intel_verify_planes(struct intel_atomic_state *state)
5903 {
5904         struct intel_plane *plane;
5905         const struct intel_plane_state *plane_state;
5906         int i;
5907
5908         for_each_new_intel_plane_in_state(state, plane,
5909                                           plane_state, i)
5910                 assert_plane(plane, plane_state->planar_slave ||
5911                              plane_state->uapi.visible);
5912 }
5913
5914 int intel_modeset_all_pipes(struct intel_atomic_state *state,
5915                             const char *reason)
5916 {
5917         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5918         struct intel_crtc *crtc;
5919
5920         /*
5921          * Add all pipes to the state, and force
5922          * a modeset on all the active ones.
5923          */
5924         for_each_intel_crtc(&dev_priv->drm, crtc) {
5925                 struct intel_crtc_state *crtc_state;
5926                 int ret;
5927
5928                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5929                 if (IS_ERR(crtc_state))
5930                         return PTR_ERR(crtc_state);
5931
5932                 if (!crtc_state->hw.active ||
5933                     drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
5934                         continue;
5935
5936                 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5937                             crtc->base.base.id, crtc->base.name, reason);
5938
5939                 crtc_state->uapi.mode_changed = true;
5940                 crtc_state->update_pipe = false;
5941
5942                 ret = drm_atomic_add_affected_connectors(&state->base,
5943                                                          &crtc->base);
5944                 if (ret)
5945                         return ret;
5946
5947                 ret = intel_atomic_add_affected_planes(state, crtc);
5948                 if (ret)
5949                         return ret;
5950
5951                 crtc_state->update_planes |= crtc_state->active_planes;
5952         }
5953
5954         return 0;
5955 }
5956
5957 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
5958 {
5959         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5960         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5961         struct drm_display_mode adjusted_mode;
5962
5963         drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
5964
5965         if (crtc_state->vrr.enable) {
5966                 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
5967                 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
5968                 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
5969                 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
5970         }
5971
5972         drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
5973
5974         crtc->mode_flags = crtc_state->mode_flags;
5975
5976         /*
5977          * The scanline counter increments at the leading edge of hsync.
5978          *
5979          * On most platforms it starts counting from vtotal-1 on the
5980          * first active line. That means the scanline counter value is
5981          * always one less than what we would expect. Ie. just after
5982          * start of vblank, which also occurs at start of hsync (on the
5983          * last active line), the scanline counter will read vblank_start-1.
5984          *
5985          * On gen2 the scanline counter starts counting from 1 instead
5986          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
5987          * to keep the value positive), instead of adding one.
5988          *
5989          * On HSW+ the behaviour of the scanline counter depends on the output
5990          * type. For DP ports it behaves like most other platforms, but on HDMI
5991          * there's an extra 1 line difference. So we need to add two instead of
5992          * one to the value.
5993          *
5994          * On VLV/CHV DSI the scanline counter would appear to increment
5995          * approx. 1/3 of a scanline before start of vblank. Unfortunately
5996          * that means we can't tell whether we're in vblank or not while
5997          * we're on that particular line. We must still set scanline_offset
5998          * to 1 so that the vblank timestamps come out correct when we query
5999          * the scanline counter from within the vblank interrupt handler.
6000          * However if queried just before the start of vblank we'll get an
6001          * answer that's slightly in the future.
6002          */
6003         if (DISPLAY_VER(dev_priv) == 2) {
6004                 int vtotal;
6005
6006                 vtotal = adjusted_mode.crtc_vtotal;
6007                 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6008                         vtotal /= 2;
6009
6010                 crtc->scanline_offset = vtotal - 1;
6011         } else if (HAS_DDI(dev_priv) &&
6012                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
6013                 crtc->scanline_offset = 2;
6014         } else {
6015                 crtc->scanline_offset = 1;
6016         }
6017 }
6018
6019 /*
6020  * This implements the workaround described in the "notes" section of the mode
6021  * set sequence documentation. When going from no pipes or single pipe to
6022  * multiple pipes, and planes are enabled after the pipe, we need to wait at
6023  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
6024  */
6025 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
6026 {
6027         struct intel_crtc_state *crtc_state;
6028         struct intel_crtc *crtc;
6029         struct intel_crtc_state *first_crtc_state = NULL;
6030         struct intel_crtc_state *other_crtc_state = NULL;
6031         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
6032         int i;
6033
6034         /* look at all crtc's that are going to be enabled in during modeset */
6035         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6036                 if (!crtc_state->hw.active ||
6037                     !intel_crtc_needs_modeset(crtc_state))
6038                         continue;
6039
6040                 if (first_crtc_state) {
6041                         other_crtc_state = crtc_state;
6042                         break;
6043                 } else {
6044                         first_crtc_state = crtc_state;
6045                         first_pipe = crtc->pipe;
6046                 }
6047         }
6048
6049         /* No workaround needed? */
6050         if (!first_crtc_state)
6051                 return 0;
6052
6053         /* w/a possibly needed, check how many crtc's are already enabled. */
6054         for_each_intel_crtc(state->base.dev, crtc) {
6055                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6056                 if (IS_ERR(crtc_state))
6057                         return PTR_ERR(crtc_state);
6058
6059                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
6060
6061                 if (!crtc_state->hw.active ||
6062                     intel_crtc_needs_modeset(crtc_state))
6063                         continue;
6064
6065                 /* 2 or more enabled crtcs means no need for w/a */
6066                 if (enabled_pipe != INVALID_PIPE)
6067                         return 0;
6068
6069                 enabled_pipe = crtc->pipe;
6070         }
6071
6072         if (enabled_pipe != INVALID_PIPE)
6073                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
6074         else if (other_crtc_state)
6075                 other_crtc_state->hsw_workaround_pipe = first_pipe;
6076
6077         return 0;
6078 }
6079
6080 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
6081                            u8 active_pipes)
6082 {
6083         const struct intel_crtc_state *crtc_state;
6084         struct intel_crtc *crtc;
6085         int i;
6086
6087         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6088                 if (crtc_state->hw.active)
6089                         active_pipes |= BIT(crtc->pipe);
6090                 else
6091                         active_pipes &= ~BIT(crtc->pipe);
6092         }
6093
6094         return active_pipes;
6095 }
6096
6097 static int intel_modeset_checks(struct intel_atomic_state *state)
6098 {
6099         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6100
6101         state->modeset = true;
6102
6103         if (IS_HASWELL(dev_priv))
6104                 return hsw_mode_set_planes_workaround(state);
6105
6106         return 0;
6107 }
6108
6109 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
6110                                      struct intel_crtc_state *new_crtc_state)
6111 {
6112         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
6113                 return;
6114
6115         new_crtc_state->uapi.mode_changed = false;
6116         if (!intel_crtc_needs_modeset(new_crtc_state))
6117                 new_crtc_state->update_pipe = true;
6118 }
6119
6120 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
6121                                           struct intel_crtc *crtc,
6122                                           u8 plane_ids_mask)
6123 {
6124         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6125         struct intel_plane *plane;
6126
6127         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6128                 struct intel_plane_state *plane_state;
6129
6130                 if ((plane_ids_mask & BIT(plane->id)) == 0)
6131                         continue;
6132
6133                 plane_state = intel_atomic_get_plane_state(state, plane);
6134                 if (IS_ERR(plane_state))
6135                         return PTR_ERR(plane_state);
6136         }
6137
6138         return 0;
6139 }
6140
6141 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
6142                                      struct intel_crtc *crtc)
6143 {
6144         const struct intel_crtc_state *old_crtc_state =
6145                 intel_atomic_get_old_crtc_state(state, crtc);
6146         const struct intel_crtc_state *new_crtc_state =
6147                 intel_atomic_get_new_crtc_state(state, crtc);
6148
6149         return intel_crtc_add_planes_to_state(state, crtc,
6150                                               old_crtc_state->enabled_planes |
6151                                               new_crtc_state->enabled_planes);
6152 }
6153
6154 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
6155 {
6156         /* See {hsw,vlv,ivb}_plane_ratio() */
6157         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
6158                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
6159                 IS_IVYBRIDGE(dev_priv);
6160 }
6161
6162 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
6163                                            struct intel_crtc *crtc,
6164                                            struct intel_crtc *other)
6165 {
6166         const struct intel_plane_state *plane_state;
6167         struct intel_plane *plane;
6168         u8 plane_ids = 0;
6169         int i;
6170
6171         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6172                 if (plane->pipe == crtc->pipe)
6173                         plane_ids |= BIT(plane->id);
6174         }
6175
6176         return intel_crtc_add_planes_to_state(state, other, plane_ids);
6177 }
6178
6179 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
6180 {
6181         struct drm_i915_private *i915 = to_i915(state->base.dev);
6182         const struct intel_crtc_state *crtc_state;
6183         struct intel_crtc *crtc;
6184         int i;
6185
6186         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6187                 struct intel_crtc *other;
6188
6189                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
6190                                                  crtc_state->bigjoiner_pipes) {
6191                         int ret;
6192
6193                         if (crtc == other)
6194                                 continue;
6195
6196                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
6197                         if (ret)
6198                                 return ret;
6199                 }
6200         }
6201
6202         return 0;
6203 }
6204
6205 static int intel_atomic_check_planes(struct intel_atomic_state *state)
6206 {
6207         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6208         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6209         struct intel_plane_state *plane_state;
6210         struct intel_plane *plane;
6211         struct intel_crtc *crtc;
6212         int i, ret;
6213
6214         ret = icl_add_linked_planes(state);
6215         if (ret)
6216                 return ret;
6217
6218         ret = intel_bigjoiner_add_affected_planes(state);
6219         if (ret)
6220                 return ret;
6221
6222         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6223                 ret = intel_plane_atomic_check(state, plane);
6224                 if (ret) {
6225                         drm_dbg_atomic(&dev_priv->drm,
6226                                        "[PLANE:%d:%s] atomic driver check failed\n",
6227                                        plane->base.base.id, plane->base.name);
6228                         return ret;
6229                 }
6230         }
6231
6232         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6233                                             new_crtc_state, i) {
6234                 u8 old_active_planes, new_active_planes;
6235
6236                 ret = icl_check_nv12_planes(new_crtc_state);
6237                 if (ret)
6238                         return ret;
6239
6240                 /*
6241                  * On some platforms the number of active planes affects
6242                  * the planes' minimum cdclk calculation. Add such planes
6243                  * to the state before we compute the minimum cdclk.
6244                  */
6245                 if (!active_planes_affects_min_cdclk(dev_priv))
6246                         continue;
6247
6248                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6249                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6250
6251                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
6252                         continue;
6253
6254                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
6255                 if (ret)
6256                         return ret;
6257         }
6258
6259         return 0;
6260 }
6261
6262 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
6263 {
6264         struct intel_crtc_state *crtc_state;
6265         struct intel_crtc *crtc;
6266         int i;
6267
6268         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6269                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6270                 int ret;
6271
6272                 ret = intel_crtc_atomic_check(state, crtc);
6273                 if (ret) {
6274                         drm_dbg_atomic(&i915->drm,
6275                                        "[CRTC:%d:%s] atomic driver check failed\n",
6276                                        crtc->base.base.id, crtc->base.name);
6277                         return ret;
6278                 }
6279         }
6280
6281         return 0;
6282 }
6283
6284 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
6285                                                u8 transcoders)
6286 {
6287         const struct intel_crtc_state *new_crtc_state;
6288         struct intel_crtc *crtc;
6289         int i;
6290
6291         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6292                 if (new_crtc_state->hw.enable &&
6293                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
6294                     intel_crtc_needs_modeset(new_crtc_state))
6295                         return true;
6296         }
6297
6298         return false;
6299 }
6300
6301 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
6302                                      u8 pipes)
6303 {
6304         const struct intel_crtc_state *new_crtc_state;
6305         struct intel_crtc *crtc;
6306         int i;
6307
6308         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6309                 if (new_crtc_state->hw.enable &&
6310                     pipes & BIT(crtc->pipe) &&
6311                     intel_crtc_needs_modeset(new_crtc_state))
6312                         return true;
6313         }
6314
6315         return false;
6316 }
6317
6318 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
6319                                         struct intel_crtc *master_crtc)
6320 {
6321         struct drm_i915_private *i915 = to_i915(state->base.dev);
6322         struct intel_crtc_state *master_crtc_state =
6323                 intel_atomic_get_new_crtc_state(state, master_crtc);
6324         struct intel_crtc *slave_crtc;
6325
6326         if (!master_crtc_state->bigjoiner_pipes)
6327                 return 0;
6328
6329         /* sanity check */
6330         if (drm_WARN_ON(&i915->drm,
6331                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
6332                 return -EINVAL;
6333
6334         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
6335                 drm_dbg_kms(&i915->drm,
6336                             "[CRTC:%d:%s] Cannot act as big joiner master "
6337                             "(need 0x%x as pipes, only 0x%x possible)\n",
6338                             master_crtc->base.base.id, master_crtc->base.name,
6339                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
6340                 return -EINVAL;
6341         }
6342
6343         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6344                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6345                 struct intel_crtc_state *slave_crtc_state;
6346                 int ret;
6347
6348                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
6349                 if (IS_ERR(slave_crtc_state))
6350                         return PTR_ERR(slave_crtc_state);
6351
6352                 /* master being enabled, slave was already configured? */
6353                 if (slave_crtc_state->uapi.enable) {
6354                         drm_dbg_kms(&i915->drm,
6355                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
6356                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
6357                                     slave_crtc->base.base.id, slave_crtc->base.name,
6358                                     master_crtc->base.base.id, master_crtc->base.name);
6359                         return -EINVAL;
6360                 }
6361
6362                 /*
6363                  * The state copy logic assumes the master crtc gets processed
6364                  * before the slave crtc during the main compute_config loop.
6365                  * This works because the crtcs are created in pipe order,
6366                  * and the hardware requires master pipe < slave pipe as well.
6367                  * Should that change we need to rethink the logic.
6368                  */
6369                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
6370                             drm_crtc_index(&slave_crtc->base)))
6371                         return -EINVAL;
6372
6373                 drm_dbg_kms(&i915->drm,
6374                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
6375                             slave_crtc->base.base.id, slave_crtc->base.name,
6376                             master_crtc->base.base.id, master_crtc->base.name);
6377
6378                 slave_crtc_state->bigjoiner_pipes =
6379                         master_crtc_state->bigjoiner_pipes;
6380
6381                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
6382                 if (ret)
6383                         return ret;
6384         }
6385
6386         return 0;
6387 }
6388
6389 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
6390                                  struct intel_crtc *master_crtc)
6391 {
6392         struct drm_i915_private *i915 = to_i915(state->base.dev);
6393         struct intel_crtc_state *master_crtc_state =
6394                 intel_atomic_get_new_crtc_state(state, master_crtc);
6395         struct intel_crtc *slave_crtc;
6396
6397         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6398                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6399                 struct intel_crtc_state *slave_crtc_state =
6400                         intel_atomic_get_new_crtc_state(state, slave_crtc);
6401
6402                 slave_crtc_state->bigjoiner_pipes = 0;
6403
6404                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
6405         }
6406
6407         master_crtc_state->bigjoiner_pipes = 0;
6408 }
6409
6410 /**
6411  * DOC: asynchronous flip implementation
6412  *
6413  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
6414  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
6415  * Correspondingly, support is currently added for primary plane only.
6416  *
6417  * Async flip can only change the plane surface address, so anything else
6418  * changing is rejected from the intel_async_flip_check_hw() function.
6419  * Once this check is cleared, flip done interrupt is enabled using
6420  * the intel_crtc_enable_flip_done() function.
6421  *
6422  * As soon as the surface address register is written, flip done interrupt is
6423  * generated and the requested events are sent to the usersapce in the interrupt
6424  * handler itself. The timestamp and sequence sent during the flip done event
6425  * correspond to the last vblank and have no relation to the actual time when
6426  * the flip done event was sent.
6427  */
6428 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
6429                                        struct intel_crtc *crtc)
6430 {
6431         struct drm_i915_private *i915 = to_i915(state->base.dev);
6432         const struct intel_crtc_state *new_crtc_state =
6433                 intel_atomic_get_new_crtc_state(state, crtc);
6434         const struct intel_plane_state *old_plane_state;
6435         struct intel_plane_state *new_plane_state;
6436         struct intel_plane *plane;
6437         int i;
6438
6439         if (!new_crtc_state->uapi.async_flip)
6440                 return 0;
6441
6442         if (!new_crtc_state->uapi.active) {
6443                 drm_dbg_kms(&i915->drm,
6444                             "[CRTC:%d:%s] not active\n",
6445                             crtc->base.base.id, crtc->base.name);
6446                 return -EINVAL;
6447         }
6448
6449         if (intel_crtc_needs_modeset(new_crtc_state)) {
6450                 drm_dbg_kms(&i915->drm,
6451                             "[CRTC:%d:%s] modeset required\n",
6452                             crtc->base.base.id, crtc->base.name);
6453                 return -EINVAL;
6454         }
6455
6456         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6457                                              new_plane_state, i) {
6458                 if (plane->pipe != crtc->pipe)
6459                         continue;
6460
6461                 /*
6462                  * TODO: Async flip is only supported through the page flip IOCTL
6463                  * as of now. So support currently added for primary plane only.
6464                  * Support for other planes on platforms on which supports
6465                  * this(vlv/chv and icl+) should be added when async flip is
6466                  * enabled in the atomic IOCTL path.
6467                  */
6468                 if (!plane->async_flip) {
6469                         drm_dbg_kms(&i915->drm,
6470                                     "[PLANE:%d:%s] async flip not supported\n",
6471                                     plane->base.base.id, plane->base.name);
6472                         return -EINVAL;
6473                 }
6474
6475                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6476                         drm_dbg_kms(&i915->drm,
6477                                     "[PLANE:%d:%s] no old or new framebuffer\n",
6478                                     plane->base.base.id, plane->base.name);
6479                         return -EINVAL;
6480                 }
6481         }
6482
6483         return 0;
6484 }
6485
6486 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6487 {
6488         struct drm_i915_private *i915 = to_i915(state->base.dev);
6489         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6490         const struct intel_plane_state *new_plane_state, *old_plane_state;
6491         struct intel_plane *plane;
6492         int i;
6493
6494         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6495         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6496
6497         if (!new_crtc_state->uapi.async_flip)
6498                 return 0;
6499
6500         if (!new_crtc_state->hw.active) {
6501                 drm_dbg_kms(&i915->drm,
6502                             "[CRTC:%d:%s] not active\n",
6503                             crtc->base.base.id, crtc->base.name);
6504                 return -EINVAL;
6505         }
6506
6507         if (intel_crtc_needs_modeset(new_crtc_state)) {
6508                 drm_dbg_kms(&i915->drm,
6509                             "[CRTC:%d:%s] modeset required\n",
6510                             crtc->base.base.id, crtc->base.name);
6511                 return -EINVAL;
6512         }
6513
6514         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6515                 drm_dbg_kms(&i915->drm,
6516                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6517                             crtc->base.base.id, crtc->base.name);
6518                 return -EINVAL;
6519         }
6520
6521         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6522                                              new_plane_state, i) {
6523                 if (plane->pipe != crtc->pipe)
6524                         continue;
6525
6526                 /*
6527                  * Only async flip capable planes should be in the state
6528                  * if we're really about to ask the hardware to perform
6529                  * an async flip. We should never get this far otherwise.
6530                  */
6531                 if (drm_WARN_ON(&i915->drm,
6532                                 new_crtc_state->do_async_flip && !plane->async_flip))
6533                         return -EINVAL;
6534
6535                 /*
6536                  * Only check async flip capable planes other planes
6537                  * may be involved in the initial commit due to
6538                  * the wm0/ddb optimization.
6539                  *
6540                  * TODO maybe should track which planes actually
6541                  * were requested to do the async flip...
6542                  */
6543                 if (!plane->async_flip)
6544                         continue;
6545
6546                 /*
6547                  * FIXME: This check is kept generic for all platforms.
6548                  * Need to verify this for all gen9 platforms to enable
6549                  * this selectively if required.
6550                  */
6551                 switch (new_plane_state->hw.fb->modifier) {
6552                 case I915_FORMAT_MOD_X_TILED:
6553                 case I915_FORMAT_MOD_Y_TILED:
6554                 case I915_FORMAT_MOD_Yf_TILED:
6555                 case I915_FORMAT_MOD_4_TILED:
6556                         break;
6557                 default:
6558                         drm_dbg_kms(&i915->drm,
6559                                     "[PLANE:%d:%s] Modifier does not support async flips\n",
6560                                     plane->base.base.id, plane->base.name);
6561                         return -EINVAL;
6562                 }
6563
6564                 if (new_plane_state->hw.fb->format->num_planes > 1) {
6565                         drm_dbg_kms(&i915->drm,
6566                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
6567                                     plane->base.base.id, plane->base.name);
6568                         return -EINVAL;
6569                 }
6570
6571                 if (old_plane_state->view.color_plane[0].mapping_stride !=
6572                     new_plane_state->view.color_plane[0].mapping_stride) {
6573                         drm_dbg_kms(&i915->drm,
6574                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6575                                     plane->base.base.id, plane->base.name);
6576                         return -EINVAL;
6577                 }
6578
6579                 if (old_plane_state->hw.fb->modifier !=
6580                     new_plane_state->hw.fb->modifier) {
6581                         drm_dbg_kms(&i915->drm,
6582                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6583                                     plane->base.base.id, plane->base.name);
6584                         return -EINVAL;
6585                 }
6586
6587                 if (old_plane_state->hw.fb->format !=
6588                     new_plane_state->hw.fb->format) {
6589                         drm_dbg_kms(&i915->drm,
6590                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6591                                     plane->base.base.id, plane->base.name);
6592                         return -EINVAL;
6593                 }
6594
6595                 if (old_plane_state->hw.rotation !=
6596                     new_plane_state->hw.rotation) {
6597                         drm_dbg_kms(&i915->drm,
6598                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6599                                     plane->base.base.id, plane->base.name);
6600                         return -EINVAL;
6601                 }
6602
6603                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6604                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6605                         drm_dbg_kms(&i915->drm,
6606                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6607                                     plane->base.base.id, plane->base.name);
6608                         return -EINVAL;
6609                 }
6610
6611                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6612                         drm_dbg_kms(&i915->drm,
6613                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6614                                     plane->base.base.id, plane->base.name);
6615                         return -EINVAL;
6616                 }
6617
6618                 if (old_plane_state->hw.pixel_blend_mode !=
6619                     new_plane_state->hw.pixel_blend_mode) {
6620                         drm_dbg_kms(&i915->drm,
6621                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6622                                     plane->base.base.id, plane->base.name);
6623                         return -EINVAL;
6624                 }
6625
6626                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6627                         drm_dbg_kms(&i915->drm,
6628                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6629                                     plane->base.base.id, plane->base.name);
6630                         return -EINVAL;
6631                 }
6632
6633                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6634                         drm_dbg_kms(&i915->drm,
6635                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6636                                     plane->base.base.id, plane->base.name);
6637                         return -EINVAL;
6638                 }
6639
6640                 /* plane decryption is allow to change only in synchronous flips */
6641                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6642                         drm_dbg_kms(&i915->drm,
6643                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6644                                     plane->base.base.id, plane->base.name);
6645                         return -EINVAL;
6646                 }
6647         }
6648
6649         return 0;
6650 }
6651
6652 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6653 {
6654         struct drm_i915_private *i915 = to_i915(state->base.dev);
6655         struct intel_crtc_state *crtc_state;
6656         struct intel_crtc *crtc;
6657         u8 affected_pipes = 0;
6658         u8 modeset_pipes = 0;
6659         int i;
6660
6661         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6662                 affected_pipes |= crtc_state->bigjoiner_pipes;
6663                 if (intel_crtc_needs_modeset(crtc_state))
6664                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6665         }
6666
6667         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6668                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6669                 if (IS_ERR(crtc_state))
6670                         return PTR_ERR(crtc_state);
6671         }
6672
6673         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6674                 int ret;
6675
6676                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6677
6678                 crtc_state->uapi.mode_changed = true;
6679
6680                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6681                 if (ret)
6682                         return ret;
6683
6684                 ret = intel_atomic_add_affected_planes(state, crtc);
6685                 if (ret)
6686                         return ret;
6687         }
6688
6689         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6690                 /* Kill old bigjoiner link, we may re-establish afterwards */
6691                 if (intel_crtc_needs_modeset(crtc_state) &&
6692                     intel_crtc_is_bigjoiner_master(crtc_state))
6693                         kill_bigjoiner_slave(state, crtc);
6694         }
6695
6696         return 0;
6697 }
6698
6699 /**
6700  * intel_atomic_check - validate state object
6701  * @dev: drm device
6702  * @_state: state to validate
6703  */
6704 static int intel_atomic_check(struct drm_device *dev,
6705                               struct drm_atomic_state *_state)
6706 {
6707         struct drm_i915_private *dev_priv = to_i915(dev);
6708         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6709         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6710         struct intel_crtc *crtc;
6711         int ret, i;
6712         bool any_ms = false;
6713
6714         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6715                                             new_crtc_state, i) {
6716                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6717                         new_crtc_state->uapi.mode_changed = true;
6718
6719                 if (new_crtc_state->uapi.scaling_filter !=
6720                     old_crtc_state->uapi.scaling_filter)
6721                         new_crtc_state->uapi.mode_changed = true;
6722         }
6723
6724         intel_vrr_check_modeset(state);
6725
6726         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6727         if (ret)
6728                 goto fail;
6729
6730         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6731                 ret = intel_async_flip_check_uapi(state, crtc);
6732                 if (ret)
6733                         return ret;
6734         }
6735
6736         ret = intel_bigjoiner_add_affected_crtcs(state);
6737         if (ret)
6738                 goto fail;
6739
6740         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6741                                             new_crtc_state, i) {
6742                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6743                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6744                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6745                         else
6746                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6747                         continue;
6748                 }
6749
6750                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6751                         drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6752                         continue;
6753                 }
6754
6755                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6756                 if (ret)
6757                         goto fail;
6758
6759                 if (!new_crtc_state->hw.enable)
6760                         continue;
6761
6762                 ret = intel_modeset_pipe_config(state, crtc);
6763                 if (ret)
6764                         goto fail;
6765
6766                 ret = intel_atomic_check_bigjoiner(state, crtc);
6767                 if (ret)
6768                         goto fail;
6769         }
6770
6771         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6772                                             new_crtc_state, i) {
6773                 if (!intel_crtc_needs_modeset(new_crtc_state))
6774                         continue;
6775
6776                 if (new_crtc_state->hw.enable) {
6777                         ret = intel_modeset_pipe_config_late(state, crtc);
6778                         if (ret)
6779                                 goto fail;
6780                 }
6781
6782                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6783         }
6784
6785         /**
6786          * Check if fastset is allowed by external dependencies like other
6787          * pipes and transcoders.
6788          *
6789          * Right now it only forces a fullmodeset when the MST master
6790          * transcoder did not changed but the pipe of the master transcoder
6791          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6792          * in case of port synced crtcs, if one of the synced crtcs
6793          * needs a full modeset, all other synced crtcs should be
6794          * forced a full modeset.
6795          */
6796         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6797                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6798                         continue;
6799
6800                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6801                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6802
6803                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6804                                 new_crtc_state->uapi.mode_changed = true;
6805                                 new_crtc_state->update_pipe = false;
6806                         }
6807                 }
6808
6809                 if (is_trans_port_sync_mode(new_crtc_state)) {
6810                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6811
6812                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6813                                 trans |= BIT(new_crtc_state->master_transcoder);
6814
6815                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
6816                                 new_crtc_state->uapi.mode_changed = true;
6817                                 new_crtc_state->update_pipe = false;
6818                         }
6819                 }
6820
6821                 if (new_crtc_state->bigjoiner_pipes) {
6822                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6823                                 new_crtc_state->uapi.mode_changed = true;
6824                                 new_crtc_state->update_pipe = false;
6825                         }
6826                 }
6827         }
6828
6829         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6830                                             new_crtc_state, i) {
6831                 if (!intel_crtc_needs_modeset(new_crtc_state))
6832                         continue;
6833
6834                 any_ms = true;
6835
6836                 intel_release_shared_dplls(state, crtc);
6837         }
6838
6839         if (any_ms && !check_digital_port_conflicts(state)) {
6840                 drm_dbg_kms(&dev_priv->drm,
6841                             "rejecting conflicting digital port configuration\n");
6842                 ret = -EINVAL;
6843                 goto fail;
6844         }
6845
6846         ret = drm_dp_mst_atomic_check(&state->base);
6847         if (ret)
6848                 goto fail;
6849
6850         ret = intel_atomic_check_planes(state);
6851         if (ret)
6852                 goto fail;
6853
6854         ret = intel_compute_global_watermarks(state);
6855         if (ret)
6856                 goto fail;
6857
6858         ret = intel_bw_atomic_check(state);
6859         if (ret)
6860                 goto fail;
6861
6862         ret = intel_cdclk_atomic_check(state, &any_ms);
6863         if (ret)
6864                 goto fail;
6865
6866         if (intel_any_crtc_needs_modeset(state))
6867                 any_ms = true;
6868
6869         if (any_ms) {
6870                 ret = intel_modeset_checks(state);
6871                 if (ret)
6872                         goto fail;
6873
6874                 ret = intel_modeset_calc_cdclk(state);
6875                 if (ret)
6876                         return ret;
6877         }
6878
6879         ret = intel_atomic_check_crtcs(state);
6880         if (ret)
6881                 goto fail;
6882
6883         ret = intel_fbc_atomic_check(state);
6884         if (ret)
6885                 goto fail;
6886
6887         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6888                                             new_crtc_state, i) {
6889                 intel_color_assert_luts(new_crtc_state);
6890
6891                 ret = intel_async_flip_check_hw(state, crtc);
6892                 if (ret)
6893                         goto fail;
6894
6895                 /* Either full modeset or fastset (or neither), never both */
6896                 drm_WARN_ON(&dev_priv->drm,
6897                             intel_crtc_needs_modeset(new_crtc_state) &&
6898                             intel_crtc_needs_fastset(new_crtc_state));
6899
6900                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6901                     !intel_crtc_needs_fastset(new_crtc_state))
6902                         continue;
6903
6904                 intel_crtc_state_dump(new_crtc_state, state,
6905                                       intel_crtc_needs_modeset(new_crtc_state) ?
6906                                       "modeset" : "fastset");
6907         }
6908
6909         return 0;
6910
6911  fail:
6912         if (ret == -EDEADLK)
6913                 return ret;
6914
6915         /*
6916          * FIXME would probably be nice to know which crtc specifically
6917          * caused the failure, in cases where we can pinpoint it.
6918          */
6919         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6920                                             new_crtc_state, i)
6921                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6922
6923         return ret;
6924 }
6925
6926 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6927 {
6928         struct intel_crtc_state *crtc_state;
6929         struct intel_crtc *crtc;
6930         int i, ret;
6931
6932         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6933         if (ret < 0)
6934                 return ret;
6935
6936         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6937                 if (intel_crtc_needs_color_update(crtc_state))
6938                         intel_dsb_prepare(crtc_state);
6939         }
6940
6941         return 0;
6942 }
6943
6944 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6945                                   struct intel_crtc_state *crtc_state)
6946 {
6947         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6948
6949         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6950                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6951
6952         if (crtc_state->has_pch_encoder) {
6953                 enum pipe pch_transcoder =
6954                         intel_crtc_pch_transcoder(crtc);
6955
6956                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6957         }
6958 }
6959
6960 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6961                                const struct intel_crtc_state *new_crtc_state)
6962 {
6963         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6964         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6965
6966         /*
6967          * Update pipe size and adjust fitter if needed: the reason for this is
6968          * that in compute_mode_changes we check the native mode (not the pfit
6969          * mode) to see if we can flip rather than do a full mode set. In the
6970          * fastboot case, we'll flip, but if we don't update the pipesrc and
6971          * pfit state, we'll end up with a big fb scanned out into the wrong
6972          * sized surface.
6973          */
6974         intel_set_pipe_src_size(new_crtc_state);
6975
6976         /* on skylake this is done by detaching scalers */
6977         if (DISPLAY_VER(dev_priv) >= 9) {
6978                 if (new_crtc_state->pch_pfit.enabled)
6979                         skl_pfit_enable(new_crtc_state);
6980         } else if (HAS_PCH_SPLIT(dev_priv)) {
6981                 if (new_crtc_state->pch_pfit.enabled)
6982                         ilk_pfit_enable(new_crtc_state);
6983                 else if (old_crtc_state->pch_pfit.enabled)
6984                         ilk_pfit_disable(old_crtc_state);
6985         }
6986
6987         /*
6988          * The register is supposedly single buffered so perhaps
6989          * not 100% correct to do this here. But SKL+ calculate
6990          * this based on the adjust pixel rate so pfit changes do
6991          * affect it and so it must be updated for fastsets.
6992          * HSW/BDW only really need this here for fastboot, after
6993          * that the value should not change without a full modeset.
6994          */
6995         if (DISPLAY_VER(dev_priv) >= 9 ||
6996             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6997                 hsw_set_linetime_wm(new_crtc_state);
6998
6999         if (new_crtc_state->seamless_m_n)
7000                 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
7001                                                &new_crtc_state->dp_m_n);
7002 }
7003
7004 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
7005                                    struct intel_crtc *crtc)
7006 {
7007         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7008         const struct intel_crtc_state *old_crtc_state =
7009                 intel_atomic_get_old_crtc_state(state, crtc);
7010         const struct intel_crtc_state *new_crtc_state =
7011                 intel_atomic_get_new_crtc_state(state, crtc);
7012         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7013
7014         /*
7015          * During modesets pipe configuration was programmed as the
7016          * CRTC was enabled.
7017          */
7018         if (!modeset) {
7019                 if (intel_crtc_needs_color_update(new_crtc_state))
7020                         intel_color_commit_arm(new_crtc_state);
7021
7022                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7023                         bdw_set_pipemisc(new_crtc_state);
7024
7025                 if (intel_crtc_needs_fastset(new_crtc_state))
7026                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
7027         }
7028
7029         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
7030
7031         intel_atomic_update_watermarks(state, crtc);
7032 }
7033
7034 static void commit_pipe_post_planes(struct intel_atomic_state *state,
7035                                     struct intel_crtc *crtc)
7036 {
7037         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7038         const struct intel_crtc_state *new_crtc_state =
7039                 intel_atomic_get_new_crtc_state(state, crtc);
7040
7041         /*
7042          * Disable the scaler(s) after the plane(s) so that we don't
7043          * get a catastrophic underrun even if the two operations
7044          * end up happening in two different frames.
7045          */
7046         if (DISPLAY_VER(dev_priv) >= 9 &&
7047             !intel_crtc_needs_modeset(new_crtc_state))
7048                 skl_detach_scalers(new_crtc_state);
7049 }
7050
7051 static void intel_enable_crtc(struct intel_atomic_state *state,
7052                               struct intel_crtc *crtc)
7053 {
7054         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7055         const struct intel_crtc_state *new_crtc_state =
7056                 intel_atomic_get_new_crtc_state(state, crtc);
7057
7058         if (!intel_crtc_needs_modeset(new_crtc_state))
7059                 return;
7060
7061         intel_crtc_update_active_timings(new_crtc_state);
7062
7063         dev_priv->display.funcs.display->crtc_enable(state, crtc);
7064
7065         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
7066                 return;
7067
7068         /* vblanks work again, re-enable pipe CRC. */
7069         intel_crtc_enable_pipe_crc(crtc);
7070 }
7071
7072 static void intel_update_crtc(struct intel_atomic_state *state,
7073                               struct intel_crtc *crtc)
7074 {
7075         struct drm_i915_private *i915 = to_i915(state->base.dev);
7076         const struct intel_crtc_state *old_crtc_state =
7077                 intel_atomic_get_old_crtc_state(state, crtc);
7078         struct intel_crtc_state *new_crtc_state =
7079                 intel_atomic_get_new_crtc_state(state, crtc);
7080         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7081
7082         if (!modeset) {
7083                 if (new_crtc_state->preload_luts &&
7084                     intel_crtc_needs_color_update(new_crtc_state))
7085                         intel_color_load_luts(new_crtc_state);
7086
7087                 intel_pre_plane_update(state, crtc);
7088
7089                 if (intel_crtc_needs_fastset(new_crtc_state))
7090                         intel_encoders_update_pipe(state, crtc);
7091
7092                 if (DISPLAY_VER(i915) >= 11 &&
7093                     intel_crtc_needs_fastset(new_crtc_state))
7094                         icl_set_pipe_chicken(new_crtc_state);
7095         }
7096
7097         intel_fbc_update(state, crtc);
7098
7099         if (!modeset &&
7100             intel_crtc_needs_color_update(new_crtc_state))
7101                 intel_color_commit_noarm(new_crtc_state);
7102
7103         intel_crtc_planes_update_noarm(state, crtc);
7104
7105         /* Perform vblank evasion around commit operation */
7106         intel_pipe_update_start(new_crtc_state);
7107
7108         commit_pipe_pre_planes(state, crtc);
7109
7110         intel_crtc_planes_update_arm(state, crtc);
7111
7112         commit_pipe_post_planes(state, crtc);
7113
7114         intel_pipe_update_end(new_crtc_state);
7115
7116         /*
7117          * We usually enable FIFO underrun interrupts as part of the
7118          * CRTC enable sequence during modesets.  But when we inherit a
7119          * valid pipe configuration from the BIOS we need to take care
7120          * of enabling them on the CRTC's first fastset.
7121          */
7122         if (intel_crtc_needs_fastset(new_crtc_state) && !modeset &&
7123             old_crtc_state->inherited)
7124                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
7125 }
7126
7127 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
7128                                           struct intel_crtc_state *old_crtc_state,
7129                                           struct intel_crtc_state *new_crtc_state,
7130                                           struct intel_crtc *crtc)
7131 {
7132         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7133
7134         /*
7135          * We need to disable pipe CRC before disabling the pipe,
7136          * or we race against vblank off.
7137          */
7138         intel_crtc_disable_pipe_crc(crtc);
7139
7140         dev_priv->display.funcs.display->crtc_disable(state, crtc);
7141         crtc->active = false;
7142         intel_fbc_disable(crtc);
7143         intel_disable_shared_dpll(old_crtc_state);
7144
7145         if (!new_crtc_state->hw.active)
7146                 intel_initial_watermarks(state, crtc);
7147 }
7148
7149 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
7150 {
7151         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7152         struct intel_crtc *crtc;
7153         u32 handled = 0;
7154         int i;
7155
7156         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7157                                             new_crtc_state, i) {
7158                 if (!intel_crtc_needs_modeset(new_crtc_state))
7159                         continue;
7160
7161                 if (!old_crtc_state->hw.active)
7162                         continue;
7163
7164                 intel_pre_plane_update(state, crtc);
7165                 intel_crtc_disable_planes(state, crtc);
7166         }
7167
7168         /* Only disable port sync and MST slaves */
7169         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7170                                             new_crtc_state, i) {
7171                 if (!intel_crtc_needs_modeset(new_crtc_state))
7172                         continue;
7173
7174                 if (!old_crtc_state->hw.active)
7175                         continue;
7176
7177                 /* In case of Transcoder port Sync master slave CRTCs can be
7178                  * assigned in any order and we need to make sure that
7179                  * slave CRTCs are disabled first and then master CRTC since
7180                  * Slave vblanks are masked till Master Vblanks.
7181                  */
7182                 if (!is_trans_port_sync_slave(old_crtc_state) &&
7183                     !intel_dp_mst_is_slave_trans(old_crtc_state) &&
7184                     !intel_crtc_is_bigjoiner_slave(old_crtc_state))
7185                         continue;
7186
7187                 intel_old_crtc_state_disables(state, old_crtc_state,
7188                                               new_crtc_state, crtc);
7189                 handled |= BIT(crtc->pipe);
7190         }
7191
7192         /* Disable everything else left on */
7193         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7194                                             new_crtc_state, i) {
7195                 if (!intel_crtc_needs_modeset(new_crtc_state) ||
7196                     (handled & BIT(crtc->pipe)))
7197                         continue;
7198
7199                 if (!old_crtc_state->hw.active)
7200                         continue;
7201
7202                 intel_old_crtc_state_disables(state, old_crtc_state,
7203                                               new_crtc_state, crtc);
7204         }
7205 }
7206
7207 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
7208 {
7209         struct intel_crtc_state *new_crtc_state;
7210         struct intel_crtc *crtc;
7211         int i;
7212
7213         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7214                 if (!new_crtc_state->hw.active)
7215                         continue;
7216
7217                 intel_enable_crtc(state, crtc);
7218                 intel_update_crtc(state, crtc);
7219         }
7220 }
7221
7222 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7223 {
7224         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7225         struct intel_crtc *crtc;
7226         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7227         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7228         u8 update_pipes = 0, modeset_pipes = 0;
7229         int i;
7230
7231         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7232                 enum pipe pipe = crtc->pipe;
7233
7234                 if (!new_crtc_state->hw.active)
7235                         continue;
7236
7237                 /* ignore allocations for crtc's that have been turned off. */
7238                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
7239                         entries[pipe] = old_crtc_state->wm.skl.ddb;
7240                         update_pipes |= BIT(pipe);
7241                 } else {
7242                         modeset_pipes |= BIT(pipe);
7243                 }
7244         }
7245
7246         /*
7247          * Whenever the number of active pipes changes, we need to make sure we
7248          * update the pipes in the right order so that their ddb allocations
7249          * never overlap with each other between CRTC updates. Otherwise we'll
7250          * cause pipe underruns and other bad stuff.
7251          *
7252          * So first lets enable all pipes that do not need a fullmodeset as
7253          * those don't have any external dependency.
7254          */
7255         while (update_pipes) {
7256                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7257                                                     new_crtc_state, i) {
7258                         enum pipe pipe = crtc->pipe;
7259
7260                         if ((update_pipes & BIT(pipe)) == 0)
7261                                 continue;
7262
7263                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7264                                                         entries, I915_MAX_PIPES, pipe))
7265                                 continue;
7266
7267                         entries[pipe] = new_crtc_state->wm.skl.ddb;
7268                         update_pipes &= ~BIT(pipe);
7269
7270                         intel_update_crtc(state, crtc);
7271
7272                         /*
7273                          * If this is an already active pipe, it's DDB changed,
7274                          * and this isn't the last pipe that needs updating
7275                          * then we need to wait for a vblank to pass for the
7276                          * new ddb allocation to take effect.
7277                          */
7278                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
7279                                                  &old_crtc_state->wm.skl.ddb) &&
7280                             (update_pipes | modeset_pipes))
7281                                 intel_crtc_wait_for_next_vblank(crtc);
7282                 }
7283         }
7284
7285         update_pipes = modeset_pipes;
7286
7287         /*
7288          * Enable all pipes that needs a modeset and do not depends on other
7289          * pipes
7290          */
7291         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7292                 enum pipe pipe = crtc->pipe;
7293
7294                 if ((modeset_pipes & BIT(pipe)) == 0)
7295                         continue;
7296
7297                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7298                     is_trans_port_sync_master(new_crtc_state) ||
7299                     intel_crtc_is_bigjoiner_master(new_crtc_state))
7300                         continue;
7301
7302                 modeset_pipes &= ~BIT(pipe);
7303
7304                 intel_enable_crtc(state, crtc);
7305         }
7306
7307         /*
7308          * Then we enable all remaining pipes that depend on other
7309          * pipes: MST slaves and port sync masters, big joiner master
7310          */
7311         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7312                 enum pipe pipe = crtc->pipe;
7313
7314                 if ((modeset_pipes & BIT(pipe)) == 0)
7315                         continue;
7316
7317                 modeset_pipes &= ~BIT(pipe);
7318
7319                 intel_enable_crtc(state, crtc);
7320         }
7321
7322         /*
7323          * Finally we do the plane updates/etc. for all pipes that got enabled.
7324          */
7325         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7326                 enum pipe pipe = crtc->pipe;
7327
7328                 if ((update_pipes & BIT(pipe)) == 0)
7329                         continue;
7330
7331                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7332                                                                         entries, I915_MAX_PIPES, pipe));
7333
7334                 entries[pipe] = new_crtc_state->wm.skl.ddb;
7335                 update_pipes &= ~BIT(pipe);
7336
7337                 intel_update_crtc(state, crtc);
7338         }
7339
7340         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7341         drm_WARN_ON(&dev_priv->drm, update_pipes);
7342 }
7343
7344 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
7345 {
7346         struct intel_atomic_state *state, *next;
7347         struct llist_node *freed;
7348
7349         freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
7350         llist_for_each_entry_safe(state, next, freed, freed)
7351                 drm_atomic_state_put(&state->base);
7352 }
7353
7354 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
7355 {
7356         struct drm_i915_private *dev_priv =
7357                 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
7358
7359         intel_atomic_helper_free_state(dev_priv);
7360 }
7361
7362 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7363 {
7364         struct wait_queue_entry wait_fence, wait_reset;
7365         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
7366
7367         init_wait_entry(&wait_fence, 0);
7368         init_wait_entry(&wait_reset, 0);
7369         for (;;) {
7370                 prepare_to_wait(&intel_state->commit_ready.wait,
7371                                 &wait_fence, TASK_UNINTERRUPTIBLE);
7372                 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7373                                               I915_RESET_MODESET),
7374                                 &wait_reset, TASK_UNINTERRUPTIBLE);
7375
7376
7377                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
7378                     test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
7379                         break;
7380
7381                 schedule();
7382         }
7383         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
7384         finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7385                                   I915_RESET_MODESET),
7386                     &wait_reset);
7387 }
7388
7389 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
7390 {
7391         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7392         struct intel_crtc *crtc;
7393         int i;
7394
7395         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7396                                             new_crtc_state, i)
7397                 intel_dsb_cleanup(old_crtc_state);
7398 }
7399
7400 static void intel_atomic_cleanup_work(struct work_struct *work)
7401 {
7402         struct intel_atomic_state *state =
7403                 container_of(work, struct intel_atomic_state, base.commit_work);
7404         struct drm_i915_private *i915 = to_i915(state->base.dev);
7405
7406         intel_cleanup_dsbs(state);
7407         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7408         drm_atomic_helper_commit_cleanup_done(&state->base);
7409         drm_atomic_state_put(&state->base);
7410
7411         intel_atomic_helper_free_state(i915);
7412 }
7413
7414 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7415 {
7416         struct drm_i915_private *i915 = to_i915(state->base.dev);
7417         struct intel_plane *plane;
7418         struct intel_plane_state *plane_state;
7419         int i;
7420
7421         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7422                 struct drm_framebuffer *fb = plane_state->hw.fb;
7423                 int cc_plane;
7424                 int ret;
7425
7426                 if (!fb)
7427                         continue;
7428
7429                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7430                 if (cc_plane < 0)
7431                         continue;
7432
7433                 /*
7434                  * The layout of the fast clear color value expected by HW
7435                  * (the DRM ABI requiring this value to be located in fb at
7436                  * offset 0 of cc plane, plane #2 previous generations or
7437                  * plane #1 for flat ccs):
7438                  * - 4 x 4 bytes per-channel value
7439                  *   (in surface type specific float/int format provided by the fb user)
7440                  * - 8 bytes native color value used by the display
7441                  *   (converted/written by GPU during a fast clear operation using the
7442                  *    above per-channel values)
7443                  *
7444                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
7445                  * caller made sure that the object is synced wrt. the related color clear value
7446                  * GPU write on it.
7447                  */
7448                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7449                                                      fb->offsets[cc_plane] + 16,
7450                                                      &plane_state->ccval,
7451                                                      sizeof(plane_state->ccval));
7452                 /* The above could only fail if the FB obj has an unexpected backing store type. */
7453                 drm_WARN_ON(&i915->drm, ret);
7454         }
7455 }
7456
7457 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7458 {
7459         struct drm_device *dev = state->base.dev;
7460         struct drm_i915_private *dev_priv = to_i915(dev);
7461         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7462         struct intel_crtc *crtc;
7463         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7464         intel_wakeref_t wakeref = 0;
7465         int i;
7466
7467         intel_atomic_commit_fence_wait(state);
7468
7469         drm_atomic_helper_wait_for_dependencies(&state->base);
7470         drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7471
7472         if (state->modeset)
7473                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
7474
7475         intel_atomic_prepare_plane_clear_colors(state);
7476
7477         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7478                                             new_crtc_state, i) {
7479                 if (intel_crtc_needs_modeset(new_crtc_state) ||
7480                     intel_crtc_needs_fastset(new_crtc_state))
7481                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7482         }
7483
7484         intel_commit_modeset_disables(state);
7485
7486         /* FIXME: Eventually get rid of our crtc->config pointer */
7487         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7488                 crtc->config = new_crtc_state;
7489
7490         if (state->modeset) {
7491                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7492
7493                 intel_set_cdclk_pre_plane_update(state);
7494
7495                 intel_modeset_verify_disabled(dev_priv, state);
7496         }
7497
7498         intel_sagv_pre_plane_update(state);
7499
7500         /* Complete the events for pipes that have now been disabled */
7501         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7502                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7503
7504                 /* Complete events for now disable pipes here. */
7505                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7506                         spin_lock_irq(&dev->event_lock);
7507                         drm_crtc_send_vblank_event(&crtc->base,
7508                                                    new_crtc_state->uapi.event);
7509                         spin_unlock_irq(&dev->event_lock);
7510
7511                         new_crtc_state->uapi.event = NULL;
7512                 }
7513         }
7514
7515         intel_encoders_update_prepare(state);
7516
7517         intel_dbuf_pre_plane_update(state);
7518         intel_mbus_dbox_update(state);
7519
7520         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7521                 if (new_crtc_state->do_async_flip)
7522                         intel_crtc_enable_flip_done(state, crtc);
7523         }
7524
7525         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7526         dev_priv->display.funcs.display->commit_modeset_enables(state);
7527
7528         intel_encoders_update_complete(state);
7529
7530         if (state->modeset)
7531                 intel_set_cdclk_post_plane_update(state);
7532
7533         intel_wait_for_vblank_workers(state);
7534
7535         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7536          * already, but still need the state for the delayed optimization. To
7537          * fix this:
7538          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7539          * - schedule that vblank worker _before_ calling hw_done
7540          * - at the start of commit_tail, cancel it _synchrously
7541          * - switch over to the vblank wait helper in the core after that since
7542          *   we don't need out special handling any more.
7543          */
7544         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7545
7546         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7547                 if (new_crtc_state->do_async_flip)
7548                         intel_crtc_disable_flip_done(state, crtc);
7549         }
7550
7551         /*
7552          * Now that the vblank has passed, we can go ahead and program the
7553          * optimal watermarks on platforms that need two-step watermark
7554          * programming.
7555          *
7556          * TODO: Move this (and other cleanup) to an async worker eventually.
7557          */
7558         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7559                                             new_crtc_state, i) {
7560                 /*
7561                  * Gen2 reports pipe underruns whenever all planes are disabled.
7562                  * So re-enable underrun reporting after some planes get enabled.
7563                  *
7564                  * We do this before .optimize_watermarks() so that we have a
7565                  * chance of catching underruns with the intermediate watermarks
7566                  * vs. the new plane configuration.
7567                  */
7568                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7569                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7570
7571                 intel_optimize_watermarks(state, crtc);
7572         }
7573
7574         intel_dbuf_post_plane_update(state);
7575         intel_psr_post_plane_update(state);
7576
7577         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7578                 intel_post_plane_update(state, crtc);
7579
7580                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7581
7582                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
7583
7584                 /*
7585                  * Activate DRRS after state readout to avoid
7586                  * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7587                  */
7588                 intel_drrs_activate(new_crtc_state);
7589
7590                 /*
7591                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7592                  * cleanup. So copy and reset the dsb structure to sync with
7593                  * commit_done and later do dsb cleanup in cleanup_work.
7594                  */
7595                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7596         }
7597
7598         /* Underruns don't always raise interrupts, so check manually */
7599         intel_check_cpu_fifo_underruns(dev_priv);
7600         intel_check_pch_fifo_underruns(dev_priv);
7601
7602         if (state->modeset)
7603                 intel_verify_planes(state);
7604
7605         intel_sagv_post_plane_update(state);
7606
7607         drm_atomic_helper_commit_hw_done(&state->base);
7608
7609         if (state->modeset) {
7610                 /* As one of the primary mmio accessors, KMS has a high
7611                  * likelihood of triggering bugs in unclaimed access. After we
7612                  * finish modesetting, see if an error has been flagged, and if
7613                  * so enable debugging for the next modeset - and hope we catch
7614                  * the culprit.
7615                  */
7616                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7617                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
7618         }
7619         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7620
7621         /*
7622          * Defer the cleanup of the old state to a separate worker to not
7623          * impede the current task (userspace for blocking modesets) that
7624          * are executed inline. For out-of-line asynchronous modesets/flips,
7625          * deferring to a new worker seems overkill, but we would place a
7626          * schedule point (cond_resched()) here anyway to keep latencies
7627          * down.
7628          */
7629         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7630         queue_work(system_highpri_wq, &state->base.commit_work);
7631 }
7632
7633 static void intel_atomic_commit_work(struct work_struct *work)
7634 {
7635         struct intel_atomic_state *state =
7636                 container_of(work, struct intel_atomic_state, base.commit_work);
7637
7638         intel_atomic_commit_tail(state);
7639 }
7640
7641 static int
7642 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7643                           enum i915_sw_fence_notify notify)
7644 {
7645         struct intel_atomic_state *state =
7646                 container_of(fence, struct intel_atomic_state, commit_ready);
7647
7648         switch (notify) {
7649         case FENCE_COMPLETE:
7650                 /* we do blocking waits in the worker, nothing to do here */
7651                 break;
7652         case FENCE_FREE:
7653                 {
7654                         struct intel_atomic_helper *helper =
7655                                 &to_i915(state->base.dev)->display.atomic_helper;
7656
7657                         if (llist_add(&state->freed, &helper->free_list))
7658                                 schedule_work(&helper->free_work);
7659                         break;
7660                 }
7661         }
7662
7663         return NOTIFY_DONE;
7664 }
7665
7666 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7667 {
7668         struct intel_plane_state *old_plane_state, *new_plane_state;
7669         struct intel_plane *plane;
7670         int i;
7671
7672         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7673                                              new_plane_state, i)
7674                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7675                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7676                                         plane->frontbuffer_bit);
7677 }
7678
7679 static int intel_atomic_commit(struct drm_device *dev,
7680                                struct drm_atomic_state *_state,
7681                                bool nonblock)
7682 {
7683         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7684         struct drm_i915_private *dev_priv = to_i915(dev);
7685         int ret = 0;
7686
7687         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7688
7689         drm_atomic_state_get(&state->base);
7690         i915_sw_fence_init(&state->commit_ready,
7691                            intel_atomic_commit_ready);
7692
7693         /*
7694          * The intel_legacy_cursor_update() fast path takes care
7695          * of avoiding the vblank waits for simple cursor
7696          * movement and flips. For cursor on/off and size changes,
7697          * we want to perform the vblank waits so that watermark
7698          * updates happen during the correct frames. Gen9+ have
7699          * double buffered watermarks and so shouldn't need this.
7700          *
7701          * Unset state->legacy_cursor_update before the call to
7702          * drm_atomic_helper_setup_commit() because otherwise
7703          * drm_atomic_helper_wait_for_flip_done() is a noop and
7704          * we get FIFO underruns because we didn't wait
7705          * for vblank.
7706          *
7707          * FIXME doing watermarks and fb cleanup from a vblank worker
7708          * (assuming we had any) would solve these problems.
7709          */
7710         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7711                 struct intel_crtc_state *new_crtc_state;
7712                 struct intel_crtc *crtc;
7713                 int i;
7714
7715                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7716                         if (new_crtc_state->wm.need_postvbl_update ||
7717                             new_crtc_state->update_wm_post)
7718                                 state->base.legacy_cursor_update = false;
7719         }
7720
7721         ret = intel_atomic_prepare_commit(state);
7722         if (ret) {
7723                 drm_dbg_atomic(&dev_priv->drm,
7724                                "Preparing state failed with %i\n", ret);
7725                 i915_sw_fence_commit(&state->commit_ready);
7726                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7727                 return ret;
7728         }
7729
7730         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7731         if (!ret)
7732                 ret = drm_atomic_helper_swap_state(&state->base, true);
7733         if (!ret)
7734                 intel_atomic_swap_global_state(state);
7735
7736         if (ret) {
7737                 struct intel_crtc_state *new_crtc_state;
7738                 struct intel_crtc *crtc;
7739                 int i;
7740
7741                 i915_sw_fence_commit(&state->commit_ready);
7742
7743                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7744                         intel_dsb_cleanup(new_crtc_state);
7745
7746                 drm_atomic_helper_cleanup_planes(dev, &state->base);
7747                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7748                 return ret;
7749         }
7750         intel_shared_dpll_swap_state(state);
7751         intel_atomic_track_fbs(state);
7752
7753         drm_atomic_state_get(&state->base);
7754         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7755
7756         i915_sw_fence_commit(&state->commit_ready);
7757         if (nonblock && state->modeset) {
7758                 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7759         } else if (nonblock) {
7760                 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7761         } else {
7762                 if (state->modeset)
7763                         flush_workqueue(dev_priv->display.wq.modeset);
7764                 intel_atomic_commit_tail(state);
7765         }
7766
7767         return 0;
7768 }
7769
7770 /**
7771  * intel_plane_destroy - destroy a plane
7772  * @plane: plane to destroy
7773  *
7774  * Common destruction function for all types of planes (primary, cursor,
7775  * sprite).
7776  */
7777 void intel_plane_destroy(struct drm_plane *plane)
7778 {
7779         drm_plane_cleanup(plane);
7780         kfree(to_intel_plane(plane));
7781 }
7782
7783 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
7784 {
7785         struct intel_plane *plane;
7786
7787         for_each_intel_plane(&dev_priv->drm, plane) {
7788                 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
7789                                                               plane->pipe);
7790
7791                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
7792         }
7793 }
7794
7795
7796 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7797                                       struct drm_file *file)
7798 {
7799         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7800         struct drm_crtc *drmmode_crtc;
7801         struct intel_crtc *crtc;
7802
7803         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7804         if (!drmmode_crtc)
7805                 return -ENOENT;
7806
7807         crtc = to_intel_crtc(drmmode_crtc);
7808         pipe_from_crtc_id->pipe = crtc->pipe;
7809
7810         return 0;
7811 }
7812
7813 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7814 {
7815         struct drm_device *dev = encoder->base.dev;
7816         struct intel_encoder *source_encoder;
7817         u32 possible_clones = 0;
7818
7819         for_each_intel_encoder(dev, source_encoder) {
7820                 if (encoders_cloneable(encoder, source_encoder))
7821                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7822         }
7823
7824         return possible_clones;
7825 }
7826
7827 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7828 {
7829         struct drm_device *dev = encoder->base.dev;
7830         struct intel_crtc *crtc;
7831         u32 possible_crtcs = 0;
7832
7833         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7834                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7835
7836         return possible_crtcs;
7837 }
7838
7839 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7840 {
7841         if (!IS_MOBILE(dev_priv))
7842                 return false;
7843
7844         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7845                 return false;
7846
7847         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7848                 return false;
7849
7850         return true;
7851 }
7852
7853 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7854 {
7855         if (DISPLAY_VER(dev_priv) >= 9)
7856                 return false;
7857
7858         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
7859                 return false;
7860
7861         if (HAS_PCH_LPT_H(dev_priv) &&
7862             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7863                 return false;
7864
7865         /* DDI E can't be used if DDI A requires 4 lanes */
7866         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7867                 return false;
7868
7869         if (!dev_priv->display.vbt.int_crt_support)
7870                 return false;
7871
7872         return true;
7873 }
7874
7875 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
7876 {
7877         struct intel_encoder *encoder;
7878         bool dpd_is_edp = false;
7879
7880         intel_pps_unlock_regs_wa(dev_priv);
7881
7882         if (!HAS_DISPLAY(dev_priv))
7883                 return;
7884
7885         if (IS_DG2(dev_priv)) {
7886                 intel_ddi_init(dev_priv, PORT_A);
7887                 intel_ddi_init(dev_priv, PORT_B);
7888                 intel_ddi_init(dev_priv, PORT_C);
7889                 intel_ddi_init(dev_priv, PORT_D_XELPD);
7890                 intel_ddi_init(dev_priv, PORT_TC1);
7891         } else if (IS_ALDERLAKE_P(dev_priv)) {
7892                 intel_ddi_init(dev_priv, PORT_A);
7893                 intel_ddi_init(dev_priv, PORT_B);
7894                 intel_ddi_init(dev_priv, PORT_TC1);
7895                 intel_ddi_init(dev_priv, PORT_TC2);
7896                 intel_ddi_init(dev_priv, PORT_TC3);
7897                 intel_ddi_init(dev_priv, PORT_TC4);
7898                 icl_dsi_init(dev_priv);
7899         } else if (IS_ALDERLAKE_S(dev_priv)) {
7900                 intel_ddi_init(dev_priv, PORT_A);
7901                 intel_ddi_init(dev_priv, PORT_TC1);
7902                 intel_ddi_init(dev_priv, PORT_TC2);
7903                 intel_ddi_init(dev_priv, PORT_TC3);
7904                 intel_ddi_init(dev_priv, PORT_TC4);
7905         } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
7906                 intel_ddi_init(dev_priv, PORT_A);
7907                 intel_ddi_init(dev_priv, PORT_B);
7908                 intel_ddi_init(dev_priv, PORT_TC1);
7909                 intel_ddi_init(dev_priv, PORT_TC2);
7910         } else if (DISPLAY_VER(dev_priv) >= 12) {
7911                 intel_ddi_init(dev_priv, PORT_A);
7912                 intel_ddi_init(dev_priv, PORT_B);
7913                 intel_ddi_init(dev_priv, PORT_TC1);
7914                 intel_ddi_init(dev_priv, PORT_TC2);
7915                 intel_ddi_init(dev_priv, PORT_TC3);
7916                 intel_ddi_init(dev_priv, PORT_TC4);
7917                 intel_ddi_init(dev_priv, PORT_TC5);
7918                 intel_ddi_init(dev_priv, PORT_TC6);
7919                 icl_dsi_init(dev_priv);
7920         } else if (IS_JSL_EHL(dev_priv)) {
7921                 intel_ddi_init(dev_priv, PORT_A);
7922                 intel_ddi_init(dev_priv, PORT_B);
7923                 intel_ddi_init(dev_priv, PORT_C);
7924                 intel_ddi_init(dev_priv, PORT_D);
7925                 icl_dsi_init(dev_priv);
7926         } else if (DISPLAY_VER(dev_priv) == 11) {
7927                 intel_ddi_init(dev_priv, PORT_A);
7928                 intel_ddi_init(dev_priv, PORT_B);
7929                 intel_ddi_init(dev_priv, PORT_C);
7930                 intel_ddi_init(dev_priv, PORT_D);
7931                 intel_ddi_init(dev_priv, PORT_E);
7932                 intel_ddi_init(dev_priv, PORT_F);
7933                 icl_dsi_init(dev_priv);
7934         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
7935                 intel_ddi_init(dev_priv, PORT_A);
7936                 intel_ddi_init(dev_priv, PORT_B);
7937                 intel_ddi_init(dev_priv, PORT_C);
7938                 vlv_dsi_init(dev_priv);
7939         } else if (DISPLAY_VER(dev_priv) >= 9) {
7940                 intel_ddi_init(dev_priv, PORT_A);
7941                 intel_ddi_init(dev_priv, PORT_B);
7942                 intel_ddi_init(dev_priv, PORT_C);
7943                 intel_ddi_init(dev_priv, PORT_D);
7944                 intel_ddi_init(dev_priv, PORT_E);
7945         } else if (HAS_DDI(dev_priv)) {
7946                 u32 found;
7947
7948                 if (intel_ddi_crt_present(dev_priv))
7949                         intel_crt_init(dev_priv);
7950
7951                 /* Haswell uses DDI functions to detect digital outputs. */
7952                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
7953                 if (found)
7954                         intel_ddi_init(dev_priv, PORT_A);
7955
7956                 found = intel_de_read(dev_priv, SFUSE_STRAP);
7957                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7958                         intel_ddi_init(dev_priv, PORT_B);
7959                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7960                         intel_ddi_init(dev_priv, PORT_C);
7961                 if (found & SFUSE_STRAP_DDID_DETECTED)
7962                         intel_ddi_init(dev_priv, PORT_D);
7963                 if (found & SFUSE_STRAP_DDIF_DETECTED)
7964                         intel_ddi_init(dev_priv, PORT_F);
7965         } else if (HAS_PCH_SPLIT(dev_priv)) {
7966                 int found;
7967
7968                 /*
7969                  * intel_edp_init_connector() depends on this completing first,
7970                  * to prevent the registration of both eDP and LVDS and the
7971                  * incorrect sharing of the PPS.
7972                  */
7973                 intel_lvds_init(dev_priv);
7974                 intel_crt_init(dev_priv);
7975
7976                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7977
7978                 if (ilk_has_edp_a(dev_priv))
7979                         g4x_dp_init(dev_priv, DP_A, PORT_A);
7980
7981                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7982                         /* PCH SDVOB multiplex with HDMIB */
7983                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7984                         if (!found)
7985                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7986                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7987                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7988                 }
7989
7990                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7991                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7992
7993                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7994                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7995
7996                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7997                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7998
7999                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
8000                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
8001         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8002                 bool has_edp, has_port;
8003
8004                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
8005                         intel_crt_init(dev_priv);
8006
8007                 /*
8008                  * The DP_DETECTED bit is the latched state of the DDC
8009                  * SDA pin at boot. However since eDP doesn't require DDC
8010                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
8011                  * eDP ports may have been muxed to an alternate function.
8012                  * Thus we can't rely on the DP_DETECTED bit alone to detect
8013                  * eDP ports. Consult the VBT as well as DP_DETECTED to
8014                  * detect eDP ports.
8015                  *
8016                  * Sadly the straps seem to be missing sometimes even for HDMI
8017                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
8018                  * and VBT for the presence of the port. Additionally we can't
8019                  * trust the port type the VBT declares as we've seen at least
8020                  * HDMI ports that the VBT claim are DP or eDP.
8021                  */
8022                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
8023                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
8024                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
8025                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
8026                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
8027                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
8028
8029                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
8030                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
8031                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
8032                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
8033                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
8034                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
8035
8036                 if (IS_CHERRYVIEW(dev_priv)) {
8037                         /*
8038                          * eDP not supported on port D,
8039                          * so no need to worry about it
8040                          */
8041                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
8042                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
8043                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
8044                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
8045                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
8046                 }
8047
8048                 vlv_dsi_init(dev_priv);
8049         } else if (IS_PINEVIEW(dev_priv)) {
8050                 intel_lvds_init(dev_priv);
8051                 intel_crt_init(dev_priv);
8052         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
8053                 bool found = false;
8054
8055                 if (IS_MOBILE(dev_priv))
8056                         intel_lvds_init(dev_priv);
8057
8058                 intel_crt_init(dev_priv);
8059
8060                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8061                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
8062                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
8063                         if (!found && IS_G4X(dev_priv)) {
8064                                 drm_dbg_kms(&dev_priv->drm,
8065                                             "probing HDMI on SDVOB\n");
8066                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
8067                         }
8068
8069                         if (!found && IS_G4X(dev_priv))
8070                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
8071                 }
8072
8073                 /* Before G4X SDVOC doesn't have its own detect register */
8074
8075                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8076                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
8077                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
8078                 }
8079
8080                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
8081
8082                         if (IS_G4X(dev_priv)) {
8083                                 drm_dbg_kms(&dev_priv->drm,
8084                                             "probing HDMI on SDVOC\n");
8085                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
8086                         }
8087                         if (IS_G4X(dev_priv))
8088                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
8089                 }
8090
8091                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
8092                         g4x_dp_init(dev_priv, DP_D, PORT_D);
8093
8094                 if (SUPPORTS_TV(dev_priv))
8095                         intel_tv_init(dev_priv);
8096         } else if (DISPLAY_VER(dev_priv) == 2) {
8097                 if (IS_I85X(dev_priv))
8098                         intel_lvds_init(dev_priv);
8099
8100                 intel_crt_init(dev_priv);
8101                 intel_dvo_init(dev_priv);
8102         }
8103
8104         for_each_intel_encoder(&dev_priv->drm, encoder) {
8105                 encoder->base.possible_crtcs =
8106                         intel_encoder_possible_crtcs(encoder);
8107                 encoder->base.possible_clones =
8108                         intel_encoder_possible_clones(encoder);
8109         }
8110
8111         intel_init_pch_refclk(dev_priv);
8112
8113         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
8114 }
8115
8116 static int max_dotclock(struct drm_i915_private *i915)
8117 {
8118         int max_dotclock = i915->max_dotclk_freq;
8119
8120         /* icl+ might use bigjoiner */
8121         if (DISPLAY_VER(i915) >= 11)
8122                 max_dotclock *= 2;
8123
8124         return max_dotclock;
8125 }
8126
8127 static enum drm_mode_status
8128 intel_mode_valid(struct drm_device *dev,
8129                  const struct drm_display_mode *mode)
8130 {
8131         struct drm_i915_private *dev_priv = to_i915(dev);
8132         int hdisplay_max, htotal_max;
8133         int vdisplay_max, vtotal_max;
8134
8135         /*
8136          * Can't reject DBLSCAN here because Xorg ddxen can add piles
8137          * of DBLSCAN modes to the output's mode list when they detect
8138          * the scaling mode property on the connector. And they don't
8139          * ask the kernel to validate those modes in any way until
8140          * modeset time at which point the client gets a protocol error.
8141          * So in order to not upset those clients we silently ignore the
8142          * DBLSCAN flag on such connectors. For other connectors we will
8143          * reject modes with the DBLSCAN flag in encoder->compute_config().
8144          * And we always reject DBLSCAN modes in connector->mode_valid()
8145          * as we never want such modes on the connector's mode list.
8146          */
8147
8148         if (mode->vscan > 1)
8149                 return MODE_NO_VSCAN;
8150
8151         if (mode->flags & DRM_MODE_FLAG_HSKEW)
8152                 return MODE_H_ILLEGAL;
8153
8154         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
8155                            DRM_MODE_FLAG_NCSYNC |
8156                            DRM_MODE_FLAG_PCSYNC))
8157                 return MODE_HSYNC;
8158
8159         if (mode->flags & (DRM_MODE_FLAG_BCAST |
8160                            DRM_MODE_FLAG_PIXMUX |
8161                            DRM_MODE_FLAG_CLKDIV2))
8162                 return MODE_BAD;
8163
8164         /*
8165          * Reject clearly excessive dotclocks early to
8166          * avoid having to worry about huge integers later.
8167          */
8168         if (mode->clock > max_dotclock(dev_priv))
8169                 return MODE_CLOCK_HIGH;
8170
8171         /* Transcoder timing limits */
8172         if (DISPLAY_VER(dev_priv) >= 11) {
8173                 hdisplay_max = 16384;
8174                 vdisplay_max = 8192;
8175                 htotal_max = 16384;
8176                 vtotal_max = 8192;
8177         } else if (DISPLAY_VER(dev_priv) >= 9 ||
8178                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
8179                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
8180                 vdisplay_max = 4096;
8181                 htotal_max = 8192;
8182                 vtotal_max = 8192;
8183         } else if (DISPLAY_VER(dev_priv) >= 3) {
8184                 hdisplay_max = 4096;
8185                 vdisplay_max = 4096;
8186                 htotal_max = 8192;
8187                 vtotal_max = 8192;
8188         } else {
8189                 hdisplay_max = 2048;
8190                 vdisplay_max = 2048;
8191                 htotal_max = 4096;
8192                 vtotal_max = 4096;
8193         }
8194
8195         if (mode->hdisplay > hdisplay_max ||
8196             mode->hsync_start > htotal_max ||
8197             mode->hsync_end > htotal_max ||
8198             mode->htotal > htotal_max)
8199                 return MODE_H_ILLEGAL;
8200
8201         if (mode->vdisplay > vdisplay_max ||
8202             mode->vsync_start > vtotal_max ||
8203             mode->vsync_end > vtotal_max ||
8204             mode->vtotal > vtotal_max)
8205                 return MODE_V_ILLEGAL;
8206
8207         if (DISPLAY_VER(dev_priv) >= 5) {
8208                 if (mode->hdisplay < 64 ||
8209                     mode->htotal - mode->hdisplay < 32)
8210                         return MODE_H_ILLEGAL;
8211
8212                 if (mode->vtotal - mode->vdisplay < 5)
8213                         return MODE_V_ILLEGAL;
8214         } else {
8215                 if (mode->htotal - mode->hdisplay < 32)
8216                         return MODE_H_ILLEGAL;
8217
8218                 if (mode->vtotal - mode->vdisplay < 3)
8219                         return MODE_V_ILLEGAL;
8220         }
8221
8222         /*
8223          * Cantiga+ cannot handle modes with a hsync front porch of 0.
8224          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8225          */
8226         if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8227             mode->hsync_start == mode->hdisplay)
8228                 return MODE_H_ILLEGAL;
8229
8230         return MODE_OK;
8231 }
8232
8233 enum drm_mode_status
8234 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
8235                                 const struct drm_display_mode *mode,
8236                                 bool bigjoiner)
8237 {
8238         int plane_width_max, plane_height_max;
8239
8240         /*
8241          * intel_mode_valid() should be
8242          * sufficient on older platforms.
8243          */
8244         if (DISPLAY_VER(dev_priv) < 9)
8245                 return MODE_OK;
8246
8247         /*
8248          * Most people will probably want a fullscreen
8249          * plane so let's not advertize modes that are
8250          * too big for that.
8251          */
8252         if (DISPLAY_VER(dev_priv) >= 11) {
8253                 plane_width_max = 5120 << bigjoiner;
8254                 plane_height_max = 4320;
8255         } else {
8256                 plane_width_max = 5120;
8257                 plane_height_max = 4096;
8258         }
8259
8260         if (mode->hdisplay > plane_width_max)
8261                 return MODE_H_ILLEGAL;
8262
8263         if (mode->vdisplay > plane_height_max)
8264                 return MODE_V_ILLEGAL;
8265
8266         return MODE_OK;
8267 }
8268
8269 static const struct drm_mode_config_funcs intel_mode_funcs = {
8270         .fb_create = intel_user_framebuffer_create,
8271         .get_format_info = intel_fb_get_format_info,
8272         .output_poll_changed = intel_fbdev_output_poll_changed,
8273         .mode_valid = intel_mode_valid,
8274         .atomic_check = intel_atomic_check,
8275         .atomic_commit = intel_atomic_commit,
8276         .atomic_state_alloc = intel_atomic_state_alloc,
8277         .atomic_state_clear = intel_atomic_state_clear,
8278         .atomic_state_free = intel_atomic_state_free,
8279 };
8280
8281 static const struct intel_display_funcs skl_display_funcs = {
8282         .get_pipe_config = hsw_get_pipe_config,
8283         .crtc_enable = hsw_crtc_enable,
8284         .crtc_disable = hsw_crtc_disable,
8285         .commit_modeset_enables = skl_commit_modeset_enables,
8286         .get_initial_plane_config = skl_get_initial_plane_config,
8287 };
8288
8289 static const struct intel_display_funcs ddi_display_funcs = {
8290         .get_pipe_config = hsw_get_pipe_config,
8291         .crtc_enable = hsw_crtc_enable,
8292         .crtc_disable = hsw_crtc_disable,
8293         .commit_modeset_enables = intel_commit_modeset_enables,
8294         .get_initial_plane_config = i9xx_get_initial_plane_config,
8295 };
8296
8297 static const struct intel_display_funcs pch_split_display_funcs = {
8298         .get_pipe_config = ilk_get_pipe_config,
8299         .crtc_enable = ilk_crtc_enable,
8300         .crtc_disable = ilk_crtc_disable,
8301         .commit_modeset_enables = intel_commit_modeset_enables,
8302         .get_initial_plane_config = i9xx_get_initial_plane_config,
8303 };
8304
8305 static const struct intel_display_funcs vlv_display_funcs = {
8306         .get_pipe_config = i9xx_get_pipe_config,
8307         .crtc_enable = valleyview_crtc_enable,
8308         .crtc_disable = i9xx_crtc_disable,
8309         .commit_modeset_enables = intel_commit_modeset_enables,
8310         .get_initial_plane_config = i9xx_get_initial_plane_config,
8311 };
8312
8313 static const struct intel_display_funcs i9xx_display_funcs = {
8314         .get_pipe_config = i9xx_get_pipe_config,
8315         .crtc_enable = i9xx_crtc_enable,
8316         .crtc_disable = i9xx_crtc_disable,
8317         .commit_modeset_enables = intel_commit_modeset_enables,
8318         .get_initial_plane_config = i9xx_get_initial_plane_config,
8319 };
8320
8321 /**
8322  * intel_init_display_hooks - initialize the display modesetting hooks
8323  * @dev_priv: device private
8324  */
8325 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8326 {
8327         if (!HAS_DISPLAY(dev_priv))
8328                 return;
8329
8330         intel_color_init_hooks(dev_priv);
8331         intel_init_cdclk_hooks(dev_priv);
8332         intel_audio_hooks_init(dev_priv);
8333
8334         intel_dpll_init_clock_hook(dev_priv);
8335
8336         if (DISPLAY_VER(dev_priv) >= 9) {
8337                 dev_priv->display.funcs.display = &skl_display_funcs;
8338         } else if (HAS_DDI(dev_priv)) {
8339                 dev_priv->display.funcs.display = &ddi_display_funcs;
8340         } else if (HAS_PCH_SPLIT(dev_priv)) {
8341                 dev_priv->display.funcs.display = &pch_split_display_funcs;
8342         } else if (IS_CHERRYVIEW(dev_priv) ||
8343                    IS_VALLEYVIEW(dev_priv)) {
8344                 dev_priv->display.funcs.display = &vlv_display_funcs;
8345         } else {
8346                 dev_priv->display.funcs.display = &i9xx_display_funcs;
8347         }
8348
8349         intel_fdi_init_hook(dev_priv);
8350 }
8351
8352 void intel_modeset_init_hw(struct drm_i915_private *i915)
8353 {
8354         struct intel_cdclk_state *cdclk_state;
8355
8356         if (!HAS_DISPLAY(i915))
8357                 return;
8358
8359         cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
8360
8361         intel_update_cdclk(i915);
8362         intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
8363         cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
8364 }
8365
8366 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
8367 {
8368         struct drm_plane *plane;
8369         struct intel_crtc *crtc;
8370
8371         for_each_intel_crtc(state->dev, crtc) {
8372                 struct intel_crtc_state *crtc_state;
8373
8374                 crtc_state = intel_atomic_get_crtc_state(state, crtc);
8375                 if (IS_ERR(crtc_state))
8376                         return PTR_ERR(crtc_state);
8377
8378                 if (crtc_state->hw.active) {
8379                         /*
8380                          * Preserve the inherited flag to avoid
8381                          * taking the full modeset path.
8382                          */
8383                         crtc_state->inherited = true;
8384                 }
8385         }
8386
8387         drm_for_each_plane(plane, state->dev) {
8388                 struct drm_plane_state *plane_state;
8389
8390                 plane_state = drm_atomic_get_plane_state(state, plane);
8391                 if (IS_ERR(plane_state))
8392                         return PTR_ERR(plane_state);
8393         }
8394
8395         return 0;
8396 }
8397
8398 /*
8399  * Calculate what we think the watermarks should be for the state we've read
8400  * out of the hardware and then immediately program those watermarks so that
8401  * we ensure the hardware settings match our internal state.
8402  *
8403  * We can calculate what we think WM's should be by creating a duplicate of the
8404  * current state (which was constructed during hardware readout) and running it
8405  * through the atomic check code to calculate new watermark values in the
8406  * state object.
8407  */
8408 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
8409 {
8410         struct drm_atomic_state *state;
8411         struct intel_atomic_state *intel_state;
8412         struct intel_crtc *crtc;
8413         struct intel_crtc_state *crtc_state;
8414         struct drm_modeset_acquire_ctx ctx;
8415         int ret;
8416         int i;
8417
8418         /* Only supported on platforms that use atomic watermark design */
8419         if (!dev_priv->display.funcs.wm->optimize_watermarks)
8420                 return;
8421
8422         state = drm_atomic_state_alloc(&dev_priv->drm);
8423         if (drm_WARN_ON(&dev_priv->drm, !state))
8424                 return;
8425
8426         intel_state = to_intel_atomic_state(state);
8427
8428         drm_modeset_acquire_init(&ctx, 0);
8429
8430 retry:
8431         state->acquire_ctx = &ctx;
8432
8433         /*
8434          * Hardware readout is the only time we don't want to calculate
8435          * intermediate watermarks (since we don't trust the current
8436          * watermarks).
8437          */
8438         if (!HAS_GMCH(dev_priv))
8439                 intel_state->skip_intermediate_wm = true;
8440
8441         ret = sanitize_watermarks_add_affected(state);
8442         if (ret)
8443                 goto fail;
8444
8445         ret = intel_atomic_check(&dev_priv->drm, state);
8446         if (ret)
8447                 goto fail;
8448
8449         /* Write calculated watermark values back */
8450         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
8451                 crtc_state->wm.need_postvbl_update = true;
8452                 intel_optimize_watermarks(intel_state, crtc);
8453
8454                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
8455         }
8456
8457 fail:
8458         if (ret == -EDEADLK) {
8459                 drm_atomic_state_clear(state);
8460                 drm_modeset_backoff(&ctx);
8461                 goto retry;
8462         }
8463
8464         /*
8465          * If we fail here, it means that the hardware appears to be
8466          * programmed in a way that shouldn't be possible, given our
8467          * understanding of watermark requirements.  This might mean a
8468          * mistake in the hardware readout code or a mistake in the
8469          * watermark calculations for a given platform.  Raise a WARN
8470          * so that this is noticeable.
8471          *
8472          * If this actually happens, we'll have to just leave the
8473          * BIOS-programmed watermarks untouched and hope for the best.
8474          */
8475         drm_WARN(&dev_priv->drm, ret,
8476                  "Could not determine valid watermarks for inherited state\n");
8477
8478         drm_atomic_state_put(state);
8479
8480         drm_modeset_drop_locks(&ctx);
8481         drm_modeset_acquire_fini(&ctx);
8482 }
8483
8484 static int intel_initial_commit(struct drm_device *dev)
8485 {
8486         struct drm_atomic_state *state = NULL;
8487         struct drm_modeset_acquire_ctx ctx;
8488         struct intel_crtc *crtc;
8489         int ret = 0;
8490
8491         state = drm_atomic_state_alloc(dev);
8492         if (!state)
8493                 return -ENOMEM;
8494
8495         drm_modeset_acquire_init(&ctx, 0);
8496
8497 retry:
8498         state->acquire_ctx = &ctx;
8499
8500         for_each_intel_crtc(dev, crtc) {
8501                 struct intel_crtc_state *crtc_state =
8502                         intel_atomic_get_crtc_state(state, crtc);
8503
8504                 if (IS_ERR(crtc_state)) {
8505                         ret = PTR_ERR(crtc_state);
8506                         goto out;
8507                 }
8508
8509                 if (crtc_state->hw.active) {
8510                         struct intel_encoder *encoder;
8511
8512                         /*
8513                          * We've not yet detected sink capabilities
8514                          * (audio,infoframes,etc.) and thus we don't want to
8515                          * force a full state recomputation yet. We want that to
8516                          * happen only for the first real commit from userspace.
8517                          * So preserve the inherited flag for the time being.
8518                          */
8519                         crtc_state->inherited = true;
8520
8521                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
8522                         if (ret)
8523                                 goto out;
8524
8525                         /*
8526                          * FIXME hack to force a LUT update to avoid the
8527                          * plane update forcing the pipe gamma on without
8528                          * having a proper LUT loaded. Remove once we
8529                          * have readout for pipe gamma enable.
8530                          */
8531                         crtc_state->uapi.color_mgmt_changed = true;
8532
8533                         for_each_intel_encoder_mask(dev, encoder,
8534                                                     crtc_state->uapi.encoder_mask) {
8535                                 if (encoder->initial_fastset_check &&
8536                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
8537                                         ret = drm_atomic_add_affected_connectors(state,
8538                                                                                  &crtc->base);
8539                                         if (ret)
8540                                                 goto out;
8541                                 }
8542                         }
8543                 }
8544         }
8545
8546         ret = drm_atomic_commit(state);
8547
8548 out:
8549         if (ret == -EDEADLK) {
8550                 drm_atomic_state_clear(state);
8551                 drm_modeset_backoff(&ctx);
8552                 goto retry;
8553         }
8554
8555         drm_atomic_state_put(state);
8556
8557         drm_modeset_drop_locks(&ctx);
8558         drm_modeset_acquire_fini(&ctx);
8559
8560         return ret;
8561 }
8562
8563 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = {
8564         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
8565 };
8566
8567 static void intel_mode_config_init(struct drm_i915_private *i915)
8568 {
8569         struct drm_mode_config *mode_config = &i915->drm.mode_config;
8570
8571         drm_mode_config_init(&i915->drm);
8572         INIT_LIST_HEAD(&i915->global_obj_list);
8573
8574         mode_config->min_width = 0;
8575         mode_config->min_height = 0;
8576
8577         mode_config->preferred_depth = 24;
8578         mode_config->prefer_shadow = 1;
8579
8580         mode_config->funcs = &intel_mode_funcs;
8581         mode_config->helper_private = &intel_mode_config_funcs;
8582
8583         mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915);
8584
8585         /*
8586          * Maximum framebuffer dimensions, chosen to match
8587          * the maximum render engine surface size on gen4+.
8588          */
8589         if (DISPLAY_VER(i915) >= 7) {
8590                 mode_config->max_width = 16384;
8591                 mode_config->max_height = 16384;
8592         } else if (DISPLAY_VER(i915) >= 4) {
8593                 mode_config->max_width = 8192;
8594                 mode_config->max_height = 8192;
8595         } else if (DISPLAY_VER(i915) == 3) {
8596                 mode_config->max_width = 4096;
8597                 mode_config->max_height = 4096;
8598         } else {
8599                 mode_config->max_width = 2048;
8600                 mode_config->max_height = 2048;
8601         }
8602
8603         if (IS_I845G(i915) || IS_I865G(i915)) {
8604                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
8605                 mode_config->cursor_height = 1023;
8606         } else if (IS_I830(i915) || IS_I85X(i915) ||
8607                    IS_I915G(i915) || IS_I915GM(i915)) {
8608                 mode_config->cursor_width = 64;
8609                 mode_config->cursor_height = 64;
8610         } else {
8611                 mode_config->cursor_width = 256;
8612                 mode_config->cursor_height = 256;
8613         }
8614 }
8615
8616 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
8617 {
8618         intel_atomic_global_obj_cleanup(i915);
8619         drm_mode_config_cleanup(&i915->drm);
8620 }
8621
8622 /* part #1: call before irq install */
8623 int intel_modeset_init_noirq(struct drm_i915_private *i915)
8624 {
8625         int ret;
8626
8627         if (i915_inject_probe_failure(i915))
8628                 return -ENODEV;
8629
8630         if (HAS_DISPLAY(i915)) {
8631                 ret = drm_vblank_init(&i915->drm,
8632                                       INTEL_NUM_PIPES(i915));
8633                 if (ret)
8634                         return ret;
8635         }
8636
8637         intel_bios_init(i915);
8638
8639         ret = intel_vga_register(i915);
8640         if (ret)
8641                 goto cleanup_bios;
8642
8643         /* FIXME: completely on the wrong abstraction layer */
8644         intel_power_domains_init_hw(i915, false);
8645
8646         if (!HAS_DISPLAY(i915))
8647                 return 0;
8648
8649         intel_dmc_ucode_init(i915);
8650
8651         i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
8652         i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
8653                                                 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
8654
8655         intel_mode_config_init(i915);
8656
8657         ret = intel_cdclk_init(i915);
8658         if (ret)
8659                 goto cleanup_vga_client_pw_domain_dmc;
8660
8661         ret = intel_color_init(i915);
8662         if (ret)
8663                 goto cleanup_vga_client_pw_domain_dmc;
8664
8665         ret = intel_dbuf_init(i915);
8666         if (ret)
8667                 goto cleanup_vga_client_pw_domain_dmc;
8668
8669         ret = intel_bw_init(i915);
8670         if (ret)
8671                 goto cleanup_vga_client_pw_domain_dmc;
8672
8673         init_llist_head(&i915->display.atomic_helper.free_list);
8674         INIT_WORK(&i915->display.atomic_helper.free_work,
8675                   intel_atomic_helper_free_state_worker);
8676
8677         intel_init_quirks(i915);
8678
8679         intel_fbc_init(i915);
8680
8681         return 0;
8682
8683 cleanup_vga_client_pw_domain_dmc:
8684         intel_dmc_ucode_fini(i915);
8685         intel_power_domains_driver_remove(i915);
8686         intel_vga_unregister(i915);
8687 cleanup_bios:
8688         intel_bios_driver_remove(i915);
8689
8690         return ret;
8691 }
8692
8693 /* part #2: call after irq install, but before gem init */
8694 int intel_modeset_init_nogem(struct drm_i915_private *i915)
8695 {
8696         struct drm_device *dev = &i915->drm;
8697         enum pipe pipe;
8698         struct intel_crtc *crtc;
8699         int ret;
8700
8701         if (!HAS_DISPLAY(i915))
8702                 return 0;
8703
8704         intel_init_pm(i915);
8705
8706         intel_panel_sanitize_ssc(i915);
8707
8708         intel_pps_setup(i915);
8709
8710         intel_gmbus_setup(i915);
8711
8712         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
8713                     INTEL_NUM_PIPES(i915),
8714                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
8715
8716         for_each_pipe(i915, pipe) {
8717                 ret = intel_crtc_init(i915, pipe);
8718                 if (ret) {
8719                         intel_mode_config_cleanup(i915);
8720                         return ret;
8721                 }
8722         }
8723
8724         intel_plane_possible_crtcs_init(i915);
8725         intel_shared_dpll_init(i915);
8726         intel_fdi_pll_freq_update(i915);
8727
8728         intel_update_czclk(i915);
8729         intel_modeset_init_hw(i915);
8730         intel_dpll_update_ref_clks(i915);
8731
8732         intel_hdcp_component_init(i915);
8733
8734         if (i915->display.cdclk.max_cdclk_freq == 0)
8735                 intel_update_max_cdclk(i915);
8736
8737         /*
8738          * If the platform has HTI, we need to find out whether it has reserved
8739          * any display resources before we create our display outputs.
8740          */
8741         if (INTEL_INFO(i915)->display.has_hti)
8742                 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
8743
8744         /* Just disable it once at startup */
8745         intel_vga_disable(i915);
8746         intel_setup_outputs(i915);
8747
8748         drm_modeset_lock_all(dev);
8749         intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
8750         intel_acpi_assign_connector_fwnodes(i915);
8751         drm_modeset_unlock_all(dev);
8752
8753         for_each_intel_crtc(dev, crtc) {
8754                 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
8755                         continue;
8756                 intel_crtc_initial_plane_config(crtc);
8757         }
8758
8759         /*
8760          * Make sure hardware watermarks really match the state we read out.
8761          * Note that we need to do this after reconstructing the BIOS fb's
8762          * since the watermark calculation done here will use pstate->fb.
8763          */
8764         if (!HAS_GMCH(i915))
8765                 sanitize_watermarks(i915);
8766
8767         return 0;
8768 }
8769
8770 /* part #3: call after gem init */
8771 int intel_modeset_init(struct drm_i915_private *i915)
8772 {
8773         int ret;
8774
8775         if (!HAS_DISPLAY(i915))
8776                 return 0;
8777
8778         /*
8779          * Force all active planes to recompute their states. So that on
8780          * mode_setcrtc after probe, all the intel_plane_state variables
8781          * are already calculated and there is no assert_plane warnings
8782          * during bootup.
8783          */
8784         ret = intel_initial_commit(&i915->drm);
8785         if (ret)
8786                 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
8787
8788         intel_overlay_setup(i915);
8789
8790         ret = intel_fbdev_init(&i915->drm);
8791         if (ret)
8792                 return ret;
8793
8794         /* Only enable hotplug handling once the fbdev is fully set up. */
8795         intel_hpd_init(i915);
8796         intel_hpd_poll_disable(i915);
8797
8798         skl_watermark_ipc_init(i915);
8799
8800         return 0;
8801 }
8802
8803 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8804 {
8805         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8806         /* 640x480@60Hz, ~25175 kHz */
8807         struct dpll clock = {
8808                 .m1 = 18,
8809                 .m2 = 7,
8810                 .p1 = 13,
8811                 .p2 = 4,
8812                 .n = 2,
8813         };
8814         u32 dpll, fp;
8815         int i;
8816
8817         drm_WARN_ON(&dev_priv->drm,
8818                     i9xx_calc_dpll_params(48000, &clock) != 25154);
8819
8820         drm_dbg_kms(&dev_priv->drm,
8821                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8822                     pipe_name(pipe), clock.vco, clock.dot);
8823
8824         fp = i9xx_dpll_compute_fp(&clock);
8825         dpll = DPLL_DVO_2X_MODE |
8826                 DPLL_VGA_MODE_DIS |
8827                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8828                 PLL_P2_DIVIDE_BY_4 |
8829                 PLL_REF_INPUT_DREFCLK |
8830                 DPLL_VCO_ENABLE;
8831
8832         intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
8833         intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
8834         intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
8835         intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
8836         intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
8837         intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
8838         intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
8839
8840         intel_de_write(dev_priv, FP0(pipe), fp);
8841         intel_de_write(dev_priv, FP1(pipe), fp);
8842
8843         /*
8844          * Apparently we need to have VGA mode enabled prior to changing
8845          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8846          * dividers, even though the register value does change.
8847          */
8848         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8849         intel_de_write(dev_priv, DPLL(pipe), dpll);
8850
8851         /* Wait for the clocks to stabilize. */
8852         intel_de_posting_read(dev_priv, DPLL(pipe));
8853         udelay(150);
8854
8855         /* The pixel multiplier can only be updated once the
8856          * DPLL is enabled and the clocks are stable.
8857          *
8858          * So write it again.
8859          */
8860         intel_de_write(dev_priv, DPLL(pipe), dpll);
8861
8862         /* We do this three times for luck */
8863         for (i = 0; i < 3 ; i++) {
8864                 intel_de_write(dev_priv, DPLL(pipe), dpll);
8865                 intel_de_posting_read(dev_priv, DPLL(pipe));
8866                 udelay(150); /* wait for warmup */
8867         }
8868
8869         intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
8870         intel_de_posting_read(dev_priv, PIPECONF(pipe));
8871
8872         intel_wait_for_pipe_scanline_moving(crtc);
8873 }
8874
8875 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8876 {
8877         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8878
8879         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8880                     pipe_name(pipe));
8881
8882         drm_WARN_ON(&dev_priv->drm,
8883                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8884         drm_WARN_ON(&dev_priv->drm,
8885                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8886         drm_WARN_ON(&dev_priv->drm,
8887                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8888         drm_WARN_ON(&dev_priv->drm,
8889                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8890         drm_WARN_ON(&dev_priv->drm,
8891                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8892
8893         intel_de_write(dev_priv, PIPECONF(pipe), 0);
8894         intel_de_posting_read(dev_priv, PIPECONF(pipe));
8895
8896         intel_wait_for_pipe_scanline_stopped(crtc);
8897
8898         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8899         intel_de_posting_read(dev_priv, DPLL(pipe));
8900 }
8901
8902 void intel_display_resume(struct drm_device *dev)
8903 {
8904         struct drm_i915_private *i915 = to_i915(dev);
8905         struct drm_atomic_state *state = i915->modeset_restore_state;
8906         struct drm_modeset_acquire_ctx ctx;
8907         int ret;
8908
8909         if (!HAS_DISPLAY(i915))
8910                 return;
8911
8912         i915->modeset_restore_state = NULL;
8913         if (state)
8914                 state->acquire_ctx = &ctx;
8915
8916         drm_modeset_acquire_init(&ctx, 0);
8917
8918         while (1) {
8919                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
8920                 if (ret != -EDEADLK)
8921                         break;
8922
8923                 drm_modeset_backoff(&ctx);
8924         }
8925
8926         if (!ret)
8927                 ret = __intel_display_resume(i915, state, &ctx);
8928
8929         skl_watermark_ipc_update(i915);
8930         drm_modeset_drop_locks(&ctx);
8931         drm_modeset_acquire_fini(&ctx);
8932
8933         if (ret)
8934                 drm_err(&i915->drm,
8935                         "Restoring old state failed with %i\n", ret);
8936         if (state)
8937                 drm_atomic_state_put(state);
8938 }
8939
8940 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
8941 {
8942         struct intel_connector *connector;
8943         struct drm_connector_list_iter conn_iter;
8944
8945         /* Kill all the work that may have been queued by hpd. */
8946         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8947         for_each_intel_connector_iter(connector, &conn_iter) {
8948                 if (connector->modeset_retry_work.func)
8949                         cancel_work_sync(&connector->modeset_retry_work);
8950                 if (connector->hdcp.shim) {
8951                         cancel_delayed_work_sync(&connector->hdcp.check_work);
8952                         cancel_work_sync(&connector->hdcp.prop_work);
8953                 }
8954         }
8955         drm_connector_list_iter_end(&conn_iter);
8956 }
8957
8958 /* part #1: call before irq uninstall */
8959 void intel_modeset_driver_remove(struct drm_i915_private *i915)
8960 {
8961         if (!HAS_DISPLAY(i915))
8962                 return;
8963
8964         flush_workqueue(i915->display.wq.flip);
8965         flush_workqueue(i915->display.wq.modeset);
8966
8967         flush_work(&i915->display.atomic_helper.free_work);
8968         drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list));
8969
8970         /*
8971          * MST topology needs to be suspended so we don't have any calls to
8972          * fbdev after it's finalized. MST will be destroyed later as part of
8973          * drm_mode_config_cleanup()
8974          */
8975         intel_dp_mst_suspend(i915);
8976 }
8977
8978 /* part #2: call after irq uninstall */
8979 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
8980 {
8981         if (!HAS_DISPLAY(i915))
8982                 return;
8983
8984         /*
8985          * Due to the hpd irq storm handling the hotplug work can re-arm the
8986          * poll handlers. Hence disable polling after hpd handling is shut down.
8987          */
8988         intel_hpd_poll_fini(i915);
8989
8990         /* poll work can call into fbdev, hence clean that up afterwards */
8991         intel_fbdev_fini(i915);
8992
8993         intel_unregister_dsm_handler();
8994
8995         /* flush any delayed tasks or pending work */
8996         flush_scheduled_work();
8997
8998         intel_hdcp_component_fini(i915);
8999
9000         intel_mode_config_cleanup(i915);
9001
9002         intel_overlay_cleanup(i915);
9003
9004         intel_gmbus_teardown(i915);
9005
9006         destroy_workqueue(i915->display.wq.flip);
9007         destroy_workqueue(i915->display.wq.modeset);
9008
9009         intel_fbc_cleanup(i915);
9010 }
9011
9012 /* part #3: call after gem init */
9013 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
9014 {
9015         intel_dmc_ucode_fini(i915);
9016
9017         intel_power_domains_driver_remove(i915);
9018
9019         intel_vga_unregister(i915);
9020
9021         intel_bios_driver_remove(i915);
9022 }
9023
9024 bool intel_modeset_probe_defer(struct pci_dev *pdev)
9025 {
9026         struct drm_privacy_screen *privacy_screen;
9027
9028         /*
9029          * apple-gmux is needed on dual GPU MacBook Pro
9030          * to probe the panel if we're the inactive GPU.
9031          */
9032         if (vga_switcheroo_client_probe_defer(pdev))
9033                 return true;
9034
9035         /* If the LCD panel has a privacy-screen, wait for it */
9036         privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL);
9037         if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
9038                 return true;
9039
9040         drm_privacy_screen_put(privacy_screen);
9041
9042         return false;
9043 }
9044
9045 void intel_display_driver_register(struct drm_i915_private *i915)
9046 {
9047         if (!HAS_DISPLAY(i915))
9048                 return;
9049
9050         intel_display_debugfs_register(i915);
9051
9052         /* Must be done after probing outputs */
9053         intel_opregion_register(i915);
9054         intel_acpi_video_register(i915);
9055
9056         intel_audio_init(i915);
9057
9058         /*
9059          * Some ports require correctly set-up hpd registers for
9060          * detection to work properly (leading to ghost connected
9061          * connector status), e.g. VGA on gm45.  Hence we can only set
9062          * up the initial fbdev config after hpd irqs are fully
9063          * enabled. We do it last so that the async config cannot run
9064          * before the connectors are registered.
9065          */
9066         intel_fbdev_initial_config_async(&i915->drm);
9067
9068         /*
9069          * We need to coordinate the hotplugs with the asynchronous
9070          * fbdev configuration, for which we use the
9071          * fbdev->async_cookie.
9072          */
9073         drm_kms_helper_poll_init(&i915->drm);
9074 }
9075
9076 void intel_display_driver_unregister(struct drm_i915_private *i915)
9077 {
9078         if (!HAS_DISPLAY(i915))
9079                 return;
9080
9081         intel_fbdev_unregister(i915);
9082         intel_audio_deinit(i915);
9083
9084         /*
9085          * After flushing the fbdev (incl. a late async config which
9086          * will have delayed queuing of a hotplug event), then flush
9087          * the hotplug events.
9088          */
9089         drm_kms_helper_poll_fini(&i915->drm);
9090         drm_atomic_helper_shutdown(&i915->drm);
9091
9092         acpi_video_unregister();
9093         intel_opregion_unregister(i915);
9094 }
9095
9096 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
9097 {
9098         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
9099 }