drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_link_training.h"
  38 #include "intel_dpio_phy.h"
  39 #include "intel_dsi.h"
  40 #include "intel_fifo_underrun.h"
  41 #include "intel_gmbus.h"
  42 #include "intel_hdcp.h"
  43 #include "intel_hdmi.h"
  44 #include "intel_hotplug.h"
  45 #include "intel_lspcon.h"
  46 #include "intel_panel.h"
  47 #include "intel_psr.h"
  48 #include "intel_sprite.h"
  49 #include "intel_tc.h"
  50 #include "intel_vdsc.h"
  51
  52 struct ddi_buf_trans {
  53         u32 trans1;     /* balance leg enable, de-emph level */
  54         u32 trans2;     /* vref sel, vswing */
  55         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  56 };
  57
  58 static const u8 index_to_dp_signal_levels[] = {
  59         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  60         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  61         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  62         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  63         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  64         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  65         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  66         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  67         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  68         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  69 };
  70
  71 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  72  * them for both DP and FDI transports, allowing those ports to
  73  * automatically adapt to HDMI connections as well
  74  */
  75 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  76         { 0x00FFFFFF, 0x0006000E, 0x0 },
  77         { 0x00D75FFF, 0x0005000A, 0x0 },
  78         { 0x00C30FFF, 0x00040006, 0x0 },
  79         { 0x80AAAFFF, 0x000B0000, 0x0 },
  80         { 0x00FFFFFF, 0x0005000A, 0x0 },
  81         { 0x00D75FFF, 0x000C0004, 0x0 },
  82         { 0x80C30FFF, 0x000B0000, 0x0 },
  83         { 0x00FFFFFF, 0x00040006, 0x0 },
  84         { 0x80D75FFF, 0x000B0000, 0x0 },
  85 };
  86
  87 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  88         { 0x00FFFFFF, 0x0007000E, 0x0 },
  89         { 0x00D75FFF, 0x000F000A, 0x0 },
  90         { 0x00C30FFF, 0x00060006, 0x0 },
  91         { 0x00AAAFFF, 0x001E0000, 0x0 },
  92         { 0x00FFFFFF, 0x000F000A, 0x0 },
  93         { 0x00D75FFF, 0x00160004, 0x0 },
  94         { 0x00C30FFF, 0x001E0000, 0x0 },
  95         { 0x00FFFFFF, 0x00060006, 0x0 },
  96         { 0x00D75FFF, 0x001E0000, 0x0 },
  97 };
  98
  99 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 100                                         /* Idx  NT mV d T mV d  db      */
 101         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 102         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 103         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 104         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 105         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 106         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 107         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 108         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 109         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 110         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 111         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 112         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 113 };
 114
 115 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 116         { 0x00FFFFFF, 0x00000012, 0x0 },
 117         { 0x00EBAFFF, 0x00020011, 0x0 },
 118         { 0x00C71FFF, 0x0006000F, 0x0 },
 119         { 0x00AAAFFF, 0x000E000A, 0x0 },
 120         { 0x00FFFFFF, 0x00020011, 0x0 },
 121         { 0x00DB6FFF, 0x0005000F, 0x0 },
 122         { 0x00BEEFFF, 0x000A000C, 0x0 },
 123         { 0x00FFFFFF, 0x0005000F, 0x0 },
 124         { 0x00DB6FFF, 0x000A000C, 0x0 },
 125 };
 126
 127 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 128         { 0x00FFFFFF, 0x0007000E, 0x0 },
 129         { 0x00D75FFF, 0x000E000A, 0x0 },
 130         { 0x00BEFFFF, 0x00140006, 0x0 },
 131         { 0x80B2CFFF, 0x001B0002, 0x0 },
 132         { 0x00FFFFFF, 0x000E000A, 0x0 },
 133         { 0x00DB6FFF, 0x00160005, 0x0 },
 134         { 0x80C71FFF, 0x001A0002, 0x0 },
 135         { 0x00F7DFFF, 0x00180004, 0x0 },
 136         { 0x80D75FFF, 0x001B0002, 0x0 },
 137 };
 138
 139 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 140         { 0x00FFFFFF, 0x0001000E, 0x0 },
 141         { 0x00D75FFF, 0x0004000A, 0x0 },
 142         { 0x00C30FFF, 0x00070006, 0x0 },
 143         { 0x00AAAFFF, 0x000C0000, 0x0 },
 144         { 0x00FFFFFF, 0x0004000A, 0x0 },
 145         { 0x00D75FFF, 0x00090004, 0x0 },
 146         { 0x00C30FFF, 0x000C0000, 0x0 },
 147         { 0x00FFFFFF, 0x00070006, 0x0 },
 148         { 0x00D75FFF, 0x000C0000, 0x0 },
 149 };
 150
 151 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 152                                         /* Idx  NT mV d T mV df db      */
 153         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 154         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 155         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 156         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 157         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 158         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 159         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 160         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 161         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 162         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 163 };
 164
 165 /* Skylake H and S */
 166 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 167         { 0x00002016, 0x000000A0, 0x0 },
 168         { 0x00005012, 0x0000009B, 0x0 },
 169         { 0x00007011, 0x00000088, 0x0 },
 170         { 0x80009010, 0x000000C0, 0x1 },
 171         { 0x00002016, 0x0000009B, 0x0 },
 172         { 0x00005012, 0x00000088, 0x0 },
 173         { 0x80007011, 0x000000C0, 0x1 },
 174         { 0x00002016, 0x000000DF, 0x0 },
 175         { 0x80005012, 0x000000C0, 0x1 },
 176 };
 177
 178 /* Skylake U */
 179 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 180         { 0x0000201B, 0x000000A2, 0x0 },
 181         { 0x00005012, 0x00000088, 0x0 },
 182         { 0x80007011, 0x000000CD, 0x1 },
 183         { 0x80009010, 0x000000C0, 0x1 },
 184         { 0x0000201B, 0x0000009D, 0x0 },
 185         { 0x80005012, 0x000000C0, 0x1 },
 186         { 0x80007011, 0x000000C0, 0x1 },
 187         { 0x00002016, 0x00000088, 0x0 },
 188         { 0x80005012, 0x000000C0, 0x1 },
 189 };
 190
 191 /* Skylake Y */
 192 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 193         { 0x00000018, 0x000000A2, 0x0 },
 194         { 0x00005012, 0x00000088, 0x0 },
 195         { 0x80007011, 0x000000CD, 0x3 },
 196         { 0x80009010, 0x000000C0, 0x3 },
 197         { 0x00000018, 0x0000009D, 0x0 },
 198         { 0x80005012, 0x000000C0, 0x3 },
 199         { 0x80007011, 0x000000C0, 0x3 },
 200         { 0x00000018, 0x00000088, 0x0 },
 201         { 0x80005012, 0x000000C0, 0x3 },
 202 };
 203
 204 /* Kabylake H and S */
 205 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 206         { 0x00002016, 0x000000A0, 0x0 },
 207         { 0x00005012, 0x0000009B, 0x0 },
 208         { 0x00007011, 0x00000088, 0x0 },
 209         { 0x80009010, 0x000000C0, 0x1 },
 210         { 0x00002016, 0x0000009B, 0x0 },
 211         { 0x00005012, 0x00000088, 0x0 },
 212         { 0x80007011, 0x000000C0, 0x1 },
 213         { 0x00002016, 0x00000097, 0x0 },
 214         { 0x80005012, 0x000000C0, 0x1 },
 215 };
 216
 217 /* Kabylake U */
 218 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 219         { 0x0000201B, 0x000000A1, 0x0 },
 220         { 0x00005012, 0x00000088, 0x0 },
 221         { 0x80007011, 0x000000CD, 0x3 },
 222         { 0x80009010, 0x000000C0, 0x3 },
 223         { 0x0000201B, 0x0000009D, 0x0 },
 224         { 0x80005012, 0x000000C0, 0x3 },
 225         { 0x80007011, 0x000000C0, 0x3 },
 226         { 0x00002016, 0x0000004F, 0x0 },
 227         { 0x80005012, 0x000000C0, 0x3 },
 228 };
 229
 230 /* Kabylake Y */
 231 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 232         { 0x00001017, 0x000000A1, 0x0 },
 233         { 0x00005012, 0x00000088, 0x0 },
 234         { 0x80007011, 0x000000CD, 0x3 },
 235         { 0x8000800F, 0x000000C0, 0x3 },
 236         { 0x00001017, 0x0000009D, 0x0 },
 237         { 0x80005012, 0x000000C0, 0x3 },
 238         { 0x80007011, 0x000000C0, 0x3 },
 239         { 0x00001017, 0x0000004C, 0x0 },
 240         { 0x80005012, 0x000000C0, 0x3 },
 241 };
 242
 243 /*
 244  * Skylake/Kabylake H and S
 245  * eDP 1.4 low vswing translation parameters
 246  */
 247 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 248         { 0x00000018, 0x000000A8, 0x0 },
 249         { 0x00004013, 0x000000A9, 0x0 },
 250         { 0x00007011, 0x000000A2, 0x0 },
 251         { 0x00009010, 0x0000009C, 0x0 },
 252         { 0x00000018, 0x000000A9, 0x0 },
 253         { 0x00006013, 0x000000A2, 0x0 },
 254         { 0x00007011, 0x000000A6, 0x0 },
 255         { 0x00000018, 0x000000AB, 0x0 },
 256         { 0x00007013, 0x0000009F, 0x0 },
 257         { 0x00000018, 0x000000DF, 0x0 },
 258 };
 259
 260 /*
 261  * Skylake/Kabylake U
 262  * eDP 1.4 low vswing translation parameters
 263  */
 264 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 265         { 0x00000018, 0x000000A8, 0x0 },
 266         { 0x00004013, 0x000000A9, 0x0 },
 267         { 0x00007011, 0x000000A2, 0x0 },
 268         { 0x00009010, 0x0000009C, 0x0 },
 269         { 0x00000018, 0x000000A9, 0x0 },
 270         { 0x00006013, 0x000000A2, 0x0 },
 271         { 0x00007011, 0x000000A6, 0x0 },
 272         { 0x00002016, 0x000000AB, 0x0 },
 273         { 0x00005013, 0x0000009F, 0x0 },
 274         { 0x00000018, 0x000000DF, 0x0 },
 275 };
 276
 277 /*
 278  * Skylake/Kabylake Y
 279  * eDP 1.4 low vswing translation parameters
 280  */
 281 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 282         { 0x00000018, 0x000000A8, 0x0 },
 283         { 0x00004013, 0x000000AB, 0x0 },
 284         { 0x00007011, 0x000000A4, 0x0 },
 285         { 0x00009010, 0x000000DF, 0x0 },
 286         { 0x00000018, 0x000000AA, 0x0 },
 287         { 0x00006013, 0x000000A4, 0x0 },
 288         { 0x00007011, 0x0000009D, 0x0 },
 289         { 0x00000018, 0x000000A0, 0x0 },
 290         { 0x00006012, 0x000000DF, 0x0 },
 291         { 0x00000018, 0x0000008A, 0x0 },
 292 };
 293
 294 /* Skylake/Kabylake U, H and S */
 295 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 296         { 0x00000018, 0x000000AC, 0x0 },
 297         { 0x00005012, 0x0000009D, 0x0 },
 298         { 0x00007011, 0x00000088, 0x0 },
 299         { 0x00000018, 0x000000A1, 0x0 },
 300         { 0x00000018, 0x00000098, 0x0 },
 301         { 0x00004013, 0x00000088, 0x0 },
 302         { 0x80006012, 0x000000CD, 0x1 },
 303         { 0x00000018, 0x000000DF, 0x0 },
 304         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 305         { 0x80003015, 0x000000C0, 0x1 },
 306         { 0x80000018, 0x000000C0, 0x1 },
 307 };
 308
 309 /* Skylake/Kabylake Y */
 310 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 311         { 0x00000018, 0x000000A1, 0x0 },
 312         { 0x00005012, 0x000000DF, 0x0 },
 313         { 0x80007011, 0x000000CB, 0x3 },
 314         { 0x00000018, 0x000000A4, 0x0 },
 315         { 0x00000018, 0x0000009D, 0x0 },
 316         { 0x00004013, 0x00000080, 0x0 },
 317         { 0x80006013, 0x000000C0, 0x3 },
 318         { 0x00000018, 0x0000008A, 0x0 },
 319         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 320         { 0x80003015, 0x000000C0, 0x3 },
 321         { 0x80000018, 0x000000C0, 0x3 },
 322 };
 323
 324 struct bxt_ddi_buf_trans {
 325         u8 margin;      /* swing value */
 326         u8 scale;       /* scale value */
 327         u8 enable;      /* scale enable */
 328         u8 deemphasis;
 329 };
 330
 331 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 332                                         /* Idx  NT mV diff      db  */
 333         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 334         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 335         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 336         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 337         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 338         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 339         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 340         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 341         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 342         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 343 };
 344
 345 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 346                                         /* Idx  NT mV diff      db  */
 347         { 26, 0, 0, 128, },     /* 0:   200             0   */
 348         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 349         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 350         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 351         { 32, 0, 0, 128, },     /* 4:   250             0   */
 352         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 353         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 354         { 43, 0, 0, 128, },     /* 7:   300             0   */
 355         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 356         { 48, 0, 0, 128, },     /* 9:   300             0   */
 357 };
 358
 359 /* BSpec has 2 recommended values - entries 0 and 8.
 360  * Using the entry with higher vswing.
 361  */
 362 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 363                                         /* Idx  NT mV diff      db  */
 364         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 365         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 366         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 367         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 368         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 369         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 370         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 371         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 372         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 373         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 374 };
 375
 376 struct cnl_ddi_buf_trans {
 377         u8 dw2_swing_sel;
 378         u8 dw7_n_scalar;
 379         u8 dw4_cursor_coeff;
 380         u8 dw4_post_cursor_2;
 381         u8 dw4_post_cursor_1;
 382 };
 383
 384 /* Voltage Swing Programming for VccIO 0.85V for DP */
 385 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 386                                                 /* NT mV Trans mV db    */
 387         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 388         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 389         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 390         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 391         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 392         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 393         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 394         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 395         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 396         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 397 };
 398
 399 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 400 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 401                                                 /* NT mV Trans mV db    */
 402         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 403         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 404         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 405         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 406         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 407         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 408         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 409 };
 410
 411 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 412 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 413                                                 /* NT mV Trans mV db    */
 414         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 415         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 416         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 417         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 418         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 419         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 420         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 421         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 422         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 423 };
 424
 425 /* Voltage Swing Programming for VccIO 0.95V for DP */
 426 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 427                                                 /* NT mV Trans mV db    */
 428         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 429         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 430         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 431         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 432         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 433         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 434         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 435         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 436         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 437         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 438 };
 439
 440 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 441 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 442                                                 /* NT mV Trans mV db    */
 443         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 444         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 445         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 446         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 447         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 448         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 449         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 450         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 451         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 452         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 453         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 454 };
 455
 456 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 457 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 458                                                 /* NT mV Trans mV db    */
 459         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 460         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 461         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 462         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 463         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 464         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 465         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 466         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 467         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 468         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 469 };
 470
 471 /* Voltage Swing Programming for VccIO 1.05V for DP */
 472 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 473                                                 /* NT mV Trans mV db    */
 474         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 475         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 476         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 477         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 478         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 479         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 480         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 481         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 482         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 483         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 484 };
 485
 486 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 487 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 488                                                 /* NT mV Trans mV db    */
 489         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 490         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 491         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 492         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 493         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 494         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 495         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 496         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 497         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 498         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 499         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 500 };
 501
 502 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 503 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 504                                                 /* NT mV Trans mV db    */
 505         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 506         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 507         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 508         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 509         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 510         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 511         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 512         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 513         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 514 };
 515
 516 /* icl_combo_phy_ddi_translations */
 517 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 518                                                 /* NT mV Trans mV db    */
 519         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 520         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 521         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 522         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 523         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 524         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 525         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 526         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 527         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 528         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 529 };
 530
 531 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 532                                                 /* NT mV Trans mV db    */
 533         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 534         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 535         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 536         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 537         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 538         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 539         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 540         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 541         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 542         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 543 };
 544
 545 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 546                                                 /* NT mV Trans mV db    */
 547         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 548         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 549         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 550         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 551         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 552         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 553         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 554         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 555         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 556         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 557 };
 558
 559 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 560                                                 /* NT mV Trans mV db    */
 561         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 562         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 563         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 564         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 565         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 566         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 567         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 568 };
 569
 570 struct icl_mg_phy_ddi_buf_trans {
 571         u32 cri_txdeemph_override_5_0;
 572         u32 cri_txdeemph_override_11_6;
 573         u32 cri_txdeemph_override_17_12;
 574 };
 575
 576 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 577                                 /* Voltage swing  pre-emphasis */
 578         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 579         { 0x0, 0x23, 0x08 },    /* 0              1   */
 580         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 581         { 0x0, 0x00, 0x00 },    /* 0              3   */
 582         { 0x0, 0x23, 0x00 },    /* 1              0   */
 583         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 584         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 585         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 586         { 0x0, 0x33, 0x0C },    /* 2              1   */
 587         { 0x0, 0x00, 0x00 },    /* 3              0   */
 588 };
 589
 590 struct tgl_dkl_phy_ddi_buf_trans {
 591         u32 dkl_vswing_control;
 592         u32 dkl_preshoot_control;
 593         u32 dkl_de_emphasis_control;
 594 };
 595
 596 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = {
 597                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 598         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 599         { 0x5, 0x0, 0x03 },     /* 0    1       400mV           3.5 dB */
 600         { 0x2, 0x0, 0x0b },     /* 0    2       400mV           6 dB */
 601         { 0x0, 0x0, 0x19 },     /* 0    3       400mV           9.5 dB */
 602         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 603         { 0x2, 0x0, 0x03 },     /* 1    1       600mV           3.5 dB */
 604         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 605         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 606         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 607         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 608 };
 609
 610 static const struct ddi_buf_trans *
 611 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 612 {
 613         if (dev_priv->vbt.edp.low_vswing) {
 614                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 615                 return bdw_ddi_translations_edp;
 616         } else {
 617                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 618                 return bdw_ddi_translations_dp;
 619         }
 620 }
 621
 622 static const struct ddi_buf_trans *
 623 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 624 {
 625         if (IS_SKL_ULX(dev_priv)) {
 626                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 627                 return skl_y_ddi_translations_dp;
 628         } else if (IS_SKL_ULT(dev_priv)) {
 629                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 630                 return skl_u_ddi_translations_dp;
 631         } else {
 632                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 633                 return skl_ddi_translations_dp;
 634         }
 635 }
 636
 637 static const struct ddi_buf_trans *
 638 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 639 {
 640         if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
 641                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 642                 return kbl_y_ddi_translations_dp;
 643         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 644                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 645                 return kbl_u_ddi_translations_dp;
 646         } else {
 647                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 648                 return kbl_ddi_translations_dp;
 649         }
 650 }
 651
 652 static const struct ddi_buf_trans *
 653 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 654 {
 655         if (dev_priv->vbt.edp.low_vswing) {
 656                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 657                     IS_CFL_ULX(dev_priv)) {
 658                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 659                         return skl_y_ddi_translations_edp;
 660                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 661                            IS_CFL_ULT(dev_priv)) {
 662                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 663                         return skl_u_ddi_translations_edp;
 664                 } else {
 665                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 666                         return skl_ddi_translations_edp;
 667                 }
 668         }
 669
 670         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 671                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 672         else
 673                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 674 }
 675
 676 static const struct ddi_buf_trans *
 677 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 678 {
 679         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
 680             IS_CFL_ULX(dev_priv)) {
 681                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 682                 return skl_y_ddi_translations_hdmi;
 683         } else {
 684                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 685                 return skl_ddi_translations_hdmi;
 686         }
 687 }
 688
 689 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 690 {
 691         /* Only DDIA and DDIE can select the 10th register with DP */
 692         if (port == PORT_A || port == PORT_E)
 693                 return min(n_entries, 10);
 694         else
 695                 return min(n_entries, 9);
 696 }
 697
 698 static const struct ddi_buf_trans *
 699 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 700                            enum port port, int *n_entries)
 701 {
 702         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 703                 const struct ddi_buf_trans *ddi_translations =
 704                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 705                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 706                 return ddi_translations;
 707         } else if (IS_SKYLAKE(dev_priv)) {
 708                 const struct ddi_buf_trans *ddi_translations =
 709                         skl_get_buf_trans_dp(dev_priv, n_entries);
 710                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 711                 return ddi_translations;
 712         } else if (IS_BROADWELL(dev_priv)) {
 713                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 714                 return  bdw_ddi_translations_dp;
 715         } else if (IS_HASWELL(dev_priv)) {
 716                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 717                 return hsw_ddi_translations_dp;
 718         }
 719
 720         *n_entries = 0;
 721         return NULL;
 722 }
 723
 724 static const struct ddi_buf_trans *
 725 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 726                             enum port port, int *n_entries)
 727 {
 728         if (IS_GEN9_BC(dev_priv)) {
 729                 const struct ddi_buf_trans *ddi_translations =
 730                         skl_get_buf_trans_edp(dev_priv, n_entries);
 731                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 732                 return ddi_translations;
 733         } else if (IS_BROADWELL(dev_priv)) {
 734                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 735         } else if (IS_HASWELL(dev_priv)) {
 736                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 737                 return hsw_ddi_translations_dp;
 738         }
 739
 740         *n_entries = 0;
 741         return NULL;
 742 }
 743
 744 static const struct ddi_buf_trans *
 745 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 746                             int *n_entries)
 747 {
 748         if (IS_BROADWELL(dev_priv)) {
 749                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 750                 return bdw_ddi_translations_fdi;
 751         } else if (IS_HASWELL(dev_priv)) {
 752                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 753                 return hsw_ddi_translations_fdi;
 754         }
 755
 756         *n_entries = 0;
 757         return NULL;
 758 }
 759
 760 static const struct ddi_buf_trans *
 761 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 762                              int *n_entries)
 763 {
 764         if (IS_GEN9_BC(dev_priv)) {
 765                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 766         } else if (IS_BROADWELL(dev_priv)) {
 767                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 768                 return bdw_ddi_translations_hdmi;
 769         } else if (IS_HASWELL(dev_priv)) {
 770                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 771                 return hsw_ddi_translations_hdmi;
 772         }
 773
 774         *n_entries = 0;
 775         return NULL;
 776 }
 777
 778 static const struct bxt_ddi_buf_trans *
 779 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 780 {
 781         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 782         return bxt_ddi_translations_dp;
 783 }
 784
 785 static const struct bxt_ddi_buf_trans *
 786 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 787 {
 788         if (dev_priv->vbt.edp.low_vswing) {
 789                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 790                 return bxt_ddi_translations_edp;
 791         }
 792
 793         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 794 }
 795
 796 static const struct bxt_ddi_buf_trans *
 797 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 798 {
 799         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 800         return bxt_ddi_translations_hdmi;
 801 }
 802
 803 static const struct cnl_ddi_buf_trans *
 804 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 805 {
 806         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 807
 808         if (voltage == VOLTAGE_INFO_0_85V) {
 809                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 810                 return cnl_ddi_translations_hdmi_0_85V;
 811         } else if (voltage == VOLTAGE_INFO_0_95V) {
 812                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 813                 return cnl_ddi_translations_hdmi_0_95V;
 814         } else if (voltage == VOLTAGE_INFO_1_05V) {
 815                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 816                 return cnl_ddi_translations_hdmi_1_05V;
 817         } else {
 818                 *n_entries = 1; /* shut up gcc */
 819                 MISSING_CASE(voltage);
 820         }
 821         return NULL;
 822 }
 823
 824 static const struct cnl_ddi_buf_trans *
 825 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 826 {
 827         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 828
 829         if (voltage == VOLTAGE_INFO_0_85V) {
 830                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 831                 return cnl_ddi_translations_dp_0_85V;
 832         } else if (voltage == VOLTAGE_INFO_0_95V) {
 833                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 834                 return cnl_ddi_translations_dp_0_95V;
 835         } else if (voltage == VOLTAGE_INFO_1_05V) {
 836                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 837                 return cnl_ddi_translations_dp_1_05V;
 838         } else {
 839                 *n_entries = 1; /* shut up gcc */
 840                 MISSING_CASE(voltage);
 841         }
 842         return NULL;
 843 }
 844
 845 static const struct cnl_ddi_buf_trans *
 846 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 847 {
 848         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 849
 850         if (dev_priv->vbt.edp.low_vswing) {
 851                 if (voltage == VOLTAGE_INFO_0_85V) {
 852                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 853                         return cnl_ddi_translations_edp_0_85V;
 854                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 855                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 856                         return cnl_ddi_translations_edp_0_95V;
 857                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 858                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 859                         return cnl_ddi_translations_edp_1_05V;
 860                 } else {
 861                         *n_entries = 1; /* shut up gcc */
 862                         MISSING_CASE(voltage);
 863                 }
 864                 return NULL;
 865         } else {
 866                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 867         }
 868 }
 869
 870 static const struct cnl_ddi_buf_trans *
 871 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 872                         int *n_entries)
 873 {
 874         if (type == INTEL_OUTPUT_HDMI) {
 875                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
 876                 return icl_combo_phy_ddi_translations_hdmi;
 877         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
 878                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 879                 return icl_combo_phy_ddi_translations_edp_hbr3;
 880         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 881                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 882                 return icl_combo_phy_ddi_translations_edp_hbr2;
 883         }
 884
 885         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
 886         return icl_combo_phy_ddi_translations_dp_hbr2;
 887 }
 888
 889 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 890 {
 891         int n_entries, level, default_entry;
 892         enum phy phy = intel_port_to_phy(dev_priv, port);
 893
 894         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 895
 896         if (INTEL_GEN(dev_priv) >= 12) {
 897                 if (intel_phy_is_combo(dev_priv, phy))
 898                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 899                                                 0, &n_entries);
 900                 else
 901                         n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
 902                 default_entry = n_entries - 1;
 903         } else if (INTEL_GEN(dev_priv) == 11) {
 904                 if (intel_phy_is_combo(dev_priv, phy))
 905                         icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 906                                                 0, &n_entries);
 907                 else
 908                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 909                 default_entry = n_entries - 1;
 910         } else if (IS_CANNONLAKE(dev_priv)) {
 911                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 912                 default_entry = n_entries - 1;
 913         } else if (IS_GEN9_LP(dev_priv)) {
 914                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 915                 default_entry = n_entries - 1;
 916         } else if (IS_GEN9_BC(dev_priv)) {
 917                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 918                 default_entry = 8;
 919         } else if (IS_BROADWELL(dev_priv)) {
 920                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 921                 default_entry = 7;
 922         } else if (IS_HASWELL(dev_priv)) {
 923                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 924                 default_entry = 6;
 925         } else {
 926                 WARN(1, "ddi translation table missing\n");
 927                 return 0;
 928         }
 929
 930         /* Choose a good default if VBT is badly populated */
 931         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 932                 level = default_entry;
 933
 934         if (WARN_ON_ONCE(n_entries == 0))
 935                 return 0;
 936         if (WARN_ON_ONCE(level >= n_entries))
 937                 level = n_entries - 1;
 938
 939         return level;
 940 }
 941
 942 /*
 943  * Starting with Haswell, DDI port buffers must be programmed with correct
 944  * values in advance. This function programs the correct values for
 945  * DP/eDP/FDI use cases.
 946  */
 947 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 948                                          const struct intel_crtc_state *crtc_state)
 949 {
 950         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 951         u32 iboost_bit = 0;
 952         int i, n_entries;
 953         enum port port = encoder->port;
 954         const struct ddi_buf_trans *ddi_translations;
 955
 956         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 957                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 958                                                                &n_entries);
 959         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 960                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 961                                                                &n_entries);
 962         else
 963                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 964                                                               &n_entries);
 965
 966         /* If we're boosting the current, set bit 31 of trans1 */
 967         if (IS_GEN9_BC(dev_priv) &&
 968             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 969                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 970
 971         for (i = 0; i < n_entries; i++) {
 972                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 973                            ddi_translations[i].trans1 | iboost_bit);
 974                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 975                            ddi_translations[i].trans2);
 976         }
 977 }
 978
 979 /*
 980  * Starting with Haswell, DDI port buffers must be programmed with correct
 981  * values in advance. This function programs the correct values for
 982  * HDMI/DVI use cases.
 983  */
 984 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 985                                            int level)
 986 {
 987         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 988         u32 iboost_bit = 0;
 989         int n_entries;
 990         enum port port = encoder->port;
 991         const struct ddi_buf_trans *ddi_translations;
 992
 993         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 994
 995         if (WARN_ON_ONCE(!ddi_translations))
 996                 return;
 997         if (WARN_ON_ONCE(level >= n_entries))
 998                 level = n_entries - 1;
 999
1000         /* If we're boosting the current, set bit 31 of trans1 */
1001         if (IS_GEN9_BC(dev_priv) &&
1002             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1003                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1004
1005         /* Entry 9 is for HDMI: */
1006         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1007                    ddi_translations[level].trans1 | iboost_bit);
1008         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1009                    ddi_translations[level].trans2);
1010 }
1011
1012 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1013                                     enum port port)
1014 {
1015         i915_reg_t reg = DDI_BUF_CTL(port);
1016         int i;
1017
1018         for (i = 0; i < 16; i++) {
1019                 udelay(1);
1020                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1021                         return;
1022         }
1023         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1024 }
1025
1026 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1027 {
1028         switch (pll->info->id) {
1029         case DPLL_ID_WRPLL1:
1030                 return PORT_CLK_SEL_WRPLL1;
1031         case DPLL_ID_WRPLL2:
1032                 return PORT_CLK_SEL_WRPLL2;
1033         case DPLL_ID_SPLL:
1034                 return PORT_CLK_SEL_SPLL;
1035         case DPLL_ID_LCPLL_810:
1036                 return PORT_CLK_SEL_LCPLL_810;
1037         case DPLL_ID_LCPLL_1350:
1038                 return PORT_CLK_SEL_LCPLL_1350;
1039         case DPLL_ID_LCPLL_2700:
1040                 return PORT_CLK_SEL_LCPLL_2700;
1041         default:
1042                 MISSING_CASE(pll->info->id);
1043                 return PORT_CLK_SEL_NONE;
1044         }
1045 }
1046
1047 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1048                                   const struct intel_crtc_state *crtc_state)
1049 {
1050         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1051         int clock = crtc_state->port_clock;
1052         const enum intel_dpll_id id = pll->info->id;
1053
1054         switch (id) {
1055         default:
1056                 /*
1057                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1058                  * here, so do warn if this get passed in
1059                  */
1060                 MISSING_CASE(id);
1061                 return DDI_CLK_SEL_NONE;
1062         case DPLL_ID_ICL_TBTPLL:
1063                 switch (clock) {
1064                 case 162000:
1065                         return DDI_CLK_SEL_TBT_162;
1066                 case 270000:
1067                         return DDI_CLK_SEL_TBT_270;
1068                 case 540000:
1069                         return DDI_CLK_SEL_TBT_540;
1070                 case 810000:
1071                         return DDI_CLK_SEL_TBT_810;
1072                 default:
1073                         MISSING_CASE(clock);
1074                         return DDI_CLK_SEL_NONE;
1075                 }
1076         case DPLL_ID_ICL_MGPLL1:
1077         case DPLL_ID_ICL_MGPLL2:
1078         case DPLL_ID_ICL_MGPLL3:
1079         case DPLL_ID_ICL_MGPLL4:
1080         case DPLL_ID_TGL_MGPLL5:
1081         case DPLL_ID_TGL_MGPLL6:
1082                 return DDI_CLK_SEL_MG;
1083         }
1084 }
1085
1086 /* Starting with Haswell, different DDI ports can work in FDI mode for
1087  * connection to the PCH-located connectors. For this, it is necessary to train
1088  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1089  *
1090  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1091  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1092  * DDI A (which is used for eDP)
1093  */
1094
1095 void hsw_fdi_link_train(struct intel_crtc *crtc,
1096                         const struct intel_crtc_state *crtc_state)
1097 {
1098         struct drm_device *dev = crtc->base.dev;
1099         struct drm_i915_private *dev_priv = to_i915(dev);
1100         struct intel_encoder *encoder;
1101         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1102
1103         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1104                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1105                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1106         }
1107
1108         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1109          * mode set "sequence for CRT port" document:
1110          * - TP1 to TP2 time with the default value
1111          * - FDI delay to 90h
1112          *
1113          * WaFDIAutoLinkSetTimingOverrride:hsw
1114          */
1115         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1116                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1117                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1118
1119         /* Enable the PCH Receiver FDI PLL */
1120         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1121                      FDI_RX_PLL_ENABLE |
1122                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1123         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1124         POSTING_READ(FDI_RX_CTL(PIPE_A));
1125         udelay(220);
1126
1127         /* Switch from Rawclk to PCDclk */
1128         rx_ctl_val |= FDI_PCDCLK;
1129         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1130
1131         /* Configure Port Clock Select */
1132         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1133         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1134         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1135
1136         /* Start the training iterating through available voltages and emphasis,
1137          * testing each value twice. */
1138         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1139                 /* Configure DP_TP_CTL with auto-training */
1140                 I915_WRITE(DP_TP_CTL(PORT_E),
1141                                         DP_TP_CTL_FDI_AUTOTRAIN |
1142                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1143                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1144                                         DP_TP_CTL_ENABLE);
1145
1146                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1147                  * DDI E does not support port reversal, the functionality is
1148                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1149                  * port reversal bit */
1150                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1151                            DDI_BUF_CTL_ENABLE |
1152                            ((crtc_state->fdi_lanes - 1) << 1) |
1153                            DDI_BUF_TRANS_SELECT(i / 2));
1154                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1155
1156                 udelay(600);
1157
1158                 /* Program PCH FDI Receiver TU */
1159                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1160
1161                 /* Enable PCH FDI Receiver with auto-training */
1162                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1163                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1164                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1165
1166                 /* Wait for FDI receiver lane calibration */
1167                 udelay(30);
1168
1169                 /* Unset FDI_RX_MISC pwrdn lanes */
1170                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1171                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1172                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1173                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1174
1175                 /* Wait for FDI auto training time */
1176                 udelay(5);
1177
1178                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1179                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1180                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1181                         break;
1182                 }
1183
1184                 /*
1185                  * Leave things enabled even if we failed to train FDI.
1186                  * Results in less fireworks from the state checker.
1187                  */
1188                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1189                         DRM_ERROR("FDI link training failed!\n");
1190                         break;
1191                 }
1192
1193                 rx_ctl_val &= ~FDI_RX_ENABLE;
1194                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1195                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1196
1197                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1198                 temp &= ~DDI_BUF_CTL_ENABLE;
1199                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1200                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1201
1202                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1203                 temp = I915_READ(DP_TP_CTL(PORT_E));
1204                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1205                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1206                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1207                 POSTING_READ(DP_TP_CTL(PORT_E));
1208
1209                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1210
1211                 /* Reset FDI_RX_MISC pwrdn lanes */
1212                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1213                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1214                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1215                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1216                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1217         }
1218
1219         /* Enable normal pixel sending for FDI */
1220         I915_WRITE(DP_TP_CTL(PORT_E),
1221                    DP_TP_CTL_FDI_AUTOTRAIN |
1222                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1223                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1224                    DP_TP_CTL_ENABLE);
1225 }
1226
1227 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1228 {
1229         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1230         struct intel_digital_port *intel_dig_port =
1231                 enc_to_dig_port(&encoder->base);
1232
1233         intel_dp->DP = intel_dig_port->saved_port_bits |
1234                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1235         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1236 }
1237
1238 static struct intel_encoder *
1239 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1240 {
1241         struct drm_device *dev = crtc->base.dev;
1242         struct intel_encoder *encoder, *ret = NULL;
1243         int num_encoders = 0;
1244
1245         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1246                 ret = encoder;
1247                 num_encoders++;
1248         }
1249
1250         if (num_encoders != 1)
1251                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1252                      pipe_name(crtc->pipe));
1253
1254         BUG_ON(ret == NULL);
1255         return ret;
1256 }
1257
1258 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1259                                    i915_reg_t reg)
1260 {
1261         int refclk;
1262         int n, p, r;
1263         u32 wrpll;
1264
1265         wrpll = I915_READ(reg);
1266         switch (wrpll & WRPLL_REF_MASK) {
1267         case WRPLL_REF_SPECIAL_HSW:
1268                 /*
1269                  * muxed-SSC for BDW.
1270                  * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1271                  * for the non-SSC reference frequency.
1272                  */
1273                 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1274                         if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1275                                 refclk = 24;
1276                         else
1277                                 refclk = 135;
1278                         break;
1279                 }
1280                 /* fall through */
1281         case WRPLL_REF_PCH_SSC:
1282                 /*
1283                  * We could calculate spread here, but our checking
1284                  * code only cares about 5% accuracy, and spread is a max of
1285                  * 0.5% downspread.
1286                  */
1287                 refclk = 135;
1288                 break;
1289         case WRPLL_REF_LCPLL:
1290                 refclk = 2700;
1291                 break;
1292         default:
1293                 MISSING_CASE(wrpll);
1294                 return 0;
1295         }
1296
1297         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1298         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1299         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1300
1301         /* Convert to KHz, p & r have a fixed point portion */
1302         return (refclk * n * 100) / (p * r);
1303 }
1304
1305 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1306 {
1307         u32 p0, p1, p2, dco_freq;
1308
1309         p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1310         p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1311
1312         if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1313                 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1314         else
1315                 p1 = 1;
1316
1317
1318         switch (p0) {
1319         case DPLL_CFGCR2_PDIV_1:
1320                 p0 = 1;
1321                 break;
1322         case DPLL_CFGCR2_PDIV_2:
1323                 p0 = 2;
1324                 break;
1325         case DPLL_CFGCR2_PDIV_3:
1326                 p0 = 3;
1327                 break;
1328         case DPLL_CFGCR2_PDIV_7:
1329                 p0 = 7;
1330                 break;
1331         }
1332
1333         switch (p2) {
1334         case DPLL_CFGCR2_KDIV_5:
1335                 p2 = 5;
1336                 break;
1337         case DPLL_CFGCR2_KDIV_2:
1338                 p2 = 2;
1339                 break;
1340         case DPLL_CFGCR2_KDIV_3:
1341                 p2 = 3;
1342                 break;
1343         case DPLL_CFGCR2_KDIV_1:
1344                 p2 = 1;
1345                 break;
1346         }
1347
1348         dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1349                 * 24 * 1000;
1350
1351         dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1352                      * 24 * 1000) / 0x8000;
1353
1354         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1355                 return 0;
1356
1357         return dco_freq / (p0 * p1 * p2 * 5);
1358 }
1359
1360 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1361                         struct intel_dpll_hw_state *pll_state)
1362 {
1363         u32 p0, p1, p2, dco_freq, ref_clock;
1364
1365         p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1366         p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1367
1368         if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1369                 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1370                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1371         else
1372                 p1 = 1;
1373
1374
1375         switch (p0) {
1376         case DPLL_CFGCR1_PDIV_2:
1377                 p0 = 2;
1378                 break;
1379         case DPLL_CFGCR1_PDIV_3:
1380                 p0 = 3;
1381                 break;
1382         case DPLL_CFGCR1_PDIV_5:
1383                 p0 = 5;
1384                 break;
1385         case DPLL_CFGCR1_PDIV_7:
1386                 p0 = 7;
1387                 break;
1388         }
1389
1390         switch (p2) {
1391         case DPLL_CFGCR1_KDIV_1:
1392                 p2 = 1;
1393                 break;
1394         case DPLL_CFGCR1_KDIV_2:
1395                 p2 = 2;
1396                 break;
1397         case DPLL_CFGCR1_KDIV_3:
1398                 p2 = 3;
1399                 break;
1400         }
1401
1402         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1403
1404         dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1405                 * ref_clock;
1406
1407         dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1408                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1409
1410         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1411                 return 0;
1412
1413         return dco_freq / (p0 * p1 * p2 * 5);
1414 }
1415
1416 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1417                                  enum port port)
1418 {
1419         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1420
1421         switch (val) {
1422         case DDI_CLK_SEL_NONE:
1423                 return 0;
1424         case DDI_CLK_SEL_TBT_162:
1425                 return 162000;
1426         case DDI_CLK_SEL_TBT_270:
1427                 return 270000;
1428         case DDI_CLK_SEL_TBT_540:
1429                 return 540000;
1430         case DDI_CLK_SEL_TBT_810:
1431                 return 810000;
1432         default:
1433                 MISSING_CASE(val);
1434                 return 0;
1435         }
1436 }
1437
1438 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1439                                 const struct intel_dpll_hw_state *pll_state)
1440 {
1441         u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1442         u64 tmp;
1443
1444         ref_clock = dev_priv->cdclk.hw.ref;
1445
1446         if (INTEL_GEN(dev_priv) >= 12) {
1447                 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
1448                 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
1449                 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
1450
1451                 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
1452                         m2_frac = pll_state->mg_pll_bias &
1453                                   DKL_PLL_BIAS_FBDIV_FRAC_MASK;
1454                         m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
1455                 } else {
1456                         m2_frac = 0;
1457                 }
1458         } else {
1459                 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1460                 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1461
1462                 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
1463                         m2_frac = pll_state->mg_pll_div0 &
1464                                   MG_PLL_DIV0_FBDIV_FRAC_MASK;
1465                         m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
1466                 } else {
1467                         m2_frac = 0;
1468                 }
1469         }
1470
1471         switch (pll_state->mg_clktop2_hsclkctl &
1472                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1473         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1474                 div1 = 2;
1475                 break;
1476         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1477                 div1 = 3;
1478                 break;
1479         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1480                 div1 = 5;
1481                 break;
1482         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1483                 div1 = 7;
1484                 break;
1485         default:
1486                 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1487                 return 0;
1488         }
1489
1490         div2 = (pll_state->mg_clktop2_hsclkctl &
1491                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1492                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1493
1494         /* div2 value of 0 is same as 1 means no div */
1495         if (div2 == 0)
1496                 div2 = 1;
1497
1498         /*
1499          * Adjust the original formula to delay the division by 2^22 in order to
1500          * minimize possible rounding errors.
1501          */
1502         tmp = (u64)m1 * m2_int * ref_clock +
1503               (((u64)m1 * m2_frac * ref_clock) >> 22);
1504         tmp = div_u64(tmp, 5 * div1 * div2);
1505
1506         return tmp;
1507 }
1508
1509 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1510 {
1511         int dotclock;
1512
1513         if (pipe_config->has_pch_encoder)
1514                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1515                                                     &pipe_config->fdi_m_n);
1516         else if (intel_crtc_has_dp_encoder(pipe_config))
1517                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1518                                                     &pipe_config->dp_m_n);
1519         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1520                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1521         else
1522                 dotclock = pipe_config->port_clock;
1523
1524         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1525             !intel_crtc_has_dp_encoder(pipe_config))
1526                 dotclock *= 2;
1527
1528         if (pipe_config->pixel_multiplier)
1529                 dotclock /= pipe_config->pixel_multiplier;
1530
1531         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1532 }
1533
1534 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1535                               struct intel_crtc_state *pipe_config)
1536 {
1537         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1538         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1539         enum port port = encoder->port;
1540         enum phy phy = intel_port_to_phy(dev_priv, port);
1541         int link_clock;
1542
1543         if (intel_phy_is_combo(dev_priv, phy)) {
1544                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1545         } else {
1546                 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1547                                                 pipe_config->shared_dpll);
1548
1549                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1550                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1551                 else
1552                         link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1553         }
1554
1555         pipe_config->port_clock = link_clock;
1556
1557         ddi_dotclock_get(pipe_config);
1558 }
1559
1560 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1561                               struct intel_crtc_state *pipe_config)
1562 {
1563         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1564         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1565         int link_clock;
1566
1567         if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1568                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1569         } else {
1570                 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1571
1572                 switch (link_clock) {
1573                 case DPLL_CFGCR0_LINK_RATE_810:
1574                         link_clock = 81000;
1575                         break;
1576                 case DPLL_CFGCR0_LINK_RATE_1080:
1577                         link_clock = 108000;
1578                         break;
1579                 case DPLL_CFGCR0_LINK_RATE_1350:
1580                         link_clock = 135000;
1581                         break;
1582                 case DPLL_CFGCR0_LINK_RATE_1620:
1583                         link_clock = 162000;
1584                         break;
1585                 case DPLL_CFGCR0_LINK_RATE_2160:
1586                         link_clock = 216000;
1587                         break;
1588                 case DPLL_CFGCR0_LINK_RATE_2700:
1589                         link_clock = 270000;
1590                         break;
1591                 case DPLL_CFGCR0_LINK_RATE_3240:
1592                         link_clock = 324000;
1593                         break;
1594                 case DPLL_CFGCR0_LINK_RATE_4050:
1595                         link_clock = 405000;
1596                         break;
1597                 default:
1598                         WARN(1, "Unsupported link rate\n");
1599                         break;
1600                 }
1601                 link_clock *= 2;
1602         }
1603
1604         pipe_config->port_clock = link_clock;
1605
1606         ddi_dotclock_get(pipe_config);
1607 }
1608
1609 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1610                               struct intel_crtc_state *pipe_config)
1611 {
1612         struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1613         int link_clock;
1614
1615         /*
1616          * ctrl1 register is already shifted for each pll, just use 0 to get
1617          * the internal shift for each field
1618          */
1619         if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1620                 link_clock = skl_calc_wrpll_link(pll_state);
1621         } else {
1622                 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1623                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1624
1625                 switch (link_clock) {
1626                 case DPLL_CTRL1_LINK_RATE_810:
1627                         link_clock = 81000;
1628                         break;
1629                 case DPLL_CTRL1_LINK_RATE_1080:
1630                         link_clock = 108000;
1631                         break;
1632                 case DPLL_CTRL1_LINK_RATE_1350:
1633                         link_clock = 135000;
1634                         break;
1635                 case DPLL_CTRL1_LINK_RATE_1620:
1636                         link_clock = 162000;
1637                         break;
1638                 case DPLL_CTRL1_LINK_RATE_2160:
1639                         link_clock = 216000;
1640                         break;
1641                 case DPLL_CTRL1_LINK_RATE_2700:
1642                         link_clock = 270000;
1643                         break;
1644                 default:
1645                         WARN(1, "Unsupported link rate\n");
1646                         break;
1647                 }
1648                 link_clock *= 2;
1649         }
1650
1651         pipe_config->port_clock = link_clock;
1652
1653         ddi_dotclock_get(pipe_config);
1654 }
1655
1656 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1657                               struct intel_crtc_state *pipe_config)
1658 {
1659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1660         int link_clock = 0;
1661         u32 val, pll;
1662
1663         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1664         switch (val & PORT_CLK_SEL_MASK) {
1665         case PORT_CLK_SEL_LCPLL_810:
1666                 link_clock = 81000;
1667                 break;
1668         case PORT_CLK_SEL_LCPLL_1350:
1669                 link_clock = 135000;
1670                 break;
1671         case PORT_CLK_SEL_LCPLL_2700:
1672                 link_clock = 270000;
1673                 break;
1674         case PORT_CLK_SEL_WRPLL1:
1675                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1676                 break;
1677         case PORT_CLK_SEL_WRPLL2:
1678                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1679                 break;
1680         case PORT_CLK_SEL_SPLL:
1681                 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1682                 if (pll == SPLL_FREQ_810MHz)
1683                         link_clock = 81000;
1684                 else if (pll == SPLL_FREQ_1350MHz)
1685                         link_clock = 135000;
1686                 else if (pll == SPLL_FREQ_2700MHz)
1687                         link_clock = 270000;
1688                 else {
1689                         WARN(1, "bad spll freq\n");
1690                         return;
1691                 }
1692                 break;
1693         default:
1694                 WARN(1, "bad port clock sel\n");
1695                 return;
1696         }
1697
1698         pipe_config->port_clock = link_clock * 2;
1699
1700         ddi_dotclock_get(pipe_config);
1701 }
1702
1703 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1704 {
1705         struct dpll clock;
1706
1707         clock.m1 = 2;
1708         clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1709         if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1710                 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1711         clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1712         clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1713         clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1714
1715         return chv_calc_dpll_params(100000, &clock);
1716 }
1717
1718 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1719                               struct intel_crtc_state *pipe_config)
1720 {
1721         pipe_config->port_clock =
1722                 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1723
1724         ddi_dotclock_get(pipe_config);
1725 }
1726
1727 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1728                                 struct intel_crtc_state *pipe_config)
1729 {
1730         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1731
1732         if (INTEL_GEN(dev_priv) >= 11)
1733                 icl_ddi_clock_get(encoder, pipe_config);
1734         else if (IS_CANNONLAKE(dev_priv))
1735                 cnl_ddi_clock_get(encoder, pipe_config);
1736         else if (IS_GEN9_LP(dev_priv))
1737                 bxt_ddi_clock_get(encoder, pipe_config);
1738         else if (IS_GEN9_BC(dev_priv))
1739                 skl_ddi_clock_get(encoder, pipe_config);
1740         else if (INTEL_GEN(dev_priv) <= 8)
1741                 hsw_ddi_clock_get(encoder, pipe_config);
1742 }
1743
1744 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1745                           const struct drm_connector_state *conn_state)
1746 {
1747         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1748         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1749         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1750         u32 temp;
1751
1752         if (!intel_crtc_has_dp_encoder(crtc_state))
1753                 return;
1754
1755         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1756
1757         temp = DP_MSA_MISC_SYNC_CLOCK;
1758
1759         switch (crtc_state->pipe_bpp) {
1760         case 18:
1761                 temp |= DP_MSA_MISC_6_BPC;
1762                 break;
1763         case 24:
1764                 temp |= DP_MSA_MISC_8_BPC;
1765                 break;
1766         case 30:
1767                 temp |= DP_MSA_MISC_10_BPC;
1768                 break;
1769         case 36:
1770                 temp |= DP_MSA_MISC_12_BPC;
1771                 break;
1772         default:
1773                 MISSING_CASE(crtc_state->pipe_bpp);
1774                 break;
1775         }
1776
1777         /* nonsense combination */
1778         WARN_ON(crtc_state->limited_color_range &&
1779                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1780
1781         if (crtc_state->limited_color_range)
1782                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1783
1784         /*
1785          * As per DP 1.2 spec section 2.3.4.3 while sending
1786          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1787          * colorspace information.
1788          */
1789         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1790                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1791
1792         /*
1793          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1794          * of Color Encoding Format and Content Color Gamut] while sending
1795          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1796          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1797          *
1798          * FIXME MST doesn't pass in the conn_state
1799          */
1800         if (conn_state && intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1801                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1802
1803         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1804 }
1805
1806 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1807                                     bool state)
1808 {
1809         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1810         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1811         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1812         u32 temp;
1813
1814         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1815         if (state == true)
1816                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1817         else
1818                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1819         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1820 }
1821
1822 /*
1823  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1824  *
1825  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1826  * intel_ddi_config_transcoder_func().
1827  */
1828 static u32
1829 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
1830 {
1831         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1832         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1833         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1834         enum pipe pipe = crtc->pipe;
1835         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1836         enum port port = encoder->port;
1837         u32 temp;
1838
1839         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1840         temp = TRANS_DDI_FUNC_ENABLE;
1841         if (INTEL_GEN(dev_priv) >= 12)
1842                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1843         else
1844                 temp |= TRANS_DDI_SELECT_PORT(port);
1845
1846         switch (crtc_state->pipe_bpp) {
1847         case 18:
1848                 temp |= TRANS_DDI_BPC_6;
1849                 break;
1850         case 24:
1851                 temp |= TRANS_DDI_BPC_8;
1852                 break;
1853         case 30:
1854                 temp |= TRANS_DDI_BPC_10;
1855                 break;
1856         case 36:
1857                 temp |= TRANS_DDI_BPC_12;
1858                 break;
1859         default:
1860                 BUG();
1861         }
1862
1863         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1864                 temp |= TRANS_DDI_PVSYNC;
1865         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1866                 temp |= TRANS_DDI_PHSYNC;
1867
1868         if (cpu_transcoder == TRANSCODER_EDP) {
1869                 switch (pipe) {
1870                 case PIPE_A:
1871                         /* On Haswell, can only use the always-on power well for
1872                          * eDP when not using the panel fitter, and when not
1873                          * using motion blur mitigation (which we don't
1874                          * support). */
1875                         if (crtc_state->pch_pfit.force_thru)
1876                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1877                         else
1878                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1879                         break;
1880                 case PIPE_B:
1881                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1882                         break;
1883                 case PIPE_C:
1884                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1885                         break;
1886                 default:
1887                         BUG();
1888                         break;
1889                 }
1890         }
1891
1892         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1893                 if (crtc_state->has_hdmi_sink)
1894                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1895                 else
1896                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1897
1898                 if (crtc_state->hdmi_scrambling)
1899                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1900                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1901                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1902         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1903                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1904                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1905         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1906                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1907                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1908
1909                 if (INTEL_GEN(dev_priv) >= 12)
1910                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
1911         } else {
1912                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1913                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1914         }
1915
1916         return temp;
1917 }
1918
1919 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1920 {
1921         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1923         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1924         u32 temp;
1925
1926         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1927         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1928 }
1929
1930 /*
1931  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1932  * bit.
1933  */
1934 static void
1935 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1936 {
1937         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1938         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1939         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1940         u32 temp;
1941
1942         temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1943         temp &= ~TRANS_DDI_FUNC_ENABLE;
1944         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1945 }
1946
1947 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1948 {
1949         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1952         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1953         u32 val = I915_READ(reg);
1954
1955         if (INTEL_GEN(dev_priv) >= 12) {
1956                 val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
1957                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1958         } else {
1959                 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
1960                          TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1961         }
1962         I915_WRITE(reg, val);
1963
1964         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1965             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1966                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1967                 /* Quirk time at 100ms for reliable operation */
1968                 msleep(100);
1969         }
1970 }
1971
1972 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1973                                      bool enable)
1974 {
1975         struct drm_device *dev = intel_encoder->base.dev;
1976         struct drm_i915_private *dev_priv = to_i915(dev);
1977         intel_wakeref_t wakeref;
1978         enum pipe pipe = 0;
1979         int ret = 0;
1980         u32 tmp;
1981
1982         wakeref = intel_display_power_get_if_enabled(dev_priv,
1983                                                      intel_encoder->power_domain);
1984         if (WARN_ON(!wakeref))
1985                 return -ENXIO;
1986
1987         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1988                 ret = -EIO;
1989                 goto out;
1990         }
1991
1992         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1993         if (enable)
1994                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1995         else
1996                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1997         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1998 out:
1999         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2000         return ret;
2001 }
2002
2003 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
2004 {
2005         struct drm_device *dev = intel_connector->base.dev;
2006         struct drm_i915_private *dev_priv = to_i915(dev);
2007         struct intel_encoder *encoder = intel_connector->encoder;
2008         int type = intel_connector->base.connector_type;
2009         enum port port = encoder->port;
2010         enum transcoder cpu_transcoder;
2011         intel_wakeref_t wakeref;
2012         enum pipe pipe = 0;
2013         u32 tmp;
2014         bool ret;
2015
2016         wakeref = intel_display_power_get_if_enabled(dev_priv,
2017                                                      encoder->power_domain);
2018         if (!wakeref)
2019                 return false;
2020
2021         if (!encoder->get_hw_state(encoder, &pipe)) {
2022                 ret = false;
2023                 goto out;
2024         }
2025
2026         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
2027                 cpu_transcoder = TRANSCODER_EDP;
2028         else
2029                 cpu_transcoder = (enum transcoder) pipe;
2030
2031         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2032
2033         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
2034         case TRANS_DDI_MODE_SELECT_HDMI:
2035         case TRANS_DDI_MODE_SELECT_DVI:
2036                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
2037                 break;
2038
2039         case TRANS_DDI_MODE_SELECT_DP_SST:
2040                 ret = type == DRM_MODE_CONNECTOR_eDP ||
2041                       type == DRM_MODE_CONNECTOR_DisplayPort;
2042                 break;
2043
2044         case TRANS_DDI_MODE_SELECT_DP_MST:
2045                 /* if the transcoder is in MST state then
2046                  * connector isn't connected */
2047                 ret = false;
2048                 break;
2049
2050         case TRANS_DDI_MODE_SELECT_FDI:
2051                 ret = type == DRM_MODE_CONNECTOR_VGA;
2052                 break;
2053
2054         default:
2055                 ret = false;
2056                 break;
2057         }
2058
2059 out:
2060         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2061
2062         return ret;
2063 }
2064
2065 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2066                                         u8 *pipe_mask, bool *is_dp_mst)
2067 {
2068         struct drm_device *dev = encoder->base.dev;
2069         struct drm_i915_private *dev_priv = to_i915(dev);
2070         enum port port = encoder->port;
2071         intel_wakeref_t wakeref;
2072         enum pipe p;
2073         u32 tmp;
2074         u8 mst_pipe_mask;
2075
2076         *pipe_mask = 0;
2077         *is_dp_mst = false;
2078
2079         wakeref = intel_display_power_get_if_enabled(dev_priv,
2080                                                      encoder->power_domain);
2081         if (!wakeref)
2082                 return;
2083
2084         tmp = I915_READ(DDI_BUF_CTL(port));
2085         if (!(tmp & DDI_BUF_CTL_ENABLE))
2086                 goto out;
2087
2088         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
2089                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2090
2091                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2092                 default:
2093                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2094                         /* fallthrough */
2095                 case TRANS_DDI_EDP_INPUT_A_ON:
2096                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2097                         *pipe_mask = BIT(PIPE_A);
2098                         break;
2099                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2100                         *pipe_mask = BIT(PIPE_B);
2101                         break;
2102                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2103                         *pipe_mask = BIT(PIPE_C);
2104                         break;
2105                 }
2106
2107                 goto out;
2108         }
2109
2110         mst_pipe_mask = 0;
2111         for_each_pipe(dev_priv, p) {
2112                 enum transcoder cpu_transcoder = (enum transcoder)p;
2113                 unsigned int port_mask, ddi_select;
2114                 intel_wakeref_t trans_wakeref;
2115
2116                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2117                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2118                 if (!trans_wakeref)
2119                         continue;
2120
2121                 if (INTEL_GEN(dev_priv) >= 12) {
2122                         port_mask = TGL_TRANS_DDI_PORT_MASK;
2123                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2124                 } else {
2125                         port_mask = TRANS_DDI_PORT_MASK;
2126                         ddi_select = TRANS_DDI_SELECT_PORT(port);
2127                 }
2128
2129                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2130                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2131                                         trans_wakeref);
2132
2133                 if ((tmp & port_mask) != ddi_select)
2134                         continue;
2135
2136                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2137                     TRANS_DDI_MODE_SELECT_DP_MST)
2138                         mst_pipe_mask |= BIT(p);
2139
2140                 *pipe_mask |= BIT(p);
2141         }
2142
2143         if (!*pipe_mask)
2144                 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n",
2145                               encoder->base.base.id, encoder->base.name);
2146
2147         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2148                 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2149                               encoder->base.base.id, encoder->base.name,
2150                               *pipe_mask);
2151                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2152         }
2153
2154         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2155                 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2156                               encoder->base.base.id, encoder->base.name,
2157                               *pipe_mask, mst_pipe_mask);
2158         else
2159                 *is_dp_mst = mst_pipe_mask;
2160
2161 out:
2162         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2163                 tmp = I915_READ(BXT_PHY_CTL(port));
2164                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2165                             BXT_PHY_LANE_POWERDOWN_ACK |
2166                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2167                         DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? "
2168                                   "(PHY_CTL %08x)\n", encoder->base.base.id,
2169                                   encoder->base.name, tmp);
2170         }
2171
2172         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2173 }
2174
2175 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2176                             enum pipe *pipe)
2177 {
2178         u8 pipe_mask;
2179         bool is_mst;
2180
2181         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2182
2183         if (is_mst || !pipe_mask)
2184                 return false;
2185
2186         *pipe = ffs(pipe_mask) - 1;
2187
2188         return true;
2189 }
2190
2191 static inline enum intel_display_power_domain
2192 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2193 {
2194         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2195          * DC states enabled at the same time, while for driver initiated AUX
2196          * transfers we need the same AUX IOs to be powered but with DC states
2197          * disabled. Accordingly use the AUX power domain here which leaves DC
2198          * states enabled.
2199          * However, for non-A AUX ports the corresponding non-EDP transcoders
2200          * would have already enabled power well 2 and DC_OFF. This means we can
2201          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2202          * specific AUX_IO reference without powering up any extra wells.
2203          * Note that PSR is enabled only on Port A even though this function
2204          * returns the correct domain for other ports too.
2205          */
2206         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2207                                               intel_aux_power_domain(dig_port);
2208 }
2209
2210 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2211                                         struct intel_crtc_state *crtc_state)
2212 {
2213         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2214         struct intel_digital_port *dig_port;
2215         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2216
2217         /*
2218          * TODO: Add support for MST encoders. Atm, the following should never
2219          * happen since fake-MST encoders don't set their get_power_domains()
2220          * hook.
2221          */
2222         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2223                 return;
2224
2225         dig_port = enc_to_dig_port(&encoder->base);
2226         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2227
2228         /*
2229          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2230          * ports.
2231          */
2232         if (intel_crtc_has_dp_encoder(crtc_state) ||
2233             intel_phy_is_tc(dev_priv, phy))
2234                 intel_display_power_get(dev_priv,
2235                                         intel_ddi_main_link_aux_domain(dig_port));
2236
2237         /*
2238          * VDSC power is needed when DSC is enabled
2239          */
2240         if (crtc_state->dsc.compression_enable)
2241                 intel_display_power_get(dev_priv,
2242                                         intel_dsc_power_domain(crtc_state));
2243 }
2244
2245 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2246 {
2247         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2248         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2249         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2250         enum port port = encoder->port;
2251         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2252
2253         if (cpu_transcoder != TRANSCODER_EDP) {
2254                 if (INTEL_GEN(dev_priv) >= 12)
2255                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2256                                    TGL_TRANS_CLK_SEL_PORT(port));
2257                 else
2258                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2259                                    TRANS_CLK_SEL_PORT(port));
2260         }
2261 }
2262
2263 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2264 {
2265         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2266         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2267
2268         if (cpu_transcoder != TRANSCODER_EDP) {
2269                 if (INTEL_GEN(dev_priv) >= 12)
2270                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2271                                    TGL_TRANS_CLK_SEL_DISABLED);
2272                 else
2273                         I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2274                                    TRANS_CLK_SEL_DISABLED);
2275         }
2276 }
2277
2278 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2279                                 enum port port, u8 iboost)
2280 {
2281         u32 tmp;
2282
2283         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2284         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2285         if (iboost)
2286                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2287         else
2288                 tmp |= BALANCE_LEG_DISABLE(port);
2289         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2290 }
2291
2292 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2293                                int level, enum intel_output_type type)
2294 {
2295         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2296         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2297         enum port port = encoder->port;
2298         u8 iboost;
2299
2300         if (type == INTEL_OUTPUT_HDMI)
2301                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2302         else
2303                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2304
2305         if (iboost == 0) {
2306                 const struct ddi_buf_trans *ddi_translations;
2307                 int n_entries;
2308
2309                 if (type == INTEL_OUTPUT_HDMI)
2310                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2311                 else if (type == INTEL_OUTPUT_EDP)
2312                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2313                 else
2314                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2315
2316                 if (WARN_ON_ONCE(!ddi_translations))
2317                         return;
2318                 if (WARN_ON_ONCE(level >= n_entries))
2319                         level = n_entries - 1;
2320
2321                 iboost = ddi_translations[level].i_boost;
2322         }
2323
2324         /* Make sure that the requested I_boost is valid */
2325         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2326                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2327                 return;
2328         }
2329
2330         _skl_ddi_set_iboost(dev_priv, port, iboost);
2331
2332         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2333                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2334 }
2335
2336 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2337                                     int level, enum intel_output_type type)
2338 {
2339         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2340         const struct bxt_ddi_buf_trans *ddi_translations;
2341         enum port port = encoder->port;
2342         int n_entries;
2343
2344         if (type == INTEL_OUTPUT_HDMI)
2345                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2346         else if (type == INTEL_OUTPUT_EDP)
2347                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2348         else
2349                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2350
2351         if (WARN_ON_ONCE(!ddi_translations))
2352                 return;
2353         if (WARN_ON_ONCE(level >= n_entries))
2354                 level = n_entries - 1;
2355
2356         bxt_ddi_phy_set_signal_level(dev_priv, port,
2357                                      ddi_translations[level].margin,
2358                                      ddi_translations[level].scale,
2359                                      ddi_translations[level].enable,
2360                                      ddi_translations[level].deemphasis);
2361 }
2362
2363 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2364 {
2365         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2366         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2367         enum port port = encoder->port;
2368         enum phy phy = intel_port_to_phy(dev_priv, port);
2369         int n_entries;
2370
2371         if (INTEL_GEN(dev_priv) >= 12) {
2372                 if (intel_phy_is_combo(dev_priv, phy))
2373                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2374                                                 intel_dp->link_rate, &n_entries);
2375                 else
2376                         n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
2377         } else if (INTEL_GEN(dev_priv) == 11) {
2378                 if (intel_phy_is_combo(dev_priv, phy))
2379                         icl_get_combo_buf_trans(dev_priv, encoder->type,
2380                                                 intel_dp->link_rate, &n_entries);
2381                 else
2382                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2383         } else if (IS_CANNONLAKE(dev_priv)) {
2384                 if (encoder->type == INTEL_OUTPUT_EDP)
2385                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2386                 else
2387                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2388         } else if (IS_GEN9_LP(dev_priv)) {
2389                 if (encoder->type == INTEL_OUTPUT_EDP)
2390                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2391                 else
2392                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2393         } else {
2394                 if (encoder->type == INTEL_OUTPUT_EDP)
2395                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2396                 else
2397                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2398         }
2399
2400         if (WARN_ON(n_entries < 1))
2401                 n_entries = 1;
2402         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2403                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2404
2405         return index_to_dp_signal_levels[n_entries - 1] &
2406                 DP_TRAIN_VOLTAGE_SWING_MASK;
2407 }
2408
2409 /*
2410  * We assume that the full set of pre-emphasis values can be
2411  * used on all DDI platforms. Should that change we need to
2412  * rethink this code.
2413  */
2414 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2415 {
2416         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2417         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2418                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2419         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2420                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2421         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2422                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2423         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2424         default:
2425                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2426         }
2427 }
2428
2429 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2430                                    int level, enum intel_output_type type)
2431 {
2432         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2433         const struct cnl_ddi_buf_trans *ddi_translations;
2434         enum port port = encoder->port;
2435         int n_entries, ln;
2436         u32 val;
2437
2438         if (type == INTEL_OUTPUT_HDMI)
2439                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2440         else if (type == INTEL_OUTPUT_EDP)
2441                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2442         else
2443                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2444
2445         if (WARN_ON_ONCE(!ddi_translations))
2446                 return;
2447         if (WARN_ON_ONCE(level >= n_entries))
2448                 level = n_entries - 1;
2449
2450         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2451         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2452         val &= ~SCALING_MODE_SEL_MASK;
2453         val |= SCALING_MODE_SEL(2);
2454         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2455
2456         /* Program PORT_TX_DW2 */
2457         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2458         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2459                  RCOMP_SCALAR_MASK);
2460         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2461         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2462         /* Rcomp scalar is fixed as 0x98 for every table entry */
2463         val |= RCOMP_SCALAR(0x98);
2464         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2465
2466         /* Program PORT_TX_DW4 */
2467         /* We cannot write to GRP. It would overrite individual loadgen */
2468         for (ln = 0; ln < 4; ln++) {
2469                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2470                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2471                          CURSOR_COEFF_MASK);
2472                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2473                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2474                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2475                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2476         }
2477
2478         /* Program PORT_TX_DW5 */
2479         /* All DW5 values are fixed for every table entry */
2480         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2481         val &= ~RTERM_SELECT_MASK;
2482         val |= RTERM_SELECT(6);
2483         val |= TAP3_DISABLE;
2484         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2485
2486         /* Program PORT_TX_DW7 */
2487         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2488         val &= ~N_SCALAR_MASK;
2489         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2490         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2491 }
2492
2493 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2494                                     int level, enum intel_output_type type)
2495 {
2496         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2497         enum port port = encoder->port;
2498         int width, rate, ln;
2499         u32 val;
2500
2501         if (type == INTEL_OUTPUT_HDMI) {
2502                 width = 4;
2503                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2504         } else {
2505                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2506
2507                 width = intel_dp->lane_count;
2508                 rate = intel_dp->link_rate;
2509         }
2510
2511         /*
2512          * 1. If port type is eDP or DP,
2513          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2514          * else clear to 0b.
2515          */
2516         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2517         if (type != INTEL_OUTPUT_HDMI)
2518                 val |= COMMON_KEEPER_EN;
2519         else
2520                 val &= ~COMMON_KEEPER_EN;
2521         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2522
2523         /* 2. Program loadgen select */
2524         /*
2525          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2526          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2527          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2528          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2529          */
2530         for (ln = 0; ln <= 3; ln++) {
2531                 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2532                 val &= ~LOADGEN_SELECT;
2533
2534                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2535                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2536                         val |= LOADGEN_SELECT;
2537                 }
2538                 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2539         }
2540
2541         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2542         val = I915_READ(CNL_PORT_CL1CM_DW5);
2543         val |= SUS_CLOCK_CONFIG;
2544         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2545
2546         /* 4. Clear training enable to change swing values */
2547         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2548         val &= ~TX_TRAINING_EN;
2549         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2550
2551         /* 5. Program swing and de-emphasis */
2552         cnl_ddi_vswing_program(encoder, level, type);
2553
2554         /* 6. Set training enable to trigger update */
2555         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2556         val |= TX_TRAINING_EN;
2557         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2558 }
2559
2560 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2561                                         u32 level, enum phy phy, int type,
2562                                         int rate)
2563 {
2564         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2565         u32 n_entries, val;
2566         int ln;
2567
2568         ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2569                                                    &n_entries);
2570         if (!ddi_translations)
2571                 return;
2572
2573         if (level >= n_entries) {
2574                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2575                 level = n_entries - 1;
2576         }
2577
2578         /* Set PORT_TX_DW5 */
2579         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2580         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2581                   TAP2_DISABLE | TAP3_DISABLE);
2582         val |= SCALING_MODE_SEL(0x2);
2583         val |= RTERM_SELECT(0x6);
2584         val |= TAP3_DISABLE;
2585         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2586
2587         /* Program PORT_TX_DW2 */
2588         val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2589         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2590                  RCOMP_SCALAR_MASK);
2591         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2592         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2593         /* Program Rcomp scalar for every table entry */
2594         val |= RCOMP_SCALAR(0x98);
2595         I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2596
2597         /* Program PORT_TX_DW4 */
2598         /* We cannot write to GRP. It would overwrite individual loadgen. */
2599         for (ln = 0; ln <= 3; ln++) {
2600                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2601                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2602                          CURSOR_COEFF_MASK);
2603                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2604                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2605                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2606                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2607         }
2608
2609         /* Program PORT_TX_DW7 */
2610         val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2611         val &= ~N_SCALAR_MASK;
2612         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2613         I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2614 }
2615
2616 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2617                                               u32 level,
2618                                               enum intel_output_type type)
2619 {
2620         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2621         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2622         int width = 0;
2623         int rate = 0;
2624         u32 val;
2625         int ln = 0;
2626
2627         if (type == INTEL_OUTPUT_HDMI) {
2628                 width = 4;
2629                 /* Rate is always < than 6GHz for HDMI */
2630         } else {
2631                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2632
2633                 width = intel_dp->lane_count;
2634                 rate = intel_dp->link_rate;
2635         }
2636
2637         /*
2638          * 1. If port type is eDP or DP,
2639          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2640          * else clear to 0b.
2641          */
2642         val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2643         if (type == INTEL_OUTPUT_HDMI)
2644                 val &= ~COMMON_KEEPER_EN;
2645         else
2646                 val |= COMMON_KEEPER_EN;
2647         I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2648
2649         /* 2. Program loadgen select */
2650         /*
2651          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2652          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2653          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2654          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2655          */
2656         for (ln = 0; ln <= 3; ln++) {
2657                 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2658                 val &= ~LOADGEN_SELECT;
2659
2660                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2661                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2662                         val |= LOADGEN_SELECT;
2663                 }
2664                 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2665         }
2666
2667         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2668         val = I915_READ(ICL_PORT_CL_DW5(phy));
2669         val |= SUS_CLOCK_CONFIG;
2670         I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2671
2672         /* 4. Clear training enable to change swing values */
2673         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2674         val &= ~TX_TRAINING_EN;
2675         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2676
2677         /* 5. Program swing and de-emphasis */
2678         icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2679
2680         /* 6. Set training enable to trigger update */
2681         val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2682         val |= TX_TRAINING_EN;
2683         I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2684 }
2685
2686 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2687                                            int link_clock,
2688                                            u32 level)
2689 {
2690         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2691         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2692         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2693         u32 n_entries, val;
2694         int ln;
2695
2696         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2697         ddi_translations = icl_mg_phy_ddi_translations;
2698         /* The table does not have values for level 3 and level 9. */
2699         if (level >= n_entries || level == 3 || level == 9) {
2700                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2701                               level, n_entries - 2);
2702                 level = n_entries - 2;
2703         }
2704
2705         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2706         for (ln = 0; ln < 2; ln++) {
2707                 val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
2708                 val &= ~CRI_USE_FS32;
2709                 I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
2710
2711                 val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
2712                 val &= ~CRI_USE_FS32;
2713                 I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
2714         }
2715
2716         /* Program MG_TX_SWINGCTRL with values from vswing table */
2717         for (ln = 0; ln < 2; ln++) {
2718                 val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
2719                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2720                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2721                         ddi_translations[level].cri_txdeemph_override_17_12);
2722                 I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
2723
2724                 val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
2725                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2726                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2727                         ddi_translations[level].cri_txdeemph_override_17_12);
2728                 I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
2729         }
2730
2731         /* Program MG_TX_DRVCTRL with values from vswing table */
2732         for (ln = 0; ln < 2; ln++) {
2733                 val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
2734                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2735                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2736                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2737                         ddi_translations[level].cri_txdeemph_override_5_0) |
2738                         CRI_TXDEEMPH_OVERRIDE_11_6(
2739                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2740                         CRI_TXDEEMPH_OVERRIDE_EN;
2741                 I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
2742
2743                 val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
2744                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2745                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2746                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2747                         ddi_translations[level].cri_txdeemph_override_5_0) |
2748                         CRI_TXDEEMPH_OVERRIDE_11_6(
2749                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2750                         CRI_TXDEEMPH_OVERRIDE_EN;
2751                 I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
2752
2753                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2754         }
2755
2756         /*
2757          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2758          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2759          * values from table for which TX1 and TX2 enabled.
2760          */
2761         for (ln = 0; ln < 2; ln++) {
2762                 val = I915_READ(MG_CLKHUB(ln, tc_port));
2763                 if (link_clock < 300000)
2764                         val |= CFG_LOW_RATE_LKREN_EN;
2765                 else
2766                         val &= ~CFG_LOW_RATE_LKREN_EN;
2767                 I915_WRITE(MG_CLKHUB(ln, tc_port), val);
2768         }
2769
2770         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2771         for (ln = 0; ln < 2; ln++) {
2772                 val = I915_READ(MG_TX1_DCC(ln, tc_port));
2773                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2774                 if (link_clock <= 500000) {
2775                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2776                 } else {
2777                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2778                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2779                 }
2780                 I915_WRITE(MG_TX1_DCC(ln, tc_port), val);
2781
2782                 val = I915_READ(MG_TX2_DCC(ln, tc_port));
2783                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2784                 if (link_clock <= 500000) {
2785                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2786                 } else {
2787                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2788                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2789                 }
2790                 I915_WRITE(MG_TX2_DCC(ln, tc_port), val);
2791         }
2792
2793         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2794         for (ln = 0; ln < 2; ln++) {
2795                 val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port));
2796                 val |= CRI_CALCINIT;
2797                 I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val);
2798
2799                 val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port));
2800                 val |= CRI_CALCINIT;
2801                 I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val);
2802         }
2803 }
2804
2805 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2806                                     int link_clock,
2807                                     u32 level,
2808                                     enum intel_output_type type)
2809 {
2810         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2811         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2812
2813         if (intel_phy_is_combo(dev_priv, phy))
2814                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2815         else
2816                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2817 }
2818
2819 static void
2820 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2821                                 u32 level)
2822 {
2823         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2824         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2825         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2826         u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2827
2828         n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
2829         ddi_translations = tgl_dkl_phy_ddi_translations;
2830
2831         if (level >= n_entries)
2832                 level = n_entries - 1;
2833
2834         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2835                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2836                       DKL_TX_VSWING_CONTROL_MASK);
2837         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2838         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2839         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2840
2841         for (ln = 0; ln < 2; ln++) {
2842                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
2843
2844                 I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0);
2845
2846                 /* All the registers are RMW */
2847                 val = I915_READ(DKL_TX_DPCNTL0(tc_port));
2848                 val &= ~dpcnt_mask;
2849                 val |= dpcnt_val;
2850                 I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
2851
2852                 val = I915_READ(DKL_TX_DPCNTL1(tc_port));
2853                 val &= ~dpcnt_mask;
2854                 val |= dpcnt_val;
2855                 I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
2856
2857                 val = I915_READ(DKL_TX_DPCNTL2(tc_port));
2858                 val &= ~DKL_TX_DP20BITMODE;
2859                 I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
2860         }
2861 }
2862
2863 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2864                                     int link_clock,
2865                                     u32 level,
2866                                     enum intel_output_type type)
2867 {
2868         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2869         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2870
2871         if (intel_phy_is_combo(dev_priv, phy))
2872                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2873         else
2874                 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
2875 }
2876
2877 static u32 translate_signal_level(int signal_levels)
2878 {
2879         int i;
2880
2881         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2882                 if (index_to_dp_signal_levels[i] == signal_levels)
2883                         return i;
2884         }
2885
2886         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2887              signal_levels);
2888
2889         return 0;
2890 }
2891
2892 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2893 {
2894         u8 train_set = intel_dp->train_set[0];
2895         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2896                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2897
2898         return translate_signal_level(signal_levels);
2899 }
2900
2901 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2902 {
2903         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2904         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2905         struct intel_encoder *encoder = &dport->base;
2906         int level = intel_ddi_dp_level(intel_dp);
2907
2908         if (INTEL_GEN(dev_priv) >= 12)
2909                 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2910                                         level, encoder->type);
2911         else if (INTEL_GEN(dev_priv) >= 11)
2912                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2913                                         level, encoder->type);
2914         else if (IS_CANNONLAKE(dev_priv))
2915                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2916         else
2917                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2918
2919         return 0;
2920 }
2921
2922 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2923 {
2924         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2925         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2926         struct intel_encoder *encoder = &dport->base;
2927         int level = intel_ddi_dp_level(intel_dp);
2928
2929         if (IS_GEN9_BC(dev_priv))
2930                 skl_ddi_set_iboost(encoder, level, encoder->type);
2931
2932         return DDI_BUF_TRANS_SELECT(level);
2933 }
2934
2935 static inline
2936 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2937                               enum phy phy)
2938 {
2939         if (intel_phy_is_combo(dev_priv, phy)) {
2940                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2941         } else if (intel_phy_is_tc(dev_priv, phy)) {
2942                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2943                                                         (enum port)phy);
2944
2945                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2946         }
2947
2948         return 0;
2949 }
2950
2951 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2952                                   const struct intel_crtc_state *crtc_state)
2953 {
2954         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2955         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2956         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2957         u32 val;
2958
2959         mutex_lock(&dev_priv->dpll_lock);
2960
2961         val = I915_READ(ICL_DPCLKA_CFGCR0);
2962         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2963
2964         if (intel_phy_is_combo(dev_priv, phy)) {
2965                 /*
2966                  * Even though this register references DDIs, note that we
2967                  * want to pass the PHY rather than the port (DDI).  For
2968                  * ICL, port=phy in all cases so it doesn't matter, but for
2969                  * EHL the bspec notes the following:
2970                  *
2971                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2972                  *   Clock Select chooses the PLL for both DDIA and DDID and
2973                  *   drives port A in all cases."
2974                  */
2975                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2976                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2977                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2978                 POSTING_READ(ICL_DPCLKA_CFGCR0);
2979         }
2980
2981         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2982         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2983
2984         mutex_unlock(&dev_priv->dpll_lock);
2985 }
2986
2987 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2988 {
2989         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2990         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2991         u32 val;
2992
2993         mutex_lock(&dev_priv->dpll_lock);
2994
2995         val = I915_READ(ICL_DPCLKA_CFGCR0);
2996         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2997         I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2998
2999         mutex_unlock(&dev_priv->dpll_lock);
3000 }
3001
3002 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
3003 {
3004         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3005         u32 val;
3006         enum port port;
3007         u32 port_mask;
3008         bool ddi_clk_needed;
3009
3010         /*
3011          * In case of DP MST, we sanitize the primary encoder only, not the
3012          * virtual ones.
3013          */
3014         if (encoder->type == INTEL_OUTPUT_DP_MST)
3015                 return;
3016
3017         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
3018                 u8 pipe_mask;
3019                 bool is_mst;
3020
3021                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
3022                 /*
3023                  * In the unlikely case that BIOS enables DP in MST mode, just
3024                  * warn since our MST HW readout is incomplete.
3025                  */
3026                 if (WARN_ON(is_mst))
3027                         return;
3028         }
3029
3030         port_mask = BIT(encoder->port);
3031         ddi_clk_needed = encoder->base.crtc;
3032
3033         if (encoder->type == INTEL_OUTPUT_DSI) {
3034                 struct intel_encoder *other_encoder;
3035
3036                 port_mask = intel_dsi_encoder_ports(encoder);
3037                 /*
3038                  * Sanity check that we haven't incorrectly registered another
3039                  * encoder using any of the ports of this DSI encoder.
3040                  */
3041                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3042                         if (other_encoder == encoder)
3043                                 continue;
3044
3045                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
3046                                 return;
3047                 }
3048                 /*
3049                  * For DSI we keep the ddi clocks gated
3050                  * except during enable/disable sequence.
3051                  */
3052                 ddi_clk_needed = false;
3053         }
3054
3055         val = I915_READ(ICL_DPCLKA_CFGCR0);
3056         for_each_port_masked(port, port_mask) {
3057                 enum phy phy = intel_port_to_phy(dev_priv, port);
3058
3059                 bool ddi_clk_ungated = !(val &
3060                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
3061                                                                    phy));
3062
3063                 if (ddi_clk_needed == ddi_clk_ungated)
3064                         continue;
3065
3066                 /*
3067                  * Punt on the case now where clock is gated, but it would
3068                  * be needed by the port. Something else is really broken then.
3069                  */
3070                 if (WARN_ON(ddi_clk_needed))
3071                         continue;
3072
3073                 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
3074                          phy_name(port));
3075                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3076                 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
3077         }
3078 }
3079
3080 static void intel_ddi_clk_select(struct intel_encoder *encoder,
3081                                  const struct intel_crtc_state *crtc_state)
3082 {
3083         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3084         enum port port = encoder->port;
3085         enum phy phy = intel_port_to_phy(dev_priv, port);
3086         u32 val;
3087         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3088
3089         if (WARN_ON(!pll))
3090                 return;
3091
3092         mutex_lock(&dev_priv->dpll_lock);
3093
3094         if (INTEL_GEN(dev_priv) >= 11) {
3095                 if (!intel_phy_is_combo(dev_priv, phy))
3096                         I915_WRITE(DDI_CLK_SEL(port),
3097                                    icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3098                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
3099                         /*
3100                          * MG does not exist but the programming is required
3101                          * to ungate DDIC and DDID
3102                          */
3103                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
3104         } else if (IS_CANNONLAKE(dev_priv)) {
3105                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3106                 val = I915_READ(DPCLKA_CFGCR0);
3107                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3108                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3109                 I915_WRITE(DPCLKA_CFGCR0, val);
3110
3111                 /*
3112                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3113                  * This step and the step before must be done with separate
3114                  * register writes.
3115                  */
3116                 val = I915_READ(DPCLKA_CFGCR0);
3117                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3118                 I915_WRITE(DPCLKA_CFGCR0, val);
3119         } else if (IS_GEN9_BC(dev_priv)) {
3120                 /* DDI -> PLL mapping  */
3121                 val = I915_READ(DPLL_CTRL2);
3122
3123                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3124                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3125                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3126                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3127
3128                 I915_WRITE(DPLL_CTRL2, val);
3129
3130         } else if (INTEL_GEN(dev_priv) < 9) {
3131                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
3132         }
3133
3134         mutex_unlock(&dev_priv->dpll_lock);
3135 }
3136
3137 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3138 {
3139         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3140         enum port port = encoder->port;
3141         enum phy phy = intel_port_to_phy(dev_priv, port);
3142
3143         if (INTEL_GEN(dev_priv) >= 11) {
3144                 if (!intel_phy_is_combo(dev_priv, phy) ||
3145                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3146                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
3147         } else if (IS_CANNONLAKE(dev_priv)) {
3148                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
3149                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3150         } else if (IS_GEN9_BC(dev_priv)) {
3151                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
3152                            DPLL_CTRL2_DDI_CLK_OFF(port));
3153         } else if (INTEL_GEN(dev_priv) < 9) {
3154                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
3155         }
3156 }
3157
3158 static void
3159 icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
3160 {
3161         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3162         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
3163         u32 val, bits;
3164         int ln;
3165
3166         if (tc_port == PORT_TC_NONE)
3167                 return;
3168
3169         bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
3170                MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
3171                MG_DP_MODE_CFG_GAONPWR_GATING;
3172
3173         for (ln = 0; ln < 2; ln++) {
3174                 if (INTEL_GEN(dev_priv) >= 12) {
3175                         I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
3176                         val = I915_READ(DKL_DP_MODE(tc_port));
3177                 } else {
3178                         val = I915_READ(MG_DP_MODE(ln, tc_port));
3179                 }
3180
3181                 if (enable)
3182                         val |= bits;
3183                 else
3184                         val &= ~bits;
3185
3186                 if (INTEL_GEN(dev_priv) >= 12)
3187                         I915_WRITE(DKL_DP_MODE(tc_port), val);
3188                 else
3189                         I915_WRITE(MG_DP_MODE(ln, tc_port), val);
3190         }
3191
3192         if (INTEL_GEN(dev_priv) == 11) {
3193                 bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
3194                        MG_MISC_SUS0_CFG_CL2PWR_GATING |
3195                        MG_MISC_SUS0_CFG_GAONPWR_GATING |
3196                        MG_MISC_SUS0_CFG_TRPWR_GATING |
3197                        MG_MISC_SUS0_CFG_CL1PWR_GATING |
3198                        MG_MISC_SUS0_CFG_DGPWR_GATING;
3199
3200                 val = I915_READ(MG_MISC_SUS0(tc_port));
3201                 if (enable)
3202                         val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
3203                 else
3204                         val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
3205                 I915_WRITE(MG_MISC_SUS0(tc_port), val);
3206         }
3207 }
3208
3209 static void
3210 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
3211                        const struct intel_crtc_state *crtc_state)
3212 {
3213         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3214         enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
3215         u32 ln0, ln1, pin_assignment;
3216         u8 width;
3217
3218         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3219                 return;
3220
3221         if (INTEL_GEN(dev_priv) >= 12) {
3222                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3223                 ln0 = I915_READ(DKL_DP_MODE(tc_port));
3224                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3225                 ln1 = I915_READ(DKL_DP_MODE(tc_port));
3226         } else {
3227                 ln0 = I915_READ(MG_DP_MODE(0, tc_port));
3228                 ln1 = I915_READ(MG_DP_MODE(1, tc_port));
3229         }
3230
3231         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
3232         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3233
3234         /* DPPATC */
3235         pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
3236         width = crtc_state->lane_count;
3237
3238         switch (pin_assignment) {
3239         case 0x0:
3240                 WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
3241                 if (width == 1) {
3242                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3243                 } else {
3244                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3245                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3246                 }
3247                 break;
3248         case 0x1:
3249                 if (width == 4) {
3250                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3251                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3252                 }
3253                 break;
3254         case 0x2:
3255                 if (width == 2) {
3256                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3257                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3258                 }
3259                 break;
3260         case 0x3:
3261         case 0x5:
3262                 if (width == 1) {
3263                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3264                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3265                 } else {
3266                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3267                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3268                 }
3269                 break;
3270         case 0x4:
3271         case 0x6:
3272                 if (width == 1) {
3273                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3274                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3275                 } else {
3276                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3277                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3278                 }
3279                 break;
3280         default:
3281                 MISSING_CASE(pin_assignment);
3282         }
3283
3284         if (INTEL_GEN(dev_priv) >= 12) {
3285                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3286                 I915_WRITE(DKL_DP_MODE(tc_port), ln0);
3287                 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3288                 I915_WRITE(DKL_DP_MODE(tc_port), ln1);
3289         } else {
3290                 I915_WRITE(MG_DP_MODE(0, tc_port), ln0);
3291                 I915_WRITE(MG_DP_MODE(1, tc_port), ln1);
3292         }
3293 }
3294
3295 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3296                                         const struct intel_crtc_state *crtc_state)
3297 {
3298         if (!crtc_state->fec_enable)
3299                 return;
3300
3301         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3302                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3303 }
3304
3305 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3306                                  const struct intel_crtc_state *crtc_state)
3307 {
3308         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3309         struct intel_dp *intel_dp;
3310         u32 val;
3311
3312         if (!crtc_state->fec_enable)
3313                 return;
3314
3315         intel_dp = enc_to_intel_dp(&encoder->base);
3316         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3317         val |= DP_TP_CTL_FEC_ENABLE;
3318         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3319
3320         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3321                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3322                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3323 }
3324
3325 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3326                                         const struct intel_crtc_state *crtc_state)
3327 {
3328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3329         struct intel_dp *intel_dp;
3330         u32 val;
3331
3332         if (!crtc_state->fec_enable)
3333                 return;
3334
3335         intel_dp = enc_to_intel_dp(&encoder->base);
3336         val = I915_READ(intel_dp->regs.dp_tp_ctl);
3337         val &= ~DP_TP_CTL_FEC_ENABLE;
3338         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3339         POSTING_READ(intel_dp->regs.dp_tp_ctl);
3340 }
3341
3342 static void
3343 tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3344 {
3345         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3346         u32 val;
3347
3348         if (!cstate->dc3co_exitline)
3349                 return;
3350
3351         val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3352         val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3353         I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3354 }
3355
3356 static void
3357 tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3358 {
3359         u32 val, exit_scanlines;
3360         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3361
3362         if (!cstate->dc3co_exitline)
3363                 return;
3364
3365         exit_scanlines = cstate->dc3co_exitline;
3366         exit_scanlines <<= EXITLINE_SHIFT;
3367         val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3368         val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3369         val |= exit_scanlines;
3370         val |= EXITLINE_ENABLE;
3371         I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3372 }
3373
3374 static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
3375                                               struct intel_crtc_state *cstate)
3376 {
3377         u32 exit_scanlines;
3378         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3379         u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
3380
3381         cstate->dc3co_exitline = 0;
3382
3383         if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
3384                 return;
3385
3386         /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
3387         if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A ||
3388             encoder->port != PORT_A)
3389                 return;
3390
3391         if (!cstate->has_psr2 || !cstate->base.active)
3392                 return;
3393
3394         /*
3395          * DC3CO Exit time 200us B.Spec 49196
3396          * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
3397          */
3398         exit_scanlines =
3399                 intel_usecs_to_scanlines(&cstate->base.adjusted_mode, 200) + 1;
3400
3401         if (WARN_ON(exit_scanlines > crtc_vdisplay))
3402                 return;
3403
3404         cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
3405         DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
3406 }
3407
3408 static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
3409 {
3410         u32 val;
3411         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3412
3413         if (INTEL_GEN(dev_priv) < 12)
3414                 return;
3415
3416         val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
3417
3418         if (val & EXITLINE_ENABLE)
3419                 crtc_state->dc3co_exitline = val & EXITLINE_MASK;
3420 }
3421
3422 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
3423                                   const struct intel_crtc_state *crtc_state,
3424                                   const struct drm_connector_state *conn_state)
3425 {
3426         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3427         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3428         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3429         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3430         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3431         int level = intel_ddi_dp_level(intel_dp);
3432         enum transcoder transcoder = crtc_state->cpu_transcoder;
3433
3434         tgl_set_psr2_transcoder_exitline(crtc_state);
3435         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3436                                  crtc_state->lane_count, is_mst);
3437
3438         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3439         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3440
3441         /* 1.a got on intel_atomic_commit_tail() */
3442
3443         /* 2. */
3444         intel_edp_panel_on(intel_dp);
3445
3446         /*
3447          * 1.b, 3. and 4.a is done before tgl_ddi_pre_enable_dp() by:
3448          * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
3449          * haswell_crtc_enable()->intel_enable_shared_dpll()
3450          */
3451
3452         /* 4.b */
3453         intel_ddi_clk_select(encoder, crtc_state);
3454
3455         /* 5. */
3456         if (!intel_phy_is_tc(dev_priv, phy) ||
3457             dig_port->tc_mode != TC_PORT_TBT_ALT)
3458                 intel_display_power_get(dev_priv,
3459                                         dig_port->ddi_io_power_domain);
3460
3461         /* 6. */
3462         icl_program_mg_dp_mode(dig_port, crtc_state);
3463
3464         /*
3465          * 7.a - Steps in this function should only be executed over MST
3466          * master, what will be taken in care by MST hook
3467          * intel_mst_pre_enable_dp()
3468          */
3469         intel_ddi_enable_pipe_clock(crtc_state);
3470
3471         /* 7.b */
3472         intel_ddi_config_transcoder_func(crtc_state);
3473
3474         /* 7.d */
3475         icl_phy_set_clock_gating(dig_port, false);
3476
3477         /* 7.e */
3478         tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3479                                 encoder->type);
3480
3481         /* 7.f */
3482         if (intel_phy_is_combo(dev_priv, phy)) {
3483                 bool lane_reversal =
3484                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3485
3486                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3487                                                crtc_state->lane_count,
3488                                                lane_reversal);
3489         }
3490
3491         /* 7.g */
3492         intel_ddi_init_dp_buf_reg(encoder);
3493
3494         if (!is_mst)
3495                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3496
3497         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3498         /*
3499          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3500          * in the FEC_CONFIGURATION register to 1 before initiating link
3501          * training
3502          */
3503         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3504         /* 7.c, 7.h, 7.i, 7.j */
3505         intel_dp_start_link_train(intel_dp);
3506
3507         /* 7.k */
3508         if (!is_trans_port_sync_mode(crtc_state))
3509                 intel_dp_stop_link_train(intel_dp);
3510
3511         /*
3512          * TODO: enable clock gating
3513          *
3514          * It is not written in DP enabling sequence but "PHY Clockgating
3515          * programming" states that clock gating should be enabled after the
3516          * link training but doing so causes all the following trainings to fail
3517          * so not enabling it for now.
3518          */
3519
3520         /* 7.l */
3521         intel_ddi_enable_fec(encoder, crtc_state);
3522         intel_dsc_enable(encoder, crtc_state);
3523 }
3524
3525 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
3526                                   const struct intel_crtc_state *crtc_state,
3527                                   const struct drm_connector_state *conn_state)
3528 {
3529         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3530         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3531         enum port port = encoder->port;
3532         enum phy phy = intel_port_to_phy(dev_priv, port);
3533         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3534         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3535         int level = intel_ddi_dp_level(intel_dp);
3536
3537         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3538
3539         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3540                                  crtc_state->lane_count, is_mst);
3541
3542         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3543         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3544
3545         intel_edp_panel_on(intel_dp);
3546
3547         intel_ddi_clk_select(encoder, crtc_state);
3548
3549         if (!intel_phy_is_tc(dev_priv, phy) ||
3550             dig_port->tc_mode != TC_PORT_TBT_ALT)
3551                 intel_display_power_get(dev_priv,
3552                                         dig_port->ddi_io_power_domain);
3553
3554         icl_program_mg_dp_mode(dig_port, crtc_state);
3555         icl_phy_set_clock_gating(dig_port, false);
3556
3557         if (INTEL_GEN(dev_priv) >= 11)
3558                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3559                                         level, encoder->type);
3560         else if (IS_CANNONLAKE(dev_priv))
3561                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3562         else if (IS_GEN9_LP(dev_priv))
3563                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3564         else
3565                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3566
3567         if (intel_phy_is_combo(dev_priv, phy)) {
3568                 bool lane_reversal =
3569                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3570
3571                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3572                                                crtc_state->lane_count,
3573                                                lane_reversal);
3574         }
3575
3576         intel_ddi_init_dp_buf_reg(encoder);
3577         if (!is_mst)
3578                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3579         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3580                                               true);
3581         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3582         intel_dp_start_link_train(intel_dp);
3583         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3584             !is_trans_port_sync_mode(crtc_state))
3585                 intel_dp_stop_link_train(intel_dp);
3586
3587         intel_ddi_enable_fec(encoder, crtc_state);
3588
3589         icl_phy_set_clock_gating(dig_port, true);
3590
3591         if (!is_mst)
3592                 intel_ddi_enable_pipe_clock(crtc_state);
3593
3594         intel_dsc_enable(encoder, crtc_state);
3595 }
3596
3597 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3598                                     const struct intel_crtc_state *crtc_state,
3599                                     const struct drm_connector_state *conn_state)
3600 {
3601         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3602
3603         if (INTEL_GEN(dev_priv) >= 12)
3604                 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3605         else
3606                 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3607
3608         intel_ddi_set_dp_msa(crtc_state, conn_state);
3609 }
3610
3611 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3612                                       const struct intel_crtc_state *crtc_state,
3613                                       const struct drm_connector_state *conn_state)
3614 {
3615         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3616         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3617         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3618         enum port port = encoder->port;
3619         int level = intel_ddi_hdmi_level(dev_priv, port);
3620         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3621
3622         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3623         intel_ddi_clk_select(encoder, crtc_state);
3624
3625         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3626
3627         icl_program_mg_dp_mode(dig_port, crtc_state);
3628         icl_phy_set_clock_gating(dig_port, false);
3629
3630         if (INTEL_GEN(dev_priv) >= 12)
3631                 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3632                                         level, INTEL_OUTPUT_HDMI);
3633         else if (INTEL_GEN(dev_priv) == 11)
3634                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3635                                         level, INTEL_OUTPUT_HDMI);
3636         else if (IS_CANNONLAKE(dev_priv))
3637                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3638         else if (IS_GEN9_LP(dev_priv))
3639                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3640         else
3641                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3642
3643         icl_phy_set_clock_gating(dig_port, true);
3644
3645         if (IS_GEN9_BC(dev_priv))
3646                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3647
3648         intel_ddi_enable_pipe_clock(crtc_state);
3649
3650         intel_dig_port->set_infoframes(encoder,
3651                                        crtc_state->has_infoframe,
3652                                        crtc_state, conn_state);
3653 }
3654
3655 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3656                                  const struct intel_crtc_state *crtc_state,
3657                                  const struct drm_connector_state *conn_state)
3658 {
3659         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3660         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3661         enum pipe pipe = crtc->pipe;
3662
3663         /*
3664          * When called from DP MST code:
3665          * - conn_state will be NULL
3666          * - encoder will be the main encoder (ie. mst->primary)
3667          * - the main connector associated with this port
3668          *   won't be active or linked to a crtc
3669          * - crtc_state will be the state of the first stream to
3670          *   be activated on this port, and it may not be the same
3671          *   stream that will be deactivated last, but each stream
3672          *   should have a state that is identical when it comes to
3673          *   the DP link parameteres
3674          */
3675
3676         WARN_ON(crtc_state->has_pch_encoder);
3677
3678         if (INTEL_GEN(dev_priv) >= 11)
3679                 icl_map_plls_to_ports(encoder, crtc_state);
3680
3681         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3682
3683         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3684                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3685         } else {
3686                 struct intel_lspcon *lspcon =
3687                                 enc_to_intel_lspcon(&encoder->base);
3688
3689                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3690                 if (lspcon->active) {
3691                         struct intel_digital_port *dig_port =
3692                                         enc_to_dig_port(&encoder->base);
3693
3694                         dig_port->set_infoframes(encoder,
3695                                                  crtc_state->has_infoframe,
3696                                                  crtc_state, conn_state);
3697                 }
3698         }
3699 }
3700
3701 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3702                                   const struct intel_crtc_state *crtc_state)
3703 {
3704         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3705         enum port port = encoder->port;
3706         bool wait = false;
3707         u32 val;
3708
3709         val = I915_READ(DDI_BUF_CTL(port));
3710         if (val & DDI_BUF_CTL_ENABLE) {
3711                 val &= ~DDI_BUF_CTL_ENABLE;
3712                 I915_WRITE(DDI_BUF_CTL(port), val);
3713                 wait = true;
3714         }
3715
3716         if (intel_crtc_has_dp_encoder(crtc_state)) {
3717                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3718
3719                 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3720                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3721                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3722                 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3723         }
3724
3725         /* Disable FEC in DP Sink */
3726         intel_ddi_disable_fec_state(encoder, crtc_state);
3727
3728         if (wait)
3729                 intel_wait_ddi_buf_idle(dev_priv, port);
3730 }
3731
3732 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3733                                       const struct intel_crtc_state *old_crtc_state,
3734                                       const struct drm_connector_state *old_conn_state)
3735 {
3736         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3737         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3738         struct intel_dp *intel_dp = &dig_port->dp;
3739         bool is_mst = intel_crtc_has_type(old_crtc_state,
3740                                           INTEL_OUTPUT_DP_MST);
3741         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3742
3743         if (!is_mst) {
3744                 intel_ddi_disable_pipe_clock(old_crtc_state);
3745                 /*
3746                  * Power down sink before disabling the port, otherwise we end
3747                  * up getting interrupts from the sink on detecting link loss.
3748                  */
3749                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3750         }
3751
3752         intel_disable_ddi_buf(encoder, old_crtc_state);
3753
3754         intel_edp_panel_vdd_on(intel_dp);
3755         intel_edp_panel_off(intel_dp);
3756
3757         if (!intel_phy_is_tc(dev_priv, phy) ||
3758             dig_port->tc_mode != TC_PORT_TBT_ALT)
3759                 intel_display_power_put_unchecked(dev_priv,
3760                                                   dig_port->ddi_io_power_domain);
3761
3762         intel_ddi_clk_disable(encoder);
3763         tgl_clear_psr2_transcoder_exitline(old_crtc_state);
3764 }
3765
3766 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3767                                         const struct intel_crtc_state *old_crtc_state,
3768                                         const struct drm_connector_state *old_conn_state)
3769 {
3770         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3771         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3772         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3773
3774         dig_port->set_infoframes(encoder, false,
3775                                  old_crtc_state, old_conn_state);
3776
3777         intel_ddi_disable_pipe_clock(old_crtc_state);
3778
3779         intel_disable_ddi_buf(encoder, old_crtc_state);
3780
3781         intel_display_power_put_unchecked(dev_priv,
3782                                           dig_port->ddi_io_power_domain);
3783
3784         intel_ddi_clk_disable(encoder);
3785
3786         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3787 }
3788
3789 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3790                                    const struct intel_crtc_state *old_crtc_state,
3791                                    const struct drm_connector_state *old_conn_state)
3792 {
3793         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3794
3795         /*
3796          * When called from DP MST code:
3797          * - old_conn_state will be NULL
3798          * - encoder will be the main encoder (ie. mst->primary)
3799          * - the main connector associated with this port
3800          *   won't be active or linked to a crtc
3801          * - old_crtc_state will be the state of the last stream to
3802          *   be deactivated on this port, and it may not be the same
3803          *   stream that was activated last, but each stream
3804          *   should have a state that is identical when it comes to
3805          *   the DP link parameteres
3806          */
3807
3808         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3809                 intel_ddi_post_disable_hdmi(encoder,
3810                                             old_crtc_state, old_conn_state);
3811         else
3812                 intel_ddi_post_disable_dp(encoder,
3813                                           old_crtc_state, old_conn_state);
3814
3815         if (INTEL_GEN(dev_priv) >= 11)
3816                 icl_unmap_plls_to_ports(encoder);
3817 }
3818
3819 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3820                                 const struct intel_crtc_state *old_crtc_state,
3821                                 const struct drm_connector_state *old_conn_state)
3822 {
3823         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3824         u32 val;
3825
3826         /*
3827          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3828          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3829          * step 13 is the correct place for it. Step 18 is where it was
3830          * originally before the BUN.
3831          */
3832         val = I915_READ(FDI_RX_CTL(PIPE_A));
3833         val &= ~FDI_RX_ENABLE;
3834         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3835
3836         intel_disable_ddi_buf(encoder, old_crtc_state);
3837         intel_ddi_clk_disable(encoder);
3838
3839         val = I915_READ(FDI_RX_MISC(PIPE_A));
3840         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3841         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3842         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3843
3844         val = I915_READ(FDI_RX_CTL(PIPE_A));
3845         val &= ~FDI_PCDCLK;
3846         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3847
3848         val = I915_READ(FDI_RX_CTL(PIPE_A));
3849         val &= ~FDI_RX_PLL_ENABLE;
3850         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3851 }
3852
3853 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3854                                 const struct intel_crtc_state *crtc_state,
3855                                 const struct drm_connector_state *conn_state)
3856 {
3857         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3858         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3859         enum port port = encoder->port;
3860
3861         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3862                 intel_dp_stop_link_train(intel_dp);
3863
3864         intel_edp_backlight_on(crtc_state, conn_state);
3865         intel_psr_enable(intel_dp, crtc_state);
3866         intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
3867         intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
3868         intel_edp_drrs_enable(intel_dp, crtc_state);
3869
3870         if (crtc_state->has_audio)
3871                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3872 }
3873
3874 static i915_reg_t
3875 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3876                                enum port port)
3877 {
3878         static const enum transcoder trans[] = {
3879                 [PORT_A] = TRANSCODER_EDP,
3880                 [PORT_B] = TRANSCODER_A,
3881                 [PORT_C] = TRANSCODER_B,
3882                 [PORT_D] = TRANSCODER_C,
3883                 [PORT_E] = TRANSCODER_A,
3884         };
3885
3886         WARN_ON(INTEL_GEN(dev_priv) < 9);
3887
3888         if (WARN_ON(port < PORT_A || port > PORT_E))
3889                 port = PORT_A;
3890
3891         return CHICKEN_TRANS(trans[port]);
3892 }
3893
3894 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3895                                   const struct intel_crtc_state *crtc_state,
3896                                   const struct drm_connector_state *conn_state)
3897 {
3898         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3899         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3900         struct drm_connector *connector = conn_state->connector;
3901         enum port port = encoder->port;
3902
3903         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3904                                                crtc_state->hdmi_high_tmds_clock_ratio,
3905                                                crtc_state->hdmi_scrambling))
3906                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3907                           connector->base.id, connector->name);
3908
3909         /* Display WA #1143: skl,kbl,cfl */
3910         if (IS_GEN9_BC(dev_priv)) {
3911                 /*
3912                  * For some reason these chicken bits have been
3913                  * stuffed into a transcoder register, event though
3914                  * the bits affect a specific DDI port rather than
3915                  * a specific transcoder.
3916                  */
3917                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3918                 u32 val;
3919
3920                 val = I915_READ(reg);
3921
3922                 if (port == PORT_E)
3923                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3924                                 DDIE_TRAINING_OVERRIDE_VALUE;
3925                 else
3926                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3927                                 DDI_TRAINING_OVERRIDE_VALUE;
3928
3929                 I915_WRITE(reg, val);
3930                 POSTING_READ(reg);
3931
3932                 udelay(1);
3933
3934                 if (port == PORT_E)
3935                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3936                                  DDIE_TRAINING_OVERRIDE_VALUE);
3937                 else
3938                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3939                                  DDI_TRAINING_OVERRIDE_VALUE);
3940
3941                 I915_WRITE(reg, val);
3942         }
3943
3944         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3945          * are ignored so nothing special needs to be done besides
3946          * enabling the port.
3947          */
3948         I915_WRITE(DDI_BUF_CTL(port),
3949                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3950
3951         if (crtc_state->has_audio)
3952                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3953 }
3954
3955 static void intel_enable_ddi(struct intel_encoder *encoder,
3956                              const struct intel_crtc_state *crtc_state,
3957                              const struct drm_connector_state *conn_state)
3958 {
3959         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3960                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3961         else
3962                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3963
3964         /* Enable hdcp if it's desired */
3965         if (conn_state->content_protection ==
3966             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3967                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3968                                   (u8)conn_state->hdcp_content_type);
3969 }
3970
3971 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3972                                  const struct intel_crtc_state *old_crtc_state,
3973                                  const struct drm_connector_state *old_conn_state)
3974 {
3975         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3976
3977         intel_dp->link_trained = false;
3978
3979         if (old_crtc_state->has_audio)
3980                 intel_audio_codec_disable(encoder,
3981                                           old_crtc_state, old_conn_state);
3982
3983         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3984         intel_psr_disable(intel_dp, old_crtc_state);
3985         intel_edp_backlight_off(old_conn_state);
3986         /* Disable the decompression in DP Sink */
3987         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3988                                               false);
3989 }
3990
3991 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3992                                    const struct intel_crtc_state *old_crtc_state,
3993                                    const struct drm_connector_state *old_conn_state)
3994 {
3995         struct drm_connector *connector = old_conn_state->connector;
3996
3997         if (old_crtc_state->has_audio)
3998                 intel_audio_codec_disable(encoder,
3999                                           old_crtc_state, old_conn_state);
4000
4001         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4002                                                false, false))
4003                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
4004                               connector->base.id, connector->name);
4005 }
4006
4007 static void intel_disable_ddi(struct intel_encoder *encoder,
4008                               const struct intel_crtc_state *old_crtc_state,
4009                               const struct drm_connector_state *old_conn_state)
4010 {
4011         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
4012
4013         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4014                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
4015         else
4016                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
4017 }
4018
4019 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
4020                                      const struct intel_crtc_state *crtc_state,
4021                                      const struct drm_connector_state *conn_state)
4022 {
4023         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4024
4025         intel_ddi_set_dp_msa(crtc_state, conn_state);
4026
4027         intel_psr_update(intel_dp, crtc_state);
4028         intel_edp_drrs_enable(intel_dp, crtc_state);
4029
4030         intel_panel_update_backlight(encoder, crtc_state, conn_state);
4031 }
4032
4033 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
4034                                   const struct intel_crtc_state *crtc_state,
4035                                   const struct drm_connector_state *conn_state)
4036 {
4037         struct intel_connector *connector =
4038                                 to_intel_connector(conn_state->connector);
4039         struct intel_hdcp *hdcp = &connector->hdcp;
4040         bool content_protection_type_changed =
4041                         (conn_state->hdcp_content_type != hdcp->content_type &&
4042                          conn_state->content_protection !=
4043                          DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
4044
4045         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4046                 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
4047
4048         /*
4049          * During the HDCP encryption session if Type change is requested,
4050          * disable the HDCP and reenable it with new TYPE value.
4051          */
4052         if (conn_state->content_protection ==
4053             DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
4054             content_protection_type_changed)
4055                 intel_hdcp_disable(connector);
4056
4057         /*
4058          * Mark the hdcp state as DESIRED after the hdcp disable of type
4059          * change procedure.
4060          */
4061         if (content_protection_type_changed) {
4062                 mutex_lock(&hdcp->mutex);
4063                 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
4064                 schedule_work(&hdcp->prop_work);
4065                 mutex_unlock(&hdcp->mutex);
4066         }
4067
4068         if (conn_state->content_protection ==
4069             DRM_MODE_CONTENT_PROTECTION_DESIRED ||
4070             content_protection_type_changed)
4071                 intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
4072 }
4073
4074 static void
4075 intel_ddi_update_prepare(struct intel_atomic_state *state,
4076                          struct intel_encoder *encoder,
4077                          struct intel_crtc *crtc)
4078 {
4079         struct intel_crtc_state *crtc_state =
4080                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4081         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4082
4083         WARN_ON(crtc && crtc->active);
4084
4085         intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
4086         if (crtc_state && crtc_state->base.active)
4087                 intel_update_active_dpll(state, crtc, encoder);
4088 }
4089
4090 static void
4091 intel_ddi_update_complete(struct intel_atomic_state *state,
4092                           struct intel_encoder *encoder,
4093                           struct intel_crtc *crtc)
4094 {
4095         intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
4096 }
4097
4098 static void
4099 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
4100                          const struct intel_crtc_state *crtc_state,
4101                          const struct drm_connector_state *conn_state)
4102 {
4103         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4104         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4105         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4106         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4107
4108         if (is_tc_port)
4109                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4110
4111         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4112                 intel_display_power_get(dev_priv,
4113                                         intel_ddi_main_link_aux_domain(dig_port));
4114
4115         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4116                 /*
4117                  * Program the lane count for static/dynamic connections on
4118                  * Type-C ports.  Skip this step for TBT.
4119                  */
4120                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4121         else if (IS_GEN9_LP(dev_priv))
4122                 bxt_ddi_phy_set_lane_optim_mask(encoder,
4123                                                 crtc_state->lane_lat_optim_mask);
4124 }
4125
4126 static void
4127 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
4128                            const struct intel_crtc_state *crtc_state,
4129                            const struct drm_connector_state *conn_state)
4130 {
4131         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4132         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4133         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4134         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4135
4136         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4137                 intel_display_power_put_unchecked(dev_priv,
4138                                                   intel_ddi_main_link_aux_domain(dig_port));
4139
4140         if (is_tc_port)
4141                 intel_tc_port_put_link(dig_port);
4142 }
4143
4144 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
4145 {
4146         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4147         struct drm_i915_private *dev_priv =
4148                 to_i915(intel_dig_port->base.base.dev);
4149         enum port port = intel_dig_port->base.port;
4150         u32 val;
4151         bool wait = false;
4152
4153         if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
4154                 val = I915_READ(DDI_BUF_CTL(port));
4155                 if (val & DDI_BUF_CTL_ENABLE) {
4156                         val &= ~DDI_BUF_CTL_ENABLE;
4157                         I915_WRITE(DDI_BUF_CTL(port), val);
4158                         wait = true;
4159                 }
4160
4161                 val = I915_READ(intel_dp->regs.dp_tp_ctl);
4162                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4163                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
4164                 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
4165                 POSTING_READ(intel_dp->regs.dp_tp_ctl);
4166
4167                 if (wait)
4168                         intel_wait_ddi_buf_idle(dev_priv, port);
4169         }
4170
4171         val = DP_TP_CTL_ENABLE |
4172               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
4173         if (intel_dp->link_mst)
4174                 val |= DP_TP_CTL_MODE_MST;
4175         else {
4176                 val |= DP_TP_CTL_MODE_SST;
4177                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4178                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4179         }
4180         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
4181         POSTING_READ(intel_dp->regs.dp_tp_ctl);
4182
4183         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4184         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
4185         POSTING_READ(DDI_BUF_CTL(port));
4186
4187         udelay(600);
4188 }
4189
4190 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4191                                        enum transcoder cpu_transcoder)
4192 {
4193         if (cpu_transcoder == TRANSCODER_EDP)
4194                 return false;
4195
4196         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4197                 return false;
4198
4199         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
4200                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4201 }
4202
4203 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4204                                          struct intel_crtc_state *crtc_state)
4205 {
4206         if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4207                 crtc_state->min_voltage_level = 1;
4208         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4209                 crtc_state->min_voltage_level = 2;
4210 }
4211
4212 void intel_ddi_get_config(struct intel_encoder *encoder,
4213                           struct intel_crtc_state *pipe_config)
4214 {
4215         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4216         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
4217         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4218         u32 temp, flags = 0;
4219
4220         /* XXX: DSI transcoder paranoia */
4221         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
4222                 return;
4223
4224         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
4225         if (temp & TRANS_DDI_PHSYNC)
4226                 flags |= DRM_MODE_FLAG_PHSYNC;
4227         else
4228                 flags |= DRM_MODE_FLAG_NHSYNC;
4229         if (temp & TRANS_DDI_PVSYNC)
4230                 flags |= DRM_MODE_FLAG_PVSYNC;
4231         else
4232                 flags |= DRM_MODE_FLAG_NVSYNC;
4233
4234         pipe_config->base.adjusted_mode.flags |= flags;
4235
4236         switch (temp & TRANS_DDI_BPC_MASK) {
4237         case TRANS_DDI_BPC_6:
4238                 pipe_config->pipe_bpp = 18;
4239                 break;
4240         case TRANS_DDI_BPC_8:
4241                 pipe_config->pipe_bpp = 24;
4242                 break;
4243         case TRANS_DDI_BPC_10:
4244                 pipe_config->pipe_bpp = 30;
4245                 break;
4246         case TRANS_DDI_BPC_12:
4247                 pipe_config->pipe_bpp = 36;
4248                 break;
4249         default:
4250                 break;
4251         }
4252
4253         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4254         case TRANS_DDI_MODE_SELECT_HDMI:
4255                 pipe_config->has_hdmi_sink = true;
4256
4257                 pipe_config->infoframes.enable |=
4258                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4259
4260                 if (pipe_config->infoframes.enable)
4261                         pipe_config->has_infoframe = true;
4262
4263                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4264                         pipe_config->hdmi_scrambling = true;
4265                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4266                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4267                 /* fall through */
4268         case TRANS_DDI_MODE_SELECT_DVI:
4269                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4270                 pipe_config->lane_count = 4;
4271                 break;
4272         case TRANS_DDI_MODE_SELECT_FDI:
4273                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4274                 break;
4275         case TRANS_DDI_MODE_SELECT_DP_SST:
4276                 if (encoder->type == INTEL_OUTPUT_EDP)
4277                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4278                 else
4279                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4280                 pipe_config->lane_count =
4281                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4282                 intel_dp_get_m_n(intel_crtc, pipe_config);
4283
4284                 if (INTEL_GEN(dev_priv) >= 11) {
4285                         i915_reg_t dp_tp_ctl;
4286
4287                         if (IS_GEN(dev_priv, 11))
4288                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
4289                         else
4290                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4291
4292                         pipe_config->fec_enable =
4293                                 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4294
4295                         DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
4296                                       encoder->base.base.id, encoder->base.name,
4297                                       pipe_config->fec_enable);
4298                 }
4299
4300                 break;
4301         case TRANS_DDI_MODE_SELECT_DP_MST:
4302                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4303                 pipe_config->lane_count =
4304                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4305                 intel_dp_get_m_n(intel_crtc, pipe_config);
4306                 break;
4307         default:
4308                 break;
4309         }
4310
4311         if (encoder->type == INTEL_OUTPUT_EDP)
4312                 tgl_dc3co_exitline_get_config(pipe_config);
4313
4314         pipe_config->has_audio =
4315                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4316
4317         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4318             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4319                 /*
4320                  * This is a big fat ugly hack.
4321                  *
4322                  * Some machines in UEFI boot mode provide us a VBT that has 18
4323                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4324                  * unknown we fail to light up. Yet the same BIOS boots up with
4325                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4326                  * max, not what it tells us to use.
4327                  *
4328                  * Note: This will still be broken if the eDP panel is not lit
4329                  * up by the BIOS, and thus we can't get the mode at module
4330                  * load.
4331                  */
4332                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4333                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4334                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4335         }
4336
4337         intel_ddi_clock_get(encoder, pipe_config);
4338
4339         if (IS_GEN9_LP(dev_priv))
4340                 pipe_config->lane_lat_optim_mask =
4341                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4342
4343         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4344
4345         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4346
4347         intel_read_infoframe(encoder, pipe_config,
4348                              HDMI_INFOFRAME_TYPE_AVI,
4349                              &pipe_config->infoframes.avi);
4350         intel_read_infoframe(encoder, pipe_config,
4351                              HDMI_INFOFRAME_TYPE_SPD,
4352                              &pipe_config->infoframes.spd);
4353         intel_read_infoframe(encoder, pipe_config,
4354                              HDMI_INFOFRAME_TYPE_VENDOR,
4355                              &pipe_config->infoframes.hdmi);
4356         intel_read_infoframe(encoder, pipe_config,
4357                              HDMI_INFOFRAME_TYPE_DRM,
4358                              &pipe_config->infoframes.drm);
4359 }
4360
4361 static enum intel_output_type
4362 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4363                               struct intel_crtc_state *crtc_state,
4364                               struct drm_connector_state *conn_state)
4365 {
4366         switch (conn_state->connector->connector_type) {
4367         case DRM_MODE_CONNECTOR_HDMIA:
4368                 return INTEL_OUTPUT_HDMI;
4369         case DRM_MODE_CONNECTOR_eDP:
4370                 return INTEL_OUTPUT_EDP;
4371         case DRM_MODE_CONNECTOR_DisplayPort:
4372                 return INTEL_OUTPUT_DP;
4373         default:
4374                 MISSING_CASE(conn_state->connector->connector_type);
4375                 return INTEL_OUTPUT_UNUSED;
4376         }
4377 }
4378
4379 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4380                                     struct intel_crtc_state *pipe_config,
4381                                     struct drm_connector_state *conn_state)
4382 {
4383         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
4384         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4385         enum port port = encoder->port;
4386         int ret;
4387
4388         if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
4389                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4390
4391         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4392                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4393         } else {
4394                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4395                 tgl_dc3co_exitline_compute_config(encoder, pipe_config);
4396         }
4397
4398         if (ret)
4399                 return ret;
4400
4401         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4402             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4403                 pipe_config->pch_pfit.force_thru =
4404                         pipe_config->pch_pfit.enabled ||
4405                         pipe_config->crc_enabled;
4406
4407         if (IS_GEN9_LP(dev_priv))
4408                 pipe_config->lane_lat_optim_mask =
4409                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4410
4411         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4412
4413         return 0;
4414 }
4415
4416 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4417 {
4418         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4419
4420         intel_dp_encoder_flush_work(encoder);
4421
4422         drm_encoder_cleanup(encoder);
4423         kfree(dig_port);
4424 }
4425
4426 static const struct drm_encoder_funcs intel_ddi_funcs = {
4427         .reset = intel_dp_encoder_reset,
4428         .destroy = intel_ddi_encoder_destroy,
4429 };
4430
4431 static struct intel_connector *
4432 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4433 {
4434         struct intel_connector *connector;
4435         enum port port = intel_dig_port->base.port;
4436
4437         connector = intel_connector_alloc();
4438         if (!connector)
4439                 return NULL;
4440
4441         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4442         intel_dig_port->dp.prepare_link_retrain =
4443                 intel_ddi_prepare_link_retrain;
4444
4445         if (!intel_dp_init_connector(intel_dig_port, connector)) {
4446                 kfree(connector);
4447                 return NULL;
4448         }
4449
4450         return connector;
4451 }
4452
4453 static int modeset_pipe(struct drm_crtc *crtc,
4454                         struct drm_modeset_acquire_ctx *ctx)
4455 {
4456         struct drm_atomic_state *state;
4457         struct drm_crtc_state *crtc_state;
4458         int ret;
4459
4460         state = drm_atomic_state_alloc(crtc->dev);
4461         if (!state)
4462                 return -ENOMEM;
4463
4464         state->acquire_ctx = ctx;
4465
4466         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4467         if (IS_ERR(crtc_state)) {
4468                 ret = PTR_ERR(crtc_state);
4469                 goto out;
4470         }
4471
4472         crtc_state->connectors_changed = true;
4473
4474         ret = drm_atomic_commit(state);
4475 out:
4476         drm_atomic_state_put(state);
4477
4478         return ret;
4479 }
4480
4481 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4482                                  struct drm_modeset_acquire_ctx *ctx)
4483 {
4484         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4485         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
4486         struct intel_connector *connector = hdmi->attached_connector;
4487         struct i2c_adapter *adapter =
4488                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4489         struct drm_connector_state *conn_state;
4490         struct intel_crtc_state *crtc_state;
4491         struct intel_crtc *crtc;
4492         u8 config;
4493         int ret;
4494
4495         if (!connector || connector->base.status != connector_status_connected)
4496                 return 0;
4497
4498         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4499                                ctx);
4500         if (ret)
4501                 return ret;
4502
4503         conn_state = connector->base.state;
4504
4505         crtc = to_intel_crtc(conn_state->crtc);
4506         if (!crtc)
4507                 return 0;
4508
4509         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4510         if (ret)
4511                 return ret;
4512
4513         crtc_state = to_intel_crtc_state(crtc->base.state);
4514
4515         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4516
4517         if (!crtc_state->base.active)
4518                 return 0;
4519
4520         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4521             !crtc_state->hdmi_scrambling)
4522                 return 0;
4523
4524         if (conn_state->commit &&
4525             !try_wait_for_completion(&conn_state->commit->hw_done))
4526                 return 0;
4527
4528         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4529         if (ret < 0) {
4530                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4531                 return 0;
4532         }
4533
4534         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4535             crtc_state->hdmi_high_tmds_clock_ratio &&
4536             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4537             crtc_state->hdmi_scrambling)
4538                 return 0;
4539
4540         /*
4541          * HDMI 2.0 says that one should not send scrambled data
4542          * prior to configuring the sink scrambling, and that
4543          * TMDS clock/data transmission should be suspended when
4544          * changing the TMDS clock rate in the sink. So let's
4545          * just do a full modeset here, even though some sinks
4546          * would be perfectly happy if were to just reconfigure
4547          * the SCDC settings on the fly.
4548          */
4549         return modeset_pipe(&crtc->base, ctx);
4550 }
4551
4552 static enum intel_hotplug_state
4553 intel_ddi_hotplug(struct intel_encoder *encoder,
4554                   struct intel_connector *connector,
4555                   bool irq_received)
4556 {
4557         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4558         struct drm_modeset_acquire_ctx ctx;
4559         enum intel_hotplug_state state;
4560         int ret;
4561
4562         state = intel_encoder_hotplug(encoder, connector, irq_received);
4563
4564         drm_modeset_acquire_init(&ctx, 0);
4565
4566         for (;;) {
4567                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4568                         ret = intel_hdmi_reset_link(encoder, &ctx);
4569                 else
4570                         ret = intel_dp_retrain_link(encoder, &ctx);
4571
4572                 if (ret == -EDEADLK) {
4573                         drm_modeset_backoff(&ctx);
4574                         continue;
4575                 }
4576
4577                 break;
4578         }
4579
4580         drm_modeset_drop_locks(&ctx);
4581         drm_modeset_acquire_fini(&ctx);
4582         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4583
4584         /*
4585          * Unpowered type-c dongles can take some time to boot and be
4586          * responsible, so here giving some time to those dongles to power up
4587          * and then retrying the probe.
4588          *
4589          * On many platforms the HDMI live state signal is known to be
4590          * unreliable, so we can't use it to detect if a sink is connected or
4591          * not. Instead we detect if it's connected based on whether we can
4592          * read the EDID or not. That in turn has a problem during disconnect,
4593          * since the HPD interrupt may be raised before the DDC lines get
4594          * disconnected (due to how the required length of DDC vs. HPD
4595          * connector pins are specified) and so we'll still be able to get a
4596          * valid EDID. To solve this schedule another detection cycle if this
4597          * time around we didn't detect any change in the sink's connection
4598          * status.
4599          */
4600         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4601             !dig_port->dp.is_mst)
4602                 state = INTEL_HOTPLUG_RETRY;
4603
4604         return state;
4605 }
4606
4607 static struct intel_connector *
4608 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4609 {
4610         struct intel_connector *connector;
4611         enum port port = intel_dig_port->base.port;
4612
4613         connector = intel_connector_alloc();
4614         if (!connector)
4615                 return NULL;
4616
4617         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4618         intel_hdmi_init_connector(intel_dig_port, connector);
4619
4620         return connector;
4621 }
4622
4623 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4624 {
4625         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4626
4627         if (dport->base.port != PORT_A)
4628                 return false;
4629
4630         if (dport->saved_port_bits & DDI_A_4_LANES)
4631                 return false;
4632
4633         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4634          *                     supported configuration
4635          */
4636         if (IS_GEN9_LP(dev_priv))
4637                 return true;
4638
4639         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4640          *             one who does also have a full A/E split called
4641          *             DDI_F what makes DDI_E useless. However for this
4642          *             case let's trust VBT info.
4643          */
4644         if (IS_CANNONLAKE(dev_priv) &&
4645             !intel_bios_is_port_present(dev_priv, PORT_E))
4646                 return true;
4647
4648         return false;
4649 }
4650
4651 static int
4652 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4653 {
4654         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4655         enum port port = intel_dport->base.port;
4656         int max_lanes = 4;
4657
4658         if (INTEL_GEN(dev_priv) >= 11)
4659                 return max_lanes;
4660
4661         if (port == PORT_A || port == PORT_E) {
4662                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4663                         max_lanes = port == PORT_A ? 4 : 0;
4664                 else
4665                         /* Both A and E share 2 lanes */
4666                         max_lanes = 2;
4667         }
4668
4669         /*
4670          * Some BIOS might fail to set this bit on port A if eDP
4671          * wasn't lit up at boot.  Force this bit set when needed
4672          * so we use the proper lane count for our calculations.
4673          */
4674         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4675                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4676                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4677                 max_lanes = 4;
4678         }
4679
4680         return max_lanes;
4681 }
4682
4683 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4684 {
4685         struct ddi_vbt_port_info *port_info =
4686                 &dev_priv->vbt.ddi_port_info[port];
4687         struct intel_digital_port *intel_dig_port;
4688         struct intel_encoder *intel_encoder;
4689         struct drm_encoder *encoder;
4690         bool init_hdmi, init_dp, init_lspcon = false;
4691         enum pipe pipe;
4692         enum phy phy = intel_port_to_phy(dev_priv, port);
4693
4694         init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4695         init_dp = port_info->supports_dp;
4696
4697         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4698                 /*
4699                  * Lspcon device needs to be driven with DP connector
4700                  * with special detection sequence. So make sure DP
4701                  * is initialized before lspcon.
4702                  */
4703                 init_dp = true;
4704                 init_lspcon = true;
4705                 init_hdmi = false;
4706                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4707         }
4708
4709         if (!init_dp && !init_hdmi) {
4710                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4711                               port_name(port));
4712                 return;
4713         }
4714
4715         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4716         if (!intel_dig_port)
4717                 return;
4718
4719         intel_encoder = &intel_dig_port->base;
4720         encoder = &intel_encoder->base;
4721
4722         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4723                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4724
4725         intel_encoder->hotplug = intel_ddi_hotplug;
4726         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4727         intel_encoder->compute_config = intel_ddi_compute_config;
4728         intel_encoder->enable = intel_enable_ddi;
4729         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4730         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4731         intel_encoder->pre_enable = intel_ddi_pre_enable;
4732         intel_encoder->disable = intel_disable_ddi;
4733         intel_encoder->post_disable = intel_ddi_post_disable;
4734         intel_encoder->update_pipe = intel_ddi_update_pipe;
4735         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4736         intel_encoder->get_config = intel_ddi_get_config;
4737         intel_encoder->suspend = intel_dp_encoder_suspend;
4738         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4739         intel_encoder->type = INTEL_OUTPUT_DDI;
4740         intel_encoder->power_domain = intel_port_to_power_domain(port);
4741         intel_encoder->port = port;
4742         intel_encoder->cloneable = 0;
4743         for_each_pipe(dev_priv, pipe)
4744                 intel_encoder->crtc_mask |= BIT(pipe);
4745
4746         if (INTEL_GEN(dev_priv) >= 11)
4747                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4748                         DDI_BUF_PORT_REVERSAL;
4749         else
4750                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4751                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4752         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4753         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4754         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4755
4756         if (intel_phy_is_tc(dev_priv, phy)) {
4757                 bool is_legacy = !port_info->supports_typec_usb &&
4758                                  !port_info->supports_tbt;
4759
4760                 intel_tc_port_init(intel_dig_port, is_legacy);
4761
4762                 intel_encoder->update_prepare = intel_ddi_update_prepare;
4763                 intel_encoder->update_complete = intel_ddi_update_complete;
4764         }
4765
4766         WARN_ON(port > PORT_I);
4767         intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4768                                               port - PORT_A;
4769
4770         if (init_dp) {
4771                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4772                         goto err;
4773
4774                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4775         }
4776
4777         /* In theory we don't need the encoder->type check, but leave it just in
4778          * case we have some really bad VBTs... */
4779         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4780                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4781                         goto err;
4782         }
4783
4784         if (init_lspcon) {
4785                 if (lspcon_init(intel_dig_port))
4786                         /* TODO: handle hdmi info frame part */
4787                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4788                                 port_name(port));
4789                 else
4790                         /*
4791                          * LSPCON init faied, but DP init was success, so
4792                          * lets try to drive as DP++ port.
4793                          */
4794                         DRM_ERROR("LSPCON init failed on port %c\n",
4795                                 port_name(port));
4796         }
4797
4798         intel_infoframe_init(intel_dig_port);
4799
4800         return;
4801
4802 err:
4803         drm_encoder_cleanup(encoder);
4804         kfree(intel_dig_port);
4805 }