2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
45 #include <drm/drm_scdc_helper.h>
47 #include "drm_crtc_internal.h"
49 #define version_greater(edid, maj, min) \
50 (((edid)->version > (maj)) || \
51 ((edid)->version == (maj) && (edid)->revision > (min)))
53 static int oui(u8 first, u8 second, u8 third)
55 return (first << 16) | (second << 8) | third;
58 #define EDID_EST_TIMINGS 16
59 #define EDID_STD_TIMINGS 8
60 #define EDID_DETAILED_TIMINGS 4
63 * EDID blocks out in the wild have a variety of bugs, try to collect
64 * them here (note that userspace may work around broken monitors first,
65 * but fixes should make their way here so that the kernel "just works"
66 * on as many displays as possible).
69 /* First detailed mode wrong, use largest 60Hz mode */
70 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
71 /* Reported 135MHz pixel clock is too high, needs adjustment */
72 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
73 /* Prefer the largest mode at 75 Hz */
74 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
75 /* Detail timing is in cm not mm */
76 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
77 /* Detailed timing descriptors have bogus size values, so just take the
78 * maximum size and use that.
80 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
81 /* use +hsync +vsync for detailed mode */
82 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
83 /* Force reduced-blanking timings for detailed modes */
84 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
86 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
88 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
90 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
92 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
93 /* Non desktop display (i.e. HMD) */
94 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
96 #define MICROSOFT_IEEE_OUI 0xca125c
98 struct detailed_mode_closure {
99 struct drm_connector *connector;
100 const struct edid *edid;
111 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
113 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
118 static const struct edid_quirk {
121 } edid_quirk_list[] = {
123 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
125 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
127 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
128 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
130 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
131 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
133 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
134 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
136 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
137 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
139 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
140 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
142 /* Belinea 10 15 55 */
143 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
144 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
146 /* Envision Peripherals, Inc. EN-7100e */
147 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
148 /* Envision EN2028 */
149 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
151 /* Funai Electronics PM36B */
152 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
153 EDID_QUIRK_DETAILED_IN_CM),
155 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
156 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
158 /* LG Philips LCD LP154W01-A5 */
159 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
160 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
162 /* Samsung SyncMaster 205BW. Note: irony */
163 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
164 /* Samsung SyncMaster 22[5-6]BW */
165 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
166 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
168 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
169 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
171 /* ViewSonic VA2026w */
172 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
174 /* Medion MD 30217 PG */
175 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
178 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
180 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
181 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
183 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
184 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
186 /* Valve Index Headset */
187 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
205 /* HTC Vive and Vive Pro VR Headsets */
206 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
209 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
210 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
215 /* Windows Mixed Reality Headsets */
216 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
223 /* Sony PlayStation VR Headset */
224 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
226 /* Sensics VR Headsets */
227 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
229 /* OSVR HDK and HDK2 VR Headsets */
230 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
234 * Autogenerated from the DMT spec.
235 * This table is copied from xfree86/modes/xf86EdidModes.c.
237 static const struct drm_display_mode drm_dmt_modes[] = {
238 /* 0x01 - 640x350@85Hz */
239 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
240 736, 832, 0, 350, 382, 385, 445, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
242 /* 0x02 - 640x400@85Hz */
243 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
244 736, 832, 0, 400, 401, 404, 445, 0,
245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
246 /* 0x03 - 720x400@85Hz */
247 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
248 828, 936, 0, 400, 401, 404, 446, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 0x04 - 640x480@60Hz */
251 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
252 752, 800, 0, 480, 490, 492, 525, 0,
253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
254 /* 0x05 - 640x480@72Hz */
255 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
256 704, 832, 0, 480, 489, 492, 520, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
258 /* 0x06 - 640x480@75Hz */
259 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
260 720, 840, 0, 480, 481, 484, 500, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
262 /* 0x07 - 640x480@85Hz */
263 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
264 752, 832, 0, 480, 481, 484, 509, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
266 /* 0x08 - 800x600@56Hz */
267 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
268 896, 1024, 0, 600, 601, 603, 625, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
270 /* 0x09 - 800x600@60Hz */
271 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
272 968, 1056, 0, 600, 601, 605, 628, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
274 /* 0x0a - 800x600@72Hz */
275 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
276 976, 1040, 0, 600, 637, 643, 666, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 0x0b - 800x600@75Hz */
279 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
280 896, 1056, 0, 600, 601, 604, 625, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x0c - 800x600@85Hz */
283 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
284 896, 1048, 0, 600, 601, 604, 631, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
286 /* 0x0d - 800x600@120Hz RB */
287 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
288 880, 960, 0, 600, 603, 607, 636, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x0e - 848x480@60Hz */
291 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
292 976, 1088, 0, 480, 486, 494, 517, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x0f - 1024x768@43Hz, interlace */
295 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
296 1208, 1264, 0, 768, 768, 776, 817, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
298 DRM_MODE_FLAG_INTERLACE) },
299 /* 0x10 - 1024x768@60Hz */
300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
301 1184, 1344, 0, 768, 771, 777, 806, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
303 /* 0x11 - 1024x768@70Hz */
304 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
305 1184, 1328, 0, 768, 771, 777, 806, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
307 /* 0x12 - 1024x768@75Hz */
308 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
309 1136, 1312, 0, 768, 769, 772, 800, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
311 /* 0x13 - 1024x768@85Hz */
312 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
313 1168, 1376, 0, 768, 769, 772, 808, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x14 - 1024x768@120Hz RB */
316 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
317 1104, 1184, 0, 768, 771, 775, 813, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
319 /* 0x15 - 1152x864@75Hz */
320 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
321 1344, 1600, 0, 864, 865, 868, 900, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
323 /* 0x55 - 1280x720@60Hz */
324 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
325 1430, 1650, 0, 720, 725, 730, 750, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
327 /* 0x16 - 1280x768@60Hz RB */
328 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
329 1360, 1440, 0, 768, 771, 778, 790, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
331 /* 0x17 - 1280x768@60Hz */
332 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
333 1472, 1664, 0, 768, 771, 778, 798, 0,
334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x18 - 1280x768@75Hz */
336 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
337 1488, 1696, 0, 768, 771, 778, 805, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
339 /* 0x19 - 1280x768@85Hz */
340 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
341 1496, 1712, 0, 768, 771, 778, 809, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x1a - 1280x768@120Hz RB */
344 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
345 1360, 1440, 0, 768, 771, 778, 813, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
347 /* 0x1b - 1280x800@60Hz RB */
348 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
349 1360, 1440, 0, 800, 803, 809, 823, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
351 /* 0x1c - 1280x800@60Hz */
352 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
353 1480, 1680, 0, 800, 803, 809, 831, 0,
354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
355 /* 0x1d - 1280x800@75Hz */
356 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
357 1488, 1696, 0, 800, 803, 809, 838, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
359 /* 0x1e - 1280x800@85Hz */
360 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
361 1496, 1712, 0, 800, 803, 809, 843, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x1f - 1280x800@120Hz RB */
364 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
365 1360, 1440, 0, 800, 803, 809, 847, 0,
366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
367 /* 0x20 - 1280x960@60Hz */
368 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
369 1488, 1800, 0, 960, 961, 964, 1000, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x21 - 1280x960@85Hz */
372 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
373 1504, 1728, 0, 960, 961, 964, 1011, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
375 /* 0x22 - 1280x960@120Hz RB */
376 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
377 1360, 1440, 0, 960, 963, 967, 1017, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
379 /* 0x23 - 1280x1024@60Hz */
380 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
381 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
383 /* 0x24 - 1280x1024@75Hz */
384 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
385 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x25 - 1280x1024@85Hz */
388 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
389 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x26 - 1280x1024@120Hz RB */
392 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
393 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
395 /* 0x27 - 1360x768@60Hz */
396 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
397 1536, 1792, 0, 768, 771, 777, 795, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
399 /* 0x28 - 1360x768@120Hz RB */
400 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
401 1440, 1520, 0, 768, 771, 776, 813, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
403 /* 0x51 - 1366x768@60Hz */
404 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
405 1579, 1792, 0, 768, 771, 774, 798, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x56 - 1366x768@60Hz */
408 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
409 1436, 1500, 0, 768, 769, 772, 800, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x29 - 1400x1050@60Hz RB */
412 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
413 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
415 /* 0x2a - 1400x1050@60Hz */
416 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
417 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x2b - 1400x1050@75Hz */
420 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
421 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
423 /* 0x2c - 1400x1050@85Hz */
424 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
425 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x2d - 1400x1050@120Hz RB */
428 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
429 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
431 /* 0x2e - 1440x900@60Hz RB */
432 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
433 1520, 1600, 0, 900, 903, 909, 926, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 0x2f - 1440x900@60Hz */
436 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
437 1672, 1904, 0, 900, 903, 909, 934, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 0x30 - 1440x900@75Hz */
440 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
441 1688, 1936, 0, 900, 903, 909, 942, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 0x31 - 1440x900@85Hz */
444 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
445 1696, 1952, 0, 900, 903, 909, 948, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
447 /* 0x32 - 1440x900@120Hz RB */
448 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
449 1520, 1600, 0, 900, 903, 909, 953, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
451 /* 0x53 - 1600x900@60Hz */
452 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
453 1704, 1800, 0, 900, 901, 904, 1000, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
455 /* 0x33 - 1600x1200@60Hz */
456 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
457 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x34 - 1600x1200@65Hz */
460 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
461 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x35 - 1600x1200@70Hz */
464 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
465 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x36 - 1600x1200@75Hz */
468 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
469 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 0x37 - 1600x1200@85Hz */
472 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
473 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x38 - 1600x1200@120Hz RB */
476 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
477 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
479 /* 0x39 - 1680x1050@60Hz RB */
480 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
481 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
483 /* 0x3a - 1680x1050@60Hz */
484 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
485 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x3b - 1680x1050@75Hz */
488 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
489 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
491 /* 0x3c - 1680x1050@85Hz */
492 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
493 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x3d - 1680x1050@120Hz RB */
496 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
497 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
499 /* 0x3e - 1792x1344@60Hz */
500 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
501 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
503 /* 0x3f - 1792x1344@75Hz */
504 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
505 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
507 /* 0x40 - 1792x1344@120Hz RB */
508 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
509 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
511 /* 0x41 - 1856x1392@60Hz */
512 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
513 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
515 /* 0x42 - 1856x1392@75Hz */
516 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
517 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
519 /* 0x43 - 1856x1392@120Hz RB */
520 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
521 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
523 /* 0x52 - 1920x1080@60Hz */
524 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
525 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
527 /* 0x44 - 1920x1200@60Hz RB */
528 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
529 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
531 /* 0x45 - 1920x1200@60Hz */
532 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
533 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
535 /* 0x46 - 1920x1200@75Hz */
536 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
537 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
539 /* 0x47 - 1920x1200@85Hz */
540 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
541 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
543 /* 0x48 - 1920x1200@120Hz RB */
544 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
545 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
547 /* 0x49 - 1920x1440@60Hz */
548 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
549 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
551 /* 0x4a - 1920x1440@75Hz */
552 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
553 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
555 /* 0x4b - 1920x1440@120Hz RB */
556 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
557 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
559 /* 0x54 - 2048x1152@60Hz */
560 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
561 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
563 /* 0x4c - 2560x1600@60Hz RB */
564 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
565 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
567 /* 0x4d - 2560x1600@60Hz */
568 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
569 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
571 /* 0x4e - 2560x1600@75Hz */
572 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
573 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
575 /* 0x4f - 2560x1600@85Hz */
576 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
577 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
579 /* 0x50 - 2560x1600@120Hz RB */
580 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
581 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
583 /* 0x57 - 4096x2160@60Hz RB */
584 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
585 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
587 /* 0x58 - 4096x2160@59.94Hz RB */
588 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
589 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
594 * These more or less come from the DMT spec. The 720x400 modes are
595 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
596 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
597 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
600 * The DMT modes have been fact-checked; the rest are mild guesses.
602 static const struct drm_display_mode edid_est_modes[] = {
603 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
604 968, 1056, 0, 600, 601, 605, 628, 0,
605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
606 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
607 896, 1024, 0, 600, 601, 603, 625, 0,
608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
609 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
610 720, 840, 0, 480, 481, 484, 500, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
613 704, 832, 0, 480, 489, 492, 520, 0,
614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
616 768, 864, 0, 480, 483, 486, 525, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
619 752, 800, 0, 480, 490, 492, 525, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
621 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
622 846, 900, 0, 400, 421, 423, 449, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
624 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
625 846, 900, 0, 400, 412, 414, 449, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
627 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
628 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
630 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
631 1136, 1312, 0, 768, 769, 772, 800, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
633 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
634 1184, 1328, 0, 768, 771, 777, 806, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
637 1184, 1344, 0, 768, 771, 777, 806, 0,
638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
639 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
640 1208, 1264, 0, 768, 768, 776, 817, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
642 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
643 928, 1152, 0, 624, 625, 628, 667, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
645 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
646 896, 1056, 0, 600, 601, 604, 625, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
648 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
649 976, 1040, 0, 600, 637, 643, 666, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
651 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
652 1344, 1600, 0, 864, 865, 868, 900, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
663 static const struct minimode est3_modes[] = {
671 { 1024, 768, 85, 0 },
672 { 1152, 864, 75, 0 },
674 { 1280, 768, 60, 1 },
675 { 1280, 768, 60, 0 },
676 { 1280, 768, 75, 0 },
677 { 1280, 768, 85, 0 },
678 { 1280, 960, 60, 0 },
679 { 1280, 960, 85, 0 },
680 { 1280, 1024, 60, 0 },
681 { 1280, 1024, 85, 0 },
683 { 1360, 768, 60, 0 },
684 { 1440, 900, 60, 1 },
685 { 1440, 900, 60, 0 },
686 { 1440, 900, 75, 0 },
687 { 1440, 900, 85, 0 },
688 { 1400, 1050, 60, 1 },
689 { 1400, 1050, 60, 0 },
690 { 1400, 1050, 75, 0 },
692 { 1400, 1050, 85, 0 },
693 { 1680, 1050, 60, 1 },
694 { 1680, 1050, 60, 0 },
695 { 1680, 1050, 75, 0 },
696 { 1680, 1050, 85, 0 },
697 { 1600, 1200, 60, 0 },
698 { 1600, 1200, 65, 0 },
699 { 1600, 1200, 70, 0 },
701 { 1600, 1200, 75, 0 },
702 { 1600, 1200, 85, 0 },
703 { 1792, 1344, 60, 0 },
704 { 1792, 1344, 75, 0 },
705 { 1856, 1392, 60, 0 },
706 { 1856, 1392, 75, 0 },
707 { 1920, 1200, 60, 1 },
708 { 1920, 1200, 60, 0 },
710 { 1920, 1200, 75, 0 },
711 { 1920, 1200, 85, 0 },
712 { 1920, 1440, 60, 0 },
713 { 1920, 1440, 75, 0 },
716 static const struct minimode extra_modes[] = {
717 { 1024, 576, 60, 0 },
718 { 1366, 768, 60, 0 },
719 { 1600, 900, 60, 0 },
720 { 1680, 945, 60, 0 },
721 { 1920, 1080, 60, 0 },
722 { 2048, 1152, 60, 0 },
723 { 2048, 1536, 60, 0 },
727 * From CEA/CTA-861 spec.
729 * Do not access directly, instead always use cea_mode_for_vic().
731 static const struct drm_display_mode edid_cea_modes_1[] = {
732 /* 1 - 640x480@60Hz 4:3 */
733 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
734 752, 800, 0, 480, 490, 492, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
737 /* 2 - 720x480@60Hz 4:3 */
738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
742 /* 3 - 720x480@60Hz 16:9 */
743 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
744 798, 858, 0, 480, 489, 495, 525, 0,
745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
747 /* 4 - 1280x720@60Hz 16:9 */
748 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
749 1430, 1650, 0, 720, 725, 730, 750, 0,
750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
751 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
752 /* 5 - 1920x1080i@60Hz 16:9 */
753 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
754 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
756 DRM_MODE_FLAG_INTERLACE),
757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
758 /* 6 - 720(1440)x480i@60Hz 4:3 */
759 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
760 801, 858, 0, 480, 488, 494, 525, 0,
761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
762 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
764 /* 7 - 720(1440)x480i@60Hz 16:9 */
765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 480, 488, 494, 525, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
770 /* 8 - 720(1440)x240@60Hz 4:3 */
771 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
772 801, 858, 0, 240, 244, 247, 262, 0,
773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
774 DRM_MODE_FLAG_DBLCLK),
775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
776 /* 9 - 720(1440)x240@60Hz 16:9 */
777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 240, 244, 247, 262, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780 DRM_MODE_FLAG_DBLCLK),
781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
782 /* 10 - 2880x480i@60Hz 4:3 */
783 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 480, 488, 494, 525, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
786 DRM_MODE_FLAG_INTERLACE),
787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
788 /* 11 - 2880x480i@60Hz 16:9 */
789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790 3204, 3432, 0, 480, 488, 494, 525, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
792 DRM_MODE_FLAG_INTERLACE),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
794 /* 12 - 2880x240@60Hz 4:3 */
795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
799 /* 13 - 2880x240@60Hz 16:9 */
800 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
801 3204, 3432, 0, 240, 244, 247, 262, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
804 /* 14 - 1440x480@60Hz 4:3 */
805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
809 /* 15 - 1440x480@60Hz 16:9 */
810 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
811 1596, 1716, 0, 480, 489, 495, 525, 0,
812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 16 - 1920x1080@60Hz 16:9 */
815 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
816 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
819 /* 17 - 720x576@50Hz 4:3 */
820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
824 /* 18 - 720x576@50Hz 16:9 */
825 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
826 796, 864, 0, 576, 581, 586, 625, 0,
827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 19 - 1280x720@50Hz 16:9 */
830 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
831 1760, 1980, 0, 720, 725, 730, 750, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
833 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
834 /* 20 - 1920x1080i@50Hz 16:9 */
835 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
836 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
838 DRM_MODE_FLAG_INTERLACE),
839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
840 /* 21 - 720(1440)x576i@50Hz 4:3 */
841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
842 795, 864, 0, 576, 580, 586, 625, 0,
843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
846 /* 22 - 720(1440)x576i@50Hz 16:9 */
847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 576, 580, 586, 625, 0,
849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
852 /* 23 - 720(1440)x288@50Hz 4:3 */
853 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
854 795, 864, 0, 288, 290, 293, 312, 0,
855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
856 DRM_MODE_FLAG_DBLCLK),
857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
858 /* 24 - 720(1440)x288@50Hz 16:9 */
859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 288, 290, 293, 312, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_DBLCLK),
863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
864 /* 25 - 2880x576i@50Hz 4:3 */
865 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 576, 580, 586, 625, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
868 DRM_MODE_FLAG_INTERLACE),
869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
870 /* 26 - 2880x576i@50Hz 16:9 */
871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872 3180, 3456, 0, 576, 580, 586, 625, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
874 DRM_MODE_FLAG_INTERLACE),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
876 /* 27 - 2880x288@50Hz 4:3 */
877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
881 /* 28 - 2880x288@50Hz 16:9 */
882 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
883 3180, 3456, 0, 288, 290, 293, 312, 0,
884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
886 /* 29 - 1440x576@50Hz 4:3 */
887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
891 /* 30 - 1440x576@50Hz 16:9 */
892 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
893 1592, 1728, 0, 576, 581, 586, 625, 0,
894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
896 /* 31 - 1920x1080@50Hz 16:9 */
897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
898 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 32 - 1920x1080@24Hz 16:9 */
902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
903 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
906 /* 33 - 1920x1080@25Hz 16:9 */
907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
908 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
911 /* 34 - 1920x1080@30Hz 16:9 */
912 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
913 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
916 /* 35 - 2880x480@60Hz 4:3 */
917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
921 /* 36 - 2880x480@60Hz 16:9 */
922 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
923 3192, 3432, 0, 480, 489, 495, 525, 0,
924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
926 /* 37 - 2880x576@50Hz 4:3 */
927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
931 /* 38 - 2880x576@50Hz 16:9 */
932 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
933 3184, 3456, 0, 576, 581, 586, 625, 0,
934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
935 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
936 /* 39 - 1920x1080i@50Hz 16:9 */
937 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
938 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
940 DRM_MODE_FLAG_INTERLACE),
941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
942 /* 40 - 1920x1080i@100Hz 16:9 */
943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
944 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
946 DRM_MODE_FLAG_INTERLACE),
947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 41 - 1280x720@100Hz 16:9 */
949 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
950 1760, 1980, 0, 720, 725, 730, 750, 0,
951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
953 /* 42 - 720x576@100Hz 4:3 */
954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
958 /* 43 - 720x576@100Hz 16:9 */
959 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 796, 864, 0, 576, 581, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
963 /* 44 - 720(1440)x576i@100Hz 4:3 */
964 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
965 795, 864, 0, 576, 580, 586, 625, 0,
966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
969 /* 45 - 720(1440)x576i@100Hz 16:9 */
970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
971 795, 864, 0, 576, 580, 586, 625, 0,
972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
975 /* 46 - 1920x1080i@120Hz 16:9 */
976 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
977 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
979 DRM_MODE_FLAG_INTERLACE),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 47 - 1280x720@120Hz 16:9 */
982 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
983 1430, 1650, 0, 720, 725, 730, 750, 0,
984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
986 /* 48 - 720x480@120Hz 4:3 */
987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
991 /* 49 - 720x480@120Hz 16:9 */
992 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
993 798, 858, 0, 480, 489, 495, 525, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
995 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
996 /* 50 - 720(1440)x480i@120Hz 4:3 */
997 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
998 801, 858, 0, 480, 488, 494, 525, 0,
999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1000 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1002 /* 51 - 720(1440)x480i@120Hz 16:9 */
1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1004 801, 858, 0, 480, 488, 494, 525, 0,
1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1008 /* 52 - 720x576@200Hz 4:3 */
1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1013 /* 53 - 720x576@200Hz 16:9 */
1014 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1015 796, 864, 0, 576, 581, 586, 625, 0,
1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1018 /* 54 - 720(1440)x576i@200Hz 4:3 */
1019 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1020 795, 864, 0, 576, 580, 586, 625, 0,
1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1022 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1024 /* 55 - 720(1440)x576i@200Hz 16:9 */
1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1026 795, 864, 0, 576, 580, 586, 625, 0,
1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1030 /* 56 - 720x480@240Hz 4:3 */
1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1035 /* 57 - 720x480@240Hz 16:9 */
1036 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1037 798, 858, 0, 480, 489, 495, 525, 0,
1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1040 /* 58 - 720(1440)x480i@240Hz 4:3 */
1041 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1042 801, 858, 0, 480, 488, 494, 525, 0,
1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1044 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1046 /* 59 - 720(1440)x480i@240Hz 16:9 */
1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1048 801, 858, 0, 480, 488, 494, 525, 0,
1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1052 /* 60 - 1280x720@24Hz 16:9 */
1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1054 3080, 3300, 0, 720, 725, 730, 750, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1057 /* 61 - 1280x720@25Hz 16:9 */
1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1059 3740, 3960, 0, 720, 725, 730, 750, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1062 /* 62 - 1280x720@30Hz 16:9 */
1063 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1064 3080, 3300, 0, 720, 725, 730, 750, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1067 /* 63 - 1920x1080@120Hz 16:9 */
1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1069 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1072 /* 64 - 1920x1080@100Hz 16:9 */
1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1074 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1077 /* 65 - 1280x720@24Hz 64:27 */
1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1079 3080, 3300, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 66 - 1280x720@25Hz 64:27 */
1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1084 3740, 3960, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 67 - 1280x720@30Hz 64:27 */
1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1089 3080, 3300, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 68 - 1280x720@50Hz 64:27 */
1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1094 1760, 1980, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 69 - 1280x720@60Hz 64:27 */
1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1099 1430, 1650, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 70 - 1280x720@100Hz 64:27 */
1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1104 1760, 1980, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 71 - 1280x720@120Hz 64:27 */
1108 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1109 1430, 1650, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 72 - 1920x1080@24Hz 64:27 */
1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1114 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 73 - 1920x1080@25Hz 64:27 */
1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1119 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 74 - 1920x1080@30Hz 64:27 */
1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1124 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 75 - 1920x1080@50Hz 64:27 */
1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1129 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 76 - 1920x1080@60Hz 64:27 */
1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1134 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 77 - 1920x1080@100Hz 64:27 */
1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1139 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 78 - 1920x1080@120Hz 64:27 */
1143 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1144 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 79 - 1680x720@24Hz 64:27 */
1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1149 3080, 3300, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 80 - 1680x720@25Hz 64:27 */
1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1154 2948, 3168, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 81 - 1680x720@30Hz 64:27 */
1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1159 2420, 2640, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1162 /* 82 - 1680x720@50Hz 64:27 */
1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1167 /* 83 - 1680x720@60Hz 64:27 */
1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1169 1980, 2200, 0, 720, 725, 730, 750, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1172 /* 84 - 1680x720@100Hz 64:27 */
1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1177 /* 85 - 1680x720@120Hz 64:27 */
1178 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1179 1780, 2000, 0, 720, 725, 730, 825, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1182 /* 86 - 2560x1080@24Hz 64:27 */
1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1184 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1187 /* 87 - 2560x1080@25Hz 64:27 */
1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1189 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1192 /* 88 - 2560x1080@30Hz 64:27 */
1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1194 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1197 /* 89 - 2560x1080@50Hz 64:27 */
1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1199 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1202 /* 90 - 2560x1080@60Hz 64:27 */
1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1204 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1207 /* 91 - 2560x1080@100Hz 64:27 */
1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1209 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1212 /* 92 - 2560x1080@120Hz 64:27 */
1213 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1214 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1217 /* 93 - 3840x2160@24Hz 16:9 */
1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1219 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1222 /* 94 - 3840x2160@25Hz 16:9 */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1224 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1227 /* 95 - 3840x2160@30Hz 16:9 */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1229 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1232 /* 96 - 3840x2160@50Hz 16:9 */
1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1234 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1237 /* 97 - 3840x2160@60Hz 16:9 */
1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1239 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1242 /* 98 - 4096x2160@24Hz 256:135 */
1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1244 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1247 /* 99 - 4096x2160@25Hz 256:135 */
1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1249 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1252 /* 100 - 4096x2160@30Hz 256:135 */
1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1254 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1257 /* 101 - 4096x2160@50Hz 256:135 */
1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1259 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1262 /* 102 - 4096x2160@60Hz 256:135 */
1263 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1264 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1267 /* 103 - 3840x2160@24Hz 64:27 */
1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1269 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1272 /* 104 - 3840x2160@25Hz 64:27 */
1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1274 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1277 /* 105 - 3840x2160@30Hz 64:27 */
1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1279 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1282 /* 106 - 3840x2160@50Hz 64:27 */
1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1284 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1287 /* 107 - 3840x2160@60Hz 64:27 */
1288 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1289 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1292 /* 108 - 1280x720@48Hz 16:9 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1297 /* 109 - 1280x720@48Hz 64:27 */
1298 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1299 2280, 2500, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1302 /* 110 - 1680x720@48Hz 64:27 */
1303 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1304 2530, 2750, 0, 720, 725, 730, 750, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1307 /* 111 - 1920x1080@48Hz 16:9 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1312 /* 112 - 1920x1080@48Hz 64:27 */
1313 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1314 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1317 /* 113 - 2560x1080@48Hz 64:27 */
1318 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1319 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1322 /* 114 - 3840x2160@48Hz 16:9 */
1323 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1327 /* 115 - 4096x2160@48Hz 256:135 */
1328 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1332 /* 116 - 3840x2160@48Hz 64:27 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1334 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1337 /* 117 - 3840x2160@100Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1339 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1342 /* 118 - 3840x2160@120Hz 16:9 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1344 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1347 /* 119 - 3840x2160@100Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1349 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1352 /* 120 - 3840x2160@120Hz 64:27 */
1353 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1354 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1357 /* 121 - 5120x2160@24Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1359 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1362 /* 122 - 5120x2160@25Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1364 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1367 /* 123 - 5120x2160@30Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1369 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1372 /* 124 - 5120x2160@48Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1374 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1377 /* 125 - 5120x2160@50Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1379 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1382 /* 126 - 5120x2160@60Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1384 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1387 /* 127 - 5120x2160@100Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1389 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1395 * From CEA/CTA-861 spec.
1397 * Do not access directly, instead always use cea_mode_for_vic().
1399 static const struct drm_display_mode edid_cea_modes_193[] = {
1400 /* 193 - 5120x2160@120Hz 64:27 */
1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1405 /* 194 - 7680x4320@24Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1407 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1410 /* 195 - 7680x4320@25Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1412 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1415 /* 196 - 7680x4320@30Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1417 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1420 /* 197 - 7680x4320@48Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1422 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1425 /* 198 - 7680x4320@50Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1427 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1430 /* 199 - 7680x4320@60Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1432 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1435 /* 200 - 7680x4320@100Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1437 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1440 /* 201 - 7680x4320@120Hz 16:9 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1442 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1445 /* 202 - 7680x4320@24Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1447 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1450 /* 203 - 7680x4320@25Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1452 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1455 /* 204 - 7680x4320@30Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1457 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1460 /* 205 - 7680x4320@48Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1462 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1465 /* 206 - 7680x4320@50Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1467 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1470 /* 207 - 7680x4320@60Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1472 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1475 /* 208 - 7680x4320@100Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1477 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1480 /* 209 - 7680x4320@120Hz 64:27 */
1481 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1482 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1485 /* 210 - 10240x4320@24Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1487 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1490 /* 211 - 10240x4320@25Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1492 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1495 /* 212 - 10240x4320@30Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1497 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1500 /* 213 - 10240x4320@48Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1502 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1505 /* 214 - 10240x4320@50Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1507 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1510 /* 215 - 10240x4320@60Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1512 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1515 /* 216 - 10240x4320@100Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1517 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1520 /* 217 - 10240x4320@120Hz 64:27 */
1521 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1522 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1525 /* 218 - 4096x2160@100Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1527 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1530 /* 219 - 4096x2160@120Hz 256:135 */
1531 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1532 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1538 * HDMI 1.4 4k modes. Index using the VIC.
1540 static const struct drm_display_mode edid_4k_modes[] = {
1541 /* 0 - dummy, VICs start at 1 */
1543 /* 1 - 3840x2160@30Hz */
1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1545 3840, 4016, 4104, 4400, 0,
1546 2160, 2168, 2178, 2250, 0,
1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1548 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1549 /* 2 - 3840x2160@25Hz */
1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551 3840, 4896, 4984, 5280, 0,
1552 2160, 2168, 2178, 2250, 0,
1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1555 /* 3 - 3840x2160@24Hz */
1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1557 3840, 5116, 5204, 5500, 0,
1558 2160, 2168, 2178, 2250, 0,
1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1561 /* 4 - 4096x2160@24Hz (SMPTE) */
1562 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 4096, 5116, 5204, 5500, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1569 /*** DDC fetch and block validation ***/
1571 static const u8 edid_header[] = {
1572 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1575 static void edid_header_fix(void *edid)
1577 memcpy(edid, edid_header, sizeof(edid_header));
1581 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1582 * @raw_edid: pointer to raw base EDID block
1584 * Sanity check the header of the base EDID block.
1586 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1588 int drm_edid_header_is_valid(const void *_edid)
1590 const struct edid *edid = _edid;
1593 for (i = 0; i < sizeof(edid_header); i++) {
1594 if (edid->header[i] == edid_header[i])
1600 EXPORT_SYMBOL(drm_edid_header_is_valid);
1602 static int edid_fixup __read_mostly = 6;
1603 module_param_named(edid_fixup, edid_fixup, int, 0400);
1604 MODULE_PARM_DESC(edid_fixup,
1605 "Minimum number of valid EDID header bytes (0-8, default 6)");
1607 static int edid_block_compute_checksum(const void *_block)
1609 const u8 *block = _block;
1611 u8 csum = 0, crc = 0;
1613 for (i = 0; i < EDID_LENGTH - 1; i++)
1621 static int edid_block_get_checksum(const void *_block)
1623 const struct edid *block = _block;
1625 return block->checksum;
1628 static int edid_block_tag(const void *_block)
1630 const u8 *block = _block;
1635 static bool edid_is_zero(const void *edid, int length)
1637 return !memchr_inv(edid, 0, length);
1641 * drm_edid_are_equal - compare two edid blobs.
1642 * @edid1: pointer to first blob
1643 * @edid2: pointer to second blob
1644 * This helper can be used during probing to determine if
1647 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1649 int edid1_len, edid2_len;
1650 bool edid1_present = edid1 != NULL;
1651 bool edid2_present = edid2 != NULL;
1653 if (edid1_present != edid2_present)
1657 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1658 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1660 if (edid1_len != edid2_len)
1663 if (memcmp(edid1, edid2, edid1_len))
1669 EXPORT_SYMBOL(drm_edid_are_equal);
1671 enum edid_block_status {
1674 EDID_BLOCK_HEADER_CORRUPT,
1675 EDID_BLOCK_HEADER_REPAIR,
1676 EDID_BLOCK_HEADER_FIXED,
1677 EDID_BLOCK_CHECKSUM,
1681 static enum edid_block_status edid_block_check(const void *_block,
1684 const struct edid *block = _block;
1687 return EDID_BLOCK_NULL;
1689 if (is_base_block) {
1690 int score = drm_edid_header_is_valid(block);
1692 if (score < clamp(edid_fixup, 0, 8))
1693 return EDID_BLOCK_HEADER_CORRUPT;
1696 return EDID_BLOCK_HEADER_REPAIR;
1699 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block))
1700 return EDID_BLOCK_CHECKSUM;
1702 if (is_base_block) {
1703 if (block->version != 1)
1704 return EDID_BLOCK_VERSION;
1707 return EDID_BLOCK_OK;
1710 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1712 return status == EDID_BLOCK_OK ||
1713 status == EDID_BLOCK_HEADER_FIXED ||
1714 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1717 static bool edid_block_valid(const void *block, bool base)
1719 return edid_block_status_valid(edid_block_check(block, base),
1720 edid_block_tag(block));
1724 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1725 * @raw_edid: pointer to raw EDID block
1726 * @block_num: type of block to validate (0 for base, extension otherwise)
1727 * @print_bad_edid: if true, dump bad EDID blocks to the console
1728 * @edid_corrupt: if true, the header or checksum is invalid
1730 * Validate a base or extension EDID block and optionally dump bad blocks to
1733 * Return: True if the block is valid, false otherwise.
1735 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1738 struct edid *block = (struct edid *)_block;
1739 enum edid_block_status status;
1740 bool is_base_block = block_num == 0;
1743 if (WARN_ON(!block))
1746 status = edid_block_check(block, is_base_block);
1747 if (status == EDID_BLOCK_HEADER_REPAIR) {
1748 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1749 edid_header_fix(block);
1751 /* Retry with fixed header, update status if that worked. */
1752 status = edid_block_check(block, is_base_block);
1753 if (status == EDID_BLOCK_OK)
1754 status = EDID_BLOCK_HEADER_FIXED;
1759 * Unknown major version isn't corrupt but we can't use it. Only
1760 * the base block can reset edid_corrupt to false.
1762 if (is_base_block &&
1763 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
1764 *edid_corrupt = false;
1765 else if (status != EDID_BLOCK_OK)
1766 *edid_corrupt = true;
1769 /* Determine whether we can use this block with this status. */
1770 valid = edid_block_status_valid(status, edid_block_tag(block));
1772 /* Some fairly random status printouts. */
1773 if (status == EDID_BLOCK_CHECKSUM) {
1775 DRM_DEBUG("EDID block checksum is invalid, remainder is %d\n",
1776 edid_block_compute_checksum(block));
1777 DRM_DEBUG("Assuming a KVM switch modified the block but left the original checksum\n");
1778 } else if (print_bad_edid) {
1779 DRM_NOTE("EDID block checksum is invalid, remainder is %d\n",
1780 edid_block_compute_checksum(block));
1782 } else if (status == EDID_BLOCK_VERSION) {
1783 DRM_NOTE("EDID has major version %d, instead of 1\n",
1787 if (!valid && print_bad_edid) {
1788 if (edid_is_zero(block, EDID_LENGTH)) {
1789 pr_notice("EDID block is all zeroes\n");
1791 pr_notice("Raw EDID:\n");
1792 print_hex_dump(KERN_NOTICE,
1793 " \t", DUMP_PREFIX_NONE, 16, 1,
1794 block, EDID_LENGTH, false);
1800 EXPORT_SYMBOL(drm_edid_block_valid);
1803 * drm_edid_is_valid - sanity check EDID data
1806 * Sanity-check an entire EDID record (including extensions)
1808 * Return: True if the EDID data is valid, false otherwise.
1810 bool drm_edid_is_valid(struct edid *edid)
1813 u8 *raw = (u8 *)edid;
1818 for (i = 0; i <= edid->extensions; i++)
1819 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1824 EXPORT_SYMBOL(drm_edid_is_valid);
1826 static struct edid *edid_filter_invalid_blocks(const struct edid *edid,
1829 struct edid *new, *dest_block;
1830 int valid_extensions = edid->extensions - invalid_blocks;
1833 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, GFP_KERNEL);
1838 for (i = 0; i <= edid->extensions; i++) {
1839 const void *block = edid + i;
1841 if (edid_block_valid(block, i == 0))
1842 memcpy(dest_block++, block, EDID_LENGTH);
1845 new->extensions = valid_extensions;
1846 new->checksum = edid_block_compute_checksum(new);
1854 #define DDC_SEGMENT_ADDR 0x30
1856 * drm_do_probe_ddc_edid() - get EDID information via I2C
1857 * @data: I2C device adapter
1858 * @buf: EDID data buffer to be filled
1859 * @block: 128 byte EDID block to start fetching from
1860 * @len: EDID data buffer length to fetch
1862 * Try to fetch EDID information by calling I2C driver functions.
1864 * Return: 0 on success or -1 on failure.
1867 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1869 struct i2c_adapter *adapter = data;
1870 unsigned char start = block * EDID_LENGTH;
1871 unsigned char segment = block >> 1;
1872 unsigned char xfers = segment ? 3 : 2;
1873 int ret, retries = 5;
1876 * The core I2C driver will automatically retry the transfer if the
1877 * adapter reports EAGAIN. However, we find that bit-banging transfers
1878 * are susceptible to errors under a heavily loaded machine and
1879 * generate spurious NAKs and timeouts. Retrying the transfer
1880 * of the individual block a few times seems to overcome this.
1883 struct i2c_msg msgs[] = {
1885 .addr = DDC_SEGMENT_ADDR,
1903 * Avoid sending the segment addr to not upset non-compliant
1906 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1908 if (ret == -ENXIO) {
1909 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1913 } while (ret != xfers && --retries);
1915 return ret == xfers ? 0 : -1;
1918 static void connector_bad_edid(struct drm_connector *connector,
1919 u8 *edid, int num_blocks)
1925 * 0x7e in the EDID is the number of extension blocks. The EDID
1926 * is 1 (base block) + num_ext_blocks big. That means we can think
1927 * of 0x7e in the EDID of the _index_ of the last block in the
1928 * combined chunk of memory.
1930 last_block = edid[0x7e];
1932 /* Calculate real checksum for the last edid extension block data */
1933 if (last_block < num_blocks)
1934 connector->real_edid_checksum =
1935 edid_block_compute_checksum(edid + last_block * EDID_LENGTH);
1937 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1940 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
1941 for (i = 0; i < num_blocks; i++) {
1942 u8 *block = edid + i * EDID_LENGTH;
1945 if (edid_is_zero(block, EDID_LENGTH))
1946 sprintf(prefix, "\t[%02x] ZERO ", i);
1947 else if (!drm_edid_block_valid(block, i, false, NULL))
1948 sprintf(prefix, "\t[%02x] BAD ", i);
1950 sprintf(prefix, "\t[%02x] GOOD ", i);
1952 print_hex_dump(KERN_DEBUG,
1953 prefix, DUMP_PREFIX_NONE, 16, 1,
1954 block, EDID_LENGTH, false);
1958 /* Get override or firmware EDID */
1959 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1961 struct edid *override = NULL;
1963 if (connector->override_edid)
1964 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1967 override = drm_load_edid_firmware(connector);
1969 return IS_ERR(override) ? NULL : override;
1973 * drm_add_override_edid_modes - add modes from override/firmware EDID
1974 * @connector: connector we're probing
1976 * Add modes from the override/firmware EDID, if available. Only to be used from
1977 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1978 * failed during drm_get_edid() and caused the override/firmware EDID to be
1981 * Return: The number of modes added or 0 if we couldn't find any.
1983 int drm_add_override_edid_modes(struct drm_connector *connector)
1985 struct edid *override;
1988 override = drm_get_override_edid(connector);
1990 drm_connector_update_edid_property(connector, override);
1991 num_modes = drm_add_edid_modes(connector, override);
1994 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1995 connector->base.id, connector->name, num_modes);
2000 EXPORT_SYMBOL(drm_add_override_edid_modes);
2002 static struct edid *drm_do_get_edid_base_block(struct drm_connector *connector,
2003 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
2007 int *null_edid_counter = connector ? &connector->null_edid_counter : NULL;
2008 bool *edid_corrupt = connector ? &connector->edid_corrupt : NULL;
2012 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
2016 /* base block fetch */
2017 for (try = 0; try < 4; try++) {
2018 if (get_edid_block(data, edid, 0, EDID_LENGTH))
2020 if (drm_edid_block_valid(edid, 0, false, edid_corrupt))
2022 if (try == 0 && edid_is_zero(edid, EDID_LENGTH)) {
2023 if (null_edid_counter)
2024 (*null_edid_counter)++;
2035 connector_bad_edid(connector, edid, 1);
2042 * drm_do_get_edid - get EDID data using a custom EDID block read function
2043 * @connector: connector we're probing
2044 * @get_edid_block: EDID block read function
2045 * @data: private data passed to the block read function
2047 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2048 * exposes a different interface to read EDID blocks this function can be used
2049 * to get EDID data using a custom block read function.
2051 * As in the general case the DDC bus is accessible by the kernel at the I2C
2052 * level, drivers must make all reasonable efforts to expose it as an I2C
2053 * adapter and use drm_get_edid() instead of abusing this function.
2055 * The EDID may be overridden using debugfs override_edid or firmware EDID
2056 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2057 * order. Having either of them bypasses actual EDID reads.
2059 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2061 struct edid *drm_do_get_edid(struct drm_connector *connector,
2062 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
2066 int j, invalid_blocks = 0;
2067 struct edid *edid, *new, *override;
2069 override = drm_get_override_edid(connector);
2073 edid = drm_do_get_edid_base_block(connector, get_edid_block, data);
2077 if (edid->extensions == 0)
2080 new = krealloc(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2085 for (j = 1; j <= edid->extensions; j++) {
2086 void *block = edid + j;
2089 for (try = 0; try < 4; try++) {
2090 if (get_edid_block(data, block, j, EDID_LENGTH))
2092 if (drm_edid_block_valid(block, j, false, NULL))
2100 if (invalid_blocks) {
2101 connector_bad_edid(connector, (u8 *)edid, edid->extensions + 1);
2103 edid = edid_filter_invalid_blocks(edid, invalid_blocks);
2112 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2115 * drm_probe_ddc() - probe DDC presence
2116 * @adapter: I2C adapter to probe
2118 * Return: True on success, false on failure.
2121 drm_probe_ddc(struct i2c_adapter *adapter)
2125 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2127 EXPORT_SYMBOL(drm_probe_ddc);
2130 * drm_get_edid - get EDID data, if available
2131 * @connector: connector we're probing
2132 * @adapter: I2C adapter to use for DDC
2134 * Poke the given I2C channel to grab EDID data if possible. If found,
2135 * attach it to the connector.
2137 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2139 struct edid *drm_get_edid(struct drm_connector *connector,
2140 struct i2c_adapter *adapter)
2144 if (connector->force == DRM_FORCE_OFF)
2147 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2150 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2151 drm_connector_update_edid_property(connector, edid);
2154 EXPORT_SYMBOL(drm_get_edid);
2156 static u32 edid_extract_panel_id(const struct edid *edid)
2159 * We represent the ID as a 32-bit number so it can easily be compared
2162 * NOTE that we deal with endianness differently for the top half
2163 * of this ID than for the bottom half. The bottom half (the product
2164 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2165 * that's how everyone seems to interpret it. The top half (the mfg_id)
2166 * gets stored as big endian because that makes
2167 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2168 * to write (it's easier to extract the ASCII). It doesn't really
2169 * matter, though, as long as the number here is unique.
2171 return (u32)edid->mfg_id[0] << 24 |
2172 (u32)edid->mfg_id[1] << 16 |
2173 (u32)EDID_PRODUCT_ID(edid);
2177 * drm_edid_get_panel_id - Get a panel's ID through DDC
2178 * @adapter: I2C adapter to use for DDC
2180 * This function reads the first block of the EDID of a panel and (assuming
2181 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2182 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2183 * supposed to be different for each different modem of panel.
2185 * This function is intended to be used during early probing on devices where
2186 * more than one panel might be present. Because of its intended use it must
2187 * assume that the EDID of the panel is correct, at least as far as the ID
2188 * is concerned (in other words, we don't process any overrides here).
2190 * NOTE: it's expected that this function and drm_do_get_edid() will both
2191 * be read the EDID, but there is no caching between them. Since we're only
2192 * reading the first block, hopefully this extra overhead won't be too big.
2194 * Return: A 32-bit ID that should be different for each make/model of panel.
2195 * See the functions drm_edid_encode_panel_id() and
2196 * drm_edid_decode_panel_id() for some details on the structure of this
2200 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2202 const struct edid *edid;
2205 edid = drm_do_get_edid_base_block(NULL, drm_do_probe_ddc_edid, adapter);
2208 * There are no manufacturer IDs of 0, so if there is a problem reading
2209 * the EDID then we'll just return 0.
2214 panel_id = edid_extract_panel_id(edid);
2219 EXPORT_SYMBOL(drm_edid_get_panel_id);
2222 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2223 * @connector: connector we're probing
2224 * @adapter: I2C adapter to use for DDC
2226 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2227 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2228 * switch DDC to the GPU which is retrieving EDID.
2230 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2232 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2233 struct i2c_adapter *adapter)
2235 struct drm_device *dev = connector->dev;
2236 struct pci_dev *pdev = to_pci_dev(dev->dev);
2239 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2242 vga_switcheroo_lock_ddc(pdev);
2243 edid = drm_get_edid(connector, adapter);
2244 vga_switcheroo_unlock_ddc(pdev);
2248 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2251 * drm_edid_duplicate - duplicate an EDID and the extensions
2252 * @edid: EDID to duplicate
2254 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2256 struct edid *drm_edid_duplicate(const struct edid *edid)
2258 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2260 EXPORT_SYMBOL(drm_edid_duplicate);
2262 /*** EDID parsing ***/
2265 * edid_get_quirks - return quirk flags for a given EDID
2266 * @edid: EDID to process
2268 * This tells subsequent routines what fixes they need to apply.
2270 static u32 edid_get_quirks(const struct edid *edid)
2272 u32 panel_id = edid_extract_panel_id(edid);
2273 const struct edid_quirk *quirk;
2276 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2277 quirk = &edid_quirk_list[i];
2278 if (quirk->panel_id == panel_id)
2279 return quirk->quirks;
2285 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2286 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2289 * edid_fixup_preferred - set preferred modes based on quirk list
2290 * @connector: has mode list to fix up
2291 * @quirks: quirks list
2293 * Walk the mode list for @connector, clearing the preferred status
2294 * on existing modes and setting it anew for the right mode ala @quirks.
2296 static void edid_fixup_preferred(struct drm_connector *connector,
2299 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2300 int target_refresh = 0;
2301 int cur_vrefresh, preferred_vrefresh;
2303 if (list_empty(&connector->probed_modes))
2306 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2307 target_refresh = 60;
2308 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2309 target_refresh = 75;
2311 preferred_mode = list_first_entry(&connector->probed_modes,
2312 struct drm_display_mode, head);
2314 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2315 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2317 if (cur_mode == preferred_mode)
2320 /* Largest mode is preferred */
2321 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2322 preferred_mode = cur_mode;
2324 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2325 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2326 /* At a given size, try to get closest to target refresh */
2327 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2328 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2329 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2330 preferred_mode = cur_mode;
2334 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2338 mode_is_rb(const struct drm_display_mode *mode)
2340 return (mode->htotal - mode->hdisplay == 160) &&
2341 (mode->hsync_end - mode->hdisplay == 80) &&
2342 (mode->hsync_end - mode->hsync_start == 32) &&
2343 (mode->vsync_start - mode->vdisplay == 3);
2347 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2348 * @dev: Device to duplicate against
2349 * @hsize: Mode width
2350 * @vsize: Mode height
2351 * @fresh: Mode refresh rate
2352 * @rb: Mode reduced-blanking-ness
2354 * Walk the DMT mode list looking for a match for the given parameters.
2356 * Return: A newly allocated copy of the mode, or NULL if not found.
2358 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2359 int hsize, int vsize, int fresh,
2364 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2365 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2367 if (hsize != ptr->hdisplay)
2369 if (vsize != ptr->vdisplay)
2371 if (fresh != drm_mode_vrefresh(ptr))
2373 if (rb != mode_is_rb(ptr))
2376 return drm_mode_duplicate(dev, ptr);
2381 EXPORT_SYMBOL(drm_mode_find_dmt);
2383 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
2385 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2386 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2387 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2389 return descriptor->pixel_clock == 0 &&
2390 descriptor->data.other_data.pad1 == 0 &&
2391 descriptor->data.other_data.type == type;
2394 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
2396 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2398 return descriptor->pixel_clock != 0;
2401 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
2404 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2408 const u8 *det_base = ext + d;
2410 if (d < 4 || d > 127)
2414 for (i = 0; i < n; i++)
2415 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2419 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2421 unsigned int i, n = min((int)ext[0x02], 6);
2422 const u8 *det_base = ext + 5;
2425 return; /* unknown version */
2427 for (i = 0; i < n; i++)
2428 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2432 drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void *closure)
2439 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2440 cb(&(edid->detailed_timings[i]), closure);
2442 for (i = 1; i <= edid->extensions; i++) {
2443 const u8 *ext = (const u8 *)edid + (i * EDID_LENGTH);
2447 cea_for_each_detailed_block(ext, cb, closure);
2450 vtb_for_each_detailed_block(ext, cb, closure);
2459 is_rb(const struct detailed_timing *descriptor, void *data)
2463 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2466 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2467 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2469 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2470 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2474 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2476 drm_monitor_supports_rb(const struct edid *edid)
2478 if (edid->revision >= 4) {
2481 drm_for_each_detailed_block(edid, is_rb, &ret);
2485 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2489 find_gtf2(const struct detailed_timing *descriptor, void *data)
2491 const struct detailed_timing **res = data;
2493 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2496 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2498 if (descriptor->data.other_data.data.range.flags == 0x02)
2502 /* Secondary GTF curve kicks in above some break frequency */
2504 drm_gtf2_hbreak(const struct edid *edid)
2506 const struct detailed_timing *descriptor = NULL;
2508 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2510 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
2512 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
2516 drm_gtf2_2c(const struct edid *edid)
2518 const struct detailed_timing *descriptor = NULL;
2520 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2522 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
2524 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
2528 drm_gtf2_m(const struct edid *edid)
2530 const struct detailed_timing *descriptor = NULL;
2532 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2534 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
2536 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
2540 drm_gtf2_k(const struct edid *edid)
2542 const struct detailed_timing *descriptor = NULL;
2544 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2546 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
2548 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
2552 drm_gtf2_2j(const struct edid *edid)
2554 const struct detailed_timing *descriptor = NULL;
2556 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2558 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
2560 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
2564 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2565 * @edid: EDID block to scan
2567 static int standard_timing_level(const struct edid *edid)
2569 if (edid->revision >= 2) {
2570 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2572 if (drm_gtf2_hbreak(edid))
2574 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2581 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2582 * monitors fill with ascii space (0x20) instead.
2585 bad_std_timing(u8 a, u8 b)
2587 return (a == 0x00 && b == 0x00) ||
2588 (a == 0x01 && b == 0x01) ||
2589 (a == 0x20 && b == 0x20);
2592 static int drm_mode_hsync(const struct drm_display_mode *mode)
2594 if (mode->htotal <= 0)
2597 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2601 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2602 * @connector: connector of for the EDID block
2603 * @edid: EDID block to scan
2604 * @t: standard timing params
2606 * Take the standard timing params (in this case width, aspect, and refresh)
2607 * and convert them into a real mode using CVT/GTF/DMT.
2609 static struct drm_display_mode *
2610 drm_mode_std(struct drm_connector *connector, const struct edid *edid,
2611 const struct std_timing *t)
2613 struct drm_device *dev = connector->dev;
2614 struct drm_display_mode *m, *mode = NULL;
2617 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2618 >> EDID_TIMING_ASPECT_SHIFT;
2619 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2620 >> EDID_TIMING_VFREQ_SHIFT;
2621 int timing_level = standard_timing_level(edid);
2623 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2626 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2627 hsize = t->hsize * 8 + 248;
2628 /* vrefresh_rate = vfreq + 60 */
2629 vrefresh_rate = vfreq + 60;
2630 /* the vdisplay is calculated based on the aspect ratio */
2631 if (aspect_ratio == 0) {
2632 if (edid->revision < 3)
2635 vsize = (hsize * 10) / 16;
2636 } else if (aspect_ratio == 1)
2637 vsize = (hsize * 3) / 4;
2638 else if (aspect_ratio == 2)
2639 vsize = (hsize * 4) / 5;
2641 vsize = (hsize * 9) / 16;
2643 /* HDTV hack, part 1 */
2644 if (vrefresh_rate == 60 &&
2645 ((hsize == 1360 && vsize == 765) ||
2646 (hsize == 1368 && vsize == 769))) {
2652 * If this connector already has a mode for this size and refresh
2653 * rate (because it came from detailed or CVT info), use that
2654 * instead. This way we don't have to guess at interlace or
2657 list_for_each_entry(m, &connector->probed_modes, head)
2658 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2659 drm_mode_vrefresh(m) == vrefresh_rate)
2662 /* HDTV hack, part 2 */
2663 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2664 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2668 mode->hdisplay = 1366;
2669 mode->hsync_start = mode->hsync_start - 1;
2670 mode->hsync_end = mode->hsync_end - 1;
2674 /* check whether it can be found in default mode table */
2675 if (drm_monitor_supports_rb(edid)) {
2676 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2681 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2685 /* okay, generate it */
2686 switch (timing_level) {
2690 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2694 * This is potentially wrong if there's ever a monitor with
2695 * more than one ranges section, each claiming a different
2696 * secondary GTF curve. Please don't do that.
2698 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2701 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2702 drm_mode_destroy(dev, mode);
2703 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2704 vrefresh_rate, 0, 0,
2712 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2720 * EDID is delightfully ambiguous about how interlaced modes are to be
2721 * encoded. Our internal representation is of frame height, but some
2722 * HDTV detailed timings are encoded as field height.
2724 * The format list here is from CEA, in frame size. Technically we
2725 * should be checking refresh rate too. Whatever.
2728 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2729 const struct detailed_pixel_timing *pt)
2732 static const struct {
2734 } cea_interlaced[] = {
2744 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2747 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2748 if ((mode->hdisplay == cea_interlaced[i].w) &&
2749 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2750 mode->vdisplay *= 2;
2751 mode->vsync_start *= 2;
2752 mode->vsync_end *= 2;
2758 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2762 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2763 * @dev: DRM device (needed to create new mode)
2765 * @timing: EDID detailed timing info
2766 * @quirks: quirks to apply
2768 * An EDID detailed timing block contains enough info for us to create and
2769 * return a new struct drm_display_mode.
2771 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2772 const struct edid *edid,
2773 const struct detailed_timing *timing,
2776 struct drm_display_mode *mode;
2777 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2778 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2779 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2780 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2781 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2782 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2783 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2784 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2785 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2787 /* ignore tiny modes */
2788 if (hactive < 64 || vactive < 64)
2791 if (pt->misc & DRM_EDID_PT_STEREO) {
2792 DRM_DEBUG_KMS("stereo mode not supported\n");
2795 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2796 DRM_DEBUG_KMS("composite sync not supported\n");
2799 /* it is incorrect if hsync/vsync width is zero */
2800 if (!hsync_pulse_width || !vsync_pulse_width) {
2801 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2802 "Wrong Hsync/Vsync pulse width\n");
2806 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2807 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2814 mode = drm_mode_create(dev);
2818 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2819 mode->clock = 1088 * 10;
2821 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2823 mode->hdisplay = hactive;
2824 mode->hsync_start = mode->hdisplay + hsync_offset;
2825 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2826 mode->htotal = mode->hdisplay + hblank;
2828 mode->vdisplay = vactive;
2829 mode->vsync_start = mode->vdisplay + vsync_offset;
2830 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2831 mode->vtotal = mode->vdisplay + vblank;
2833 /* Some EDIDs have bogus h/vtotal values */
2834 if (mode->hsync_end > mode->htotal)
2835 mode->htotal = mode->hsync_end + 1;
2836 if (mode->vsync_end > mode->vtotal)
2837 mode->vtotal = mode->vsync_end + 1;
2839 drm_mode_do_interlace_quirk(mode, pt);
2841 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2842 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
2844 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2845 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2846 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2847 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2851 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2852 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2854 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2855 mode->width_mm *= 10;
2856 mode->height_mm *= 10;
2859 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2860 mode->width_mm = edid->width_cm * 10;
2861 mode->height_mm = edid->height_cm * 10;
2864 mode->type = DRM_MODE_TYPE_DRIVER;
2865 drm_mode_set_name(mode);
2871 mode_in_hsync_range(const struct drm_display_mode *mode,
2872 const struct edid *edid, const u8 *t)
2874 int hsync, hmin, hmax;
2877 if (edid->revision >= 4)
2878 hmin += ((t[4] & 0x04) ? 255 : 0);
2880 if (edid->revision >= 4)
2881 hmax += ((t[4] & 0x08) ? 255 : 0);
2882 hsync = drm_mode_hsync(mode);
2884 return (hsync <= hmax && hsync >= hmin);
2888 mode_in_vsync_range(const struct drm_display_mode *mode,
2889 const struct edid *edid, const u8 *t)
2891 int vsync, vmin, vmax;
2894 if (edid->revision >= 4)
2895 vmin += ((t[4] & 0x01) ? 255 : 0);
2897 if (edid->revision >= 4)
2898 vmax += ((t[4] & 0x02) ? 255 : 0);
2899 vsync = drm_mode_vrefresh(mode);
2901 return (vsync <= vmax && vsync >= vmin);
2905 range_pixel_clock(const struct edid *edid, const u8 *t)
2908 if (t[9] == 0 || t[9] == 255)
2911 /* 1.4 with CVT support gives us real precision, yay */
2912 if (edid->revision >= 4 && t[10] == 0x04)
2913 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2915 /* 1.3 is pathetic, so fuzz up a bit */
2916 return t[9] * 10000 + 5001;
2920 mode_in_range(const struct drm_display_mode *mode, const struct edid *edid,
2921 const struct detailed_timing *timing)
2924 const u8 *t = (const u8 *)timing;
2926 if (!mode_in_hsync_range(mode, edid, t))
2929 if (!mode_in_vsync_range(mode, edid, t))
2932 if ((max_clock = range_pixel_clock(edid, t)))
2933 if (mode->clock > max_clock)
2936 /* 1.4 max horizontal check */
2937 if (edid->revision >= 4 && t[10] == 0x04)
2938 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2941 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2947 static bool valid_inferred_mode(const struct drm_connector *connector,
2948 const struct drm_display_mode *mode)
2950 const struct drm_display_mode *m;
2953 list_for_each_entry(m, &connector->probed_modes, head) {
2954 if (mode->hdisplay == m->hdisplay &&
2955 mode->vdisplay == m->vdisplay &&
2956 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2957 return false; /* duplicated */
2958 if (mode->hdisplay <= m->hdisplay &&
2959 mode->vdisplay <= m->vdisplay)
2966 drm_dmt_modes_for_range(struct drm_connector *connector, const struct edid *edid,
2967 const struct detailed_timing *timing)
2970 struct drm_display_mode *newmode;
2971 struct drm_device *dev = connector->dev;
2973 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2974 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2975 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2976 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2978 drm_mode_probed_add(connector, newmode);
2987 /* fix up 1366x768 mode from 1368x768;
2988 * GFT/CVT can't express 1366 width which isn't dividable by 8
2990 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2992 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2993 mode->hdisplay = 1366;
2994 mode->hsync_start--;
2996 drm_mode_set_name(mode);
3001 drm_gtf_modes_for_range(struct drm_connector *connector, const struct edid *edid,
3002 const struct detailed_timing *timing)
3005 struct drm_display_mode *newmode;
3006 struct drm_device *dev = connector->dev;
3008 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3009 const struct minimode *m = &extra_modes[i];
3011 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3015 drm_mode_fixup_1366x768(newmode);
3016 if (!mode_in_range(newmode, edid, timing) ||
3017 !valid_inferred_mode(connector, newmode)) {
3018 drm_mode_destroy(dev, newmode);
3022 drm_mode_probed_add(connector, newmode);
3030 drm_cvt_modes_for_range(struct drm_connector *connector, const struct edid *edid,
3031 const struct detailed_timing *timing)
3034 struct drm_display_mode *newmode;
3035 struct drm_device *dev = connector->dev;
3036 bool rb = drm_monitor_supports_rb(edid);
3038 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3039 const struct minimode *m = &extra_modes[i];
3041 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3045 drm_mode_fixup_1366x768(newmode);
3046 if (!mode_in_range(newmode, edid, timing) ||
3047 !valid_inferred_mode(connector, newmode)) {
3048 drm_mode_destroy(dev, newmode);
3052 drm_mode_probed_add(connector, newmode);
3060 do_inferred_modes(const struct detailed_timing *timing, void *c)
3062 struct detailed_mode_closure *closure = c;
3063 const struct detailed_non_pixel *data = &timing->data.other_data;
3064 const struct detailed_data_monitor_range *range = &data->data.range;
3066 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3069 closure->modes += drm_dmt_modes_for_range(closure->connector,
3073 if (!version_greater(closure->edid, 1, 1))
3074 return; /* GTF not defined yet */
3076 switch (range->flags) {
3077 case 0x02: /* secondary gtf, XXX could do more */
3078 case 0x00: /* default gtf */
3079 closure->modes += drm_gtf_modes_for_range(closure->connector,
3083 case 0x04: /* cvt, only in 1.4+ */
3084 if (!version_greater(closure->edid, 1, 3))
3087 closure->modes += drm_cvt_modes_for_range(closure->connector,
3091 case 0x01: /* just the ranges, no formula */
3098 add_inferred_modes(struct drm_connector *connector, const struct edid *edid)
3100 struct detailed_mode_closure closure = {
3101 .connector = connector,
3105 if (version_greater(edid, 1, 0))
3106 drm_for_each_detailed_block(edid, do_inferred_modes, &closure);
3108 return closure.modes;
3112 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3114 int i, j, m, modes = 0;
3115 struct drm_display_mode *mode;
3116 const u8 *est = ((const u8 *)timing) + 6;
3118 for (i = 0; i < 6; i++) {
3119 for (j = 7; j >= 0; j--) {
3120 m = (i * 8) + (7 - j);
3121 if (m >= ARRAY_SIZE(est3_modes))
3123 if (est[i] & (1 << j)) {
3124 mode = drm_mode_find_dmt(connector->dev,
3130 drm_mode_probed_add(connector, mode);
3141 do_established_modes(const struct detailed_timing *timing, void *c)
3143 struct detailed_mode_closure *closure = c;
3145 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3148 closure->modes += drm_est3_modes(closure->connector, timing);
3152 * add_established_modes - get est. modes from EDID and add them
3153 * @connector: connector to add mode(s) to
3154 * @edid: EDID block to scan
3156 * Each EDID block contains a bitmap of the supported "established modes" list
3157 * (defined above). Tease them out and add them to the global modes list.
3160 add_established_modes(struct drm_connector *connector, const struct edid *edid)
3162 struct drm_device *dev = connector->dev;
3163 unsigned long est_bits = edid->established_timings.t1 |
3164 (edid->established_timings.t2 << 8) |
3165 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3167 struct detailed_mode_closure closure = {
3168 .connector = connector,
3172 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3173 if (est_bits & (1<<i)) {
3174 struct drm_display_mode *newmode;
3176 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3178 drm_mode_probed_add(connector, newmode);
3184 if (version_greater(edid, 1, 0))
3185 drm_for_each_detailed_block(edid, do_established_modes,
3188 return modes + closure.modes;
3192 do_standard_modes(const struct detailed_timing *timing, void *c)
3194 struct detailed_mode_closure *closure = c;
3195 const struct detailed_non_pixel *data = &timing->data.other_data;
3196 struct drm_connector *connector = closure->connector;
3197 const struct edid *edid = closure->edid;
3200 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3203 for (i = 0; i < 6; i++) {
3204 const struct std_timing *std = &data->data.timings[i];
3205 struct drm_display_mode *newmode;
3207 newmode = drm_mode_std(connector, edid, std);
3209 drm_mode_probed_add(connector, newmode);
3216 * add_standard_modes - get std. modes from EDID and add them
3217 * @connector: connector to add mode(s) to
3218 * @edid: EDID block to scan
3220 * Standard modes can be calculated using the appropriate standard (DMT,
3221 * GTF or CVT. Grab them from @edid and add them to the list.
3224 add_standard_modes(struct drm_connector *connector, const struct edid *edid)
3227 struct detailed_mode_closure closure = {
3228 .connector = connector,
3232 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3233 struct drm_display_mode *newmode;
3235 newmode = drm_mode_std(connector, edid,
3236 &edid->standard_timings[i]);
3238 drm_mode_probed_add(connector, newmode);
3243 if (version_greater(edid, 1, 0))
3244 drm_for_each_detailed_block(edid, do_standard_modes,
3247 /* XXX should also look for standard codes in VTB blocks */
3249 return modes + closure.modes;
3252 static int drm_cvt_modes(struct drm_connector *connector,
3253 const struct detailed_timing *timing)
3255 int i, j, modes = 0;
3256 struct drm_display_mode *newmode;
3257 struct drm_device *dev = connector->dev;
3258 const struct cvt_timing *cvt;
3259 const int rates[] = { 60, 85, 75, 60, 50 };
3260 const u8 empty[3] = { 0, 0, 0 };
3262 for (i = 0; i < 4; i++) {
3265 cvt = &(timing->data.other_data.data.cvt[i]);
3267 if (!memcmp(cvt->code, empty, 3))
3270 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3271 switch (cvt->code[1] & 0x0c) {
3272 /* default - because compiler doesn't see that we've enumerated all cases */
3275 width = height * 4 / 3;
3278 width = height * 16 / 9;
3281 width = height * 16 / 10;
3284 width = height * 15 / 9;
3288 for (j = 1; j < 5; j++) {
3289 if (cvt->code[2] & (1 << j)) {
3290 newmode = drm_cvt_mode(dev, width, height,
3294 drm_mode_probed_add(connector, newmode);
3305 do_cvt_mode(const struct detailed_timing *timing, void *c)
3307 struct detailed_mode_closure *closure = c;
3309 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
3312 closure->modes += drm_cvt_modes(closure->connector, timing);
3316 add_cvt_modes(struct drm_connector *connector, const struct edid *edid)
3318 struct detailed_mode_closure closure = {
3319 .connector = connector,
3323 if (version_greater(edid, 1, 2))
3324 drm_for_each_detailed_block(edid, do_cvt_mode, &closure);
3326 /* XXX should also look for CVT codes in VTB blocks */
3328 return closure.modes;
3331 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3334 do_detailed_mode(const struct detailed_timing *timing, void *c)
3336 struct detailed_mode_closure *closure = c;
3337 struct drm_display_mode *newmode;
3339 if (!is_detailed_timing_descriptor(timing))
3342 newmode = drm_mode_detailed(closure->connector->dev,
3343 closure->edid, timing,
3348 if (closure->preferred)
3349 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3352 * Detailed modes are limited to 10kHz pixel clock resolution,
3353 * so fix up anything that looks like CEA/HDMI mode, but the clock
3354 * is just slightly off.
3356 fixup_detailed_cea_mode_clock(newmode);
3358 drm_mode_probed_add(closure->connector, newmode);
3360 closure->preferred = false;
3364 * add_detailed_modes - Add modes from detailed timings
3365 * @connector: attached connector
3366 * @edid: EDID block to scan
3367 * @quirks: quirks to apply
3370 add_detailed_modes(struct drm_connector *connector, const struct edid *edid,
3373 struct detailed_mode_closure closure = {
3374 .connector = connector,
3380 if (closure.preferred && !version_greater(edid, 1, 3))
3382 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3384 drm_for_each_detailed_block(edid, do_detailed_mode, &closure);
3386 return closure.modes;
3389 #define AUDIO_BLOCK 0x01
3390 #define VIDEO_BLOCK 0x02
3391 #define VENDOR_BLOCK 0x03
3392 #define SPEAKER_BLOCK 0x04
3393 #define HDR_STATIC_METADATA_BLOCK 0x6
3394 #define USE_EXTENDED_TAG 0x07
3395 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3396 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
3397 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3398 #define EDID_BASIC_AUDIO (1 << 6)
3399 #define EDID_CEA_YCRCB444 (1 << 5)
3400 #define EDID_CEA_YCRCB422 (1 << 4)
3401 #define EDID_CEA_VCDB_QS (1 << 6)
3404 * Search EDID for CEA extension block.
3406 const u8 *drm_find_edid_extension(const struct edid *edid,
3407 int ext_id, int *ext_index)
3409 const u8 *edid_ext = NULL;
3412 /* No EDID or EDID extensions */
3413 if (edid == NULL || edid->extensions == 0)
3416 /* Find CEA extension */
3417 for (i = *ext_index; i < edid->extensions; i++) {
3418 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1);
3419 if (edid_block_tag(edid_ext) == ext_id)
3423 if (i >= edid->extensions)
3431 static const u8 *drm_find_cea_extension(const struct edid *edid)
3433 const struct displayid_block *block;
3434 struct displayid_iter iter;
3438 /* Look for a top level CEA extension block */
3439 /* FIXME: make callers iterate through multiple CEA ext blocks? */
3440 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
3444 /* CEA blocks can also be found embedded in a DisplayID block */
3445 displayid_iter_edid_begin(edid, &iter);
3446 displayid_iter_for_each(block, &iter) {
3447 if (block->tag == DATA_BLOCK_CTA) {
3448 cea = (const u8 *)block;
3452 displayid_iter_end(&iter);
3457 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3459 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3460 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3462 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3463 return &edid_cea_modes_1[vic - 1];
3464 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3465 return &edid_cea_modes_193[vic - 193];
3469 static u8 cea_num_vics(void)
3471 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3474 static u8 cea_next_vic(u8 vic)
3476 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3482 * Calculate the alternate clock for the CEA mode
3483 * (60Hz vs. 59.94Hz etc.)
3486 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3488 unsigned int clock = cea_mode->clock;
3490 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3494 * edid_cea_modes contains the 59.94Hz
3495 * variant for 240 and 480 line modes,
3496 * and the 60Hz variant otherwise.
3498 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3499 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3501 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3507 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3510 * For certain VICs the spec allows the vertical
3511 * front porch to vary by one or two lines.
3513 * cea_modes[] stores the variant with the shortest
3514 * vertical front porch. We can adjust the mode to
3515 * get the other variants by simply increasing the
3516 * vertical front porch length.
3518 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3519 cea_mode_for_vic(9)->vtotal != 262 ||
3520 cea_mode_for_vic(12)->vtotal != 262 ||
3521 cea_mode_for_vic(13)->vtotal != 262 ||
3522 cea_mode_for_vic(23)->vtotal != 312 ||
3523 cea_mode_for_vic(24)->vtotal != 312 ||
3524 cea_mode_for_vic(27)->vtotal != 312 ||
3525 cea_mode_for_vic(28)->vtotal != 312);
3527 if (((vic == 8 || vic == 9 ||
3528 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3529 ((vic == 23 || vic == 24 ||
3530 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3531 mode->vsync_start++;
3541 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3542 unsigned int clock_tolerance)
3544 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3547 if (!to_match->clock)
3550 if (to_match->picture_aspect_ratio)
3551 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3553 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3554 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3555 unsigned int clock1, clock2;
3557 /* Check both 60Hz and 59.94Hz */
3558 clock1 = cea_mode.clock;
3559 clock2 = cea_mode_alternate_clock(&cea_mode);
3561 if (abs(to_match->clock - clock1) > clock_tolerance &&
3562 abs(to_match->clock - clock2) > clock_tolerance)
3566 if (drm_mode_match(to_match, &cea_mode, match_flags))
3568 } while (cea_mode_alternate_timings(vic, &cea_mode));
3575 * drm_match_cea_mode - look for a CEA mode matching given mode
3576 * @to_match: display mode
3578 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3581 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3583 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3586 if (!to_match->clock)
3589 if (to_match->picture_aspect_ratio)
3590 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3592 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3593 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3594 unsigned int clock1, clock2;
3596 /* Check both 60Hz and 59.94Hz */
3597 clock1 = cea_mode.clock;
3598 clock2 = cea_mode_alternate_clock(&cea_mode);
3600 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3601 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3605 if (drm_mode_match(to_match, &cea_mode, match_flags))
3607 } while (cea_mode_alternate_timings(vic, &cea_mode));
3612 EXPORT_SYMBOL(drm_match_cea_mode);
3614 static bool drm_valid_cea_vic(u8 vic)
3616 return cea_mode_for_vic(vic) != NULL;
3619 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3621 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3624 return mode->picture_aspect_ratio;
3626 return HDMI_PICTURE_ASPECT_NONE;
3629 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3631 return edid_4k_modes[video_code].picture_aspect_ratio;
3635 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3639 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3641 return cea_mode_alternate_clock(hdmi_mode);
3644 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3645 unsigned int clock_tolerance)
3647 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3650 if (!to_match->clock)
3653 if (to_match->picture_aspect_ratio)
3654 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3656 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3657 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3658 unsigned int clock1, clock2;
3660 /* Make sure to also match alternate clocks */
3661 clock1 = hdmi_mode->clock;
3662 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3664 if (abs(to_match->clock - clock1) > clock_tolerance &&
3665 abs(to_match->clock - clock2) > clock_tolerance)
3668 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3676 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3677 * @to_match: display mode
3679 * An HDMI mode is one defined in the HDMI vendor specific block.
3681 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3683 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3685 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3688 if (!to_match->clock)
3691 if (to_match->picture_aspect_ratio)
3692 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3694 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3695 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3696 unsigned int clock1, clock2;
3698 /* Make sure to also match alternate clocks */
3699 clock1 = hdmi_mode->clock;
3700 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3702 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3703 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3704 drm_mode_match(to_match, hdmi_mode, match_flags))
3710 static bool drm_valid_hdmi_vic(u8 vic)
3712 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3716 add_alternate_cea_modes(struct drm_connector *connector, const struct edid *edid)
3718 struct drm_device *dev = connector->dev;
3719 struct drm_display_mode *mode, *tmp;
3723 /* Don't add CEA modes if the CEA extension block is missing */
3724 if (!drm_find_cea_extension(edid))
3728 * Go through all probed modes and create a new mode
3729 * with the alternate clock for certain CEA modes.
3731 list_for_each_entry(mode, &connector->probed_modes, head) {
3732 const struct drm_display_mode *cea_mode = NULL;
3733 struct drm_display_mode *newmode;
3734 u8 vic = drm_match_cea_mode(mode);
3735 unsigned int clock1, clock2;
3737 if (drm_valid_cea_vic(vic)) {
3738 cea_mode = cea_mode_for_vic(vic);
3739 clock2 = cea_mode_alternate_clock(cea_mode);
3741 vic = drm_match_hdmi_mode(mode);
3742 if (drm_valid_hdmi_vic(vic)) {
3743 cea_mode = &edid_4k_modes[vic];
3744 clock2 = hdmi_mode_alternate_clock(cea_mode);
3751 clock1 = cea_mode->clock;
3753 if (clock1 == clock2)
3756 if (mode->clock != clock1 && mode->clock != clock2)
3759 newmode = drm_mode_duplicate(dev, cea_mode);
3763 /* Carry over the stereo flags */
3764 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3767 * The current mode could be either variant. Make
3768 * sure to pick the "other" clock for the new mode.
3770 if (mode->clock != clock1)
3771 newmode->clock = clock1;
3773 newmode->clock = clock2;
3775 list_add_tail(&newmode->head, &list);
3778 list_for_each_entry_safe(mode, tmp, &list, head) {
3779 list_del(&mode->head);
3780 drm_mode_probed_add(connector, mode);
3787 static u8 svd_to_vic(u8 svd)
3789 /* 0-6 bit vic, 7th bit native mode indicator */
3790 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3796 static struct drm_display_mode *
3797 drm_display_mode_from_vic_index(struct drm_connector *connector,
3798 const u8 *video_db, u8 video_len,
3801 struct drm_device *dev = connector->dev;
3802 struct drm_display_mode *newmode;
3805 if (video_db == NULL || video_index >= video_len)
3808 /* CEA modes are numbered 1..127 */
3809 vic = svd_to_vic(video_db[video_index]);
3810 if (!drm_valid_cea_vic(vic))
3813 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3821 * do_y420vdb_modes - Parse YCBCR 420 only modes
3822 * @connector: connector corresponding to the HDMI sink
3823 * @svds: start of the data block of CEA YCBCR 420 VDB
3824 * @len: length of the CEA YCBCR 420 VDB
3826 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3827 * which contains modes which can be supported in YCBCR 420
3828 * output format only.
3830 static int do_y420vdb_modes(struct drm_connector *connector,
3831 const u8 *svds, u8 svds_len)
3834 struct drm_device *dev = connector->dev;
3835 struct drm_display_info *info = &connector->display_info;
3836 struct drm_hdmi_info *hdmi = &info->hdmi;
3838 for (i = 0; i < svds_len; i++) {
3839 u8 vic = svd_to_vic(svds[i]);
3840 struct drm_display_mode *newmode;
3842 if (!drm_valid_cea_vic(vic))
3845 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3848 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3849 drm_mode_probed_add(connector, newmode);
3854 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
3859 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3860 * @connector: connector corresponding to the HDMI sink
3861 * @vic: CEA vic for the video mode to be added in the map
3863 * Makes an entry for a videomode in the YCBCR 420 bitmap
3866 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3868 u8 vic = svd_to_vic(svd);
3869 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3871 if (!drm_valid_cea_vic(vic))
3874 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3878 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
3880 * @video_code: CEA VIC of the mode
3882 * Creates a new mode matching the specified CEA VIC.
3884 * Returns: A new drm_display_mode on success or NULL on failure
3886 struct drm_display_mode *
3887 drm_display_mode_from_cea_vic(struct drm_device *dev,
3890 const struct drm_display_mode *cea_mode;
3891 struct drm_display_mode *newmode;
3893 cea_mode = cea_mode_for_vic(video_code);
3897 newmode = drm_mode_duplicate(dev, cea_mode);
3903 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
3906 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3909 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3911 for (i = 0; i < len; i++) {
3912 struct drm_display_mode *mode;
3914 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3917 * YCBCR420 capability block contains a bitmap which
3918 * gives the index of CEA modes from CEA VDB, which
3919 * can support YCBCR 420 sampling output also (apart
3920 * from RGB/YCBCR444 etc).
3921 * For example, if the bit 0 in bitmap is set,
3922 * first mode in VDB can support YCBCR420 output too.
3923 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3925 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3926 drm_add_cmdb_modes(connector, db[i]);
3928 drm_mode_probed_add(connector, mode);
3936 struct stereo_mandatory_mode {
3937 int width, height, vrefresh;
3941 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3942 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3943 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3945 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3947 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3948 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3949 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3950 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3951 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3955 stereo_match_mandatory(const struct drm_display_mode *mode,
3956 const struct stereo_mandatory_mode *stereo_mode)
3958 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3960 return mode->hdisplay == stereo_mode->width &&
3961 mode->vdisplay == stereo_mode->height &&
3962 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3963 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3966 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3968 struct drm_device *dev = connector->dev;
3969 const struct drm_display_mode *mode;
3970 struct list_head stereo_modes;
3973 INIT_LIST_HEAD(&stereo_modes);
3975 list_for_each_entry(mode, &connector->probed_modes, head) {
3976 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3977 const struct stereo_mandatory_mode *mandatory;
3978 struct drm_display_mode *new_mode;
3980 if (!stereo_match_mandatory(mode,
3981 &stereo_mandatory_modes[i]))
3984 mandatory = &stereo_mandatory_modes[i];
3985 new_mode = drm_mode_duplicate(dev, mode);
3989 new_mode->flags |= mandatory->flags;
3990 list_add_tail(&new_mode->head, &stereo_modes);
3995 list_splice_tail(&stereo_modes, &connector->probed_modes);
4000 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4002 struct drm_device *dev = connector->dev;
4003 struct drm_display_mode *newmode;
4005 if (!drm_valid_hdmi_vic(vic)) {
4006 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4010 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4014 drm_mode_probed_add(connector, newmode);
4019 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4020 const u8 *video_db, u8 video_len, u8 video_index)
4022 struct drm_display_mode *newmode;
4025 if (structure & (1 << 0)) {
4026 newmode = drm_display_mode_from_vic_index(connector, video_db,
4030 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4031 drm_mode_probed_add(connector, newmode);
4035 if (structure & (1 << 6)) {
4036 newmode = drm_display_mode_from_vic_index(connector, video_db,
4040 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4041 drm_mode_probed_add(connector, newmode);
4045 if (structure & (1 << 8)) {
4046 newmode = drm_display_mode_from_vic_index(connector, video_db,
4050 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4051 drm_mode_probed_add(connector, newmode);
4060 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4061 * @connector: connector corresponding to the HDMI sink
4062 * @db: start of the CEA vendor specific block
4063 * @len: length of the CEA block payload, ie. one can access up to db[len]
4065 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4066 * also adds the stereo 3d modes when applicable.
4069 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4070 const u8 *video_db, u8 video_len)
4072 struct drm_display_info *info = &connector->display_info;
4073 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4074 u8 vic_len, hdmi_3d_len = 0;
4081 /* no HDMI_Video_Present */
4082 if (!(db[8] & (1 << 5)))
4085 /* Latency_Fields_Present */
4086 if (db[8] & (1 << 7))
4089 /* I_Latency_Fields_Present */
4090 if (db[8] & (1 << 6))
4093 /* the declared length is not long enough for the 2 first bytes
4094 * of additional video format capabilities */
4095 if (len < (8 + offset + 2))
4100 if (db[8 + offset] & (1 << 7)) {
4101 modes += add_hdmi_mandatory_stereo_modes(connector);
4103 /* 3D_Multi_present */
4104 multi_present = (db[8 + offset] & 0x60) >> 5;
4108 vic_len = db[8 + offset] >> 5;
4109 hdmi_3d_len = db[8 + offset] & 0x1f;
4111 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4114 vic = db[9 + offset + i];
4115 modes += add_hdmi_mode(connector, vic);
4117 offset += 1 + vic_len;
4119 if (multi_present == 1)
4121 else if (multi_present == 2)
4126 if (len < (8 + offset + hdmi_3d_len - 1))
4129 if (hdmi_3d_len < multi_len)
4132 if (multi_present == 1 || multi_present == 2) {
4133 /* 3D_Structure_ALL */
4134 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4136 /* check if 3D_MASK is present */
4137 if (multi_present == 2)
4138 mask = (db[10 + offset] << 8) | db[11 + offset];
4142 for (i = 0; i < 16; i++) {
4143 if (mask & (1 << i))
4144 modes += add_3d_struct_modes(connector,
4151 offset += multi_len;
4153 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4155 struct drm_display_mode *newmode = NULL;
4156 unsigned int newflag = 0;
4157 bool detail_present;
4159 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4161 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4164 /* 2D_VIC_order_X */
4165 vic_index = db[8 + offset + i] >> 4;
4167 /* 3D_Structure_X */
4168 switch (db[8 + offset + i] & 0x0f) {
4170 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4173 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4177 if ((db[9 + offset + i] >> 4) == 1)
4178 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4183 newmode = drm_display_mode_from_vic_index(connector,
4189 newmode->flags |= newflag;
4190 drm_mode_probed_add(connector, newmode);
4201 info->has_hdmi_infoframe = true;
4206 cea_db_payload_len(const u8 *db)
4208 return db[0] & 0x1f;
4212 cea_db_extended_tag(const u8 *db)
4218 cea_db_tag(const u8 *db)
4224 cea_revision(const u8 *cea)
4227 * FIXME is this correct for the DispID variant?
4228 * The DispID spec doesn't really specify whether
4229 * this is the revision of the CEA extension or
4230 * the DispID CEA data block. And the only value
4231 * given as an example is 0.
4237 cea_db_offsets(const u8 *cea, int *start, int *end)
4239 /* DisplayID CTA extension blocks and top-level CEA EDID
4240 * block header definitions differ in the following bytes:
4241 * 1) Byte 2 of the header specifies length differently,
4242 * 2) Byte 3 is only present in the CEA top level block.
4244 * The different definitions for byte 2 follow.
4246 * DisplayID CTA extension block defines byte 2 as:
4247 * Number of payload bytes
4249 * CEA EDID block defines byte 2 as:
4250 * Byte number (decimal) within this block where the 18-byte
4251 * DTDs begin. If no non-DTD data is present in this extension
4252 * block, the value should be set to 04h (the byte after next).
4253 * If set to 00h, there are no DTDs present in this block and
4256 if (cea[0] == DATA_BLOCK_CTA) {
4258 * for_each_displayid_db() has already verified
4259 * that these stay within expected bounds.
4262 *end = *start + cea[2];
4263 } else if (cea[0] == CEA_EXT) {
4264 /* Data block offset in CEA extension block */
4269 if (*end < 4 || *end > 127)
4278 static bool cea_db_is_hdmi_vsdb(const u8 *db)
4280 if (cea_db_tag(db) != VENDOR_BLOCK)
4283 if (cea_db_payload_len(db) < 5)
4286 return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
4289 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4291 if (cea_db_tag(db) != VENDOR_BLOCK)
4294 if (cea_db_payload_len(db) < 7)
4297 return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
4300 static bool cea_db_is_microsoft_vsdb(const u8 *db)
4302 if (cea_db_tag(db) != VENDOR_BLOCK)
4305 if (cea_db_payload_len(db) != 21)
4308 return oui(db[3], db[2], db[1]) == MICROSOFT_IEEE_OUI;
4311 static bool cea_db_is_vcdb(const u8 *db)
4313 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4316 if (cea_db_payload_len(db) != 2)
4319 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4325 static bool cea_db_is_y420cmdb(const u8 *db)
4327 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4330 if (!cea_db_payload_len(db))
4333 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4339 static bool cea_db_is_y420vdb(const u8 *db)
4341 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4344 if (!cea_db_payload_len(db))
4347 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4353 #define for_each_cea_db(cea, i, start, end) \
4354 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4356 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4359 struct drm_display_info *info = &connector->display_info;
4360 struct drm_hdmi_info *hdmi = &info->hdmi;
4361 u8 map_len = cea_db_payload_len(db) - 1;
4366 /* All CEA modes support ycbcr420 sampling also.*/
4367 hdmi->y420_cmdb_map = U64_MAX;
4368 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4373 * This map indicates which of the existing CEA block modes
4374 * from VDB can support YCBCR420 output too. So if bit=0 is
4375 * set, first mode from VDB can support YCBCR420 output too.
4376 * We will parse and keep this map, before parsing VDB itself
4377 * to avoid going through the same block again and again.
4379 * Spec is not clear about max possible size of this block.
4380 * Clamping max bitmap block size at 8 bytes. Every byte can
4381 * address 8 CEA modes, in this way this map can address
4382 * 8*8 = first 64 SVDs.
4384 if (WARN_ON_ONCE(map_len > 8))
4387 for (count = 0; count < map_len; count++)
4388 map |= (u64)db[2 + count] << (8 * count);
4391 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4393 hdmi->y420_cmdb_map = map;
4397 add_cea_modes(struct drm_connector *connector, const struct edid *edid)
4399 const u8 *cea = drm_find_cea_extension(edid);
4400 const u8 *db, *hdmi = NULL, *video = NULL;
4401 u8 dbl, hdmi_len, video_len = 0;
4404 if (cea && cea_revision(cea) >= 3) {
4407 if (cea_db_offsets(cea, &start, &end))
4410 for_each_cea_db(cea, i, start, end) {
4412 dbl = cea_db_payload_len(db);
4414 if (cea_db_tag(db) == VIDEO_BLOCK) {
4417 modes += do_cea_modes(connector, video, dbl);
4418 } else if (cea_db_is_hdmi_vsdb(db)) {
4421 } else if (cea_db_is_y420vdb(db)) {
4422 const u8 *vdb420 = &db[2];
4424 /* Add 4:2:0(only) modes present in EDID */
4425 modes += do_y420vdb_modes(connector,
4433 * We parse the HDMI VSDB after having added the cea modes as we will
4434 * be patching their flags when the sink supports stereo 3D.
4437 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4443 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4445 const struct drm_display_mode *cea_mode;
4446 int clock1, clock2, clock;
4451 * allow 5kHz clock difference either way to account for
4452 * the 10kHz clock resolution limit of detailed timings.
4454 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4455 if (drm_valid_cea_vic(vic)) {
4457 cea_mode = cea_mode_for_vic(vic);
4458 clock1 = cea_mode->clock;
4459 clock2 = cea_mode_alternate_clock(cea_mode);
4461 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4462 if (drm_valid_hdmi_vic(vic)) {
4464 cea_mode = &edid_4k_modes[vic];
4465 clock1 = cea_mode->clock;
4466 clock2 = hdmi_mode_alternate_clock(cea_mode);
4472 /* pick whichever is closest */
4473 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4478 if (mode->clock == clock)
4481 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4482 type, vic, mode->clock, clock);
4483 mode->clock = clock;
4486 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4488 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4491 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4494 if (cea_db_payload_len(db) < 3)
4500 static uint8_t eotf_supported(const u8 *edid_ext)
4502 return edid_ext[2] &
4503 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4504 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4505 BIT(HDMI_EOTF_SMPTE_ST2084) |
4506 BIT(HDMI_EOTF_BT_2100_HLG));
4509 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4511 return edid_ext[3] &
4512 BIT(HDMI_STATIC_METADATA_TYPE1);
4516 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4520 len = cea_db_payload_len(db);
4522 connector->hdr_sink_metadata.hdmi_type1.eotf =
4524 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4525 hdr_metadata_type(db);
4528 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4530 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4532 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4536 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4538 u8 len = cea_db_payload_len(db);
4540 if (len >= 6 && (db[6] & (1 << 7)))
4541 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4543 connector->latency_present[0] = db[8] >> 7;
4544 connector->latency_present[1] = (db[8] >> 6) & 1;
4547 connector->video_latency[0] = db[9];
4549 connector->audio_latency[0] = db[10];
4551 connector->video_latency[1] = db[11];
4553 connector->audio_latency[1] = db[12];
4555 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4556 "video latency %d %d, "
4557 "audio latency %d %d\n",
4558 connector->latency_present[0],
4559 connector->latency_present[1],
4560 connector->video_latency[0],
4561 connector->video_latency[1],
4562 connector->audio_latency[0],
4563 connector->audio_latency[1]);
4567 monitor_name(const struct detailed_timing *timing, void *data)
4569 const char **res = data;
4571 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
4574 *res = timing->data.other_data.data.str.str;
4577 static int get_monitor_name(const struct edid *edid, char name[13])
4579 const char *edid_name = NULL;
4585 drm_for_each_detailed_block(edid, monitor_name, &edid_name);
4586 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4587 if (edid_name[mnl] == 0x0a)
4590 name[mnl] = edid_name[mnl];
4597 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4598 * @edid: monitor EDID information
4599 * @name: pointer to a character array to hold the name of the monitor
4600 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4603 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
4611 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4612 memcpy(name, buf, name_length);
4613 name[name_length] = '\0';
4615 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4617 static void clear_eld(struct drm_connector *connector)
4619 memset(connector->eld, 0, sizeof(connector->eld));
4621 connector->latency_present[0] = false;
4622 connector->latency_present[1] = false;
4623 connector->video_latency[0] = 0;
4624 connector->audio_latency[0] = 0;
4625 connector->video_latency[1] = 0;
4626 connector->audio_latency[1] = 0;
4630 * drm_edid_to_eld - build ELD from EDID
4631 * @connector: connector corresponding to the HDMI/DP sink
4632 * @edid: EDID to parse
4634 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4635 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4637 static void drm_edid_to_eld(struct drm_connector *connector,
4638 const struct edid *edid)
4640 uint8_t *eld = connector->eld;
4643 int total_sad_count = 0;
4647 clear_eld(connector);
4652 cea = drm_find_cea_extension(edid);
4654 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4658 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4659 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4661 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4662 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4664 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4666 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4667 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4668 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4669 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4671 if (cea_revision(cea) >= 3) {
4675 if (cea_db_offsets(cea, &start, &end)) {
4680 for_each_cea_db(cea, i, start, end) {
4682 dbl = cea_db_payload_len(db);
4684 switch (cea_db_tag(db)) {
4686 /* Audio Data Block, contains SADs */
4687 sad_count = min(dbl / 3, 15 - total_sad_count);
4689 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4690 &db[1], sad_count * 3);
4691 total_sad_count += sad_count;
4694 /* Speaker Allocation Data Block */
4696 eld[DRM_ELD_SPEAKER] = db[1];
4699 /* HDMI Vendor-Specific Data Block */
4700 if (cea_db_is_hdmi_vsdb(db))
4701 drm_parse_hdmi_vsdb_audio(connector, db);
4708 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4710 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4711 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4712 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4714 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4716 eld[DRM_ELD_BASELINE_ELD_LEN] =
4717 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4719 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4720 drm_eld_size(eld), total_sad_count);
4724 * drm_edid_to_sad - extracts SADs from EDID
4725 * @edid: EDID to parse
4726 * @sads: pointer that will be set to the extracted SADs
4728 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4730 * Note: The returned pointer needs to be freed using kfree().
4732 * Return: The number of found SADs or negative number on error.
4734 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
4737 int i, start, end, dbl;
4740 cea = drm_find_cea_extension(edid);
4742 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4746 if (cea_revision(cea) < 3) {
4747 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4751 if (cea_db_offsets(cea, &start, &end)) {
4752 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4756 for_each_cea_db(cea, i, start, end) {
4757 const u8 *db = &cea[i];
4759 if (cea_db_tag(db) == AUDIO_BLOCK) {
4762 dbl = cea_db_payload_len(db);
4764 count = dbl / 3; /* SAD is 3B */
4765 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4768 for (j = 0; j < count; j++) {
4769 const u8 *sad = &db[1 + j * 3];
4771 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4772 (*sads)[j].channels = sad[0] & 0x7;
4773 (*sads)[j].freq = sad[1] & 0x7F;
4774 (*sads)[j].byte2 = sad[2];
4782 EXPORT_SYMBOL(drm_edid_to_sad);
4785 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4786 * @edid: EDID to parse
4787 * @sadb: pointer to the speaker block
4789 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4791 * Note: The returned pointer needs to be freed using kfree().
4793 * Return: The number of found Speaker Allocation Blocks or negative number on
4796 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
4799 int i, start, end, dbl;
4802 cea = drm_find_cea_extension(edid);
4804 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4808 if (cea_revision(cea) < 3) {
4809 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4813 if (cea_db_offsets(cea, &start, &end)) {
4814 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4818 for_each_cea_db(cea, i, start, end) {
4819 const u8 *db = &cea[i];
4821 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4822 dbl = cea_db_payload_len(db);
4824 /* Speaker Allocation Data Block */
4826 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4837 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4840 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4841 * @connector: connector associated with the HDMI/DP sink
4842 * @mode: the display mode
4844 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4845 * the sink doesn't support audio or video.
4847 int drm_av_sync_delay(struct drm_connector *connector,
4848 const struct drm_display_mode *mode)
4850 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4853 if (!connector->latency_present[0])
4855 if (!connector->latency_present[1])
4858 a = connector->audio_latency[i];
4859 v = connector->video_latency[i];
4862 * HDMI/DP sink doesn't support audio or video?
4864 if (a == 255 || v == 255)
4868 * Convert raw EDID values to millisecond.
4869 * Treat unknown latency as 0ms.
4872 a = min(2 * (a - 1), 500);
4874 v = min(2 * (v - 1), 500);
4876 return max(v - a, 0);
4878 EXPORT_SYMBOL(drm_av_sync_delay);
4881 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4882 * @edid: monitor EDID information
4884 * Parse the CEA extension according to CEA-861-B.
4886 * Drivers that have added the modes parsed from EDID to drm_display_info
4887 * should use &drm_display_info.is_hdmi instead of calling this function.
4889 * Return: True if the monitor is HDMI, false if not or unknown.
4891 bool drm_detect_hdmi_monitor(const struct edid *edid)
4895 int start_offset, end_offset;
4897 edid_ext = drm_find_cea_extension(edid);
4901 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4905 * Because HDMI identifier is in Vendor Specific Block,
4906 * search it from all data blocks of CEA extension.
4908 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4909 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4915 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4918 * drm_detect_monitor_audio - check monitor audio capability
4919 * @edid: EDID block to scan
4921 * Monitor should have CEA extension block.
4922 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4923 * audio' only. If there is any audio extension block and supported
4924 * audio format, assume at least 'basic audio' support, even if 'basic
4925 * audio' is not defined in EDID.
4927 * Return: True if the monitor supports audio, false otherwise.
4929 bool drm_detect_monitor_audio(const struct edid *edid)
4933 bool has_audio = false;
4934 int start_offset, end_offset;
4936 edid_ext = drm_find_cea_extension(edid);
4940 has_audio = (edid_ext[0] == CEA_EXT &&
4941 (edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4944 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4948 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4951 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4952 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4954 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4955 DRM_DEBUG_KMS("CEA audio format %d\n",
4956 (edid_ext[i + j] >> 3) & 0xf);
4963 EXPORT_SYMBOL(drm_detect_monitor_audio);
4967 * drm_default_rgb_quant_range - default RGB quantization range
4968 * @mode: display mode
4970 * Determine the default RGB quantization range for the mode,
4971 * as specified in CEA-861.
4973 * Return: The default RGB quantization range for the mode
4975 enum hdmi_quantization_range
4976 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4978 /* All CEA modes other than VIC 1 use limited quantization range. */
4979 return drm_match_cea_mode(mode) > 1 ?
4980 HDMI_QUANTIZATION_RANGE_LIMITED :
4981 HDMI_QUANTIZATION_RANGE_FULL;
4983 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4985 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4987 struct drm_display_info *info = &connector->display_info;
4989 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4991 if (db[2] & EDID_CEA_VCDB_QS)
4992 info->rgb_quant_range_selectable = true;
4996 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
4998 switch (max_frl_rate) {
5001 *max_rate_per_lane = 3;
5005 *max_rate_per_lane = 6;
5009 *max_rate_per_lane = 6;
5013 *max_rate_per_lane = 8;
5017 *max_rate_per_lane = 10;
5021 *max_rate_per_lane = 12;
5026 *max_rate_per_lane = 0;
5030 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5034 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5036 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5037 hdmi->y420_dc_modes = dc_mask;
5040 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
5043 struct drm_display_info *display = &connector->display_info;
5044 struct drm_hdmi_info *hdmi = &display->hdmi;
5046 display->has_hdmi_infoframe = true;
5048 if (hf_vsdb[6] & 0x80) {
5049 hdmi->scdc.supported = true;
5050 if (hf_vsdb[6] & 0x40)
5051 hdmi->scdc.read_request = true;
5055 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5056 * And as per the spec, three factors confirm this:
5057 * * Availability of a HF-VSDB block in EDID (check)
5058 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5059 * * SCDC support available (let's check)
5060 * Lets check it out.
5064 /* max clock is 5000 KHz times block value */
5065 u32 max_tmds_clock = hf_vsdb[5] * 5000;
5066 struct drm_scdc *scdc = &hdmi->scdc;
5068 if (max_tmds_clock > 340000) {
5069 display->max_tmds_clock = max_tmds_clock;
5070 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5071 display->max_tmds_clock);
5074 if (scdc->supported) {
5075 scdc->scrambling.supported = true;
5077 /* Few sinks support scrambling for clocks < 340M */
5078 if ((hf_vsdb[6] & 0x8))
5079 scdc->scrambling.low_rates = true;
5085 u8 dsc_max_frl_rate;
5087 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5089 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5090 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5091 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5092 &hdmi->max_frl_rate_per_lane);
5093 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
5095 if (hdmi_dsc->v_1p2) {
5096 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420;
5097 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
5099 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
5100 hdmi_dsc->bpc_supported = 16;
5101 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
5102 hdmi_dsc->bpc_supported = 12;
5103 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
5104 hdmi_dsc->bpc_supported = 10;
5106 hdmi_dsc->bpc_supported = 0;
5108 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5109 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5110 &hdmi_dsc->max_frl_rate_per_lane);
5111 hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5113 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
5114 switch (dsc_max_slices) {
5116 hdmi_dsc->max_slices = 1;
5117 hdmi_dsc->clk_per_slice = 340;
5120 hdmi_dsc->max_slices = 2;
5121 hdmi_dsc->clk_per_slice = 340;
5124 hdmi_dsc->max_slices = 4;
5125 hdmi_dsc->clk_per_slice = 340;
5128 hdmi_dsc->max_slices = 8;
5129 hdmi_dsc->clk_per_slice = 340;
5132 hdmi_dsc->max_slices = 8;
5133 hdmi_dsc->clk_per_slice = 400;
5136 hdmi_dsc->max_slices = 12;
5137 hdmi_dsc->clk_per_slice = 400;
5140 hdmi_dsc->max_slices = 16;
5141 hdmi_dsc->clk_per_slice = 400;
5145 hdmi_dsc->max_slices = 0;
5146 hdmi_dsc->clk_per_slice = 0;
5151 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
5154 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5157 struct drm_display_info *info = &connector->display_info;
5158 unsigned int dc_bpc = 0;
5160 /* HDMI supports at least 8 bpc */
5163 if (cea_db_payload_len(hdmi) < 6)
5166 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5168 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
5169 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5173 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5175 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
5176 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5180 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5182 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
5183 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5188 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5193 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5194 connector->name, dc_bpc);
5197 /* YCRCB444 is optional according to spec. */
5198 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5199 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
5200 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5205 * Spec says that if any deep color mode is supported at all,
5206 * then deep color 36 bit must be supported.
5208 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5209 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5215 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5217 struct drm_display_info *info = &connector->display_info;
5218 u8 len = cea_db_payload_len(db);
5220 info->is_hdmi = true;
5223 info->dvi_dual = db[6] & 1;
5225 info->max_tmds_clock = db[7] * 5000;
5227 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5228 "max TMDS clock %d kHz\n",
5230 info->max_tmds_clock);
5232 drm_parse_hdmi_deep_color_info(connector, db);
5236 * See EDID extension for head-mounted and specialized monitors, specified at:
5237 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5239 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5242 struct drm_display_info *info = &connector->display_info;
5244 bool desktop_usage = db[5] & BIT(6);
5246 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5247 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5248 info->non_desktop = true;
5250 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5254 static void drm_parse_cea_ext(struct drm_connector *connector,
5255 const struct edid *edid)
5257 struct drm_display_info *info = &connector->display_info;
5261 edid_ext = drm_find_cea_extension(edid);
5265 info->cea_rev = edid_ext[1];
5267 /* The existence of a CEA block should imply RGB support */
5268 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5270 /* CTA DisplayID Data Block does not have byte #3 */
5271 if (edid_ext[0] == CEA_EXT) {
5272 if (edid_ext[3] & EDID_CEA_YCRCB444)
5273 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
5274 if (edid_ext[3] & EDID_CEA_YCRCB422)
5275 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
5278 if (cea_db_offsets(edid_ext, &start, &end))
5281 for_each_cea_db(edid_ext, i, start, end) {
5282 const u8 *db = &edid_ext[i];
5284 if (cea_db_is_hdmi_vsdb(db))
5285 drm_parse_hdmi_vsdb_video(connector, db);
5286 if (cea_db_is_hdmi_forum_vsdb(db))
5287 drm_parse_hdmi_forum_vsdb(connector, db);
5288 if (cea_db_is_microsoft_vsdb(db))
5289 drm_parse_microsoft_vsdb(connector, db);
5290 if (cea_db_is_y420cmdb(db))
5291 drm_parse_y420cmdb_bitmap(connector, db);
5292 if (cea_db_is_vcdb(db))
5293 drm_parse_vcdb(connector, db);
5294 if (cea_db_is_hdmi_hdr_metadata_block(db))
5295 drm_parse_hdr_metadata_block(connector, db);
5300 void get_monitor_range(const struct detailed_timing *timing,
5301 void *info_monitor_range)
5303 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5304 const struct detailed_non_pixel *data = &timing->data.other_data;
5305 const struct detailed_data_monitor_range *range = &data->data.range;
5307 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
5311 * Check for flag range limits only. If flag == 1 then
5312 * no additional timing information provided.
5313 * Default GTF, GTF Secondary curve and CVT are not
5316 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5319 monitor_range->min_vfreq = range->min_vfreq;
5320 monitor_range->max_vfreq = range->max_vfreq;
5324 void drm_get_monitor_range(struct drm_connector *connector,
5325 const struct edid *edid)
5327 struct drm_display_info *info = &connector->display_info;
5329 if (!version_greater(edid, 1, 1))
5332 drm_for_each_detailed_block(edid, get_monitor_range,
5333 &info->monitor_range);
5335 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5336 info->monitor_range.min_vfreq,
5337 info->monitor_range.max_vfreq);
5340 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
5341 const struct displayid_block *block)
5343 struct displayid_vesa_vendor_specific_block *vesa =
5344 (struct displayid_vesa_vendor_specific_block *)block;
5345 struct drm_display_info *info = &connector->display_info;
5347 if (block->num_bytes < 3) {
5348 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
5353 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
5356 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
5357 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
5361 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
5363 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
5366 info->mso_stream_count = 0;
5369 info->mso_stream_count = 2; /* 2 or 4 links */
5372 info->mso_stream_count = 4; /* 4 links */
5376 if (!info->mso_stream_count) {
5377 info->mso_pixel_overlap = 0;
5381 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
5382 if (info->mso_pixel_overlap > 8) {
5383 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
5384 info->mso_pixel_overlap);
5385 info->mso_pixel_overlap = 8;
5388 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
5389 info->mso_stream_count, info->mso_pixel_overlap);
5392 static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
5394 const struct displayid_block *block;
5395 struct displayid_iter iter;
5397 displayid_iter_edid_begin(edid, &iter);
5398 displayid_iter_for_each(block, &iter) {
5399 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
5400 drm_parse_vesa_mso_data(connector, block);
5402 displayid_iter_end(&iter);
5405 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5406 * all of the values which would have been set from EDID
5409 drm_reset_display_info(struct drm_connector *connector)
5411 struct drm_display_info *info = &connector->display_info;
5414 info->height_mm = 0;
5417 info->color_formats = 0;
5419 info->max_tmds_clock = 0;
5420 info->dvi_dual = false;
5421 info->is_hdmi = false;
5422 info->has_hdmi_infoframe = false;
5423 info->rgb_quant_range_selectable = false;
5424 memset(&info->hdmi, 0, sizeof(info->hdmi));
5426 info->edid_hdmi_rgb444_dc_modes = 0;
5427 info->edid_hdmi_ycbcr444_dc_modes = 0;
5429 info->non_desktop = 0;
5430 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5432 info->mso_stream_count = 0;
5433 info->mso_pixel_overlap = 0;
5436 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5438 struct drm_display_info *info = &connector->display_info;
5440 u32 quirks = edid_get_quirks(edid);
5442 drm_reset_display_info(connector);
5444 info->width_mm = edid->width_cm * 10;
5445 info->height_mm = edid->height_cm * 10;
5447 drm_get_monitor_range(connector, edid);
5449 if (edid->revision < 3)
5452 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5455 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5456 drm_parse_cea_ext(connector, edid);
5459 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5461 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5462 * tells us to assume 8 bpc color depth if the EDID doesn't have
5463 * extensions which tell otherwise.
5465 if (info->bpc == 0 && edid->revision == 3 &&
5466 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5468 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5469 connector->name, info->bpc);
5472 /* Only defined for 1.4 with digital displays */
5473 if (edid->revision < 4)
5476 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5477 case DRM_EDID_DIGITAL_DEPTH_6:
5480 case DRM_EDID_DIGITAL_DEPTH_8:
5483 case DRM_EDID_DIGITAL_DEPTH_10:
5486 case DRM_EDID_DIGITAL_DEPTH_12:
5489 case DRM_EDID_DIGITAL_DEPTH_14:
5492 case DRM_EDID_DIGITAL_DEPTH_16:
5495 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5501 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
5502 connector->name, info->bpc);
5504 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5505 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
5506 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5507 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
5509 drm_update_mso(connector, edid);
5512 if (quirks & EDID_QUIRK_NON_DESKTOP) {
5513 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
5514 info->non_desktop ? " (redundant quirk)" : "");
5515 info->non_desktop = true;
5521 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5522 struct displayid_detailed_timings_1 *timings,
5525 struct drm_display_mode *mode;
5526 unsigned pixel_clock = (timings->pixel_clock[0] |
5527 (timings->pixel_clock[1] << 8) |
5528 (timings->pixel_clock[2] << 16)) + 1;
5529 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5530 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5531 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5532 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5533 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5534 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5535 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5536 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5537 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5538 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5540 mode = drm_mode_create(dev);
5544 /* resolution is kHz for type VII, and 10 kHz for type I */
5545 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
5546 mode->hdisplay = hactive;
5547 mode->hsync_start = mode->hdisplay + hsync;
5548 mode->hsync_end = mode->hsync_start + hsync_width;
5549 mode->htotal = mode->hdisplay + hblank;
5551 mode->vdisplay = vactive;
5552 mode->vsync_start = mode->vdisplay + vsync;
5553 mode->vsync_end = mode->vsync_start + vsync_width;
5554 mode->vtotal = mode->vdisplay + vblank;
5557 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5558 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5559 mode->type = DRM_MODE_TYPE_DRIVER;
5561 if (timings->flags & 0x80)
5562 mode->type |= DRM_MODE_TYPE_PREFERRED;
5563 drm_mode_set_name(mode);
5568 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5569 const struct displayid_block *block)
5571 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5574 struct drm_display_mode *newmode;
5576 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
5577 /* blocks must be multiple of 20 bytes length */
5578 if (block->num_bytes % 20)
5581 num_timings = block->num_bytes / 20;
5582 for (i = 0; i < num_timings; i++) {
5583 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5585 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
5589 drm_mode_probed_add(connector, newmode);
5595 static int add_displayid_detailed_modes(struct drm_connector *connector,
5596 const struct edid *edid)
5598 const struct displayid_block *block;
5599 struct displayid_iter iter;
5602 displayid_iter_edid_begin(edid, &iter);
5603 displayid_iter_for_each(block, &iter) {
5604 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
5605 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5606 num_modes += add_displayid_detailed_1_modes(connector, block);
5608 displayid_iter_end(&iter);
5613 static int drm_edid_connector_update(struct drm_connector *connector,
5614 const struct edid *edid)
5620 clear_eld(connector);
5624 drm_edid_to_eld(connector, edid);
5627 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5628 * To avoid multiple parsing of same block, lets parse that map
5629 * from sink info, before parsing CEA modes.
5631 quirks = drm_add_display_info(connector, edid);
5634 * EDID spec says modes should be preferred in this order:
5635 * - preferred detailed mode
5636 * - other detailed modes from base block
5637 * - detailed modes from extension blocks
5638 * - CVT 3-byte code modes
5639 * - standard timing codes
5640 * - established timing codes
5641 * - modes inferred from GTF or CVT range information
5643 * We get this pretty much right.
5645 * XXX order for additional mode types in extension blocks?
5647 num_modes += add_detailed_modes(connector, edid, quirks);
5648 num_modes += add_cvt_modes(connector, edid);
5649 num_modes += add_standard_modes(connector, edid);
5650 num_modes += add_established_modes(connector, edid);
5651 num_modes += add_cea_modes(connector, edid);
5652 num_modes += add_alternate_cea_modes(connector, edid);
5653 num_modes += add_displayid_detailed_modes(connector, edid);
5654 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5655 num_modes += add_inferred_modes(connector, edid);
5657 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5658 edid_fixup_preferred(connector, quirks);
5660 if (quirks & EDID_QUIRK_FORCE_6BPC)
5661 connector->display_info.bpc = 6;
5663 if (quirks & EDID_QUIRK_FORCE_8BPC)
5664 connector->display_info.bpc = 8;
5666 if (quirks & EDID_QUIRK_FORCE_10BPC)
5667 connector->display_info.bpc = 10;
5669 if (quirks & EDID_QUIRK_FORCE_12BPC)
5670 connector->display_info.bpc = 12;
5676 * drm_add_edid_modes - add modes from EDID data, if available
5677 * @connector: connector we're probing
5680 * Add the specified modes to the connector's mode list. Also fills out the
5681 * &drm_display_info structure and ELD in @connector with any information which
5682 * can be derived from the edid.
5684 * Return: The number of modes added or 0 if we couldn't find any.
5686 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5688 if (edid && !drm_edid_is_valid(edid)) {
5689 drm_warn(connector->dev, "%s: EDID invalid.\n",
5694 return drm_edid_connector_update(connector, edid);
5696 EXPORT_SYMBOL(drm_add_edid_modes);
5699 * drm_add_modes_noedid - add modes for the connectors without EDID
5700 * @connector: connector we're probing
5701 * @hdisplay: the horizontal display limit
5702 * @vdisplay: the vertical display limit
5704 * Add the specified modes to the connector's mode list. Only when the
5705 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5707 * Return: The number of modes added or 0 if we couldn't find any.
5709 int drm_add_modes_noedid(struct drm_connector *connector,
5710 int hdisplay, int vdisplay)
5712 int i, count, num_modes = 0;
5713 struct drm_display_mode *mode;
5714 struct drm_device *dev = connector->dev;
5716 count = ARRAY_SIZE(drm_dmt_modes);
5722 for (i = 0; i < count; i++) {
5723 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5725 if (hdisplay && vdisplay) {
5727 * Only when two are valid, they will be used to check
5728 * whether the mode should be added to the mode list of
5731 if (ptr->hdisplay > hdisplay ||
5732 ptr->vdisplay > vdisplay)
5735 if (drm_mode_vrefresh(ptr) > 61)
5737 mode = drm_mode_duplicate(dev, ptr);
5739 drm_mode_probed_add(connector, mode);
5745 EXPORT_SYMBOL(drm_add_modes_noedid);
5748 * drm_set_preferred_mode - Sets the preferred mode of a connector
5749 * @connector: connector whose mode list should be processed
5750 * @hpref: horizontal resolution of preferred mode
5751 * @vpref: vertical resolution of preferred mode
5753 * Marks a mode as preferred if it matches the resolution specified by @hpref
5756 void drm_set_preferred_mode(struct drm_connector *connector,
5757 int hpref, int vpref)
5759 struct drm_display_mode *mode;
5761 list_for_each_entry(mode, &connector->probed_modes, head) {
5762 if (mode->hdisplay == hpref &&
5763 mode->vdisplay == vpref)
5764 mode->type |= DRM_MODE_TYPE_PREFERRED;
5767 EXPORT_SYMBOL(drm_set_preferred_mode);
5769 static bool is_hdmi2_sink(const struct drm_connector *connector)
5772 * FIXME: sil-sii8620 doesn't have a connector around when
5773 * we need one, so we have to be prepared for a NULL connector.
5778 return connector->display_info.hdmi.scdc.supported ||
5779 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
5782 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5784 return sink_eotf & BIT(output_eotf);
5788 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5789 * HDR metadata from userspace
5790 * @frame: HDMI DRM infoframe
5791 * @conn_state: Connector state containing HDR metadata
5793 * Return: 0 on success or a negative error code on failure.
5796 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5797 const struct drm_connector_state *conn_state)
5799 struct drm_connector *connector;
5800 struct hdr_output_metadata *hdr_metadata;
5803 if (!frame || !conn_state)
5806 connector = conn_state->connector;
5808 if (!conn_state->hdr_output_metadata)
5811 hdr_metadata = conn_state->hdr_output_metadata->data;
5813 if (!hdr_metadata || !connector)
5816 /* Sink EOTF is Bit map while infoframe is absolute values */
5817 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5818 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5819 DRM_DEBUG_KMS("EOTF Not Supported\n");
5823 err = hdmi_drm_infoframe_init(frame);
5827 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5828 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5830 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5831 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5832 BUILD_BUG_ON(sizeof(frame->white_point) !=
5833 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5835 memcpy(&frame->display_primaries,
5836 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5837 sizeof(frame->display_primaries));
5839 memcpy(&frame->white_point,
5840 &hdr_metadata->hdmi_metadata_type1.white_point,
5841 sizeof(frame->white_point));
5843 frame->max_display_mastering_luminance =
5844 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5845 frame->min_display_mastering_luminance =
5846 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5847 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5848 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5852 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5854 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
5855 const struct drm_display_mode *mode)
5857 bool has_hdmi_infoframe = connector ?
5858 connector->display_info.has_hdmi_infoframe : false;
5860 if (!has_hdmi_infoframe)
5863 /* No HDMI VIC when signalling 3D video format */
5864 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5867 return drm_match_hdmi_mode(mode);
5870 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
5871 const struct drm_display_mode *mode)
5876 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5877 * we should send its VIC in vendor infoframes, else send the
5878 * VIC in AVI infoframes. Lets check if this mode is present in
5879 * HDMI 1.4b 4K modes
5881 if (drm_mode_hdmi_vic(connector, mode))
5884 vic = drm_match_cea_mode(mode);
5887 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5888 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5889 * have to make sure we dont break HDMI 1.4 sinks.
5891 if (!is_hdmi2_sink(connector) && vic > 64)
5898 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5899 * data from a DRM display mode
5900 * @frame: HDMI AVI infoframe
5901 * @connector: the connector
5902 * @mode: DRM display mode
5904 * Return: 0 on success or a negative error code on failure.
5907 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5908 const struct drm_connector *connector,
5909 const struct drm_display_mode *mode)
5911 enum hdmi_picture_aspect picture_aspect;
5914 if (!frame || !mode)
5917 hdmi_avi_infoframe_init(frame);
5919 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5920 frame->pixel_repeat = 1;
5922 vic = drm_mode_cea_vic(connector, mode);
5923 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5925 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5928 * As some drivers don't support atomic, we can't use connector state.
5929 * So just initialize the frame with default values, just the same way
5930 * as it's done with other properties here.
5932 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5936 * Populate picture aspect ratio from either
5937 * user input (if specified) or from the CEA/HDMI mode lists.
5939 picture_aspect = mode->picture_aspect_ratio;
5940 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5942 picture_aspect = drm_get_cea_aspect_ratio(vic);
5944 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5948 * The infoframe can't convey anything but none, 4:3
5949 * and 16:9, so if the user has asked for anything else
5950 * we can only satisfy it by specifying the right VIC.
5952 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5954 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5956 } else if (hdmi_vic) {
5957 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5963 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5966 frame->video_code = vic;
5967 frame->picture_aspect = picture_aspect;
5968 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5969 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5973 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5975 /* HDMI Colorspace Spec Definitions */
5976 #define FULL_COLORIMETRY_MASK 0x1FF
5977 #define NORMAL_COLORIMETRY_MASK 0x3
5978 #define EXTENDED_COLORIMETRY_MASK 0x7
5979 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5981 #define C(x) ((x) << 0)
5982 #define EC(x) ((x) << 2)
5983 #define ACE(x) ((x) << 5)
5985 #define HDMI_COLORIMETRY_NO_DATA 0x0
5986 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5987 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5988 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5989 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5990 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5991 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5992 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5993 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5994 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5995 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5996 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5997 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5999 static const u32 hdmi_colorimetry_val[] = {
6000 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
6001 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
6002 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
6003 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
6004 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
6005 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
6006 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
6007 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
6008 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
6009 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
6010 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
6018 * drm_hdmi_avi_infoframe_colorimetry() - fill the HDMI AVI infoframe
6019 * colorimetry information
6020 * @frame: HDMI AVI infoframe
6021 * @conn_state: connector state
6024 drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame,
6025 const struct drm_connector_state *conn_state)
6027 u32 colorimetry_val;
6028 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
6030 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
6031 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
6033 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
6035 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
6037 * ToDo: Extend it for ACE formats as well. Modify the infoframe
6038 * structure and extend it in drivers/video/hdmi
6040 frame->extended_colorimetry = (colorimetry_val >> 2) &
6041 EXTENDED_COLORIMETRY_MASK;
6043 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorimetry);
6046 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6047 * quantization range information
6048 * @frame: HDMI AVI infoframe
6049 * @connector: the connector
6050 * @mode: DRM display mode
6051 * @rgb_quant_range: RGB quantization range (Q)
6054 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
6055 const struct drm_connector *connector,
6056 const struct drm_display_mode *mode,
6057 enum hdmi_quantization_range rgb_quant_range)
6059 const struct drm_display_info *info = &connector->display_info;
6063 * "A Source shall not send a non-zero Q value that does not correspond
6064 * to the default RGB Quantization Range for the transmitted Picture
6065 * unless the Sink indicates support for the Q bit in a Video
6066 * Capabilities Data Block."
6068 * HDMI 2.0 recommends sending non-zero Q when it does match the
6069 * default RGB quantization range for the mode, even when QS=0.
6071 if (info->rgb_quant_range_selectable ||
6072 rgb_quant_range == drm_default_rgb_quant_range(mode))
6073 frame->quantization_range = rgb_quant_range;
6075 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
6079 * "When transmitting any RGB colorimetry, the Source should set the
6080 * YQ-field to match the RGB Quantization Range being transmitted
6081 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6082 * set YQ=1) and the Sink shall ignore the YQ-field."
6084 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6085 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6086 * good way to tell which version of CEA-861 the sink supports, so
6087 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6090 if (!is_hdmi2_sink(connector) ||
6091 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
6092 frame->ycc_quantization_range =
6093 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6095 frame->ycc_quantization_range =
6096 HDMI_YCC_QUANTIZATION_RANGE_FULL;
6098 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6101 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
6103 * @frame: HDMI AVI infoframe
6104 * @conn_state: connector state
6107 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
6108 const struct drm_connector_state *conn_state)
6110 frame->right_bar = conn_state->tv.margins.right;
6111 frame->left_bar = conn_state->tv.margins.left;
6112 frame->top_bar = conn_state->tv.margins.top;
6113 frame->bottom_bar = conn_state->tv.margins.bottom;
6115 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
6117 static enum hdmi_3d_structure
6118 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6120 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6123 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6124 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6125 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6126 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6127 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6128 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6129 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6130 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6131 case DRM_MODE_FLAG_3D_L_DEPTH:
6132 return HDMI_3D_STRUCTURE_L_DEPTH;
6133 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6134 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6135 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6136 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6137 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6138 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6140 return HDMI_3D_STRUCTURE_INVALID;
6145 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6146 * data from a DRM display mode
6147 * @frame: HDMI vendor infoframe
6148 * @connector: the connector
6149 * @mode: DRM display mode
6151 * Note that there's is a need to send HDMI vendor infoframes only when using a
6152 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6153 * function will return -EINVAL, error that can be safely ignored.
6155 * Return: 0 on success or a negative error code on failure.
6158 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
6159 const struct drm_connector *connector,
6160 const struct drm_display_mode *mode)
6163 * FIXME: sil-sii8620 doesn't have a connector around when
6164 * we need one, so we have to be prepared for a NULL connector.
6166 bool has_hdmi_infoframe = connector ?
6167 connector->display_info.has_hdmi_infoframe : false;
6170 if (!frame || !mode)
6173 if (!has_hdmi_infoframe)
6176 err = hdmi_vendor_infoframe_init(frame);
6181 * Even if it's not absolutely necessary to send the infoframe
6182 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6183 * know that the sink can handle it. This is based on a
6184 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
6185 * have trouble realizing that they should switch from 3D to 2D
6186 * mode if the source simply stops sending the infoframe when
6187 * it wants to switch from 3D to 2D.
6189 frame->vic = drm_mode_hdmi_vic(connector, mode);
6190 frame->s3d_struct = s3d_structure_from_display_mode(mode);
6194 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
6196 static void drm_parse_tiled_block(struct drm_connector *connector,
6197 const struct displayid_block *block)
6199 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
6201 u8 tile_v_loc, tile_h_loc;
6202 u8 num_v_tile, num_h_tile;
6203 struct drm_tile_group *tg;
6205 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6206 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6208 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6209 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6210 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6211 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6213 connector->has_tile = true;
6214 if (tile->tile_cap & 0x80)
6215 connector->tile_is_single_monitor = true;
6217 connector->num_h_tile = num_h_tile + 1;
6218 connector->num_v_tile = num_v_tile + 1;
6219 connector->tile_h_loc = tile_h_loc;
6220 connector->tile_v_loc = tile_v_loc;
6221 connector->tile_h_size = w + 1;
6222 connector->tile_v_size = h + 1;
6224 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6225 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6226 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6227 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6228 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6230 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
6232 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
6236 if (connector->tile_group != tg) {
6237 /* if we haven't got a pointer,
6238 take the reference, drop ref to old tile group */
6239 if (connector->tile_group)
6240 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6241 connector->tile_group = tg;
6243 /* if same tile group, then release the ref we just took. */
6244 drm_mode_put_tile_group(connector->dev, tg);
6248 void drm_update_tile_info(struct drm_connector *connector,
6249 const struct edid *edid)
6251 const struct displayid_block *block;
6252 struct displayid_iter iter;
6254 connector->has_tile = false;
6256 displayid_iter_edid_begin(edid, &iter);
6257 displayid_iter_for_each(block, &iter) {
6258 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6259 drm_parse_tiled_block(connector, block);
6261 displayid_iter_end(&iter);
6263 if (!connector->has_tile && connector->tile_group) {
6264 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6265 connector->tile_group = NULL;
git.samba.org / sfrench / cifs-2.6.git / blob