drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * DesignWare HDMI audio driver
   4  *
   5  * Written and tested against the Designware HDMI Tx found in iMX6.
   6  */
   7 #include <linux/io.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/module.h>
  10 #include <linux/platform_device.h>
  11 #include <drm/bridge/dw_hdmi.h>
  12 #include <drm/drm_edid.h>
  13
  14 #include <sound/asoundef.h>
  15 #include <sound/core.h>
  16 #include <sound/initval.h>
  17 #include <sound/pcm.h>
  18 #include <sound/pcm_drm_eld.h>
  19 #include <sound/pcm_iec958.h>
  20
  21 #include "dw-hdmi-audio.h"
  22
  23 #define DRIVER_NAME "dw-hdmi-ahb-audio"
  24
  25 /* Provide some bits rather than bit offsets */
  26 enum {
  27         HDMI_AHB_DMA_CONF0_SW_FIFO_RST = BIT(7),
  28         HDMI_AHB_DMA_CONF0_EN_HLOCK = BIT(3),
  29         HDMI_AHB_DMA_START_START = BIT(0),
  30         HDMI_AHB_DMA_STOP_STOP = BIT(0),
  31         HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = BIT(5),
  32         HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = BIT(4),
  33         HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = BIT(3),
  34         HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = BIT(2),
  35         HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = BIT(1),
  36         HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0),
  37         HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL =
  38                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR |
  39                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST |
  40                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY |
  41                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE |
  42                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL |
  43                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY,
  44         HDMI_IH_AHBDMAAUD_STAT0_ERROR = BIT(5),
  45         HDMI_IH_AHBDMAAUD_STAT0_LOST = BIT(4),
  46         HDMI_IH_AHBDMAAUD_STAT0_RETRY = BIT(3),
  47         HDMI_IH_AHBDMAAUD_STAT0_DONE = BIT(2),
  48         HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = BIT(1),
  49         HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0),
  50         HDMI_IH_AHBDMAAUD_STAT0_ALL =
  51                 HDMI_IH_AHBDMAAUD_STAT0_ERROR |
  52                 HDMI_IH_AHBDMAAUD_STAT0_LOST |
  53                 HDMI_IH_AHBDMAAUD_STAT0_RETRY |
  54                 HDMI_IH_AHBDMAAUD_STAT0_DONE |
  55                 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL |
  56                 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY,
  57         HDMI_AHB_DMA_CONF0_INCR16 = 2 << 1,
  58         HDMI_AHB_DMA_CONF0_INCR8 = 1 << 1,
  59         HDMI_AHB_DMA_CONF0_INCR4 = 0,
  60         HDMI_AHB_DMA_CONF0_BURST_MODE = BIT(0),
  61         HDMI_AHB_DMA_MASK_DONE = BIT(7),
  62
  63         HDMI_REVISION_ID = 0x0001,
  64         HDMI_IH_AHBDMAAUD_STAT0 = 0x0109,
  65         HDMI_IH_MUTE_AHBDMAAUD_STAT0 = 0x0189,
  66         HDMI_FC_AUDICONF2 = 0x1027,
  67         HDMI_FC_AUDSCONF = 0x1063,
  68         HDMI_FC_AUDSCONF_LAYOUT1 = 1 << 0,
  69         HDMI_FC_AUDSCONF_LAYOUT0 = 0 << 0,
  70         HDMI_AHB_DMA_CONF0 = 0x3600,
  71         HDMI_AHB_DMA_START = 0x3601,
  72         HDMI_AHB_DMA_STOP = 0x3602,
  73         HDMI_AHB_DMA_THRSLD = 0x3603,
  74         HDMI_AHB_DMA_STRADDR0 = 0x3604,
  75         HDMI_AHB_DMA_STPADDR0 = 0x3608,
  76         HDMI_AHB_DMA_MASK = 0x3614,
  77         HDMI_AHB_DMA_POL = 0x3615,
  78         HDMI_AHB_DMA_CONF1 = 0x3616,
  79         HDMI_AHB_DMA_BUFFPOL = 0x361a,
  80 };
  81
  82 struct dw_hdmi_channel_conf {
  83         u8 conf1;
  84         u8 ca;
  85 };
  86
  87 /*
  88  * The default mapping of ALSA channels to HDMI channels and speaker
  89  * allocation bits.  Note that we can't do channel remapping here -
  90  * channels must be in the same order.
  91  *
  92  * Mappings for alsa-lib pcm/surround*.conf files:
  93  *
  94  *              Front   Sur4.0  Sur4.1  Sur5.0  Sur5.1  Sur7.1
  95  * Channels     2       4       6       6       6       8
  96  *
  97  * Our mapping from ALSA channel to CEA686D speaker name and HDMI channel:
  98  *
  99  *                              Number of ALSA channels
 100  * ALSA Channel 2       3       4       5       6       7       8
 101  * 0            FL:0    =       =       =       =       =       =
 102  * 1            FR:1    =       =       =       =       =       =
 103  * 2                    FC:3    RL:4    LFE:2   =       =       =
 104  * 3                            RR:5    RL:4    FC:3    =       =
 105  * 4                                    RR:5    RL:4    =       =
 106  * 5                                            RR:5    =       =
 107  * 6                                                    RC:6    =
 108  * 7                                                    RLC/FRC RLC/FRC
 109  */
 110 static struct dw_hdmi_channel_conf default_hdmi_channel_config[7] = {
 111         { 0x03, 0x00 }, /* FL,FR */
 112         { 0x0b, 0x02 }, /* FL,FR,FC */
 113         { 0x33, 0x08 }, /* FL,FR,RL,RR */
 114         { 0x37, 0x09 }, /* FL,FR,LFE,RL,RR */
 115         { 0x3f, 0x0b }, /* FL,FR,LFE,FC,RL,RR */
 116         { 0x7f, 0x0f }, /* FL,FR,LFE,FC,RL,RR,RC */
 117         { 0xff, 0x13 }, /* FL,FR,LFE,FC,RL,RR,[FR]RC,[FR]LC */
 118 };
 119
 120 struct snd_dw_hdmi {
 121         struct snd_card *card;
 122         struct snd_pcm *pcm;
 123         spinlock_t lock;
 124         struct dw_hdmi_audio_data data;
 125         struct snd_pcm_substream *substream;
 126         void (*reformat)(struct snd_dw_hdmi *, size_t, size_t);
 127         void *buf_src;
 128         void *buf_dst;
 129         dma_addr_t buf_addr;
 130         unsigned buf_offset;
 131         unsigned buf_period;
 132         unsigned buf_size;
 133         unsigned channels;
 134         u8 revision;
 135         u8 iec_offset;
 136         u8 cs[192][8];
 137 };
 138
 139 static void dw_hdmi_writel(u32 val, void __iomem *ptr)
 140 {
 141         writeb_relaxed(val, ptr);
 142         writeb_relaxed(val >> 8, ptr + 1);
 143         writeb_relaxed(val >> 16, ptr + 2);
 144         writeb_relaxed(val >> 24, ptr + 3);
 145 }
 146
 147 /*
 148  * Convert to hardware format: The userspace buffer contains IEC958 samples,
 149  * with the PCUV bits in bits 31..28 and audio samples in bits 27..4.  We
 150  * need these to be in bits 27..24, with the IEC B bit in bit 28, and audio
 151  * samples in 23..0.
 152  *
 153  * Default preamble in bits 3..0: 8 = block start, 4 = even 2 = odd
 154  *
 155  * Ideally, we could do with having the data properly formatted in userspace.
 156  */
 157 static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw,
 158         size_t offset, size_t bytes)
 159 {
 160         u32 *src = dw->buf_src + offset;
 161         u32 *dst = dw->buf_dst + offset;
 162         u32 *end = dw->buf_src + offset + bytes;
 163
 164         do {
 165                 u32 b, sample = *src++;
 166
 167                 b = (sample & 8) << (28 - 3);
 168
 169                 sample >>= 4;
 170
 171                 *dst++ = sample | b;
 172         } while (src < end);
 173 }
 174
 175 static u32 parity(u32 sample)
 176 {
 177         sample ^= sample >> 16;
 178         sample ^= sample >> 8;
 179         sample ^= sample >> 4;
 180         sample ^= sample >> 2;
 181         sample ^= sample >> 1;
 182         return (sample & 1) << 27;
 183 }
 184
 185 static void dw_hdmi_reformat_s24(struct snd_dw_hdmi *dw,
 186         size_t offset, size_t bytes)
 187 {
 188         u32 *src = dw->buf_src + offset;
 189         u32 *dst = dw->buf_dst + offset;
 190         u32 *end = dw->buf_src + offset + bytes;
 191
 192         do {
 193                 unsigned i;
 194                 u8 *cs;
 195
 196                 cs = dw->cs[dw->iec_offset++];
 197                 if (dw->iec_offset >= 192)
 198                         dw->iec_offset = 0;
 199
 200                 i = dw->channels;
 201                 do {
 202                         u32 sample = *src++;
 203
 204                         sample &= ~0xff000000;
 205                         sample |= *cs++ << 24;
 206                         sample |= parity(sample & ~0xf8000000);
 207
 208                         *dst++ = sample;
 209                 } while (--i);
 210         } while (src < end);
 211 }
 212
 213 static void dw_hdmi_create_cs(struct snd_dw_hdmi *dw,
 214         struct snd_pcm_runtime *runtime)
 215 {
 216         u8 cs[4];
 217         unsigned ch, i, j;
 218
 219         snd_pcm_create_iec958_consumer(runtime, cs, sizeof(cs));
 220
 221         memset(dw->cs, 0, sizeof(dw->cs));
 222
 223         for (ch = 0; ch < 8; ch++) {
 224                 cs[2] &= ~IEC958_AES2_CON_CHANNEL;
 225                 cs[2] |= (ch + 1) << 4;
 226
 227                 for (i = 0; i < ARRAY_SIZE(cs); i++) {
 228                         unsigned c = cs[i];
 229
 230                         for (j = 0; j < 8; j++, c >>= 1)
 231                                 dw->cs[i * 8 + j][ch] = (c & 1) << 2;
 232                 }
 233         }
 234         dw->cs[0][0] |= BIT(4);
 235 }
 236
 237 static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw)
 238 {
 239         void __iomem *base = dw->data.base;
 240         unsigned offset = dw->buf_offset;
 241         unsigned period = dw->buf_period;
 242         u32 start, stop;
 243
 244         dw->reformat(dw, offset, period);
 245
 246         /* Clear all irqs before enabling irqs and starting DMA */
 247         writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL,
 248                        base + HDMI_IH_AHBDMAAUD_STAT0);
 249
 250         start = dw->buf_addr + offset;
 251         stop = start + period - 1;
 252
 253         /* Setup the hardware start/stop addresses */
 254         dw_hdmi_writel(start, base + HDMI_AHB_DMA_STRADDR0);
 255         dw_hdmi_writel(stop, base + HDMI_AHB_DMA_STPADDR0);
 256
 257         writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK);
 258         writeb(HDMI_AHB_DMA_START_START, base + HDMI_AHB_DMA_START);
 259
 260         offset += period;
 261         if (offset >= dw->buf_size)
 262                 offset = 0;
 263         dw->buf_offset = offset;
 264 }
 265
 266 static void dw_hdmi_stop_dma(struct snd_dw_hdmi *dw)
 267 {
 268         /* Disable interrupts before disabling DMA */
 269         writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK);
 270         writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP);
 271 }
 272
 273 static irqreturn_t snd_dw_hdmi_irq(int irq, void *data)
 274 {
 275         struct snd_dw_hdmi *dw = data;
 276         struct snd_pcm_substream *substream;
 277         unsigned stat;
 278
 279         stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);
 280         if (!stat)
 281                 return IRQ_NONE;
 282
 283         writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);
 284
 285         substream = dw->substream;
 286         if (stat & HDMI_IH_AHBDMAAUD_STAT0_DONE && substream) {
 287                 snd_pcm_period_elapsed(substream);
 288
 289                 spin_lock(&dw->lock);
 290                 if (dw->substream)
 291                         dw_hdmi_start_dma(dw);
 292                 spin_unlock(&dw->lock);
 293         }
 294
 295         return IRQ_HANDLED;
 296 }
 297
 298 static struct snd_pcm_hardware dw_hdmi_hw = {
 299         .info = SNDRV_PCM_INFO_INTERLEAVED |
 300                 SNDRV_PCM_INFO_BLOCK_TRANSFER |
 301                 SNDRV_PCM_INFO_MMAP |
 302                 SNDRV_PCM_INFO_MMAP_VALID,
 303         .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE |
 304                    SNDRV_PCM_FMTBIT_S24_LE,
 305         .rates = SNDRV_PCM_RATE_32000 |
 306                  SNDRV_PCM_RATE_44100 |
 307                  SNDRV_PCM_RATE_48000 |
 308                  SNDRV_PCM_RATE_88200 |
 309                  SNDRV_PCM_RATE_96000 |
 310                  SNDRV_PCM_RATE_176400 |
 311                  SNDRV_PCM_RATE_192000,
 312         .channels_min = 2,
 313         .channels_max = 8,
 314         .buffer_bytes_max = 1024 * 1024,
 315         .period_bytes_min = 256,
 316         .period_bytes_max = 8192,       /* ERR004323: must limit to 8k */
 317         .periods_min = 2,
 318         .periods_max = 16,
 319         .fifo_size = 0,
 320 };
 321
 322 static int dw_hdmi_open(struct snd_pcm_substream *substream)
 323 {
 324         struct snd_pcm_runtime *runtime = substream->runtime;
 325         struct snd_dw_hdmi *dw = substream->private_data;
 326         void __iomem *base = dw->data.base;
 327         int ret;
 328
 329         runtime->hw = dw_hdmi_hw;
 330
 331         ret = snd_pcm_hw_constraint_eld(runtime, dw->data.eld);
 332         if (ret < 0)
 333                 return ret;
 334
 335         ret = snd_pcm_limit_hw_rates(runtime);
 336         if (ret < 0)
 337                 return ret;
 338
 339         ret = snd_pcm_hw_constraint_integer(runtime,
 340                                             SNDRV_PCM_HW_PARAM_PERIODS);
 341         if (ret < 0)
 342                 return ret;
 343
 344         /* Limit the buffer size to the size of the preallocated buffer */
 345         ret = snd_pcm_hw_constraint_minmax(runtime,
 346                                            SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 347                                            0, substream->dma_buffer.bytes);
 348         if (ret < 0)
 349                 return ret;
 350
 351         /* Clear FIFO */
 352         writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST,
 353                        base + HDMI_AHB_DMA_CONF0);
 354
 355         /* Configure interrupt polarities */
 356         writeb_relaxed(~0, base + HDMI_AHB_DMA_POL);
 357         writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL);
 358
 359         /* Keep interrupts masked, and clear any pending */
 360         writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK);
 361         writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0);
 362
 363         ret = request_irq(dw->data.irq, snd_dw_hdmi_irq, IRQF_SHARED,
 364                           "dw-hdmi-audio", dw);
 365         if (ret)
 366                 return ret;
 367
 368         /* Un-mute done interrupt */
 369         writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL &
 370                        ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE,
 371                        base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
 372
 373         return 0;
 374 }
 375
 376 static int dw_hdmi_close(struct snd_pcm_substream *substream)
 377 {
 378         struct snd_dw_hdmi *dw = substream->private_data;
 379
 380         /* Mute all interrupts */
 381         writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,
 382                        dw->data.base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
 383
 384         free_irq(dw->data.irq, dw);
 385
 386         return 0;
 387 }
 388
 389 static int dw_hdmi_hw_free(struct snd_pcm_substream *substream)
 390 {
 391         return snd_pcm_lib_free_vmalloc_buffer(substream);
 392 }
 393
 394 static int dw_hdmi_hw_params(struct snd_pcm_substream *substream,
 395         struct snd_pcm_hw_params *params)
 396 {
 397         /* Allocate the PCM runtime buffer, which is exposed to userspace. */
 398         return snd_pcm_lib_alloc_vmalloc_buffer(substream,
 399                                                 params_buffer_bytes(params));
 400 }
 401
 402 static int dw_hdmi_prepare(struct snd_pcm_substream *substream)
 403 {
 404         struct snd_pcm_runtime *runtime = substream->runtime;
 405         struct snd_dw_hdmi *dw = substream->private_data;
 406         u8 threshold, conf0, conf1, layout, ca;
 407
 408         /* Setup as per 3.0.5 FSL 4.1.0 BSP */
 409         switch (dw->revision) {
 410         case 0x0a:
 411                 conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
 412                         HDMI_AHB_DMA_CONF0_INCR4;
 413                 if (runtime->channels == 2)
 414                         threshold = 126;
 415                 else
 416                         threshold = 124;
 417                 break;
 418         case 0x1a:
 419                 conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
 420                         HDMI_AHB_DMA_CONF0_INCR8;
 421                 threshold = 128;
 422                 break;
 423         default:
 424                 /* NOTREACHED */
 425                 return -EINVAL;
 426         }
 427
 428         dw_hdmi_set_sample_rate(dw->data.hdmi, runtime->rate);
 429
 430         /* Minimum number of bytes in the fifo. */
 431         runtime->hw.fifo_size = threshold * 32;
 432
 433         conf0 |= HDMI_AHB_DMA_CONF0_EN_HLOCK;
 434         conf1 = default_hdmi_channel_config[runtime->channels - 2].conf1;
 435         ca = default_hdmi_channel_config[runtime->channels - 2].ca;
 436
 437         /*
 438          * For >2 channel PCM audio, we need to select layout 1
 439          * and set an appropriate channel map.
 440          */
 441         if (runtime->channels > 2)
 442                 layout = HDMI_FC_AUDSCONF_LAYOUT1;
 443         else
 444                 layout = HDMI_FC_AUDSCONF_LAYOUT0;
 445
 446         writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD);
 447         writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0);
 448         writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1);
 449         writeb_relaxed(layout, dw->data.base + HDMI_FC_AUDSCONF);
 450         writeb_relaxed(ca, dw->data.base + HDMI_FC_AUDICONF2);
 451
 452         switch (runtime->format) {
 453         case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
 454                 dw->reformat = dw_hdmi_reformat_iec958;
 455                 break;
 456         case SNDRV_PCM_FORMAT_S24_LE:
 457                 dw_hdmi_create_cs(dw, runtime);
 458                 dw->reformat = dw_hdmi_reformat_s24;
 459                 break;
 460         }
 461         dw->iec_offset = 0;
 462         dw->channels = runtime->channels;
 463         dw->buf_src  = runtime->dma_area;
 464         dw->buf_dst  = substream->dma_buffer.area;
 465         dw->buf_addr = substream->dma_buffer.addr;
 466         dw->buf_period = snd_pcm_lib_period_bytes(substream);
 467         dw->buf_size = snd_pcm_lib_buffer_bytes(substream);
 468
 469         return 0;
 470 }
 471
 472 static int dw_hdmi_trigger(struct snd_pcm_substream *substream, int cmd)
 473 {
 474         struct snd_dw_hdmi *dw = substream->private_data;
 475         unsigned long flags;
 476         int ret = 0;
 477
 478         switch (cmd) {
 479         case SNDRV_PCM_TRIGGER_START:
 480                 spin_lock_irqsave(&dw->lock, flags);
 481                 dw->buf_offset = 0;
 482                 dw->substream = substream;
 483                 dw_hdmi_start_dma(dw);
 484                 dw_hdmi_audio_enable(dw->data.hdmi);
 485                 spin_unlock_irqrestore(&dw->lock, flags);
 486                 substream->runtime->delay = substream->runtime->period_size;
 487                 break;
 488
 489         case SNDRV_PCM_TRIGGER_STOP:
 490                 spin_lock_irqsave(&dw->lock, flags);
 491                 dw->substream = NULL;
 492                 dw_hdmi_stop_dma(dw);
 493                 dw_hdmi_audio_disable(dw->data.hdmi);
 494                 spin_unlock_irqrestore(&dw->lock, flags);
 495                 break;
 496
 497         default:
 498                 ret = -EINVAL;
 499                 break;
 500         }
 501
 502         return ret;
 503 }
 504
 505 static snd_pcm_uframes_t dw_hdmi_pointer(struct snd_pcm_substream *substream)
 506 {
 507         struct snd_pcm_runtime *runtime = substream->runtime;
 508         struct snd_dw_hdmi *dw = substream->private_data;
 509
 510         /*
 511          * We are unable to report the exact hardware position as
 512          * reading the 32-bit DMA position using 8-bit reads is racy.
 513          */
 514         return bytes_to_frames(runtime, dw->buf_offset);
 515 }
 516
 517 static const struct snd_pcm_ops snd_dw_hdmi_ops = {
 518         .open = dw_hdmi_open,
 519         .close = dw_hdmi_close,
 520         .ioctl = snd_pcm_lib_ioctl,
 521         .hw_params = dw_hdmi_hw_params,
 522         .hw_free = dw_hdmi_hw_free,
 523         .prepare = dw_hdmi_prepare,
 524         .trigger = dw_hdmi_trigger,
 525         .pointer = dw_hdmi_pointer,
 526         .page = snd_pcm_lib_get_vmalloc_page,
 527 };
 528
 529 static int snd_dw_hdmi_probe(struct platform_device *pdev)
 530 {
 531         const struct dw_hdmi_audio_data *data = pdev->dev.platform_data;
 532         struct device *dev = pdev->dev.parent;
 533         struct snd_dw_hdmi *dw;
 534         struct snd_card *card;
 535         struct snd_pcm *pcm;
 536         unsigned revision;
 537         int ret;
 538
 539         writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,
 540                        data->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
 541         revision = readb_relaxed(data->base + HDMI_REVISION_ID);
 542         if (revision != 0x0a && revision != 0x1a) {
 543                 dev_err(dev, "dw-hdmi-audio: unknown revision 0x%02x\n",
 544                         revision);
 545                 return -ENXIO;
 546         }
 547
 548         ret = snd_card_new(dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
 549                               THIS_MODULE, sizeof(struct snd_dw_hdmi), &card);
 550         if (ret < 0)
 551                 return ret;
 552
 553         strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
 554         strlcpy(card->shortname, "DW-HDMI", sizeof(card->shortname));
 555         snprintf(card->longname, sizeof(card->longname),
 556                  "%s rev 0x%02x, irq %d", card->shortname, revision,
 557                  data->irq);
 558
 559         dw = card->private_data;
 560         dw->card = card;
 561         dw->data = *data;
 562         dw->revision = revision;
 563
 564         spin_lock_init(&dw->lock);
 565
 566         ret = snd_pcm_new(card, "DW HDMI", 0, 1, 0, &pcm);
 567         if (ret < 0)
 568                 goto err;
 569
 570         dw->pcm = pcm;
 571         pcm->private_data = dw;
 572         strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
 573         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dw_hdmi_ops);
 574
 575         /*
 576          * To support 8-channel 96kHz audio reliably, we need 512k
 577          * to satisfy alsa with our restricted period (ERR004323).
 578          */
 579         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 580                         dev, 128 * 1024, 1024 * 1024);
 581
 582         ret = snd_card_register(card);
 583         if (ret < 0)
 584                 goto err;
 585
 586         platform_set_drvdata(pdev, dw);
 587
 588         return 0;
 589
 590 err:
 591         snd_card_free(card);
 592         return ret;
 593 }
 594
 595 static int snd_dw_hdmi_remove(struct platform_device *pdev)
 596 {
 597         struct snd_dw_hdmi *dw = platform_get_drvdata(pdev);
 598
 599         snd_card_free(dw->card);
 600
 601         return 0;
 602 }
 603
 604 #if defined(CONFIG_PM_SLEEP) && defined(IS_NOT_BROKEN)
 605 /*
 606  * This code is fine, but requires implementation in the dw_hdmi_trigger()
 607  * method which is currently missing as I have no way to test this.
 608  */
 609 static int snd_dw_hdmi_suspend(struct device *dev)
 610 {
 611         struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
 612
 613         snd_power_change_state(dw->card, SNDRV_CTL_POWER_D3cold);
 614
 615         return 0;
 616 }
 617
 618 static int snd_dw_hdmi_resume(struct device *dev)
 619 {
 620         struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
 621
 622         snd_power_change_state(dw->card, SNDRV_CTL_POWER_D0);
 623
 624         return 0;
 625 }
 626
 627 static SIMPLE_DEV_PM_OPS(snd_dw_hdmi_pm, snd_dw_hdmi_suspend,
 628                          snd_dw_hdmi_resume);
 629 #define PM_OPS &snd_dw_hdmi_pm
 630 #else
 631 #define PM_OPS NULL
 632 #endif
 633
 634 static struct platform_driver snd_dw_hdmi_driver = {
 635         .probe  = snd_dw_hdmi_probe,
 636         .remove = snd_dw_hdmi_remove,
 637         .driver = {
 638                 .name = DRIVER_NAME,
 639                 .pm = PM_OPS,
 640         },
 641 };
 642
 643 module_platform_driver(snd_dw_hdmi_driver);
 644
 645 MODULE_AUTHOR("Russell King <rmk+kernel@arm.linux.org.uk>");
 646 MODULE_DESCRIPTION("Synopsis Designware HDMI AHB ALSA interface");
 647 MODULE_LICENSE("GPL v2");
 648 MODULE_ALIAS("platform:" DRIVER_NAME);