drivers/gpu/drm/amd/powerplay/inc/smu72.h

   1 #ifndef SMU72_H
   2 #define SMU72_H
   3
   4 #if !defined(SMC_MICROCODE)
   5 #pragma pack(push, 1)
   6 #endif
   7
   8 #define SMU__NUM_SCLK_DPM_STATE  8
   9 #define SMU__NUM_MCLK_DPM_LEVELS 4
  10 #define SMU__NUM_LCLK_DPM_LEVELS 8
  11 #define SMU__NUM_PCIE_DPM_LEVELS 8
  12
  13 enum SID_OPTION {
  14         SID_OPTION_HI,
  15         SID_OPTION_LO,
  16         SID_OPTION_COUNT
  17 };
  18
  19 enum Poly3rdOrderCoeff {
  20         LEAKAGE_TEMPERATURE_SCALAR,
  21         LEAKAGE_VOLTAGE_SCALAR,
  22         DYNAMIC_VOLTAGE_SCALAR,
  23         POLY_3RD_ORDER_COUNT
  24 };
  25
  26 struct SMU7_Poly3rdOrder_Data {
  27         int32_t a;
  28         int32_t b;
  29         int32_t c;
  30         int32_t d;
  31         uint8_t a_shift;
  32         uint8_t b_shift;
  33         uint8_t c_shift;
  34         uint8_t x_shift;
  35 };
  36
  37 typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
  38
  39 struct Power_Calculator_Data {
  40         uint16_t NoLoadVoltage;
  41         uint16_t LoadVoltage;
  42         uint16_t Resistance;
  43         uint16_t Temperature;
  44         uint16_t BaseLeakage;
  45         uint16_t LkgTempScalar;
  46         uint16_t LkgVoltScalar;
  47         uint16_t LkgAreaScalar;
  48         uint16_t LkgPower;
  49         uint16_t DynVoltScalar;
  50         uint32_t Cac;
  51         uint32_t DynPower;
  52         uint32_t TotalCurrent;
  53         uint32_t TotalPower;
  54 };
  55
  56 typedef struct Power_Calculator_Data PowerCalculatorData_t;
  57
  58 struct Gc_Cac_Weight_Data {
  59         uint8_t index;
  60         uint32_t value;
  61 };
  62
  63 typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
  64
  65
  66 typedef struct {
  67         uint32_t high;
  68         uint32_t low;
  69 } data_64_t;
  70
  71 typedef struct {
  72         data_64_t high;
  73         data_64_t low;
  74 } data_128_t;
  75
  76 #define SMU7_CONTEXT_ID_SMC        1
  77 #define SMU7_CONTEXT_ID_VBIOS      2
  78
  79 #define SMU72_MAX_LEVELS_VDDC            16
  80 #define SMU72_MAX_LEVELS_VDDGFX          16
  81 #define SMU72_MAX_LEVELS_VDDCI           8
  82 #define SMU72_MAX_LEVELS_MVDD            4
  83
  84 #define SMU_MAX_SMIO_LEVELS              4
  85
  86 #define SMU72_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   /* SCLK + SQ DPM + ULV */
  87 #define SMU72_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   /* MCLK Levels DPM */
  88 #define SMU72_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  /* LCLK Levels */
  89 #define SMU72_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  /* PCIe speed and number of lanes. */
  90 #define SMU72_MAX_LEVELS_UVD             8   /* VCLK/DCLK levels for UVD. */
  91 #define SMU72_MAX_LEVELS_VCE             8   /* ECLK levels for VCE. */
  92 #define SMU72_MAX_LEVELS_ACP             8   /* ACLK levels for ACP. */
  93 #define SMU72_MAX_LEVELS_SAMU            8   /* SAMCLK levels for SAMU. */
  94 #define SMU72_MAX_ENTRIES_SMIO           32  /* Number of entries in SMIO table. */
  95
  96 #define DPM_NO_LIMIT 0
  97 #define DPM_NO_UP 1
  98 #define DPM_GO_DOWN 2
  99 #define DPM_GO_UP 3
 100
 101 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
 102 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
 103
 104 #define GPIO_CLAMP_MODE_VRHOT      1
 105 #define GPIO_CLAMP_MODE_THERM      2
 106 #define GPIO_CLAMP_MODE_DC         4
 107
 108 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
 109 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
 110 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
 111 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
 112 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
 113 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
 114 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
 115 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
 116 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
 117 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
 118 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
 119 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
 120 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
 121 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
 122 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
 123 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
 124 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
 125 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
 126 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
 127 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
 128
 129 /* Virtualization Defines */
 130 #define CG_XDMA_MASK  0x1
 131 #define CG_XDMA_SHIFT 0
 132 #define CG_UVD_MASK   0x2
 133 #define CG_UVD_SHIFT  1
 134 #define CG_VCE_MASK   0x4
 135 #define CG_VCE_SHIFT  2
 136 #define CG_SAMU_MASK  0x8
 137 #define CG_SAMU_SHIFT 3
 138 #define CG_GFX_MASK   0x10
 139 #define CG_GFX_SHIFT  4
 140 #define CG_SDMA_MASK  0x20
 141 #define CG_SDMA_SHIFT 5
 142 #define CG_HDP_MASK   0x40
 143 #define CG_HDP_SHIFT  6
 144 #define CG_MC_MASK    0x80
 145 #define CG_MC_SHIFT   7
 146 #define CG_DRM_MASK   0x100
 147 #define CG_DRM_SHIFT  8
 148 #define CG_ROM_MASK   0x200
 149 #define CG_ROM_SHIFT  9
 150 #define CG_BIF_MASK   0x400
 151 #define CG_BIF_SHIFT  10
 152
 153 #define SMU72_DTE_ITERATIONS 5
 154 #define SMU72_DTE_SOURCES 3
 155 #define SMU72_DTE_SINKS 1
 156 #define SMU72_NUM_CPU_TES 0
 157 #define SMU72_NUM_GPU_TES 1
 158 #define SMU72_NUM_NON_TES 2
 159 #define SMU72_DTE_FAN_SCALAR_MIN 0x100
 160 #define SMU72_DTE_FAN_SCALAR_MAX 0x166
 161 #define SMU72_DTE_FAN_TEMP_MAX 93
 162 #define SMU72_DTE_FAN_TEMP_MIN 83
 163
 164 #if defined SMU__FUSION_ONLY
 165 #define SMU7_DTE_ITERATIONS 5
 166 #define SMU7_DTE_SOURCES 5
 167 #define SMU7_DTE_SINKS 3
 168 #define SMU7_NUM_CPU_TES 2
 169 #define SMU7_NUM_GPU_TES 1
 170 #define SMU7_NUM_NON_TES 2
 171 #endif
 172
 173 struct SMU7_HystController_Data {
 174         uint8_t waterfall_up;
 175         uint8_t waterfall_down;
 176         uint8_t waterfall_limit;
 177         uint8_t spare;
 178         uint16_t release_cnt;
 179         uint16_t release_limit;
 180 };
 181
 182 typedef struct SMU7_HystController_Data SMU7_HystController_Data;
 183
 184 struct SMU72_PIDController {
 185         uint32_t Ki;
 186         int32_t LFWindupUpperLim;
 187         int32_t LFWindupLowerLim;
 188         uint32_t StatePrecision;
 189         uint32_t LfPrecision;
 190         uint32_t LfOffset;
 191         uint32_t MaxState;
 192         uint32_t MaxLfFraction;
 193         uint32_t StateShift;
 194 };
 195
 196 typedef struct SMU72_PIDController SMU72_PIDController;
 197
 198 struct SMU7_LocalDpmScoreboard {
 199         uint32_t PercentageBusy;
 200
 201         int32_t  PIDError;
 202         int32_t  PIDIntegral;
 203         int32_t  PIDOutput;
 204
 205         uint32_t SigmaDeltaAccum;
 206         uint32_t SigmaDeltaOutput;
 207         uint32_t SigmaDeltaLevel;
 208
 209         uint32_t UtilizationSetpoint;
 210
 211         uint8_t  TdpClampMode;
 212         uint8_t  TdcClampMode;
 213         uint8_t  ThermClampMode;
 214         uint8_t  VoltageBusy;
 215
 216         int8_t   CurrLevel;
 217         int8_t   TargLevel;
 218         uint8_t  LevelChangeInProgress;
 219         uint8_t  UpHyst;
 220
 221         uint8_t  DownHyst;
 222         uint8_t  VoltageDownHyst;
 223         uint8_t  DpmEnable;
 224         uint8_t  DpmRunning;
 225
 226         uint8_t  DpmForce;
 227         uint8_t  DpmForceLevel;
 228         uint8_t  DisplayWatermark;
 229         uint8_t  McArbIndex;
 230
 231         uint32_t MinimumPerfSclk;
 232
 233         uint8_t  AcpiReq;
 234         uint8_t  AcpiAck;
 235         uint8_t  GfxClkSlow;
 236         uint8_t  GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */
 237
 238         uint8_t  FpsFilterWeight;
 239         uint8_t  EnabledLevelsChange;
 240         uint8_t  DteClampMode;
 241         uint8_t  FpsClampMode;
 242
 243         uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS];
 244         uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS];
 245
 246         void     (*TargetStateCalculator)(uint8_t);
 247         void     (*SavedTargetStateCalculator)(uint8_t);
 248
 249         uint16_t AutoDpmInterval;
 250         uint16_t AutoDpmRange;
 251
 252         uint8_t  FpsEnabled;
 253         uint8_t  MaxPerfLevel;
 254         uint8_t  AllowLowClkInterruptToHost;
 255         uint8_t  FpsRunning;
 256
 257         uint32_t MaxAllowedFrequency;
 258
 259         uint32_t FilteredSclkFrequency;
 260         uint32_t LastSclkFrequency;
 261         uint32_t FilteredSclkFrequencyCnt;
 262 };
 263
 264 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
 265
 266 #define SMU7_MAX_VOLTAGE_CLIENTS 12
 267
 268 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
 269
 270 struct SMU_VoltageLevel {
 271         uint8_t Vddc;
 272         uint8_t Vddci;
 273         uint8_t VddGfx;
 274         uint8_t Phases;
 275 };
 276
 277 typedef struct SMU_VoltageLevel SMU_VoltageLevel;
 278
 279 struct SMU7_VoltageScoreboard {
 280         SMU_VoltageLevel CurrentVoltage;
 281         SMU_VoltageLevel TargetVoltage;
 282         uint16_t MaxVid;
 283         uint8_t  HighestVidOffset;
 284         uint8_t  CurrentVidOffset;
 285
 286         uint8_t  ControllerBusy;
 287         uint8_t  CurrentVid;
 288         uint8_t  CurrentVddciVid;
 289         uint8_t  VddGfxShutdown; /* 0 = normal mode, 1 = shut down */
 290
 291         SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
 292         uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
 293
 294         uint8_t  TargetIndex;
 295         uint8_t  Delay;
 296         uint8_t  ControllerEnable;
 297         uint8_t  ControllerRunning;
 298         uint16_t CurrentStdVoltageHiSidd;
 299         uint16_t CurrentStdVoltageLoSidd;
 300         uint8_t  OverrideVoltage;
 301         uint8_t  VddcUseUlvOffset;
 302         uint8_t  VddGfxUseUlvOffset;
 303         uint8_t  padding;
 304
 305         VoltageChangeHandler_t ChangeVddc;
 306         VoltageChangeHandler_t ChangeVddGfx;
 307         VoltageChangeHandler_t ChangeVddci;
 308         VoltageChangeHandler_t ChangePhase;
 309         VoltageChangeHandler_t ChangeMvdd;
 310
 311         VoltageChangeHandler_t functionLinks[6];
 312
 313         uint8_t *VddcFollower1;
 314         uint8_t *VddcFollower2;
 315         int16_t  Driver_OD_RequestedVidOffset1;
 316         int16_t  Driver_OD_RequestedVidOffset2;
 317
 318 };
 319
 320 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
 321
 322 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
 323
 324 struct SMU7_PCIeLinkSpeedScoreboard {
 325         uint8_t     DpmEnable;
 326         uint8_t     DpmRunning;
 327         uint8_t     DpmForce;
 328         uint8_t     DpmForceLevel;
 329
 330         uint8_t     CurrentLinkSpeed;
 331         uint8_t     EnabledLevelsChange;
 332         uint16_t    AutoDpmInterval;
 333
 334         uint16_t    AutoDpmRange;
 335         uint16_t    AutoDpmCount;
 336
 337         uint8_t     DpmMode;
 338         uint8_t     AcpiReq;
 339         uint8_t     AcpiAck;
 340         uint8_t     CurrentLinkLevel;
 341
 342 };
 343
 344 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
 345
 346 /* -------------------------------------------------------- CAC table ------------------------------------------------------ */
 347 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
 348 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
 349 #define SMU7_SCALE_I  7
 350 #define SMU7_SCALE_R 12
 351
 352 struct SMU7_PowerScoreboard {
 353         PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT];
 354         PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
 355
 356         uint32_t TotalGpuPower;
 357         uint32_t TdcCurrent;
 358
 359         uint16_t   VddciTotalPower;
 360         uint16_t   sparesasfsdfd;
 361         uint16_t   Vddr1Power;
 362         uint16_t   RocPower;
 363
 364         uint16_t   CalcMeasPowerBlend;
 365         uint8_t    SidOptionPower;
 366         uint8_t    SidOptionCurrent;
 367
 368         uint32_t   WinTime;
 369
 370         uint16_t Telemetry_1_slope;
 371         uint16_t Telemetry_2_slope;
 372         int32_t Telemetry_1_offset;
 373         int32_t Telemetry_2_offset;
 374
 375         uint32_t VddcCurrentTelemetry;
 376         uint32_t VddGfxCurrentTelemetry;
 377         uint32_t VddcPowerTelemetry;
 378         uint32_t VddGfxPowerTelemetry;
 379         uint32_t VddciPowerTelemetry;
 380
 381         uint32_t VddcPower;
 382         uint32_t VddGfxPower;
 383         uint32_t VddciPower;
 384
 385         uint32_t TelemetryCurrent[2];
 386         uint32_t TelemetryVoltage[2];
 387         uint32_t TelemetryPower[2];
 388 };
 389
 390 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
 391
 392 struct SMU7_ThermalScoreboard {
 393         int16_t  GpuLimit;
 394         int16_t  GpuHyst;
 395         uint16_t CurrGnbTemp;
 396         uint16_t FilteredGnbTemp;
 397
 398         uint8_t  ControllerEnable;
 399         uint8_t  ControllerRunning;
 400         uint8_t  AutoTmonCalInterval;
 401         uint8_t  AutoTmonCalEnable;
 402
 403         uint8_t  ThermalDpmEnabled;
 404         uint8_t  SclkEnabledMask;
 405         uint8_t  spare[2];
 406         int32_t  temperature_gradient;
 407
 408         SMU7_HystController_Data HystControllerData;
 409         int32_t  WeightedSensorTemperature;
 410         uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS];
 411         uint32_t Alpha;
 412 };
 413
 414 typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
 415
 416 /* For FeatureEnables: */
 417 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
 418 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
 419 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
 420 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
 421 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
 422 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
 423 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
 424 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
 425 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
 426
 427 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
 428 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
 429 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
 430 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
 431 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
 432 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
 433
 434 /* All 'soft registers' should be uint32_t. */
 435 struct SMU72_SoftRegisters {
 436         uint32_t        RefClockFrequency;
 437         uint32_t        PmTimerPeriod;
 438         uint32_t        FeatureEnables;
 439
 440         uint32_t        PreVBlankGap;
 441         uint32_t        VBlankTimeout;
 442         uint32_t        TrainTimeGap;
 443
 444         uint32_t        MvddSwitchTime;
 445         uint32_t        LongestAcpiTrainTime;
 446         uint32_t        AcpiDelay;
 447         uint32_t        G5TrainTime;
 448         uint32_t        DelayMpllPwron;
 449         uint32_t        VoltageChangeTimeout;
 450
 451         uint32_t        HandshakeDisables;
 452
 453         uint8_t         DisplayPhy1Config;
 454         uint8_t         DisplayPhy2Config;
 455         uint8_t         DisplayPhy3Config;
 456         uint8_t         DisplayPhy4Config;
 457
 458         uint8_t         DisplayPhy5Config;
 459         uint8_t         DisplayPhy6Config;
 460         uint8_t         DisplayPhy7Config;
 461         uint8_t         DisplayPhy8Config;
 462
 463         uint32_t        AverageGraphicsActivity;
 464         uint32_t        AverageMemoryActivity;
 465         uint32_t        AverageGioActivity;
 466
 467         uint8_t         SClkDpmEnabledLevels;
 468         uint8_t         MClkDpmEnabledLevels;
 469         uint8_t         LClkDpmEnabledLevels;
 470         uint8_t         PCIeDpmEnabledLevels;
 471
 472         uint8_t         UVDDpmEnabledLevels;
 473         uint8_t         SAMUDpmEnabledLevels;
 474         uint8_t         ACPDpmEnabledLevels;
 475         uint8_t         VCEDpmEnabledLevels;
 476
 477         uint32_t        DRAM_LOG_ADDR_H;
 478         uint32_t        DRAM_LOG_ADDR_L;
 479         uint32_t        DRAM_LOG_PHY_ADDR_H;
 480         uint32_t        DRAM_LOG_PHY_ADDR_L;
 481         uint32_t        DRAM_LOG_BUFF_SIZE;
 482         uint32_t        UlvEnterCount;
 483         uint32_t        UlvTime;
 484         uint32_t        UcodeLoadStatus;
 485         uint32_t        Reserved[2];
 486
 487 };
 488
 489 typedef struct SMU72_SoftRegisters SMU72_SoftRegisters;
 490
 491 struct SMU72_Firmware_Header {
 492         uint32_t Digest[5];
 493         uint32_t Version;
 494         uint32_t HeaderSize;
 495         uint32_t Flags;
 496         uint32_t EntryPoint;
 497         uint32_t CodeSize;
 498         uint32_t ImageSize;
 499
 500         uint32_t Rtos;
 501         uint32_t SoftRegisters;
 502         uint32_t DpmTable;
 503         uint32_t FanTable;
 504         uint32_t CacConfigTable;
 505         uint32_t CacStatusTable;
 506         uint32_t mcRegisterTable;
 507         uint32_t mcArbDramTimingTable;
 508         uint32_t PmFuseTable;
 509         uint32_t Globals;
 510         uint32_t ClockStretcherTable;
 511         uint32_t Reserved[41];
 512         uint32_t Signature;
 513 };
 514
 515 typedef struct SMU72_Firmware_Header SMU72_Firmware_Header;
 516
 517 #define SMU72_FIRMWARE_HEADER_LOCATION 0x20000
 518
 519 enum  DisplayConfig {
 520         PowerDown = 1,
 521         DP54x4,
 522         DP54x2,
 523         DP54x1,
 524         DP27x4,
 525         DP27x2,
 526         DP27x1,
 527         HDMI297,
 528         HDMI162,
 529         LVDS,
 530         DP324x4,
 531         DP324x2,
 532         DP324x1
 533 };
 534
 535 #define MC_BLOCK_COUNT 1
 536 #define CPL_BLOCK_COUNT 5
 537 #define SE_BLOCK_COUNT 15
 538 #define GC_BLOCK_COUNT 24
 539
 540 struct SMU7_Local_Cac {
 541         uint8_t BlockId;
 542         uint8_t SignalId;
 543         uint8_t Threshold;
 544         uint8_t Padding;
 545 };
 546
 547 typedef struct SMU7_Local_Cac SMU7_Local_Cac;
 548
 549 struct SMU7_Local_Cac_Table {
 550         SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
 551         SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
 552         SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
 553         SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
 554 };
 555
 556 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
 557
 558 #if !defined(SMC_MICROCODE)
 559 #pragma pack(pop)
 560 #endif
 561
 562 /* Description of Clock Gating bitmask for Tonga: */
 563 /* System Clock Gating */
 564 #define CG_SYS_BITMASK_FIRST_BIT      0  /* First bit of Sys CG bitmask */
 565 #define CG_SYS_BITMASK_LAST_BIT       9  /* Last bit of Sys CG bitmask */
 566 #define CG_SYS_BIF_MGLS_SHIFT         0
 567 #define CG_SYS_ROM_SHIFT              1
 568 #define CG_SYS_MC_MGCG_SHIFT          2
 569 #define CG_SYS_MC_MGLS_SHIFT          3
 570 #define CG_SYS_SDMA_MGCG_SHIFT        4
 571 #define CG_SYS_SDMA_MGLS_SHIFT        5
 572 #define CG_SYS_DRM_MGCG_SHIFT         6
 573 #define CG_SYS_HDP_MGCG_SHIFT         7
 574 #define CG_SYS_HDP_MGLS_SHIFT         8
 575 #define CG_SYS_DRM_MGLS_SHIFT         9
 576
 577 #define CG_SYS_BIF_MGLS_MASK          0x1
 578 #define CG_SYS_ROM_MASK               0x2
 579 #define CG_SYS_MC_MGCG_MASK           0x4
 580 #define CG_SYS_MC_MGLS_MASK           0x8
 581 #define CG_SYS_SDMA_MGCG_MASK         0x10
 582 #define CG_SYS_SDMA_MGLS_MASK         0x20
 583 #define CG_SYS_DRM_MGCG_MASK          0x40
 584 #define CG_SYS_HDP_MGCG_MASK          0x80
 585 #define CG_SYS_HDP_MGLS_MASK          0x100
 586 #define CG_SYS_DRM_MGLS_MASK          0x200
 587
 588 /* Graphics Clock Gating */
 589 #define CG_GFX_BITMASK_FIRST_BIT      16 /* First bit of Gfx CG bitmask */
 590 #define CG_GFX_BITMASK_LAST_BIT       20 /* Last bit of Gfx CG bitmask */
 591 #define CG_GFX_CGCG_SHIFT             16
 592 #define CG_GFX_CGLS_SHIFT             17
 593 #define CG_CPF_MGCG_SHIFT             18
 594 #define CG_RLC_MGCG_SHIFT             19
 595 #define CG_GFX_OTHERS_MGCG_SHIFT      20
 596
 597 #define CG_GFX_CGCG_MASK              0x00010000
 598 #define CG_GFX_CGLS_MASK              0x00020000
 599 #define CG_CPF_MGCG_MASK              0x00040000
 600 #define CG_RLC_MGCG_MASK              0x00080000
 601 #define CG_GFX_OTHERS_MGCG_MASK       0x00100000
 602
 603 /* Voltage Regulator Configuration */
 604 /* VR Config info is contained in dpmTable.VRConfig */
 605
 606 #define VRCONF_VDDC_MASK         0x000000FF
 607 #define VRCONF_VDDC_SHIFT        0
 608 #define VRCONF_VDDGFX_MASK       0x0000FF00
 609 #define VRCONF_VDDGFX_SHIFT      8
 610 #define VRCONF_VDDCI_MASK        0x00FF0000
 611 #define VRCONF_VDDCI_SHIFT       16
 612 #define VRCONF_MVDD_MASK         0xFF000000
 613 #define VRCONF_MVDD_SHIFT        24
 614
 615 #define VR_MERGED_WITH_VDDC      0
 616 #define VR_SVI2_PLANE_1          1
 617 #define VR_SVI2_PLANE_2          2
 618 #define VR_SMIO_PATTERN_1        3
 619 #define VR_SMIO_PATTERN_2        4
 620 #define VR_STATIC_VOLTAGE        5
 621
 622 /* Clock Stretcher Configuration */
 623
 624 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4
 625 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4
 626
 627 /* The 'settings' field is subdivided in the following way: */
 628 #define CLOCK_STRETCHER_SETTING_DDT_MASK             0x01
 629 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT            0x0
 630 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK  0x1E
 631 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
 632 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK          0x80
 633 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT         0x7
 634
 635 struct SMU_ClockStretcherDataTableEntry {
 636         uint8_t minVID;
 637         uint8_t maxVID;
 638
 639         uint16_t setting;
 640 };
 641 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
 642
 643 struct SMU_ClockStretcherDataTable {
 644         SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
 645 };
 646 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
 647
 648 struct SMU_CKS_LOOKUPTableEntry {
 649         uint16_t minFreq;
 650         uint16_t maxFreq;
 651
 652         uint8_t setting;
 653         uint8_t padding[3];
 654 };
 655 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
 656
 657 struct SMU_CKS_LOOKUPTable {
 658         SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
 659 };
 660 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
 661
 662 #endif
 663
 664