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23 #ifndef SMU_13_0_6_DRIVER_IF_H
24 #define SMU_13_0_6_DRIVER_IF_H
27 // PMFW TEAM: Always increment the interface version if
28 // anything is changed in this file
29 #define SMU13_0_6_DRIVER_IF_VERSION 0x08042024
32 #define NUM_I2C_CONTROLLERS 8
33 #define I2C_CONTROLLER_ENABLED 1
34 #define I2C_CONTROLLER_DISABLED 0
36 #define MAX_SW_I2C_COMMANDS 24
39 I2C_CONTROLLER_PORT_0, //CKSVII2C0
40 I2C_CONTROLLER_PORT_1, //CKSVII2C1
41 I2C_CONTROLLER_PORT_COUNT,
42 } I2cControllerPort_e;
45 UNSUPPORTED_1, //50 Kbits/s not supported anymore!
46 I2C_SPEED_STANDARD_100K, //100 Kbits/s
47 I2C_SPEED_FAST_400K, //400 Kbits/s
48 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
49 UNSUPPORTED_2, //1 Mbits/s (in high speed mode) not supported anymore!
50 UNSUPPORTED_3, //2.3 Mbits/s not supported anymore!
60 #define CMDCONFIG_STOP_BIT 0
61 #define CMDCONFIG_RESTART_BIT 1
62 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write
64 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT)
65 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
66 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT)
72 CODE_UTCL2_ROUTER = 10,
112 CODE_SMN_SLVERR = 40,
122 // GCEA Pin UE_ERR regs
137 // GCEA Pin, UE_EDC regs
150 // SOC error codes 40-42 are common with ERR_CODE_e
151 MP5_CODE_SMN_SLVERR = 40,
152 MP5_CODE_UNKNOWN = 42,
157 uint8_t ReadWriteData; //Return data for read. Data to send for write
158 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write
159 } SwI2cCmd_t; //SW I2C Command Table
162 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
163 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select
164 uint8_t SlaveAddress; //Slave address of device
165 uint8_t NumCmds; //Number of commands
166 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
167 } SwI2cRequest_t; // SW I2C Request Table
170 SwI2cRequest_t SwI2cRequest;
172 uint32_t MmHubPadding[8]; // SMU internal use
173 } SwI2cRequestExternal_t;
186 GPIO_INT_POLARITY_ACTIVE_LOW,
187 GPIO_INT_POLARITY_ACTIVE_HIGH,
190 //TODO confirm if this is used in SMU_13_0_6 PPSMC_MSG_SetUclkDpmMode
192 UCLK_DPM_MODE_BANDWIDTH,
193 UCLK_DPM_MODE_LATENCY,
197 //0-23 SOC, 24-26 SOCIO, 27-29 SOC
198 uint16_t avgPsmCount[30];
199 uint16_t minPsmCount[30];
200 float avgPsmVoltage[30];
201 float minPsmVoltage[30];
202 } AvfsDebugTableAid_t;
205 //0-27 GFX, 28-29 SOC
206 uint16_t avgPsmCount[30];
207 uint16_t minPsmCount[30];
208 float avgPsmVoltage[30];
209 float minPsmVoltage[30];
210 } AvfsDebugTableXcd_t;
212 // Defines used for IH-based thermal interrupts to GFX driver - A/X only
213 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE
214 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7
216 //thermal over-temp mask defines for IH interrupt to host
217 #define THROTTLER_PROCHOT_BIT 0
218 #define THROTTLER_PPT_BIT 1
219 #define THROTTLER_THERMAL_SOCKET_BIT 2//AID, XCD, CCD throttling
220 #define THROTTLER_THERMAL_VR_BIT 3//VRHOT
221 #define THROTTLER_THERMAL_HBM_BIT 4
223 #define ClearMcaOnRead_UE_FLAG_MASK 0x1
224 #define ClearMcaOnRead_CE_POLL_MASK 0x2
226 // These defines are used with the following messages:
227 // SMC_MSG_TransferTableDram2Smu
228 // SMC_MSG_TransferTableSmu2Dram
229 // #define TABLE_PPTABLE 0
230 // #define TABLE_AVFS_PSM_DEBUG 1
231 // #define TABLE_AVFS_FUSE_OVERRIDE 2
232 // #define TABLE_PMSTATUSLOG 3
233 // #define TABLE_SMU_METRICS 4
234 // #define TABLE_DRIVER_SMU_CONFIG 5
235 // #define TABLE_I2C_COMMANDS 6
236 // #define TABLE_COUNT 7
238 // // Table transfer status
239 // #define TABLE_TRANSFER_OK 0x0
240 // #define TABLE_TRANSFER_FAILED 0xFF
241 // #define TABLE_TRANSFER_PENDING 0xAB