2 * Copyright 2016 Advanced Micro Devices, Inc.
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25 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
26 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
28 #include "dm_services.h"
30 /* macro for register read/write
31 * user of macro need to define
33 * CTX ==> macro to ptr to dc_context
34 * eg. aud110->base.ctx
36 * REG ==> macro to location of register offset
37 * eg. aud110->regs->reg
39 #define REG_READ(reg_name) \
40 dm_read_reg(CTX, REG(reg_name))
42 #define REG_WRITE(reg_name, value) \
43 dm_write_reg(CTX, REG(reg_name), value)
53 /* macro to set register fields. */
54 #define REG_SET_N(reg_name, n, initial_val, ...) \
55 generic_reg_update_ex(CTX, \
60 #define FN(reg_name, field) \
61 FD(reg_name##__##field)
63 #define REG_SET(reg_name, initial_val, field, val) \
64 REG_SET_N(reg_name, 1, initial_val, \
65 FN(reg_name, field), val)
67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \
68 REG_SET_N(reg, 2, init_value, \
72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
73 REG_SET_N(reg, 3, init_value, \
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
79 REG_SET_N(reg, 4, init_value, \
85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
87 REG_SET_N(reg, 5, init_value, \
94 #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
96 REG_SET_N(reg, 6, init_value, \
104 #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
105 f5, v5, f6, v6, f7, v7) \
106 REG_SET_N(reg, 7, init_value, \
115 #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
116 f5, v5, f6, v6, f7, v7, f8, v8) \
117 REG_SET_N(reg, 8, init_value, \
127 #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
128 v5, f6, v6, f7, v7, f8, v8, f9, v9) \
129 REG_SET_N(reg, 9, init_value, \
140 #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
141 v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
142 REG_SET_N(reg, 10, init_value, \
154 /* macro to get register fields
155 * read given register and fill in field value in output parameter */
156 #define REG_GET(reg_name, field, val) \
157 generic_reg_get(CTX, REG(reg_name), \
158 FN(reg_name, field), val)
160 #define REG_GET_2(reg_name, f1, v1, f2, v2) \
161 generic_reg_get2(CTX, REG(reg_name), \
162 FN(reg_name, f1), v1, \
163 FN(reg_name, f2), v2)
165 #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \
166 generic_reg_get3(CTX, REG(reg_name), \
167 FN(reg_name, f1), v1, \
168 FN(reg_name, f2), v2, \
169 FN(reg_name, f3), v3)
171 #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \
172 generic_reg_get4(CTX, REG(reg_name), \
173 FN(reg_name, f1), v1, \
174 FN(reg_name, f2), v2, \
175 FN(reg_name, f3), v3, \
176 FN(reg_name, f4), v4)
178 #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
179 generic_reg_get5(CTX, REG(reg_name), \
180 FN(reg_name, f1), v1, \
181 FN(reg_name, f2), v2, \
182 FN(reg_name, f3), v3, \
183 FN(reg_name, f4), v4, \
184 FN(reg_name, f5), v5)
186 /* macro to poll and wait for a register field to read back given value */
188 #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
189 generic_reg_wait(CTX, \
190 REG(reg_name), FN(reg_name, field), val,\
191 delay_between_poll_us, max_try, __func__, __LINE__)
193 /* macro to update (read, modify, write) register fields
195 #define REG_UPDATE_N(reg_name, n, ...) \
196 generic_reg_update_ex(CTX, \
198 REG_READ(reg_name), \
201 #define REG_UPDATE(reg_name, field, val) \
202 REG_UPDATE_N(reg_name, 1, \
203 FN(reg_name, field), val)
205 #define REG_UPDATE_2(reg, f1, v1, f2, v2) \
206 REG_UPDATE_N(reg, 2,\
210 #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \
211 REG_UPDATE_N(reg, 3, \
216 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
217 REG_UPDATE_N(reg, 4, \
223 #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
224 REG_UPDATE_N(reg, 5, \
231 #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
232 REG_UPDATE_N(reg, 6, \
240 #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
241 REG_UPDATE_N(reg, 7, \
250 #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
251 REG_UPDATE_N(reg, 8, \
261 #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \
262 REG_UPDATE_N(reg, 9, \
273 #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
274 REG_UPDATE_N(reg, 10, \
286 #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
287 v10, f11, v11, f12, v12, f13, v13, f14, v14)\
288 REG_UPDATE_N(reg, 14, \
304 #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
305 v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19)\
306 REG_UPDATE_N(reg, 19, \
327 #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
328 v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19, f20, v20)\
329 REG_UPDATE_N(reg, 20, \
350 /* macro to update a register field to specified values in given sequences.
351 * useful when toggling bits
353 #define REG_UPDATE_SEQ(reg, field, value1, value2) \
354 { uint32_t val = REG_UPDATE(reg, field, value1); \
355 REG_SET(reg, val, field, value2); }
357 /* macro to update fields in register 1 field at a time in given order */
358 #define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \
359 { uint32_t val = REG_UPDATE(reg, f1, v1); \
360 REG_SET(reg, val, f2, v2); }
362 #define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \
363 { uint32_t val = REG_UPDATE(reg, f1, v1); \
364 val = REG_SET(reg, val, f2, v2); \
365 REG_SET(reg, val, f3, v3); }
367 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
368 uint8_t shift, uint32_t mask, uint32_t *field_value);
370 uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
371 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
372 uint8_t shift2, uint32_t mask2, uint32_t *field_value2);
374 uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
375 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
376 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
377 uint8_t shift3, uint32_t mask3, uint32_t *field_value3);
379 uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
380 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
381 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
382 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
383 uint8_t shift4, uint32_t mask4, uint32_t *field_value4);
385 uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
386 uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
387 uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
388 uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
389 uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
390 uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
392 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */