drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "reg_helper.h"
  28
  29 #include "core_types.h"
  30 #include "link_encoder.h"
  31 #include "dcn31_dio_link_encoder.h"
  32 #include "stream_encoder.h"
  33 #include "i2caux_interface.h"
  34 #include "dc_bios_types.h"
  35
  36 #include "gpio_service_interface.h"
  37
  38 #include "link_enc_cfg.h"
  39 #include "dc_dmub_srv.h"
  40
  41 #define CTX \
  42         enc10->base.ctx
  43 #define DC_LOGGER \
  44         enc10->base.ctx->logger
  45
  46 #define REG(reg)\
  47         (enc10->link_regs->reg)
  48
  49 #undef FN
  50 #define FN(reg_name, field_name) \
  51         enc10->link_shift->field_name, enc10->link_mask->field_name
  52
  53 #define IND_REG(index) \
  54         (enc10->link_regs->index)
  55
  56 #define AUX_REG(reg)\
  57         (enc10->aux_regs->reg)
  58
  59 #define AUX_REG_READ(reg_name) \
  60                 dm_read_reg(CTX, AUX_REG(reg_name))
  61
  62 #define AUX_REG_WRITE(reg_name, val) \
  63                         dm_write_reg(CTX, AUX_REG(reg_name), val)
  64
  65 void dcn31_link_encoder_set_dio_phy_mux(
  66         struct link_encoder *enc,
  67         enum encoder_type_select sel,
  68         uint32_t hpo_inst)
  69 {
  70         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
  71
  72         switch (enc->transmitter) {
  73         case TRANSMITTER_UNIPHY_A:
  74                 if (sel == ENCODER_TYPE_HDMI_FRL)
  75                         REG_UPDATE(DIO_LINKA_CNTL,
  76                                         HPO_HDMI_ENC_SEL, hpo_inst);
  77                 else if (sel == ENCODER_TYPE_DP_128B132B)
  78                         REG_UPDATE(DIO_LINKA_CNTL,
  79                                         HPO_DP_ENC_SEL, hpo_inst);
  80                 REG_UPDATE(DIO_LINKA_CNTL,
  81                                 ENC_TYPE_SEL, sel);
  82                 break;
  83         case TRANSMITTER_UNIPHY_B:
  84                 if (sel == ENCODER_TYPE_HDMI_FRL)
  85                         REG_UPDATE(DIO_LINKB_CNTL,
  86                                         HPO_HDMI_ENC_SEL, hpo_inst);
  87                 else if (sel == ENCODER_TYPE_DP_128B132B)
  88                         REG_UPDATE(DIO_LINKB_CNTL,
  89                                         HPO_DP_ENC_SEL, hpo_inst);
  90                 REG_UPDATE(DIO_LINKB_CNTL,
  91                                 ENC_TYPE_SEL, sel);
  92                 break;
  93         case TRANSMITTER_UNIPHY_C:
  94                 if (sel == ENCODER_TYPE_HDMI_FRL)
  95                         REG_UPDATE(DIO_LINKC_CNTL,
  96                                         HPO_HDMI_ENC_SEL, hpo_inst);
  97                 else if (sel == ENCODER_TYPE_DP_128B132B)
  98                         REG_UPDATE(DIO_LINKC_CNTL,
  99                                         HPO_DP_ENC_SEL, hpo_inst);
 100                 REG_UPDATE(DIO_LINKC_CNTL,
 101                                 ENC_TYPE_SEL, sel);
 102                 break;
 103         case TRANSMITTER_UNIPHY_D:
 104                 if (sel == ENCODER_TYPE_HDMI_FRL)
 105                         REG_UPDATE(DIO_LINKD_CNTL,
 106                                         HPO_HDMI_ENC_SEL, hpo_inst);
 107                 else if (sel == ENCODER_TYPE_DP_128B132B)
 108                         REG_UPDATE(DIO_LINKD_CNTL,
 109                                         HPO_DP_ENC_SEL, hpo_inst);
 110                 REG_UPDATE(DIO_LINKD_CNTL,
 111                                 ENC_TYPE_SEL, sel);
 112                 break;
 113         case TRANSMITTER_UNIPHY_E:
 114                 if (sel == ENCODER_TYPE_HDMI_FRL)
 115                         REG_UPDATE(DIO_LINKE_CNTL,
 116                                         HPO_HDMI_ENC_SEL, hpo_inst);
 117                 else if (sel == ENCODER_TYPE_DP_128B132B)
 118                         REG_UPDATE(DIO_LINKE_CNTL,
 119                                         HPO_DP_ENC_SEL, hpo_inst);
 120                 REG_UPDATE(DIO_LINKE_CNTL,
 121                                 ENC_TYPE_SEL, sel);
 122                 break;
 123         case TRANSMITTER_UNIPHY_F:
 124                 if (sel == ENCODER_TYPE_HDMI_FRL)
 125                         REG_UPDATE(DIO_LINKF_CNTL,
 126                                         HPO_HDMI_ENC_SEL, hpo_inst);
 127                 else if (sel == ENCODER_TYPE_DP_128B132B)
 128                         REG_UPDATE(DIO_LINKF_CNTL,
 129                                         HPO_DP_ENC_SEL, hpo_inst);
 130                 REG_UPDATE(DIO_LINKF_CNTL,
 131                                 ENC_TYPE_SEL, sel);
 132                 break;
 133         default:
 134                 /* Do nothing */
 135                 break;
 136         }
 137 }
 138
 139 void enc31_hw_init(struct link_encoder *enc)
 140 {
 141         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 142
 143 /*
 144         00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
 145         01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
 146         02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
 147         03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
 148         04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
 149         05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
 150         06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
 151         07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
 152 */
 153
 154 /*
 155         AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
 156         AUX_RX_START_WINDOW = 1 [6:4]
 157         AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
 158         AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
 159         AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
 160         AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
 161         AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
 162         AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
 163         AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
 164         AUX_RX_DETECTION_THRESHOLD [30:28] = 1
 165 */
 166         AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
 167
 168         AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
 169
 170         //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
 171         // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
 172         // 27MHz -> 0xd
 173         // 100MHz -> 0x32
 174         // 48MHz -> 0x18
 175
 176 #ifdef CLEANUP_FIXME
 177         /*from display_init*/
 178         REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0);
 179 #endif
 180
 181         // Set TMDS_CTL0 to 1.  This is a legacy setting.
 182         REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
 183
 184         /*HW default is 5*/
 185         REG_UPDATE(RDPCSTX_CNTL,
 186                         RDPCS_TX_FIFO_RD_START_DELAY, 4);
 187
 188         dcn10_aux_initialize(enc10);
 189 }
 190
 191 static const struct link_encoder_funcs dcn31_link_enc_funcs = {
 192         .read_state = link_enc2_read_state,
 193         .validate_output_with_stream =
 194                         dcn30_link_encoder_validate_output_with_stream,
 195         .hw_init = enc31_hw_init,
 196         .setup = dcn10_link_encoder_setup,
 197         .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
 198         .enable_dp_output = dcn31_link_encoder_enable_dp_output,
 199         .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
 200         .disable_output = dcn31_link_encoder_disable_output,
 201         .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
 202         .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
 203         .update_mst_stream_allocation_table =
 204                 dcn10_link_encoder_update_mst_stream_allocation_table,
 205         .psr_program_dp_dphy_fast_training =
 206                         dcn10_psr_program_dp_dphy_fast_training,
 207         .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
 208         .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
 209         .enable_hpd = dcn10_link_encoder_enable_hpd,
 210         .disable_hpd = dcn10_link_encoder_disable_hpd,
 211         .is_dig_enabled = dcn10_is_dig_enabled,
 212         .destroy = dcn10_link_encoder_destroy,
 213         .fec_set_enable = enc2_fec_set_enable,
 214         .fec_set_ready = enc2_fec_set_ready,
 215         .fec_is_active = enc2_fec_is_active,
 216         .get_dig_frontend = dcn10_get_dig_frontend,
 217         .get_dig_mode = dcn10_get_dig_mode,
 218         .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
 219         .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
 220         .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
 221 };
 222
 223 void dcn31_link_encoder_construct(
 224         struct dcn20_link_encoder *enc20,
 225         const struct encoder_init_data *init_data,
 226         const struct encoder_feature_support *enc_features,
 227         const struct dcn10_link_enc_registers *link_regs,
 228         const struct dcn10_link_enc_aux_registers *aux_regs,
 229         const struct dcn10_link_enc_hpd_registers *hpd_regs,
 230         const struct dcn10_link_enc_shift *link_shift,
 231         const struct dcn10_link_enc_mask *link_mask)
 232 {
 233         struct bp_encoder_cap_info bp_cap_info = {0};
 234         const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
 235         enum bp_result result = BP_RESULT_OK;
 236         struct dcn10_link_encoder *enc10 = &enc20->enc10;
 237
 238         enc10->base.funcs = &dcn31_link_enc_funcs;
 239         enc10->base.ctx = init_data->ctx;
 240         enc10->base.id = init_data->encoder;
 241
 242         enc10->base.hpd_source = init_data->hpd_source;
 243         enc10->base.connector = init_data->connector;
 244
 245         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 246
 247         enc10->base.features = *enc_features;
 248
 249         enc10->base.transmitter = init_data->transmitter;
 250
 251         /* set the flag to indicate whether driver poll the I2C data pin
 252          * while doing the DP sink detect
 253          */
 254
 255 /*      if (dal_adapter_service_is_feature_supported(as,
 256                 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 257                 enc10->base.features.flags.bits.
 258                         DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 259
 260         enc10->base.output_signals =
 261                 SIGNAL_TYPE_DVI_SINGLE_LINK |
 262                 SIGNAL_TYPE_DVI_DUAL_LINK |
 263                 SIGNAL_TYPE_LVDS |
 264                 SIGNAL_TYPE_DISPLAY_PORT |
 265                 SIGNAL_TYPE_DISPLAY_PORT_MST |
 266                 SIGNAL_TYPE_EDP |
 267                 SIGNAL_TYPE_HDMI_TYPE_A;
 268
 269         /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 270          * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 271          * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 272          * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 273          * Prefer DIG assignment is decided by board design.
 274          * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 275          * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 276          * By this, adding DIGG should not hurt DCE 8.0.
 277          * This will let DCE 8.1 share DCE 8.0 as much as possible
 278          */
 279
 280         enc10->link_regs = link_regs;
 281         enc10->aux_regs = aux_regs;
 282         enc10->hpd_regs = hpd_regs;
 283         enc10->link_shift = link_shift;
 284         enc10->link_mask = link_mask;
 285
 286         switch (enc10->base.transmitter) {
 287         case TRANSMITTER_UNIPHY_A:
 288                 enc10->base.preferred_engine = ENGINE_ID_DIGA;
 289         break;
 290         case TRANSMITTER_UNIPHY_B:
 291                 enc10->base.preferred_engine = ENGINE_ID_DIGB;
 292         break;
 293         case TRANSMITTER_UNIPHY_C:
 294                 enc10->base.preferred_engine = ENGINE_ID_DIGC;
 295         break;
 296         case TRANSMITTER_UNIPHY_D:
 297                 enc10->base.preferred_engine = ENGINE_ID_DIGD;
 298         break;
 299         case TRANSMITTER_UNIPHY_E:
 300                 enc10->base.preferred_engine = ENGINE_ID_DIGE;
 301         break;
 302         case TRANSMITTER_UNIPHY_F:
 303                 enc10->base.preferred_engine = ENGINE_ID_DIGF;
 304         break;
 305         default:
 306                 ASSERT_CRITICAL(false);
 307                 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 308         }
 309
 310         /* default to one to mirror Windows behavior */
 311         enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
 312
 313         result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
 314                                                 enc10->base.id, &bp_cap_info);
 315
 316         /* Override features with DCE-specific values */
 317         if (result == BP_RESULT_OK) {
 318                 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
 319                                 bp_cap_info.DP_HBR2_EN;
 320                 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
 321                                 bp_cap_info.DP_HBR3_EN;
 322                 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
 323                 enc10->base.features.flags.bits.DP_IS_USB_C =
 324                                 bp_cap_info.DP_IS_USB_C;
 325         } else {
 326                 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 327                                 __func__,
 328                                 result);
 329         }
 330         if (enc10->base.ctx->dc->debug.hdmi20_disable) {
 331                 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
 332         }
 333 }
 334
 335 void dcn31_link_encoder_construct_minimal(
 336         struct dcn20_link_encoder *enc20,
 337         struct dc_context *ctx,
 338         const struct encoder_feature_support *enc_features,
 339         const struct dcn10_link_enc_registers *link_regs,
 340         enum engine_id eng_id)
 341 {
 342         struct dcn10_link_encoder *enc10 = &enc20->enc10;
 343
 344         enc10->base.funcs = &dcn31_link_enc_funcs;
 345         enc10->base.ctx = ctx;
 346         enc10->base.id.type = OBJECT_TYPE_ENCODER;
 347         enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN;
 348         enc10->base.connector.type = OBJECT_TYPE_CONNECTOR;
 349         enc10->base.preferred_engine = eng_id;
 350         enc10->base.features = *enc_features;
 351         enc10->base.transmitter = TRANSMITTER_UNKNOWN;
 352         enc10->link_regs = link_regs;
 353
 354         enc10->base.output_signals =
 355                 SIGNAL_TYPE_DISPLAY_PORT |
 356                 SIGNAL_TYPE_DISPLAY_PORT_MST |
 357                 SIGNAL_TYPE_EDP;
 358 }
 359
 360 void dcn31_link_encoder_enable_dp_output(
 361         struct link_encoder *enc,
 362         const struct dc_link_settings *link_settings,
 363         enum clock_source_id clock_source)
 364 {
 365         /* Enable transmitter and encoder. */
 366         if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
 367
 368                 dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
 369
 370         } else {
 371
 372                 /** @todo Handle transmitter with programmable mapping to link encoder. */
 373         }
 374 }
 375
 376 void dcn31_link_encoder_enable_dp_mst_output(
 377         struct link_encoder *enc,
 378         const struct dc_link_settings *link_settings,
 379         enum clock_source_id clock_source)
 380 {
 381         /* Enable transmitter and encoder. */
 382         if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
 383
 384                 dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
 385
 386         } else {
 387
 388                 /** @todo Handle transmitter with programmable mapping to link encoder. */
 389         }
 390 }
 391
 392 void dcn31_link_encoder_disable_output(
 393         struct link_encoder *enc,
 394         enum signal_type signal)
 395 {
 396         /* Disable transmitter and encoder. */
 397         if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
 398
 399                 dcn10_link_encoder_disable_output(enc, signal);
 400
 401         } else {
 402
 403                 /** @todo Handle transmitter with programmable mapping to link encoder. */
 404         }
 405 }
 406