drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15 #include "dc_dmub_srv.h"
  16 #include "dce/dmub_hw_lock_mgr.h"
  17 #include "inc/link_enc_cfg.h"
  18
  19 /*Travis*/
  20 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  21 /*Nutmeg*/
  22 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  23
  24 #define DC_LOGGER \
  25         link->ctx->logger
  26 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  27
  28 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
  29
  30         /* maximum pre emphasis level allowed for each voltage swing level*/
  31         static const enum dc_pre_emphasis
  32         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  33                                             PRE_EMPHASIS_LEVEL2,
  34                                             PRE_EMPHASIS_LEVEL1,
  35                                             PRE_EMPHASIS_DISABLED };
  36
  37 enum {
  38         POST_LT_ADJ_REQ_LIMIT = 6,
  39         POST_LT_ADJ_REQ_TIMEOUT = 200
  40 };
  41
  42 enum {
  43         LINK_TRAINING_MAX_RETRY_COUNT = 5,
  44         /* to avoid infinite loop where-in the receiver
  45          * switches between different VS
  46          */
  47         LINK_TRAINING_MAX_CR_RETRY = 100
  48 };
  49
  50 static bool decide_fallback_link_setting(
  51                 struct dc_link_settings initial_link_settings,
  52                 struct dc_link_settings *current_link_setting,
  53                 enum link_training_result training_result);
  54 static struct dc_link_settings get_common_supported_link_settings(
  55                 struct dc_link_settings link_setting_a,
  56                 struct dc_link_settings link_setting_b);
  57
  58 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  59                 const struct dc_link_settings *link_settings)
  60 {
  61         union training_aux_rd_interval training_rd_interval;
  62         uint32_t wait_in_micro_secs = 100;
  63
  64         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  65         core_link_read_dpcd(
  66                         link,
  67                         DP_TRAINING_AUX_RD_INTERVAL,
  68                         (uint8_t *)&training_rd_interval,
  69                         sizeof(training_rd_interval));
  70         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  71                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  72         return wait_in_micro_secs;
  73 }
  74
  75 static uint32_t get_eq_training_aux_rd_interval(
  76         struct dc_link *link,
  77         const struct dc_link_settings *link_settings)
  78 {
  79         union training_aux_rd_interval training_rd_interval;
  80         uint32_t wait_in_micro_secs = 400;
  81
  82         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  83         /* overwrite the delay if rev > 1.1*/
  84         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  85                 /* DP 1.2 or later - retrieve delay through
  86                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  87                 core_link_read_dpcd(
  88                         link,
  89                         DP_TRAINING_AUX_RD_INTERVAL,
  90                         (uint8_t *)&training_rd_interval,
  91                         sizeof(training_rd_interval));
  92
  93                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  94                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  95         }
  96
  97         return wait_in_micro_secs;
  98 }
  99
 100 static void wait_for_training_aux_rd_interval(
 101         struct dc_link *link,
 102         uint32_t wait_in_micro_secs)
 103 {
 104         udelay(wait_in_micro_secs);
 105
 106         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
 107                 __func__,
 108                 wait_in_micro_secs);
 109 }
 110
 111 static enum dpcd_training_patterns
 112         dc_dp_training_pattern_to_dpcd_training_pattern(
 113         struct dc_link *link,
 114         enum dc_dp_training_pattern pattern)
 115 {
 116         enum dpcd_training_patterns dpcd_tr_pattern =
 117         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 118
 119         switch (pattern) {
 120         case DP_TRAINING_PATTERN_SEQUENCE_1:
 121                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 122                 break;
 123         case DP_TRAINING_PATTERN_SEQUENCE_2:
 124                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 125                 break;
 126         case DP_TRAINING_PATTERN_SEQUENCE_3:
 127                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 128                 break;
 129         case DP_TRAINING_PATTERN_SEQUENCE_4:
 130                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 131                 break;
 132         case DP_TRAINING_PATTERN_VIDEOIDLE:
 133                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 134                 break;
 135         default:
 136                 ASSERT(0);
 137                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 138                         __func__, pattern);
 139                 break;
 140         }
 141
 142         return dpcd_tr_pattern;
 143 }
 144
 145 static void dpcd_set_training_pattern(
 146         struct dc_link *link,
 147         enum dc_dp_training_pattern training_pattern)
 148 {
 149         union dpcd_training_pattern dpcd_pattern = { {0} };
 150
 151         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 152                         dc_dp_training_pattern_to_dpcd_training_pattern(
 153                                         link, training_pattern);
 154
 155         core_link_write_dpcd(
 156                 link,
 157                 DP_TRAINING_PATTERN_SET,
 158                 &dpcd_pattern.raw,
 159                 1);
 160
 161         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 162                 __func__,
 163                 DP_TRAINING_PATTERN_SET,
 164                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 165 }
 166
 167 static enum dc_dp_training_pattern decide_cr_training_pattern(
 168                 const struct dc_link_settings *link_settings)
 169 {
 170         return DP_TRAINING_PATTERN_SEQUENCE_1;
 171 }
 172
 173 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 174                 const struct dc_link_settings *link_settings)
 175 {
 176         struct link_encoder *link_enc;
 177         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 178         struct encoder_feature_support *features;
 179         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 180
 181         /* Access link encoder capability based on whether it is statically
 182          * or dynamically assigned to a link.
 183          */
 184         if (link->is_dig_mapping_flexible &&
 185                         link->dc->res_pool->funcs->link_encs_assign)
 186                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
 187         else
 188                 link_enc = link->link_enc;
 189         ASSERT(link_enc);
 190         features = &link_enc->features;
 191
 192         if (features->flags.bits.IS_TPS3_CAPABLE)
 193                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 194
 195         if (features->flags.bits.IS_TPS4_CAPABLE)
 196                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 197
 198         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 199                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 200                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 201
 202         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 203                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 204                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 205
 206         return DP_TRAINING_PATTERN_SEQUENCE_2;
 207 }
 208
 209 static void dpcd_set_link_settings(
 210         struct dc_link *link,
 211         const struct link_training_settings *lt_settings)
 212 {
 213         uint8_t rate;
 214
 215         union down_spread_ctrl downspread = { {0} };
 216         union lane_count_set lane_count_set = { {0} };
 217
 218         downspread.raw = (uint8_t)
 219         (lt_settings->link_settings.link_spread);
 220
 221         lane_count_set.bits.LANE_COUNT_SET =
 222         lt_settings->link_settings.lane_count;
 223
 224         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 225         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 226
 227
 228         if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 229                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 230                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 231         }
 232
 233         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 234                 &downspread.raw, sizeof(downspread));
 235
 236         core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 237                 &lane_count_set.raw, 1);
 238
 239         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 240                         lt_settings->link_settings.use_link_rate_set == true) {
 241                 rate = 0;
 242                 /* WA for some MUX chips that will power down with eDP and lose supported
 243                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 244                  * MUX chip gets link rate set back before link training.
 245                  */
 246                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 247                         uint8_t supported_link_rates[16];
 248
 249                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 250                                         supported_link_rates, sizeof(supported_link_rates));
 251                 }
 252                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 253                 core_link_write_dpcd(link, DP_LINK_RATE_SET,
 254                                 &lt_settings->link_settings.link_rate_set, 1);
 255         } else {
 256                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 257                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 258         }
 259
 260         if (rate) {
 261                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 262                         __func__,
 263                         DP_LINK_BW_SET,
 264                         lt_settings->link_settings.link_rate,
 265                         DP_LANE_COUNT_SET,
 266                         lt_settings->link_settings.lane_count,
 267                         lt_settings->enhanced_framing,
 268                         DP_DOWNSPREAD_CTRL,
 269                         lt_settings->link_settings.link_spread);
 270         } else {
 271                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 272                         __func__,
 273                         DP_LINK_RATE_SET,
 274                         lt_settings->link_settings.link_rate_set,
 275                         DP_LANE_COUNT_SET,
 276                         lt_settings->link_settings.lane_count,
 277                         lt_settings->enhanced_framing,
 278                         DP_DOWNSPREAD_CTRL,
 279                         lt_settings->link_settings.link_spread);
 280         }
 281 }
 282
 283 static uint8_t dc_dp_initialize_scrambling_data_symbols(
 284         struct dc_link *link,
 285         enum dc_dp_training_pattern pattern)
 286 {
 287         uint8_t disable_scrabled_data_symbols = 0;
 288
 289         switch (pattern) {
 290         case DP_TRAINING_PATTERN_SEQUENCE_1:
 291         case DP_TRAINING_PATTERN_SEQUENCE_2:
 292         case DP_TRAINING_PATTERN_SEQUENCE_3:
 293                 disable_scrabled_data_symbols = 1;
 294                 break;
 295         case DP_TRAINING_PATTERN_SEQUENCE_4:
 296                 disable_scrabled_data_symbols = 0;
 297                 break;
 298         default:
 299                 ASSERT(0);
 300                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 301                         __func__, pattern);
 302                 break;
 303         }
 304         return disable_scrabled_data_symbols;
 305 }
 306
 307 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 308 {
 309         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 310 }
 311
 312 static void dpcd_set_lt_pattern_and_lane_settings(
 313         struct dc_link *link,
 314         const struct link_training_settings *lt_settings,
 315         enum dc_dp_training_pattern pattern,
 316         uint32_t offset)
 317 {
 318         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 319
 320         uint32_t dpcd_base_lt_offset;
 321
 322         uint8_t dpcd_lt_buffer[5] = {0};
 323         union dpcd_training_pattern dpcd_pattern = { {0} };
 324         uint32_t lane;
 325         uint32_t size_in_bytes;
 326         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 327         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 328
 329         if (is_repeater(link, offset))
 330                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 331                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 332
 333         /*****************************************************************
 334         * DpcdAddress_TrainingPatternSet
 335         *****************************************************************/
 336         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 337                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 338
 339         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 340                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 341
 342         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 343                 = dpcd_pattern.raw;
 344
 345         if (is_repeater(link, offset)) {
 346                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 347                         __func__,
 348                         offset,
 349                         dpcd_base_lt_offset,
 350                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 351         } else {
 352                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 353                         __func__,
 354                         dpcd_base_lt_offset,
 355                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 356         }
 357         /*****************************************************************
 358         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 359         *****************************************************************/
 360         for (lane = 0; lane <
 361                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 362
 363                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 364                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 365                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 366                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 367
 368                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 369                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 370                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 371                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 372                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 373                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 374         }
 375
 376         /* concatenate everything into one buffer*/
 377
 378         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 379
 380          // 0x00103 - 0x00102
 381         memmove(
 382                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 383                 dpcd_lane,
 384                 size_in_bytes);
 385
 386         if (is_repeater(link, offset)) {
 387                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 388                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 389                         __func__,
 390                         offset,
 391                         dpcd_base_lt_offset,
 392                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 393                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 394                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 395                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 396         } else {
 397                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 398                         __func__,
 399                         dpcd_base_lt_offset,
 400                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 401                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 402                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 403                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 404         }
 405         if (edp_workaround) {
 406                 /* for eDP write in 2 parts because the 5-byte burst is
 407                 * causing issues on some eDP panels (EPR#366724)
 408                 */
 409                 core_link_write_dpcd(
 410                         link,
 411                         DP_TRAINING_PATTERN_SET,
 412                         &dpcd_pattern.raw,
 413                         sizeof(dpcd_pattern.raw));
 414
 415                 core_link_write_dpcd(
 416                         link,
 417                         DP_TRAINING_LANE0_SET,
 418                         (uint8_t *)(dpcd_lane),
 419                         size_in_bytes);
 420
 421                 } else
 422                 /* write it all in (1 + number-of-lanes)-byte burst*/
 423                         core_link_write_dpcd(
 424                                 link,
 425                                 dpcd_base_lt_offset,
 426                                 dpcd_lt_buffer,
 427                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 428
 429         link->cur_lane_setting = lt_settings->lane_settings[0];
 430 }
 431
 432 static bool is_cr_done(enum dc_lane_count ln_count,
 433         union lane_status *dpcd_lane_status)
 434 {
 435         uint32_t lane;
 436         /*LANEx_CR_DONE bits All 1's?*/
 437         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 438                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 439                         return false;
 440         }
 441         return true;
 442 }
 443
 444 static bool is_ch_eq_done(enum dc_lane_count ln_count,
 445                 union lane_status *dpcd_lane_status)
 446 {
 447         bool done = true;
 448         uint32_t lane;
 449         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 450                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 451                         done = false;
 452         return done;
 453 }
 454
 455 static bool is_symbol_locked(enum dc_lane_count ln_count,
 456                 union lane_status *dpcd_lane_status)
 457 {
 458         bool locked = true;
 459         uint32_t lane;
 460         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 461                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
 462                         locked = false;
 463         return locked;
 464 }
 465
 466 static inline bool is_interlane_aligned(union lane_align_status_updated align_status)
 467 {
 468         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 469 }
 470
 471 static void update_drive_settings(
 472                 struct link_training_settings *dest,
 473                 struct link_training_settings src)
 474 {
 475         uint32_t lane;
 476         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 477                 if (dest->voltage_swing == NULL)
 478                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 479                 else
 480                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 481
 482                 if (dest->pre_emphasis == NULL)
 483                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 484                 else
 485                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 486
 487                 if (dest->post_cursor2 == NULL)
 488                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 489                 else
 490                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 491         }
 492 }
 493
 494 static uint8_t get_nibble_at_index(const uint8_t *buf,
 495         uint32_t index)
 496 {
 497         uint8_t nibble;
 498         nibble = buf[index / 2];
 499
 500         if (index % 2)
 501                 nibble >>= 4;
 502         else
 503                 nibble &= 0x0F;
 504
 505         return nibble;
 506 }
 507
 508 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 509         enum dc_voltage_swing voltage)
 510 {
 511         enum dc_pre_emphasis pre_emphasis;
 512         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 513
 514         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 515                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 516
 517         return pre_emphasis;
 518
 519 }
 520
 521 static void find_max_drive_settings(
 522         const struct link_training_settings *link_training_setting,
 523         struct link_training_settings *max_lt_setting)
 524 {
 525         uint32_t lane;
 526         struct dc_lane_settings max_requested;
 527
 528         max_requested.VOLTAGE_SWING =
 529                 link_training_setting->
 530                 lane_settings[0].VOLTAGE_SWING;
 531         max_requested.PRE_EMPHASIS =
 532                 link_training_setting->
 533                 lane_settings[0].PRE_EMPHASIS;
 534         /*max_requested.postCursor2 =
 535          * link_training_setting->laneSettings[0].postCursor2;*/
 536
 537         /* Determine what the maximum of the requested settings are*/
 538         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 539                         lane++) {
 540                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 541                         max_requested.VOLTAGE_SWING)
 542
 543                         max_requested.VOLTAGE_SWING =
 544                         link_training_setting->
 545                         lane_settings[lane].VOLTAGE_SWING;
 546
 547                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 548                                 max_requested.PRE_EMPHASIS)
 549                         max_requested.PRE_EMPHASIS =
 550                         link_training_setting->
 551                         lane_settings[lane].PRE_EMPHASIS;
 552
 553                 /*
 554                 if (link_training_setting->laneSettings[lane].postCursor2 >
 555                  max_requested.postCursor2)
 556                 {
 557                 max_requested.postCursor2 =
 558                 link_training_setting->laneSettings[lane].postCursor2;
 559                 }
 560                 */
 561         }
 562
 563         /* make sure the requested settings are
 564          * not higher than maximum settings*/
 565         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 566                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 567
 568         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 569                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 570         /*
 571         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 572         max_requested.postCursor2 = PostCursor2_MaxLevel;
 573         */
 574
 575         /* make sure the pre-emphasis matches the voltage swing*/
 576         if (max_requested.PRE_EMPHASIS >
 577                 get_max_pre_emphasis_for_voltage_swing(
 578                         max_requested.VOLTAGE_SWING))
 579                 max_requested.PRE_EMPHASIS =
 580                 get_max_pre_emphasis_for_voltage_swing(
 581                         max_requested.VOLTAGE_SWING);
 582
 583         /*
 584          * Post Cursor2 levels are completely independent from
 585          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 586          * can only be applied to each allowable combination of voltage
 587          * swing and pre-emphasis levels */
 588          /* if ( max_requested.postCursor2 >
 589           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 590           *  max_requested.postCursor2 =
 591           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 592           */
 593
 594         max_lt_setting->link_settings.link_rate =
 595                 link_training_setting->link_settings.link_rate;
 596         max_lt_setting->link_settings.lane_count =
 597         link_training_setting->link_settings.lane_count;
 598         max_lt_setting->link_settings.link_spread =
 599                 link_training_setting->link_settings.link_spread;
 600
 601         for (lane = 0; lane <
 602                 link_training_setting->link_settings.lane_count;
 603                 lane++) {
 604                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 605                         max_requested.VOLTAGE_SWING;
 606                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 607                         max_requested.PRE_EMPHASIS;
 608                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 609                  * max_requested.postCursor2;
 610                  */
 611         }
 612
 613 }
 614
 615 static void get_lane_status_and_drive_settings(
 616         struct dc_link *link,
 617         const struct link_training_settings *link_training_setting,
 618         union lane_status *ln_status,
 619         union lane_align_status_updated *ln_status_updated,
 620         struct link_training_settings *req_settings,
 621         uint32_t offset)
 622 {
 623         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 624         uint8_t lane_adjust_offset = 4;
 625         unsigned int lane01_adjust_address;
 626         uint8_t dpcd_buf[6] = {0};
 627         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 628         struct link_training_settings request_settings = { {0} };
 629         uint32_t lane;
 630
 631         memset(req_settings, '\0', sizeof(struct link_training_settings));
 632
 633         if (is_repeater(link, offset)) {
 634                 lane01_status_address =
 635                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 636                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 637                 lane_adjust_offset = 3;
 638         }
 639
 640         core_link_read_dpcd(
 641                 link,
 642                 lane01_status_address,
 643                 (uint8_t *)(dpcd_buf),
 644                 sizeof(dpcd_buf));
 645
 646         for (lane = 0; lane <
 647                 (uint32_t)(link_training_setting->link_settings.lane_count);
 648                 lane++) {
 649
 650                 ln_status[lane].raw =
 651                         get_nibble_at_index(&dpcd_buf[0], lane);
 652                 dpcd_lane_adjust[lane].raw =
 653                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 654         }
 655
 656         ln_status_updated->raw = dpcd_buf[2];
 657
 658         if (is_repeater(link, offset)) {
 659                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 660                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 661                         __func__,
 662                         offset,
 663                         lane01_status_address, dpcd_buf[0],
 664                         lane01_status_address + 1, dpcd_buf[1]);
 665         } else {
 666                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 667                         __func__,
 668                         lane01_status_address, dpcd_buf[0],
 669                         lane01_status_address + 1, dpcd_buf[1]);
 670         }
 671         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 672
 673         if (is_repeater(link, offset))
 674                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 675                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 676
 677         if (is_repeater(link, offset)) {
 678                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 679                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 680                                         __func__,
 681                                         offset,
 682                                         lane01_adjust_address,
 683                                         dpcd_buf[lane_adjust_offset],
 684                                         lane01_adjust_address + 1,
 685                                         dpcd_buf[lane_adjust_offset + 1]);
 686         } else {
 687                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 688                         __func__,
 689                         lane01_adjust_address,
 690                         dpcd_buf[lane_adjust_offset],
 691                         lane01_adjust_address + 1,
 692                         dpcd_buf[lane_adjust_offset + 1]);
 693         }
 694
 695         /*copy to req_settings*/
 696         request_settings.link_settings.lane_count =
 697                 link_training_setting->link_settings.lane_count;
 698         request_settings.link_settings.link_rate =
 699                 link_training_setting->link_settings.link_rate;
 700         request_settings.link_settings.link_spread =
 701                 link_training_setting->link_settings.link_spread;
 702
 703         for (lane = 0; lane <
 704                 (uint32_t)(link_training_setting->link_settings.lane_count);
 705                 lane++) {
 706
 707                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 708                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 709                                 VOLTAGE_SWING_LANE);
 710                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 711                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 712                                 PRE_EMPHASIS_LANE);
 713         }
 714
 715         /*Note: for postcursor2, read adjusted
 716          * postcursor2 settings from*/
 717         /*DpcdAddress_AdjustRequestPostCursor2 =
 718          *0x020C (not implemented yet)*/
 719
 720         /* we find the maximum of the requested settings across all lanes*/
 721         /* and set this maximum for all lanes*/
 722         find_max_drive_settings(&request_settings, req_settings);
 723
 724         /* if post cursor 2 is needed in the future,
 725          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 726          */
 727
 728 }
 729
 730 static void dpcd_set_lane_settings(
 731         struct dc_link *link,
 732         const struct link_training_settings *link_training_setting,
 733         uint32_t offset)
 734 {
 735         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 736         uint32_t lane;
 737         unsigned int lane0_set_address;
 738
 739         lane0_set_address = DP_TRAINING_LANE0_SET;
 740
 741         if (is_repeater(link, offset))
 742                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 743                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 744
 745         for (lane = 0; lane <
 746                 (uint32_t)(link_training_setting->
 747                 link_settings.lane_count);
 748                 lane++) {
 749                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 750                         (uint8_t)(link_training_setting->
 751                         lane_settings[lane].VOLTAGE_SWING);
 752                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 753                         (uint8_t)(link_training_setting->
 754                         lane_settings[lane].PRE_EMPHASIS);
 755                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 756                         (link_training_setting->
 757                         lane_settings[lane].VOLTAGE_SWING ==
 758                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 759                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 760                         (link_training_setting->
 761                         lane_settings[lane].PRE_EMPHASIS ==
 762                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 763         }
 764
 765         core_link_write_dpcd(link,
 766                 lane0_set_address,
 767                 (uint8_t *)(dpcd_lane),
 768                 link_training_setting->link_settings.lane_count);
 769
 770         /*
 771         if (LTSettings.link.rate == LinkRate_High2)
 772         {
 773                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 774                 for ( uint32_t lane = 0;
 775                 lane < lane_count_DPMax; lane++)
 776                 {
 777                         dpcd_lane2[lane].bits.post_cursor2_set =
 778                         static_cast<unsigned char>(
 779                         LTSettings.laneSettings[lane].postCursor2);
 780                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 781                 }
 782                 m_pDpcdAccessSrv->WriteDpcdData(
 783                 DpcdAddress_Lane0Set2,
 784                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 785                 LTSettings.link.lanes);
 786         }
 787         */
 788
 789         if (is_repeater(link, offset)) {
 790                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 791                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 792                         __func__,
 793                         offset,
 794                         lane0_set_address,
 795                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 796                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 797                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 798                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 799
 800         } else {
 801                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 802                         __func__,
 803                         lane0_set_address,
 804                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 805                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 806                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 807                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 808         }
 809         link->cur_lane_setting = link_training_setting->lane_settings[0];
 810
 811 }
 812
 813 static bool is_max_vs_reached(
 814         const struct link_training_settings *lt_settings)
 815 {
 816         uint32_t lane;
 817         for (lane = 0; lane <
 818                 (uint32_t)(lt_settings->link_settings.lane_count);
 819                 lane++) {
 820                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 821                         == VOLTAGE_SWING_MAX_LEVEL)
 822                         return true;
 823         }
 824         return false;
 825
 826 }
 827
 828 static bool perform_post_lt_adj_req_sequence(
 829         struct dc_link *link,
 830         struct link_training_settings *lt_settings)
 831 {
 832         enum dc_lane_count lane_count =
 833         lt_settings->link_settings.lane_count;
 834
 835         uint32_t adj_req_count;
 836         uint32_t adj_req_timer;
 837         bool req_drv_setting_changed;
 838         uint32_t lane;
 839
 840         req_drv_setting_changed = false;
 841         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 842         adj_req_count++) {
 843
 844                 req_drv_setting_changed = false;
 845
 846                 for (adj_req_timer = 0;
 847                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 848                         adj_req_timer++) {
 849
 850                         struct link_training_settings req_settings;
 851                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 852                         union lane_align_status_updated
 853                                 dpcd_lane_status_updated;
 854
 855                         get_lane_status_and_drive_settings(
 856                         link,
 857                         lt_settings,
 858                         dpcd_lane_status,
 859                         &dpcd_lane_status_updated,
 860                         &req_settings,
 861                         DPRX);
 862
 863                         if (dpcd_lane_status_updated.bits.
 864                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 865                                 return true;
 866
 867                         if (!is_cr_done(lane_count, dpcd_lane_status))
 868                                 return false;
 869
 870                         if (!is_ch_eq_done(lane_count, dpcd_lane_status) ||
 871                                         !is_symbol_locked(lane_count, dpcd_lane_status) ||
 872                                         !is_interlane_aligned(dpcd_lane_status_updated))
 873                                 return false;
 874
 875                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 876
 877                                 if (lt_settings->
 878                                 lane_settings[lane].VOLTAGE_SWING !=
 879                                 req_settings.lane_settings[lane].
 880                                 VOLTAGE_SWING ||
 881                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 882                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 883
 884                                         req_drv_setting_changed = true;
 885                                         break;
 886                                 }
 887                         }
 888
 889                         if (req_drv_setting_changed) {
 890                                 update_drive_settings(
 891                                         lt_settings, req_settings);
 892
 893                                 dc_link_dp_set_drive_settings(link,
 894                                                 lt_settings);
 895                                 break;
 896                         }
 897
 898                         msleep(1);
 899                 }
 900
 901                 if (!req_drv_setting_changed) {
 902                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 903                                 __func__);
 904
 905                         ASSERT(0);
 906                         return true;
 907                 }
 908         }
 909         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 910                 __func__);
 911
 912         ASSERT(0);
 913         return true;
 914
 915 }
 916
 917 /* Only used for channel equalization */
 918 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 919 {
 920         unsigned int aux_rd_interval_us = 400;
 921
 922         switch (dpcd_aux_read_interval) {
 923         case 0x01:
 924                 aux_rd_interval_us = 4000;
 925                 break;
 926         case 0x02:
 927                 aux_rd_interval_us = 8000;
 928                 break;
 929         case 0x03:
 930                 aux_rd_interval_us = 12000;
 931                 break;
 932         case 0x04:
 933                 aux_rd_interval_us = 16000;
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939         return aux_rd_interval_us;
 940 }
 941
 942 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 943                                         union lane_status *dpcd_lane_status)
 944 {
 945         enum link_training_result result = LINK_TRAINING_SUCCESS;
 946
 947         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 948                 result = LINK_TRAINING_CR_FAIL_LANE0;
 949         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 950                 result = LINK_TRAINING_CR_FAIL_LANE1;
 951         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 952                 result = LINK_TRAINING_CR_FAIL_LANE23;
 953         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 954                 result = LINK_TRAINING_CR_FAIL_LANE23;
 955         return result;
 956 }
 957
 958 static enum link_training_result perform_channel_equalization_sequence(
 959         struct dc_link *link,
 960         struct link_training_settings *lt_settings,
 961         uint32_t offset)
 962 {
 963         struct link_training_settings req_settings;
 964         enum dc_dp_training_pattern tr_pattern;
 965         uint32_t retries_ch_eq;
 966         uint32_t wait_time_microsec;
 967         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 968         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 969         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 970
 971         /* Note: also check that TPS4 is a supported feature*/
 972
 973         tr_pattern = lt_settings->pattern_for_eq;
 974
 975         if (is_repeater(link, offset))
 976                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 977
 978         dp_set_hw_training_pattern(link, tr_pattern, offset);
 979
 980         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 981                 retries_ch_eq++) {
 982
 983                 dp_set_hw_lane_settings(link, lt_settings, offset);
 984
 985                 /* 2. update DPCD*/
 986                 if (!retries_ch_eq)
 987                         /* EPR #361076 - write as a 5-byte burst,
 988                          * but only for the 1-st iteration
 989                          */
 990
 991                         dpcd_set_lt_pattern_and_lane_settings(
 992                                 link,
 993                                 lt_settings,
 994                                 tr_pattern, offset);
 995                 else
 996                         dpcd_set_lane_settings(link, lt_settings, offset);
 997
 998                 /* 3. wait for receiver to lock-on*/
 999                 wait_time_microsec = lt_settings->eq_pattern_time;
1000
1001                 if (is_repeater(link, offset))
1002                         wait_time_microsec =
1003                                         translate_training_aux_read_interval(
1004                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1005
1006                 wait_for_training_aux_rd_interval(
1007                                 link,
1008                                 wait_time_microsec);
1009
1010                 /* 4. Read lane status and requested
1011                  * drive settings as set by the sink*/
1012
1013                 get_lane_status_and_drive_settings(
1014                         link,
1015                         lt_settings,
1016                         dpcd_lane_status,
1017                         &dpcd_lane_status_updated,
1018                         &req_settings,
1019                         offset);
1020
1021                 /* 5. check CR done*/
1022                 if (!is_cr_done(lane_count, dpcd_lane_status))
1023                         return LINK_TRAINING_EQ_FAIL_CR;
1024
1025                 /* 6. check CHEQ done*/
1026                 if (is_ch_eq_done(lane_count, dpcd_lane_status) &&
1027                                 is_symbol_locked(lane_count, dpcd_lane_status) &&
1028                                 is_interlane_aligned(dpcd_lane_status_updated))
1029                         return LINK_TRAINING_SUCCESS;
1030
1031                 /* 7. update VS/PE/PC2 in lt_settings*/
1032                 update_drive_settings(lt_settings, req_settings);
1033         }
1034
1035         return LINK_TRAINING_EQ_FAIL_EQ;
1036
1037 }
1038 #define TRAINING_AUX_RD_INTERVAL 100 //us
1039
1040 static void start_clock_recovery_pattern_early(struct dc_link *link,
1041                 struct link_training_settings *lt_settings,
1042                 uint32_t offset)
1043 {
1044         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1045                         __func__);
1046         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1047         dp_set_hw_lane_settings(link, lt_settings, offset);
1048         udelay(400);
1049 }
1050
1051 static enum link_training_result perform_clock_recovery_sequence(
1052         struct dc_link *link,
1053         struct link_training_settings *lt_settings,
1054         uint32_t offset)
1055 {
1056         uint32_t retries_cr;
1057         uint32_t retry_count;
1058         uint32_t wait_time_microsec;
1059         struct link_training_settings req_settings;
1060         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1061         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1062         union lane_align_status_updated dpcd_lane_status_updated;
1063
1064         retries_cr = 0;
1065         retry_count = 0;
1066
1067         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1068                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1069
1070         /* najeeb - The synaptics MST hub can put the LT in
1071         * infinite loop by switching the VS
1072         */
1073         /* between level 0 and level 1 continuously, here
1074         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1075         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1076                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1077
1078                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1079                 memset(&dpcd_lane_status_updated, '\0',
1080                 sizeof(dpcd_lane_status_updated));
1081
1082                 /* 1. call HWSS to set lane settings*/
1083                 dp_set_hw_lane_settings(
1084                                 link,
1085                                 lt_settings,
1086                                 offset);
1087
1088                 /* 2. update DPCD of the receiver*/
1089                 if (!retry_count)
1090                         /* EPR #361076 - write as a 5-byte burst,
1091                          * but only for the 1-st iteration.*/
1092                         dpcd_set_lt_pattern_and_lane_settings(
1093                                         link,
1094                                         lt_settings,
1095                                         lt_settings->pattern_for_cr,
1096                                         offset);
1097                 else
1098                         dpcd_set_lane_settings(
1099                                         link,
1100                                         lt_settings,
1101                                         offset);
1102
1103                 /* 3. wait receiver to lock-on*/
1104                 wait_time_microsec = lt_settings->cr_pattern_time;
1105
1106                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1107                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1108
1109                 wait_for_training_aux_rd_interval(
1110                                 link,
1111                                 wait_time_microsec);
1112
1113                 /* 4. Read lane status and requested drive
1114                 * settings as set by the sink
1115                 */
1116                 get_lane_status_and_drive_settings(
1117                                 link,
1118                                 lt_settings,
1119                                 dpcd_lane_status,
1120                                 &dpcd_lane_status_updated,
1121                                 &req_settings,
1122                                 offset);
1123
1124                 /* 5. check CR done*/
1125                 if (is_cr_done(lane_count, dpcd_lane_status))
1126                         return LINK_TRAINING_SUCCESS;
1127
1128                 /* 6. max VS reached*/
1129                 if (is_max_vs_reached(lt_settings))
1130                         break;
1131
1132                 /* 7. same lane settings*/
1133                 /* Note: settings are the same for all lanes,
1134                  * so comparing first lane is sufficient*/
1135                 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1136                         req_settings.lane_settings[0].VOLTAGE_SWING)
1137                         && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1138                                 req_settings.lane_settings[0].PRE_EMPHASIS))
1139                         retries_cr++;
1140                 else
1141                         retries_cr = 0;
1142
1143                 /* 8. update VS/PE/PC2 in lt_settings*/
1144                 update_drive_settings(lt_settings, req_settings);
1145
1146                 retry_count++;
1147         }
1148
1149         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1150                 ASSERT(0);
1151                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1152                         __func__,
1153                         LINK_TRAINING_MAX_CR_RETRY);
1154
1155         }
1156
1157         return get_cr_failure(lane_count, dpcd_lane_status);
1158 }
1159
1160 static inline enum link_training_result perform_link_training_int(
1161         struct dc_link *link,
1162         struct link_training_settings *lt_settings,
1163         enum link_training_result status)
1164 {
1165         union lane_count_set lane_count_set = { {0} };
1166
1167         /* 4. mainlink output idle pattern*/
1168         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1169
1170         /*
1171          * 5. post training adjust if required
1172          * If the upstream DPTX and downstream DPRX both support TPS4,
1173          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1174          */
1175         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1176                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)
1177                 return status;
1178
1179         if (status == LINK_TRAINING_SUCCESS &&
1180                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1181                 status = LINK_TRAINING_LQA_FAIL;
1182
1183         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1184         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1185         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1186
1187         core_link_write_dpcd(
1188                 link,
1189                 DP_LANE_COUNT_SET,
1190                 &lane_count_set.raw,
1191                 sizeof(lane_count_set));
1192
1193         return status;
1194 }
1195
1196 enum link_training_result dp_check_link_loss_status(
1197         struct dc_link *link,
1198         const struct link_training_settings *link_training_setting)
1199 {
1200         enum link_training_result status = LINK_TRAINING_SUCCESS;
1201         union lane_status lane_status;
1202         uint8_t dpcd_buf[6] = {0};
1203         uint32_t lane;
1204
1205         core_link_read_dpcd(
1206                         link,
1207                         DP_SINK_COUNT,
1208                         (uint8_t *)(dpcd_buf),
1209                         sizeof(dpcd_buf));
1210
1211         /*parse lane status*/
1212         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1213                 /*
1214                  * check lanes status
1215                  */
1216                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1217
1218                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1219                         !lane_status.bits.CR_DONE_0 ||
1220                         !lane_status.bits.SYMBOL_LOCKED_0) {
1221                         /* if one of the channel equalization, clock
1222                          * recovery or symbol lock is dropped
1223                          * consider it as (link has been
1224                          * dropped) dp sink status has changed
1225                          */
1226                         status = LINK_TRAINING_LINK_LOSS;
1227                         break;
1228                 }
1229         }
1230
1231         return status;
1232 }
1233
1234 static void initialize_training_settings(
1235          struct dc_link *link,
1236         const struct dc_link_settings *link_setting,
1237         const struct dc_link_training_overrides *overrides,
1238         struct link_training_settings *lt_settings)
1239 {
1240         uint32_t lane;
1241
1242         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1243
1244         /* Initialize link settings */
1245         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1246         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1247
1248         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1249                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1250         else
1251                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1252
1253         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1254                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1255         else
1256                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1257
1258         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1259
1260         /* TODO hard coded to SS for now
1261          * lt_settings.link_settings.link_spread =
1262          * dal_display_path_is_ss_supported(
1263          * path_mode->display_path) ?
1264          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1265          * LINK_SPREAD_DISABLED;
1266          */
1267         /* Initialize link spread */
1268         if (link->dp_ss_off)
1269                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1270         else if (overrides->downspread != NULL)
1271                 lt_settings->link_settings.link_spread
1272                         = *overrides->downspread
1273                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1274                         : LINK_SPREAD_DISABLED;
1275         else
1276                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1277
1278         /* Initialize lane settings overrides */
1279         if (overrides->voltage_swing != NULL)
1280                 lt_settings->voltage_swing = overrides->voltage_swing;
1281
1282         if (overrides->pre_emphasis != NULL)
1283                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1284
1285         if (overrides->post_cursor2 != NULL)
1286                 lt_settings->post_cursor2 = overrides->post_cursor2;
1287
1288         /* Initialize lane settings (VS/PE/PC2) */
1289         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1290                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1291                         lt_settings->voltage_swing != NULL ?
1292                         *lt_settings->voltage_swing :
1293                         VOLTAGE_SWING_LEVEL0;
1294                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1295                         lt_settings->pre_emphasis != NULL ?
1296                         *lt_settings->pre_emphasis
1297                         : PRE_EMPHASIS_DISABLED;
1298                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1299                         lt_settings->post_cursor2 != NULL ?
1300                         *lt_settings->post_cursor2
1301                         : POST_CURSOR2_DISABLED;
1302         }
1303
1304         /* Initialize training timings */
1305         if (overrides->cr_pattern_time != NULL)
1306                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1307         else
1308                 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1309
1310         if (overrides->eq_pattern_time != NULL)
1311                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1312         else
1313                 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1314
1315         if (overrides->pattern_for_cr != NULL)
1316                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1317         else
1318                 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1319         if (overrides->pattern_for_eq != NULL)
1320                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1321         else
1322                 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1323
1324         if (overrides->enhanced_framing != NULL)
1325                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1326         else
1327                 lt_settings->enhanced_framing = 1;
1328 }
1329
1330 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1331 {
1332         switch (lttpr_repeater_count) {
1333         case 0x80: // 1 lttpr repeater
1334                 return 1;
1335         case 0x40: // 2 lttpr repeaters
1336                 return 2;
1337         case 0x20: // 3 lttpr repeaters
1338                 return 3;
1339         case 0x10: // 4 lttpr repeaters
1340                 return 4;
1341         case 0x08: // 5 lttpr repeaters
1342                 return 5;
1343         case 0x04: // 6 lttpr repeaters
1344                 return 6;
1345         case 0x02: // 7 lttpr repeaters
1346                 return 7;
1347         case 0x01: // 8 lttpr repeaters
1348                 return 8;
1349         default:
1350                 break;
1351         }
1352         return 0; // invalid value
1353 }
1354
1355 static void configure_lttpr_mode_transparent(struct dc_link *link)
1356 {
1357         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1358
1359         core_link_write_dpcd(link,
1360                         DP_PHY_REPEATER_MODE,
1361                         (uint8_t *)&repeater_mode,
1362                         sizeof(repeater_mode));
1363 }
1364
1365 static void configure_lttpr_mode_non_transparent(struct dc_link *link)
1366 {
1367         /* aux timeout is already set to extended */
1368         /* RESET/SET lttpr mode to enable non transparent mode */
1369         uint8_t repeater_cnt;
1370         uint32_t aux_interval_address;
1371         uint8_t repeater_id;
1372         enum dc_status result = DC_ERROR_UNEXPECTED;
1373         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1374
1375         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1376         result = core_link_write_dpcd(link,
1377                         DP_PHY_REPEATER_MODE,
1378                         (uint8_t *)&repeater_mode,
1379                         sizeof(repeater_mode));
1380
1381         if (result == DC_OK) {
1382                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1383         }
1384
1385         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1386
1387                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1388
1389                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1390                 result = core_link_write_dpcd(link,
1391                                 DP_PHY_REPEATER_MODE,
1392                                 (uint8_t *)&repeater_mode,
1393                                 sizeof(repeater_mode));
1394
1395                 if (result == DC_OK) {
1396                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1397                 }
1398
1399                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1400
1401                 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1402                         aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1403                                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1404                         core_link_read_dpcd(
1405                                 link,
1406                                 aux_interval_address,
1407                                 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1408                                 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1409                         link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1410                 }
1411         }
1412 }
1413
1414 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1415 {
1416         union dpcd_training_pattern dpcd_pattern = { {0} };
1417
1418         const uint32_t dpcd_base_lt_offset =
1419                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1420                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1421         /* Set training not in progress*/
1422         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1423
1424         core_link_write_dpcd(
1425                 link,
1426                 dpcd_base_lt_offset,
1427                 &dpcd_pattern.raw,
1428                 1);
1429
1430         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1431                 __func__,
1432                 offset,
1433                 dpcd_base_lt_offset,
1434                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1435 }
1436
1437 static void print_status_message(
1438         struct dc_link *link,
1439         const struct link_training_settings *lt_settings,
1440         enum link_training_result status)
1441 {
1442         char *link_rate = "Unknown";
1443         char *lt_result = "Unknown";
1444         char *lt_spread = "Disabled";
1445
1446         switch (lt_settings->link_settings.link_rate) {
1447         case LINK_RATE_LOW:
1448                 link_rate = "RBR";
1449                 break;
1450         case LINK_RATE_RATE_2:
1451                 link_rate = "R2";
1452                 break;
1453         case LINK_RATE_RATE_3:
1454                 link_rate = "R3";
1455                 break;
1456         case LINK_RATE_HIGH:
1457                 link_rate = "HBR";
1458                 break;
1459         case LINK_RATE_RBR2:
1460                 link_rate = "RBR2";
1461                 break;
1462         case LINK_RATE_RATE_6:
1463                 link_rate = "R6";
1464                 break;
1465         case LINK_RATE_HIGH2:
1466                 link_rate = "HBR2";
1467                 break;
1468         case LINK_RATE_HIGH3:
1469                 link_rate = "HBR3";
1470                 break;
1471         default:
1472                 break;
1473         }
1474
1475         switch (status) {
1476         case LINK_TRAINING_SUCCESS:
1477                 lt_result = "pass";
1478                 break;
1479         case LINK_TRAINING_CR_FAIL_LANE0:
1480                 lt_result = "CR failed lane0";
1481                 break;
1482         case LINK_TRAINING_CR_FAIL_LANE1:
1483                 lt_result = "CR failed lane1";
1484                 break;
1485         case LINK_TRAINING_CR_FAIL_LANE23:
1486                 lt_result = "CR failed lane23";
1487                 break;
1488         case LINK_TRAINING_EQ_FAIL_CR:
1489                 lt_result = "CR failed in EQ";
1490                 break;
1491         case LINK_TRAINING_EQ_FAIL_EQ:
1492                 lt_result = "EQ failed";
1493                 break;
1494         case LINK_TRAINING_LQA_FAIL:
1495                 lt_result = "LQA failed";
1496                 break;
1497         case LINK_TRAINING_LINK_LOSS:
1498                 lt_result = "Link loss";
1499                 break;
1500         default:
1501                 break;
1502         }
1503
1504         switch (lt_settings->link_settings.link_spread) {
1505         case LINK_SPREAD_DISABLED:
1506                 lt_spread = "Disabled";
1507                 break;
1508         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1509                 lt_spread = "0.5% 30KHz";
1510                 break;
1511         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1512                 lt_spread = "0.5% 33KHz";
1513                 break;
1514         default:
1515                 break;
1516         }
1517
1518         /* Connectivity log: link training */
1519         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1520                                 link_rate,
1521                                 lt_settings->link_settings.lane_count,
1522                                 lt_result,
1523                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1524                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1525                                 lt_spread);
1526 }
1527
1528 void dc_link_dp_set_drive_settings(
1529         struct dc_link *link,
1530         struct link_training_settings *lt_settings)
1531 {
1532         /* program ASIC PHY settings*/
1533         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1534
1535         /* Notify DP sink the PHY settings from source */
1536         dpcd_set_lane_settings(link, lt_settings, DPRX);
1537 }
1538
1539 bool dc_link_dp_perform_link_training_skip_aux(
1540         struct dc_link *link,
1541         const struct dc_link_settings *link_setting)
1542 {
1543         struct link_training_settings lt_settings;
1544
1545         initialize_training_settings(
1546                         link,
1547                         link_setting,
1548                         &link->preferred_training_settings,
1549                         &lt_settings);
1550
1551         /* 1. Perform_clock_recovery_sequence. */
1552
1553         /* transmit training pattern for clock recovery */
1554         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1555
1556         /* call HWSS to set lane settings*/
1557         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1558
1559         /* wait receiver to lock-on*/
1560         wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1561
1562         /* 2. Perform_channel_equalization_sequence. */
1563
1564         /* transmit training pattern for channel equalization. */
1565         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1566
1567         /* call HWSS to set lane settings*/
1568         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1569
1570         /* wait receiver to lock-on. */
1571         wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1572
1573         /* 3. Perform_link_training_int. */
1574
1575         /* Mainlink output idle pattern. */
1576         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1577
1578         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1579
1580         return true;
1581 }
1582
1583 enum link_training_result dc_link_dp_perform_link_training(
1584         struct dc_link *link,
1585         const struct dc_link_settings *link_setting,
1586         bool skip_video_pattern)
1587 {
1588         enum link_training_result status = LINK_TRAINING_SUCCESS;
1589         struct link_training_settings lt_settings;
1590
1591         bool fec_enable;
1592         uint8_t repeater_cnt;
1593         uint8_t repeater_id;
1594
1595         initialize_training_settings(
1596                         link,
1597                         link_setting,
1598                         &link->preferred_training_settings,
1599                         &lt_settings);
1600
1601         /* Configure lttpr mode */
1602         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1603                 configure_lttpr_mode_non_transparent(link);
1604         else if (link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1605                 configure_lttpr_mode_transparent(link);
1606
1607         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1608                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1609
1610         /* 1. set link rate, lane count and spread. */
1611         dpcd_set_link_settings(link, &lt_settings);
1612
1613         if (link->preferred_training_settings.fec_enable != NULL)
1614                 fec_enable = *link->preferred_training_settings.fec_enable;
1615         else
1616                 fec_enable = true;
1617
1618         dp_set_fec_ready(link, fec_enable);
1619
1620         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1621
1622                 /* 2. perform link training (set link training done
1623                  *  to false is done as well)
1624                  */
1625                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1626
1627                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1628                                 repeater_id--) {
1629                         status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1630
1631                         if (status != LINK_TRAINING_SUCCESS)
1632                                 break;
1633
1634                         status = perform_channel_equalization_sequence(link,
1635                                         &lt_settings,
1636                                         repeater_id);
1637
1638                         if (status != LINK_TRAINING_SUCCESS)
1639                                 break;
1640
1641                         repeater_training_done(link, repeater_id);
1642                 }
1643         }
1644
1645         if (status == LINK_TRAINING_SUCCESS) {
1646                 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1647         if (status == LINK_TRAINING_SUCCESS) {
1648                 status = perform_channel_equalization_sequence(link,
1649                                         &lt_settings,
1650                                         DPRX);
1651                 }
1652         }
1653
1654         /* 3. set training not in progress*/
1655         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1656         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1657                 status = perform_link_training_int(link,
1658                                 &lt_settings,
1659                                 status);
1660         }
1661
1662         /* delay 5ms after Main Link output idle pattern and then check
1663          * DPCD 0202h.
1664          */
1665         if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1666                 msleep(5);
1667                 status = dp_check_link_loss_status(link, &lt_settings);
1668         }
1669
1670         /* 6. print status message*/
1671         print_status_message(link, &lt_settings, status);
1672
1673         if (status != LINK_TRAINING_SUCCESS)
1674                 link->ctx->dc->debug_data.ltFailCount++;
1675
1676         return status;
1677 }
1678
1679 static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
1680 {
1681         struct dc_link *link = stream->link;
1682         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1683 #ifdef CONFIG_DRM_AMD_DC_HDCP
1684         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1685 #endif
1686
1687         /* ASSR must be supported on the panel */
1688         if (panel_mode == DP_PANEL_MODE_DEFAULT)
1689                 return panel_mode;
1690
1691         /* eDP or internal DP only */
1692         if (link->connector_signal != SIGNAL_TYPE_EDP &&
1693                 !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1694                  link->is_internal_display))
1695                 return DP_PANEL_MODE_DEFAULT;
1696
1697 #ifdef CONFIG_DRM_AMD_DC_HDCP
1698         if (cp_psp && cp_psp->funcs.enable_assr) {
1699                 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1700                         /* since eDP implies ASSR on, change panel
1701                          * mode to disable ASSR
1702                          */
1703                         panel_mode = DP_PANEL_MODE_DEFAULT;
1704                 }
1705         } else
1706                 panel_mode = DP_PANEL_MODE_DEFAULT;
1707
1708 #else
1709         /* turn off ASSR if the implementation is not compiled in */
1710         panel_mode = DP_PANEL_MODE_DEFAULT;
1711 #endif
1712         return panel_mode;
1713 }
1714
1715 bool perform_link_training_with_retries(
1716         const struct dc_link_settings *link_setting,
1717         bool skip_video_pattern,
1718         int attempts,
1719         struct pipe_ctx *pipe_ctx,
1720         enum signal_type signal,
1721         bool do_fallback)
1722 {
1723         uint8_t j;
1724         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1725         struct dc_stream_state *stream = pipe_ctx->stream;
1726         struct dc_link *link = stream->link;
1727         enum dp_panel_mode panel_mode;
1728         struct link_encoder *link_enc;
1729         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1730         struct dc_link_settings currnet_setting = *link_setting;
1731
1732         /* Dynamically assigned link encoders associated with stream rather than
1733          * link.
1734          */
1735         if (link->dc->res_pool->funcs->link_encs_assign)
1736                 link_enc = stream->link_enc;
1737         else
1738                 link_enc = link->link_enc;
1739         ASSERT(link_enc);
1740
1741         /* We need to do this before the link training to ensure the idle pattern in SST
1742          * mode will be sent right after the link training
1743          */
1744         link_enc->funcs->connect_dig_be_to_fe(link_enc,
1745                                                         pipe_ctx->stream_res.stream_enc->id, true);
1746
1747         for (j = 0; j < attempts; ++j) {
1748
1749                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1750                         __func__, (unsigned int)j + 1, attempts);
1751
1752                 dp_enable_link_phy(
1753                         link,
1754                         signal,
1755                         pipe_ctx->clock_source->id,
1756                         &currnet_setting);
1757
1758                 if (stream->sink_patches.dppowerup_delay > 0) {
1759                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1760
1761                         msleep(delay_dp_power_up_in_ms);
1762                 }
1763
1764                 panel_mode = try_enable_assr(stream);
1765                 dp_set_panel_mode(link, panel_mode);
1766                 DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
1767                          link->link_index,
1768                          panel_mode != DP_PANEL_MODE_DEFAULT);
1769
1770                 if (link->aux_access_disabled) {
1771                         dc_link_dp_perform_link_training_skip_aux(link, &currnet_setting);
1772                         return true;
1773                 } else {
1774                                 status = dc_link_dp_perform_link_training(
1775                                                                                 link,
1776                                                                                 &currnet_setting,
1777                                                                                 skip_video_pattern);
1778                         if (status == LINK_TRAINING_SUCCESS)
1779                                 return true;
1780                 }
1781
1782                 /* latest link training still fail, skip delay and keep PHY on
1783                  */
1784                 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1785                         break;
1786
1787                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1788                         __func__, (unsigned int)j + 1, attempts);
1789
1790                 dp_disable_link_phy(link, signal);
1791
1792                 /* Abort link training if failure due to sink being unplugged. */
1793                 if (status == LINK_TRAINING_ABORT)
1794                         break;
1795                 else if (do_fallback) {
1796                         decide_fallback_link_setting(*link_setting, &currnet_setting, status);
1797                         /* Fail link training if reduced link bandwidth no longer meets
1798                          * stream requirements.
1799                          */
1800                         if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1801                                         dc_link_bandwidth_kbps(link, &currnet_setting))
1802                                 break;
1803                 }
1804
1805                 msleep(delay_between_attempts);
1806
1807                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1808         }
1809
1810         return false;
1811 }
1812
1813 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1814 {
1815         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1816         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1817
1818         if (dp_cs != NULL) {
1819                 dp_cs_id = dp_cs->id;
1820         } else {
1821                 /*
1822                  * dp clock source is not initialized for some reason.
1823                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1824                  */
1825                 ASSERT(dp_cs);
1826         }
1827
1828         return dp_cs_id;
1829 }
1830
1831 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1832 {
1833         if (mst_enable == false &&
1834                 link->type == dc_connection_mst_branch) {
1835                 /* Disable MST on link. Use only local sink. */
1836                 dp_disable_link_phy_mst(link, link->connector_signal);
1837
1838                 link->type = dc_connection_single;
1839                 link->local_sink = link->remote_sinks[0];
1840                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1841         } else if (mst_enable == true &&
1842                         link->type == dc_connection_single &&
1843                         link->remote_sinks[0] != NULL) {
1844                 /* Re-enable MST on link. */
1845                 dp_disable_link_phy(link, link->connector_signal);
1846                 dp_enable_mst_on_sink(link, true);
1847
1848                 link->type = dc_connection_mst_branch;
1849                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1850         }
1851 }
1852
1853 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1854 {
1855         /* Begin Sync LT. During this time,
1856          * DPCD:600h must not be powered down.
1857          */
1858         link->sync_lt_in_progress = true;
1859
1860         /*Clear any existing preferred settings.*/
1861         memset(&link->preferred_training_settings, 0,
1862                 sizeof(struct dc_link_training_overrides));
1863         memset(&link->preferred_link_setting, 0,
1864                 sizeof(struct dc_link_settings));
1865
1866         return true;
1867 }
1868
1869 enum link_training_result dc_link_dp_sync_lt_attempt(
1870     struct dc_link *link,
1871     struct dc_link_settings *link_settings,
1872     struct dc_link_training_overrides *lt_overrides)
1873 {
1874         struct link_training_settings lt_settings;
1875         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1876         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1877         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1878         bool fec_enable = false;
1879
1880         initialize_training_settings(
1881                 link,
1882                 link_settings,
1883                 lt_overrides,
1884                 &lt_settings);
1885
1886         /* Setup MST Mode */
1887         if (lt_overrides->mst_enable)
1888                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1889
1890         /* Disable link */
1891         dp_disable_link_phy(link, link->connector_signal);
1892
1893         /* Enable link */
1894         dp_cs_id = get_clock_source_id(link);
1895         dp_enable_link_phy(link, link->connector_signal,
1896                 dp_cs_id, link_settings);
1897
1898         /* Set FEC enable */
1899         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1900         dp_set_fec_ready(link, fec_enable);
1901
1902         if (lt_overrides->alternate_scrambler_reset) {
1903                 if (*lt_overrides->alternate_scrambler_reset)
1904                         panel_mode = DP_PANEL_MODE_EDP;
1905                 else
1906                         panel_mode = DP_PANEL_MODE_DEFAULT;
1907         } else
1908                 panel_mode = dp_get_panel_mode(link);
1909
1910         dp_set_panel_mode(link, panel_mode);
1911
1912         /* Attempt to train with given link training settings */
1913         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1914                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1915
1916         /* Set link rate, lane count and spread. */
1917         dpcd_set_link_settings(link, &lt_settings);
1918
1919         /* 2. perform link training (set link training done
1920          *  to false is done as well)
1921          */
1922         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1923         if (lt_status == LINK_TRAINING_SUCCESS) {
1924                 lt_status = perform_channel_equalization_sequence(link,
1925                                                 &lt_settings,
1926                                                 DPRX);
1927         }
1928
1929         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1930         /* 4. print status message*/
1931         print_status_message(link, &lt_settings, lt_status);
1932
1933         return lt_status;
1934 }
1935
1936 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1937 {
1938         /* If input parameter is set, shut down phy.
1939          * Still shouldn't turn off dp_receiver (DPCD:600h)
1940          */
1941         if (link_down == true) {
1942                 dp_disable_link_phy(link, link->connector_signal);
1943                 dp_set_fec_ready(link, false);
1944         }
1945
1946         link->sync_lt_in_progress = false;
1947         return true;
1948 }
1949
1950 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
1951 {
1952         if (!max_link_enc_cap) {
1953                 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
1954                 return false;
1955         }
1956
1957         if (link->link_enc->funcs->get_max_link_cap) {
1958                 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
1959                 return true;
1960         }
1961
1962         DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
1963         max_link_enc_cap->lane_count = 1;
1964         max_link_enc_cap->link_rate = 6;
1965         return false;
1966 }
1967
1968 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1969 {
1970         struct dc_link_settings max_link_cap = {0};
1971
1972         /* get max link encoder capability */
1973         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1974
1975         /* Lower link settings based on sink's link cap */
1976         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1977                 max_link_cap.lane_count =
1978                                 link->reported_link_cap.lane_count;
1979         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1980                 max_link_cap.link_rate =
1981                                 link->reported_link_cap.link_rate;
1982         if (link->reported_link_cap.link_spread <
1983                         max_link_cap.link_spread)
1984                 max_link_cap.link_spread =
1985                                 link->reported_link_cap.link_spread;
1986         /*
1987          * account for lttpr repeaters cap
1988          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1989          */
1990         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1991                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1992                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1993
1994                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1995                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
1996
1997                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
1998                                                 __func__,
1999                                                 max_link_cap.lane_count,
2000                                                 max_link_cap.link_rate);
2001         }
2002         return max_link_cap;
2003 }
2004
2005 enum dc_status read_hpd_rx_irq_data(
2006         struct dc_link *link,
2007         union hpd_irq_data *irq_data)
2008 {
2009         static enum dc_status retval;
2010
2011         /* The HW reads 16 bytes from 200h on HPD,
2012          * but if we get an AUX_DEFER, the HW cannot retry
2013          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2014          * fail, so we now explicitly read 6 bytes which is
2015          * the req from the above mentioned test cases.
2016          *
2017          * For DP 1.4 we need to read those from 2002h range.
2018          */
2019         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2020                 retval = core_link_read_dpcd(
2021                         link,
2022                         DP_SINK_COUNT,
2023                         irq_data->raw,
2024                         sizeof(union hpd_irq_data));
2025         else {
2026                 /* Read 14 bytes in a single read and then copy only the required fields.
2027                  * This is more efficient than doing it in two separate AUX reads. */
2028
2029                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2030
2031                 retval = core_link_read_dpcd(
2032                         link,
2033                         DP_SINK_COUNT_ESI,
2034                         tmp,
2035                         sizeof(tmp));
2036
2037                 if (retval != DC_OK)
2038                         return retval;
2039
2040                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2041                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2042                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2043                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2044                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2045                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2046         }
2047
2048         return retval;
2049 }
2050
2051 static bool hpd_rx_irq_check_link_loss_status(
2052         struct dc_link *link,
2053         union hpd_irq_data *hpd_irq_dpcd_data)
2054 {
2055         uint8_t irq_reg_rx_power_state = 0;
2056         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2057         union lane_status lane_status;
2058         uint32_t lane;
2059         bool sink_status_changed;
2060         bool return_code;
2061
2062         sink_status_changed = false;
2063         return_code = false;
2064
2065         if (link->cur_link_settings.lane_count == 0)
2066                 return return_code;
2067
2068         /*1. Check that Link Status changed, before re-training.*/
2069
2070         /*parse lane status*/
2071         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2072                 /* check status of lanes 0,1
2073                  * changed DpcdAddress_Lane01Status (0x202)
2074                  */
2075                 lane_status.raw = get_nibble_at_index(
2076                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2077                         lane);
2078
2079                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2080                         !lane_status.bits.CR_DONE_0 ||
2081                         !lane_status.bits.SYMBOL_LOCKED_0) {
2082                         /* if one of the channel equalization, clock
2083                          * recovery or symbol lock is dropped
2084                          * consider it as (link has been
2085                          * dropped) dp sink status has changed
2086                          */
2087                         sink_status_changed = true;
2088                         break;
2089                 }
2090         }
2091
2092         /* Check interlane align.*/
2093         if (sink_status_changed ||
2094                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2095
2096                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2097
2098                 return_code = true;
2099
2100                 /*2. Check that we can handle interrupt: Not in FS DOS,
2101                  *  Not in "Display Timeout" state, Link is trained.
2102                  */
2103                 dpcd_result = core_link_read_dpcd(link,
2104                         DP_SET_POWER,
2105                         &irq_reg_rx_power_state,
2106                         sizeof(irq_reg_rx_power_state));
2107
2108                 if (dpcd_result != DC_OK) {
2109                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2110                                 __func__);
2111                 } else {
2112                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2113                                 return_code = false;
2114                 }
2115         }
2116
2117         return return_code;
2118 }
2119
2120 bool dp_verify_link_cap(
2121         struct dc_link *link,
2122         struct dc_link_settings *known_limit_link_setting,
2123         int *fail_count)
2124 {
2125         struct dc_link_settings max_link_cap = {0};
2126         struct dc_link_settings cur_link_setting = {0};
2127         struct dc_link_settings *cur = &cur_link_setting;
2128         struct dc_link_settings initial_link_settings = {0};
2129         bool success;
2130         bool skip_link_training;
2131         bool skip_video_pattern;
2132         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2133         enum link_training_result status;
2134         union hpd_irq_data irq_data;
2135
2136         if (link->dc->debug.skip_detection_link_training) {
2137                 link->verified_link_cap = *known_limit_link_setting;
2138                 return true;
2139         }
2140
2141         memset(&irq_data, 0, sizeof(irq_data));
2142         success = false;
2143         skip_link_training = false;
2144
2145         max_link_cap = get_max_link_cap(link);
2146
2147         /* Grant extended timeout request */
2148         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2149                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2150
2151                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2152         }
2153
2154         /* TODO implement override and monitor patch later */
2155
2156         /* try to train the link from high to low to
2157          * find the physical link capability
2158          */
2159         /* disable PHY done possible by BIOS, will be done by driver itself */
2160         dp_disable_link_phy(link, link->connector_signal);
2161
2162         dp_cs_id = get_clock_source_id(link);
2163
2164         /* link training starts with the maximum common settings
2165          * supported by both sink and ASIC.
2166          */
2167         initial_link_settings = get_common_supported_link_settings(
2168                         *known_limit_link_setting,
2169                         max_link_cap);
2170         cur_link_setting = initial_link_settings;
2171
2172         /* Temporary Renoir-specific workaround for SWDEV-215184;
2173          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2174          * so add extra cycle of enabling and disabling the PHY before first link training.
2175          */
2176         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2177                         link->dc->debug.usbc_combo_phy_reset_wa) {
2178                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2179                 dp_disable_link_phy(link, link->connector_signal);
2180         }
2181
2182         do {
2183                 skip_video_pattern = true;
2184
2185                 if (cur->link_rate == LINK_RATE_LOW)
2186                         skip_video_pattern = false;
2187
2188                 dp_enable_link_phy(
2189                                 link,
2190                                 link->connector_signal,
2191                                 dp_cs_id,
2192                                 cur);
2193
2194
2195                 if (skip_link_training)
2196                         success = true;
2197                 else {
2198                         status = dc_link_dp_perform_link_training(
2199                                                         link,
2200                                                         cur,
2201                                                         skip_video_pattern);
2202                         if (status == LINK_TRAINING_SUCCESS)
2203                                 success = true;
2204                         else
2205                                 (*fail_count)++;
2206                 }
2207
2208                 if (success) {
2209                         link->verified_link_cap = *cur;
2210                         udelay(1000);
2211                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2212                                 if (hpd_rx_irq_check_link_loss_status(
2213                                                 link,
2214                                                 &irq_data))
2215                                         (*fail_count)++;
2216                 }
2217                 /* always disable the link before trying another
2218                  * setting or before returning we'll enable it later
2219                  * based on the actual mode we're driving
2220                  */
2221                 dp_disable_link_phy(link, link->connector_signal);
2222         } while (!success && decide_fallback_link_setting(
2223                         initial_link_settings, cur, status));
2224
2225         /* Link Training failed for all Link Settings
2226          *  (Lane Count is still unknown)
2227          */
2228         if (!success) {
2229                 /* If all LT fails for all settings,
2230                  * set verified = failed safe (1 lane low)
2231                  */
2232                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2233                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2234
2235                 link->verified_link_cap.link_spread =
2236                 LINK_SPREAD_DISABLED;
2237         }
2238
2239
2240         return success;
2241 }
2242
2243 bool dp_verify_link_cap_with_retries(
2244         struct dc_link *link,
2245         struct dc_link_settings *known_limit_link_setting,
2246         int attempts)
2247 {
2248         uint8_t i = 0;
2249         bool success = false;
2250
2251         for (i = 0; i < attempts; i++) {
2252                 int fail_count = 0;
2253                 enum dc_connection_type type = dc_connection_none;
2254
2255                 memset(&link->verified_link_cap, 0,
2256                                 sizeof(struct dc_link_settings));
2257                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2258                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2259                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2260                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2261                         break;
2262                 } else if (dp_verify_link_cap(link,
2263                                 &link->reported_link_cap,
2264                                 &fail_count) && fail_count == 0) {
2265                         success = true;
2266                         break;
2267                 }
2268                 msleep(10);
2269         }
2270         return success;
2271 }
2272
2273 bool dp_verify_mst_link_cap(
2274         struct dc_link *link)
2275 {
2276         struct dc_link_settings max_link_cap = {0};
2277
2278         max_link_cap = get_max_link_cap(link);
2279         link->verified_link_cap = get_common_supported_link_settings(
2280                 link->reported_link_cap,
2281                 max_link_cap);
2282
2283         return true;
2284 }
2285
2286 static struct dc_link_settings get_common_supported_link_settings(
2287                 struct dc_link_settings link_setting_a,
2288                 struct dc_link_settings link_setting_b)
2289 {
2290         struct dc_link_settings link_settings = {0};
2291
2292         link_settings.lane_count =
2293                 (link_setting_a.lane_count <=
2294                         link_setting_b.lane_count) ?
2295                         link_setting_a.lane_count :
2296                         link_setting_b.lane_count;
2297         link_settings.link_rate =
2298                 (link_setting_a.link_rate <=
2299                         link_setting_b.link_rate) ?
2300                         link_setting_a.link_rate :
2301                         link_setting_b.link_rate;
2302         link_settings.link_spread = LINK_SPREAD_DISABLED;
2303
2304         /* in DP compliance test, DPR-120 may have
2305          * a random value in its MAX_LINK_BW dpcd field.
2306          * We map it to the maximum supported link rate that
2307          * is smaller than MAX_LINK_BW in this case.
2308          */
2309         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2310                 link_settings.link_rate = LINK_RATE_HIGH3;
2311         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2312                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2313                 link_settings.link_rate = LINK_RATE_HIGH2;
2314         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2315                         && link_settings.link_rate > LINK_RATE_HIGH) {
2316                 link_settings.link_rate = LINK_RATE_HIGH;
2317         } else if (link_settings.link_rate < LINK_RATE_HIGH
2318                         && link_settings.link_rate > LINK_RATE_LOW) {
2319                 link_settings.link_rate = LINK_RATE_LOW;
2320         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2321                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2322         }
2323
2324         return link_settings;
2325 }
2326
2327 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2328 {
2329         return lane_count <= LANE_COUNT_ONE;
2330 }
2331
2332 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2333 {
2334         return link_rate <= LINK_RATE_LOW;
2335 }
2336
2337 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2338 {
2339         switch (lane_count) {
2340         case LANE_COUNT_FOUR:
2341                 return LANE_COUNT_TWO;
2342         case LANE_COUNT_TWO:
2343                 return LANE_COUNT_ONE;
2344         case LANE_COUNT_ONE:
2345                 return LANE_COUNT_UNKNOWN;
2346         default:
2347                 return LANE_COUNT_UNKNOWN;
2348         }
2349 }
2350
2351 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2352 {
2353         switch (link_rate) {
2354         case LINK_RATE_HIGH3:
2355                 return LINK_RATE_HIGH2;
2356         case LINK_RATE_HIGH2:
2357                 return LINK_RATE_HIGH;
2358         case LINK_RATE_HIGH:
2359                 return LINK_RATE_LOW;
2360         case LINK_RATE_LOW:
2361                 return LINK_RATE_UNKNOWN;
2362         default:
2363                 return LINK_RATE_UNKNOWN;
2364         }
2365 }
2366
2367 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2368 {
2369         switch (lane_count) {
2370         case LANE_COUNT_ONE:
2371                 return LANE_COUNT_TWO;
2372         case LANE_COUNT_TWO:
2373                 return LANE_COUNT_FOUR;
2374         default:
2375                 return LANE_COUNT_UNKNOWN;
2376         }
2377 }
2378
2379 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2380 {
2381         switch (link_rate) {
2382         case LINK_RATE_LOW:
2383                 return LINK_RATE_HIGH;
2384         case LINK_RATE_HIGH:
2385                 return LINK_RATE_HIGH2;
2386         case LINK_RATE_HIGH2:
2387                 return LINK_RATE_HIGH3;
2388         default:
2389                 return LINK_RATE_UNKNOWN;
2390         }
2391 }
2392
2393 /*
2394  * function: set link rate and lane count fallback based
2395  * on current link setting and last link training result
2396  * return value:
2397  *                      true - link setting could be set
2398  *                      false - has reached minimum setting
2399  *                                      and no further fallback could be done
2400  */
2401 static bool decide_fallback_link_setting(
2402                 struct dc_link_settings initial_link_settings,
2403                 struct dc_link_settings *current_link_setting,
2404                 enum link_training_result training_result)
2405 {
2406         if (!current_link_setting)
2407                 return false;
2408
2409         switch (training_result) {
2410         case LINK_TRAINING_CR_FAIL_LANE0:
2411         case LINK_TRAINING_CR_FAIL_LANE1:
2412         case LINK_TRAINING_CR_FAIL_LANE23:
2413         case LINK_TRAINING_LQA_FAIL:
2414         {
2415                 if (!reached_minimum_link_rate
2416                                 (current_link_setting->link_rate)) {
2417                         current_link_setting->link_rate =
2418                                 reduce_link_rate(
2419                                         current_link_setting->link_rate);
2420                 } else if (!reached_minimum_lane_count
2421                                 (current_link_setting->lane_count)) {
2422                         current_link_setting->link_rate =
2423                                 initial_link_settings.link_rate;
2424                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2425                                 return false;
2426                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2427                                 current_link_setting->lane_count =
2428                                                 LANE_COUNT_ONE;
2429                         else if (training_result ==
2430                                         LINK_TRAINING_CR_FAIL_LANE23)
2431                                 current_link_setting->lane_count =
2432                                                 LANE_COUNT_TWO;
2433                         else
2434                                 current_link_setting->lane_count =
2435                                         reduce_lane_count(
2436                                         current_link_setting->lane_count);
2437                 } else {
2438                         return false;
2439                 }
2440                 break;
2441         }
2442         case LINK_TRAINING_EQ_FAIL_EQ:
2443         {
2444                 if (!reached_minimum_lane_count
2445                                 (current_link_setting->lane_count)) {
2446                         current_link_setting->lane_count =
2447                                 reduce_lane_count(
2448                                         current_link_setting->lane_count);
2449                 } else if (!reached_minimum_link_rate
2450                                 (current_link_setting->link_rate)) {
2451                         current_link_setting->link_rate =
2452                                 reduce_link_rate(
2453                                         current_link_setting->link_rate);
2454                 } else {
2455                         return false;
2456                 }
2457                 break;
2458         }
2459         case LINK_TRAINING_EQ_FAIL_CR:
2460         {
2461                 if (!reached_minimum_link_rate
2462                                 (current_link_setting->link_rate)) {
2463                         current_link_setting->link_rate =
2464                                 reduce_link_rate(
2465                                         current_link_setting->link_rate);
2466                 } else {
2467                         return false;
2468                 }
2469                 break;
2470         }
2471         default:
2472                 return false;
2473         }
2474         return true;
2475 }
2476
2477 bool dp_validate_mode_timing(
2478         struct dc_link *link,
2479         const struct dc_crtc_timing *timing)
2480 {
2481         uint32_t req_bw;
2482         uint32_t max_bw;
2483
2484         const struct dc_link_settings *link_setting;
2485
2486         /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2487         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2488                         !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2489                         dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2490                 return false;
2491
2492         /*always DP fail safe mode*/
2493         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2494                 timing->h_addressable == (uint32_t) 640 &&
2495                 timing->v_addressable == (uint32_t) 480)
2496                 return true;
2497
2498         link_setting = dc_link_get_link_cap(link);
2499
2500         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2501         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2502                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2503                 link_setting = &link->verified_link_cap;
2504         */
2505
2506         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2507         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2508
2509         if (req_bw <= max_bw) {
2510                 /* remember the biggest mode here, during
2511                  * initial link training (to get
2512                  * verified_link_cap), LS sends event about
2513                  * cannot train at reported cap to upper
2514                  * layer and upper layer will re-enumerate modes.
2515                  * this is not necessary if the lower
2516                  * verified_link_cap is enough to drive
2517                  * all the modes */
2518
2519                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2520                 /* if (flags.DYNAMIC_VALIDATION == 1)
2521                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2522                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2523                 return true;
2524         } else
2525                 return false;
2526 }
2527
2528 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2529 {
2530         struct dc_link_settings initial_link_setting = {
2531                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2532         struct dc_link_settings current_link_setting =
2533                         initial_link_setting;
2534         uint32_t link_bw;
2535
2536         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2537                 return false;
2538
2539         /* search for the minimum link setting that:
2540          * 1. is supported according to the link training result
2541          * 2. could support the b/w requested by the timing
2542          */
2543         while (current_link_setting.link_rate <=
2544                         link->verified_link_cap.link_rate) {
2545                 link_bw = dc_link_bandwidth_kbps(
2546                                 link,
2547                                 &current_link_setting);
2548                 if (req_bw <= link_bw) {
2549                         *link_setting = current_link_setting;
2550                         return true;
2551                 }
2552
2553                 if (current_link_setting.lane_count <
2554                                 link->verified_link_cap.lane_count) {
2555                         current_link_setting.lane_count =
2556                                         increase_lane_count(
2557                                                         current_link_setting.lane_count);
2558                 } else {
2559                         current_link_setting.link_rate =
2560                                         increase_link_rate(
2561                                                         current_link_setting.link_rate);
2562                         current_link_setting.lane_count =
2563                                         initial_link_setting.lane_count;
2564                 }
2565         }
2566
2567         return false;
2568 }
2569
2570 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2571 {
2572         struct dc_link_settings initial_link_setting;
2573         struct dc_link_settings current_link_setting;
2574         uint32_t link_bw;
2575
2576         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
2577                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2578                 *link_setting = link->verified_link_cap;
2579                 return true;
2580         }
2581
2582         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2583         initial_link_setting.lane_count = LANE_COUNT_ONE;
2584         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2585         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2586         initial_link_setting.use_link_rate_set = true;
2587         initial_link_setting.link_rate_set = 0;
2588         current_link_setting = initial_link_setting;
2589
2590         /* search for the minimum link setting that:
2591          * 1. is supported according to the link training result
2592          * 2. could support the b/w requested by the timing
2593          */
2594         while (current_link_setting.link_rate <=
2595                         link->verified_link_cap.link_rate) {
2596                 link_bw = dc_link_bandwidth_kbps(
2597                                 link,
2598                                 &current_link_setting);
2599                 if (req_bw <= link_bw) {
2600                         *link_setting = current_link_setting;
2601                         return true;
2602                 }
2603
2604                 if (current_link_setting.lane_count <
2605                                 link->verified_link_cap.lane_count) {
2606                         current_link_setting.lane_count =
2607                                         increase_lane_count(
2608                                                         current_link_setting.lane_count);
2609                 } else {
2610                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2611                                 current_link_setting.link_rate_set++;
2612                                 current_link_setting.link_rate =
2613                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2614                                 current_link_setting.lane_count =
2615                                                                         initial_link_setting.lane_count;
2616                         } else
2617                                 break;
2618                 }
2619         }
2620         return false;
2621 }
2622
2623 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2624 {
2625         *link_setting = link->verified_link_cap;
2626         return true;
2627 }
2628
2629 void decide_link_settings(struct dc_stream_state *stream,
2630         struct dc_link_settings *link_setting)
2631 {
2632         struct dc_link *link;
2633         uint32_t req_bw;
2634
2635         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2636
2637         link = stream->link;
2638
2639         /* if preferred is specified through AMDDP, use it, if it's enough
2640          * to drive the mode
2641          */
2642         if (link->preferred_link_setting.lane_count !=
2643                         LANE_COUNT_UNKNOWN &&
2644                         link->preferred_link_setting.link_rate !=
2645                                         LINK_RATE_UNKNOWN) {
2646                 *link_setting =  link->preferred_link_setting;
2647                 return;
2648         }
2649
2650         /* MST doesn't perform link training for now
2651          * TODO: add MST specific link training routine
2652          */
2653         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2654                 if (decide_mst_link_settings(link, link_setting))
2655                         return;
2656         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2657                 if (decide_edp_link_settings(link, link_setting, req_bw))
2658                         return;
2659         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2660                 return;
2661
2662         BREAK_TO_DEBUGGER();
2663         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2664
2665         *link_setting = link->verified_link_cap;
2666 }
2667
2668 /*************************Short Pulse IRQ***************************/
2669 static bool allow_hpd_rx_irq(const struct dc_link *link)
2670 {
2671         /*
2672          * Don't handle RX IRQ unless one of following is met:
2673          * 1) The link is established (cur_link_settings != unknown)
2674          * 2) We know we're dealing with a branch device, SST or MST
2675          */
2676
2677         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2678                 is_dp_branch_device(link))
2679                 return true;
2680
2681         return false;
2682 }
2683
2684 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2685 {
2686         union dpcd_psr_configuration psr_configuration;
2687
2688         if (!link->psr_settings.psr_feature_enabled)
2689                 return false;
2690
2691         dm_helpers_dp_read_dpcd(
2692                 link->ctx,
2693                 link,
2694                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2695                 &psr_configuration.raw,
2696                 sizeof(psr_configuration.raw));
2697
2698
2699         if (psr_configuration.bits.ENABLE) {
2700                 unsigned char dpcdbuf[3] = {0};
2701                 union psr_error_status psr_error_status;
2702                 union psr_sink_psr_status psr_sink_psr_status;
2703
2704                 dm_helpers_dp_read_dpcd(
2705                         link->ctx,
2706                         link,
2707                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2708                         (unsigned char *) dpcdbuf,
2709                         sizeof(dpcdbuf));
2710
2711                 /*DPCD 2006h   ERROR STATUS*/
2712                 psr_error_status.raw = dpcdbuf[0];
2713                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2714                 psr_sink_psr_status.raw = dpcdbuf[2];
2715
2716                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2717                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2718                                 psr_error_status.bits.VSC_SDP_ERROR) {
2719                         /* Acknowledge and clear error bits */
2720                         dm_helpers_dp_write_dpcd(
2721                                 link->ctx,
2722                                 link,
2723                                 8198,/*DpcdAddress_PSR_Error_Status*/
2724                                 &psr_error_status.raw,
2725                                 sizeof(psr_error_status.raw));
2726
2727                         /* PSR error, disable and re-enable PSR */
2728                         dc_link_set_psr_allow_active(link, false, true, false);
2729                         dc_link_set_psr_allow_active(link, true, true, false);
2730
2731                         return true;
2732                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2733                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2734                         /* No error is detect, PSR is active.
2735                          * We should return with IRQ_HPD handled without
2736                          * checking for loss of sync since PSR would have
2737                          * powered down main link.
2738                          */
2739                         return true;
2740                 }
2741         }
2742         return false;
2743 }
2744
2745 static void dp_test_send_link_training(struct dc_link *link)
2746 {
2747         struct dc_link_settings link_settings = {0};
2748
2749         core_link_read_dpcd(
2750                         link,
2751                         DP_TEST_LANE_COUNT,
2752                         (unsigned char *)(&link_settings.lane_count),
2753                         1);
2754         core_link_read_dpcd(
2755                         link,
2756                         DP_TEST_LINK_RATE,
2757                         (unsigned char *)(&link_settings.link_rate),
2758                         1);
2759
2760         /* Set preferred link settings */
2761         link->verified_link_cap.lane_count = link_settings.lane_count;
2762         link->verified_link_cap.link_rate = link_settings.link_rate;
2763
2764         dp_retrain_link_dp_test(link, &link_settings, false);
2765 }
2766
2767 /* TODO Raven hbr2 compliance eye output is unstable
2768  * (toggling on and off) with debugger break
2769  * This caueses intermittent PHY automation failure
2770  * Need to look into the root cause */
2771 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2772 {
2773         union phy_test_pattern dpcd_test_pattern;
2774         union lane_adjust dpcd_lane_adjustment[2];
2775         unsigned char dpcd_post_cursor_2_adjustment = 0;
2776         unsigned char test_80_bit_pattern[
2777                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2778                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2779         enum dp_test_pattern test_pattern;
2780         struct dc_link_training_settings link_settings;
2781         union lane_adjust dpcd_lane_adjust;
2782         unsigned int lane;
2783         struct link_training_settings link_training_settings;
2784         int i = 0;
2785
2786         dpcd_test_pattern.raw = 0;
2787         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2788         memset(&link_settings, 0, sizeof(link_settings));
2789
2790         /* get phy test pattern and pattern parameters from DP receiver */
2791         core_link_read_dpcd(
2792                         link,
2793                         DP_PHY_TEST_PATTERN,
2794                         &dpcd_test_pattern.raw,
2795                         sizeof(dpcd_test_pattern));
2796         core_link_read_dpcd(
2797                         link,
2798                         DP_ADJUST_REQUEST_LANE0_1,
2799                         &dpcd_lane_adjustment[0].raw,
2800                         sizeof(dpcd_lane_adjustment));
2801
2802         /*get post cursor 2 parameters
2803          * For DP 1.1a or eariler, this DPCD register's value is 0
2804          * For DP 1.2 or later:
2805          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2806          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2807          */
2808         core_link_read_dpcd(
2809                         link,
2810                         DP_ADJUST_REQUEST_POST_CURSOR2,
2811                         &dpcd_post_cursor_2_adjustment,
2812                         sizeof(dpcd_post_cursor_2_adjustment));
2813
2814         /* translate request */
2815         switch (dpcd_test_pattern.bits.PATTERN) {
2816         case PHY_TEST_PATTERN_D10_2:
2817                 test_pattern = DP_TEST_PATTERN_D102;
2818                 break;
2819         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2820                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2821                 break;
2822         case PHY_TEST_PATTERN_PRBS7:
2823                 test_pattern = DP_TEST_PATTERN_PRBS7;
2824                 break;
2825         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2826                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2827                 break;
2828         case PHY_TEST_PATTERN_CP2520_1:
2829                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2830                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2831                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2832                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2833                 break;
2834         case PHY_TEST_PATTERN_CP2520_2:
2835                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2836                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2837                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2838                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2839                 break;
2840         case PHY_TEST_PATTERN_CP2520_3:
2841                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2842                 break;
2843         default:
2844                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2845         break;
2846         }
2847
2848         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2849                 core_link_read_dpcd(
2850                                 link,
2851                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2852                                 test_80_bit_pattern,
2853                                 sizeof(test_80_bit_pattern));
2854
2855         /* prepare link training settings */
2856         link_settings.link = link->cur_link_settings;
2857
2858         for (lane = 0; lane <
2859                 (unsigned int)(link->cur_link_settings.lane_count);
2860                 lane++) {
2861                 dpcd_lane_adjust.raw =
2862                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2863                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2864                         (enum dc_voltage_swing)
2865                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2866                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2867                         (enum dc_pre_emphasis)
2868                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2869                 link_settings.lane_settings[lane].POST_CURSOR2 =
2870                         (enum dc_post_cursor2)
2871                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2872         }
2873
2874         for (i = 0; i < 4; i++)
2875                 link_training_settings.lane_settings[i] =
2876                                 link_settings.lane_settings[i];
2877         link_training_settings.link_settings = link_settings.link;
2878         link_training_settings.allow_invalid_msa_timing_param = false;
2879         /*Usage: Measure DP physical lane signal
2880          * by DP SI test equipment automatically.
2881          * PHY test pattern request is generated by equipment via HPD interrupt.
2882          * HPD needs to be active all the time. HPD should be active
2883          * all the time. Do not touch it.
2884          * forward request to DS
2885          */
2886         dc_link_dp_set_test_pattern(
2887                 link,
2888                 test_pattern,
2889                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2890                 &link_training_settings,
2891                 test_80_bit_pattern,
2892                 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2893                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
2894 }
2895
2896 static void dp_test_send_link_test_pattern(struct dc_link *link)
2897 {
2898         union link_test_pattern dpcd_test_pattern;
2899         union test_misc dpcd_test_params;
2900         enum dp_test_pattern test_pattern;
2901         enum dp_test_pattern_color_space test_pattern_color_space =
2902                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2903         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2904         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2905         struct pipe_ctx *pipe_ctx = NULL;
2906         int i;
2907
2908         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2909         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2910
2911         for (i = 0; i < MAX_PIPES; i++) {
2912                 if (pipes[i].stream == NULL)
2913                         continue;
2914
2915                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
2916                         pipe_ctx = &pipes[i];
2917                         break;
2918                 }
2919         }
2920
2921         if (pipe_ctx == NULL)
2922                 return;
2923
2924         /* get link test pattern and pattern parameters */
2925         core_link_read_dpcd(
2926                         link,
2927                         DP_TEST_PATTERN,
2928                         &dpcd_test_pattern.raw,
2929                         sizeof(dpcd_test_pattern));
2930         core_link_read_dpcd(
2931                         link,
2932                         DP_TEST_MISC0,
2933                         &dpcd_test_params.raw,
2934                         sizeof(dpcd_test_params));
2935
2936         switch (dpcd_test_pattern.bits.PATTERN) {
2937         case LINK_TEST_PATTERN_COLOR_RAMP:
2938                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2939         break;
2940         case LINK_TEST_PATTERN_VERTICAL_BARS:
2941                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2942         break; /* black and white */
2943         case LINK_TEST_PATTERN_COLOR_SQUARES:
2944                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2945                                 TEST_DYN_RANGE_VESA ?
2946                                 DP_TEST_PATTERN_COLOR_SQUARES :
2947                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2948         break;
2949         default:
2950                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2951         break;
2952         }
2953
2954         if (dpcd_test_params.bits.CLR_FORMAT == 0)
2955                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2956         else
2957                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2958                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2959                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2960
2961         switch (dpcd_test_params.bits.BPC) {
2962         case 0: // 6 bits
2963                 requestColorDepth = COLOR_DEPTH_666;
2964                 break;
2965         case 1: // 8 bits
2966                 requestColorDepth = COLOR_DEPTH_888;
2967                 break;
2968         case 2: // 10 bits
2969                 requestColorDepth = COLOR_DEPTH_101010;
2970                 break;
2971         case 3: // 12 bits
2972                 requestColorDepth = COLOR_DEPTH_121212;
2973                 break;
2974         default:
2975                 break;
2976         }
2977
2978         switch (dpcd_test_params.bits.CLR_FORMAT) {
2979         case 0:
2980                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
2981                 break;
2982         case 1:
2983                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
2984                 break;
2985         case 2:
2986                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
2987                 break;
2988         default:
2989                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
2990                 break;
2991         }
2992
2993
2994         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
2995                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
2996                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
2997                                 __func__,
2998                                 pipe_ctx->stream->timing.display_color_depth,
2999                                 requestColorDepth);
3000                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
3001         }
3002
3003         dp_update_dsc_config(pipe_ctx);
3004
3005         dc_link_dp_set_test_pattern(
3006                         link,
3007                         test_pattern,
3008                         test_pattern_color_space,
3009                         NULL,
3010                         NULL,
3011                         0);
3012 }
3013
3014 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3015 {
3016         union audio_test_mode            dpcd_test_mode = {0};
3017         struct audio_test_pattern_type   dpcd_pattern_type = {0};
3018         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3019         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3020
3021         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3022         struct pipe_ctx *pipe_ctx = &pipes[0];
3023         unsigned int channel_count;
3024         unsigned int channel = 0;
3025         unsigned int modes = 0;
3026         unsigned int sampling_rate_in_hz = 0;
3027
3028         // get audio test mode and test pattern parameters
3029         core_link_read_dpcd(
3030                 link,
3031                 DP_TEST_AUDIO_MODE,
3032                 &dpcd_test_mode.raw,
3033                 sizeof(dpcd_test_mode));
3034
3035         core_link_read_dpcd(
3036                 link,
3037                 DP_TEST_AUDIO_PATTERN_TYPE,
3038                 &dpcd_pattern_type.value,
3039                 sizeof(dpcd_pattern_type));
3040
3041         channel_count = dpcd_test_mode.bits.channel_count + 1;
3042
3043         // read pattern periods for requested channels when sawTooth pattern is requested
3044         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3045                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3046
3047                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3048                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3049                 // read period for each channel
3050                 for (channel = 0; channel < channel_count; channel++) {
3051                         core_link_read_dpcd(
3052                                                         link,
3053                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
3054                                                         &dpcd_pattern_period[channel].raw,
3055                                                         sizeof(dpcd_pattern_period[channel]));
3056                 }
3057         }
3058
3059         // translate sampling rate
3060         switch (dpcd_test_mode.bits.sampling_rate) {
3061         case AUDIO_SAMPLING_RATE_32KHZ:
3062                 sampling_rate_in_hz = 32000;
3063                 break;
3064         case AUDIO_SAMPLING_RATE_44_1KHZ:
3065                 sampling_rate_in_hz = 44100;
3066                 break;
3067         case AUDIO_SAMPLING_RATE_48KHZ:
3068                 sampling_rate_in_hz = 48000;
3069                 break;
3070         case AUDIO_SAMPLING_RATE_88_2KHZ:
3071                 sampling_rate_in_hz = 88200;
3072                 break;
3073         case AUDIO_SAMPLING_RATE_96KHZ:
3074                 sampling_rate_in_hz = 96000;
3075                 break;
3076         case AUDIO_SAMPLING_RATE_176_4KHZ:
3077                 sampling_rate_in_hz = 176400;
3078                 break;
3079         case AUDIO_SAMPLING_RATE_192KHZ:
3080                 sampling_rate_in_hz = 192000;
3081                 break;
3082         default:
3083                 sampling_rate_in_hz = 0;
3084                 break;
3085         }
3086
3087         link->audio_test_data.flags.test_requested = 1;
3088         link->audio_test_data.flags.disable_video = disable_video;
3089         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3090         link->audio_test_data.channel_count = channel_count;
3091         link->audio_test_data.pattern_type = test_pattern;
3092
3093         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3094                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3095                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3096                 }
3097         }
3098 }
3099
3100 static void handle_automated_test(struct dc_link *link)
3101 {
3102         union test_request test_request;
3103         union test_response test_response;
3104
3105         memset(&test_request, 0, sizeof(test_request));
3106         memset(&test_response, 0, sizeof(test_response));
3107
3108         core_link_read_dpcd(
3109                 link,
3110                 DP_TEST_REQUEST,
3111                 &test_request.raw,
3112                 sizeof(union test_request));
3113         if (test_request.bits.LINK_TRAINING) {
3114                 /* ACK first to let DP RX test box monitor LT sequence */
3115                 test_response.bits.ACK = 1;
3116                 core_link_write_dpcd(
3117                         link,
3118                         DP_TEST_RESPONSE,
3119                         &test_response.raw,
3120                         sizeof(test_response));
3121                 dp_test_send_link_training(link);
3122                 /* no acknowledge request is needed again */
3123                 test_response.bits.ACK = 0;
3124         }
3125         if (test_request.bits.LINK_TEST_PATTRN) {
3126                 dp_test_send_link_test_pattern(link);
3127                 test_response.bits.ACK = 1;
3128         }
3129
3130         if (test_request.bits.AUDIO_TEST_PATTERN) {
3131                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3132                 test_response.bits.ACK = 1;
3133         }
3134
3135         if (test_request.bits.PHY_TEST_PATTERN) {
3136                 dp_test_send_phy_test_pattern(link);
3137                 test_response.bits.ACK = 1;
3138         }
3139
3140         /* send request acknowledgment */
3141         if (test_response.bits.ACK)
3142                 core_link_write_dpcd(
3143                         link,
3144                         DP_TEST_RESPONSE,
3145                         &test_response.raw,
3146                         sizeof(test_response));
3147 }
3148
3149 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3150 {
3151         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3152         union device_service_irq device_service_clear = { { 0 } };
3153         enum dc_status result;
3154         bool status = false;
3155         struct pipe_ctx *pipe_ctx;
3156         int i;
3157
3158         if (out_link_loss)
3159                 *out_link_loss = false;
3160         /* For use cases related to down stream connection status change,
3161          * PSR and device auto test, refer to function handle_sst_hpd_irq
3162          * in DAL2.1*/
3163
3164         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3165                 __func__, link->link_index);
3166
3167
3168          /* All the "handle_hpd_irq_xxx()" methods
3169                  * should be called only after
3170                  * dal_dpsst_ls_read_hpd_irq_data
3171                  * Order of calls is important too
3172                  */
3173         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3174         if (out_hpd_irq_dpcd_data)
3175                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3176
3177         if (result != DC_OK) {
3178                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3179                         __func__);
3180                 return false;
3181         }
3182
3183         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3184                 device_service_clear.bits.AUTOMATED_TEST = 1;
3185                 core_link_write_dpcd(
3186                         link,
3187                         DP_DEVICE_SERVICE_IRQ_VECTOR,
3188                         &device_service_clear.raw,
3189                         sizeof(device_service_clear.raw));
3190                 device_service_clear.raw = 0;
3191                 handle_automated_test(link);
3192                 return false;
3193         }
3194
3195         if (!allow_hpd_rx_irq(link)) {
3196                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3197                         __func__, link->link_index);
3198                 return false;
3199         }
3200
3201         if (handle_hpd_irq_psr_sink(link))
3202                 /* PSR-related error was detected and handled */
3203                 return true;
3204
3205         /* If PSR-related error handled, Main link may be off,
3206          * so do not handle as a normal sink status change interrupt.
3207          */
3208
3209         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3210                 return true;
3211
3212         /* check if we have MST msg and return since we poll for it */
3213         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3214                 return false;
3215
3216         /* For now we only handle 'Downstream port status' case.
3217          * If we got sink count changed it means
3218          * Downstream port status changed,
3219          * then DM should call DC to do the detection.
3220          * NOTE: Do not handle link loss on eDP since it is internal link*/
3221         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3222                 hpd_rx_irq_check_link_loss_status(
3223                         link,
3224                         &hpd_irq_dpcd_data)) {
3225                 /* Connectivity log: link loss */
3226                 CONN_DATA_LINK_LOSS(link,
3227                                         hpd_irq_dpcd_data.raw,
3228                                         sizeof(hpd_irq_dpcd_data),
3229                                         "Status: ");
3230
3231                 for (i = 0; i < MAX_PIPES; i++) {
3232                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3233                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3234                                 break;
3235                 }
3236
3237                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3238                         return false;
3239
3240
3241                 for (i = 0; i < MAX_PIPES; i++) {
3242                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3243                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3244                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3245                                 core_link_disable_stream(pipe_ctx);
3246                 }
3247
3248                 for (i = 0; i < MAX_PIPES; i++) {
3249                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3250                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3251                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3252                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3253                 }
3254
3255                 status = false;
3256                 if (out_link_loss)
3257                         *out_link_loss = true;
3258         }
3259
3260         if (link->type == dc_connection_sst_branch &&
3261                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3262                         != link->dpcd_sink_count)
3263                 status = true;
3264
3265         /* reasons for HPD RX:
3266          * 1. Link Loss - ie Re-train the Link
3267          * 2. MST sideband message
3268          * 3. Automated Test - ie. Internal Commit
3269          * 4. CP (copy protection) - (not interesting for DM???)
3270          * 5. DRR
3271          * 6. Downstream Port status changed
3272          * -ie. Detect - this the only one
3273          * which is interesting for DM because
3274          * it must call dc_link_detect.
3275          */
3276         return status;
3277 }
3278
3279 /*query dpcd for version and mst cap addresses*/
3280 bool is_mst_supported(struct dc_link *link)
3281 {
3282         bool mst          = false;
3283         enum dc_status st = DC_OK;
3284         union dpcd_rev rev;
3285         union mstm_cap cap;
3286
3287         if (link->preferred_training_settings.mst_enable &&
3288                 *link->preferred_training_settings.mst_enable == false) {
3289                 return false;
3290         }
3291
3292         rev.raw  = 0;
3293         cap.raw  = 0;
3294
3295         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3296                         sizeof(rev));
3297
3298         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3299
3300                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3301                                 &cap.raw, sizeof(cap));
3302                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3303                         mst = true;
3304         }
3305         return mst;
3306
3307 }
3308
3309 bool is_dp_active_dongle(const struct dc_link *link)
3310 {
3311         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3312                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3313 }
3314
3315 bool is_dp_branch_device(const struct dc_link *link)
3316 {
3317         return link->dpcd_caps.is_branch_dev;
3318 }
3319
3320 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3321 {
3322         switch (bpc) {
3323         case DOWN_STREAM_MAX_8BPC:
3324                 return 8;
3325         case DOWN_STREAM_MAX_10BPC:
3326                 return 10;
3327         case DOWN_STREAM_MAX_12BPC:
3328                 return 12;
3329         case DOWN_STREAM_MAX_16BPC:
3330                 return 16;
3331         default:
3332                 break;
3333         }
3334
3335         return -1;
3336 }
3337
3338 static void read_dp_device_vendor_id(struct dc_link *link)
3339 {
3340         struct dp_device_vendor_id dp_id;
3341
3342         /* read IEEE branch device id */
3343         core_link_read_dpcd(
3344                 link,
3345                 DP_BRANCH_OUI,
3346                 (uint8_t *)&dp_id,
3347                 sizeof(dp_id));
3348
3349         link->dpcd_caps.branch_dev_id =
3350                 (dp_id.ieee_oui[0] << 16) +
3351                 (dp_id.ieee_oui[1] << 8) +
3352                 dp_id.ieee_oui[2];
3353
3354         memmove(
3355                 link->dpcd_caps.branch_dev_name,
3356                 dp_id.ieee_device_id,
3357                 sizeof(dp_id.ieee_device_id));
3358 }
3359
3360
3361
3362 static void get_active_converter_info(
3363         uint8_t data, struct dc_link *link)
3364 {
3365         union dp_downstream_port_present ds_port = { .byte = data };
3366         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3367
3368         /* decode converter info*/
3369         if (!ds_port.fields.PORT_PRESENT) {
3370                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3371                 ddc_service_set_dongle_type(link->ddc,
3372                                 link->dpcd_caps.dongle_type);
3373                 link->dpcd_caps.is_branch_dev = false;
3374                 return;
3375         }
3376
3377         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3378         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3379
3380         switch (ds_port.fields.PORT_TYPE) {
3381         case DOWNSTREAM_VGA:
3382                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3383                 break;
3384         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3385                 /* At this point we don't know is it DVI or HDMI or DP++,
3386                  * assume DVI.*/
3387                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3388                 break;
3389         default:
3390                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3391                 break;
3392         }
3393
3394         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3395                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3396                 union dwnstream_port_caps_byte0 *port_caps =
3397                         (union dwnstream_port_caps_byte0 *)det_caps;
3398                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3399                                 det_caps, sizeof(det_caps)) == DC_OK) {
3400
3401                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3402                         /*Handle DP case as DONGLE_NONE*/
3403                         case DOWN_STREAM_DETAILED_DP:
3404                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3405                                 break;
3406                         case DOWN_STREAM_DETAILED_VGA:
3407                                 link->dpcd_caps.dongle_type =
3408                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3409                                 break;
3410                         case DOWN_STREAM_DETAILED_DVI:
3411                                 link->dpcd_caps.dongle_type =
3412                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3413                                 break;
3414                         case DOWN_STREAM_DETAILED_HDMI:
3415                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3416                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3417                                 link->dpcd_caps.dongle_type =
3418                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3419
3420                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3421                                 if (ds_port.fields.DETAILED_CAPS) {
3422
3423                                         union dwnstream_port_caps_byte3_hdmi
3424                                                 hdmi_caps = {.raw = det_caps[3] };
3425                                         union dwnstream_port_caps_byte2
3426                                                 hdmi_color_caps = {.raw = det_caps[2] };
3427                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3428                                                 det_caps[1] * 2500;
3429
3430                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3431                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3432                                         /*YCBCR capability only for HDMI case*/
3433                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3434                                                         == DOWN_STREAM_DETAILED_HDMI) {
3435                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3436                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3437                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3438                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3439                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3440                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3441                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3442                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3443                                         }
3444
3445                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3446                                                 translate_dpcd_max_bpc(
3447                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3448
3449                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3450                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3451                                 }
3452
3453                                 break;
3454                         }
3455                 }
3456         }
3457
3458         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3459
3460         {
3461                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3462
3463                 core_link_read_dpcd(
3464                         link,
3465                         DP_BRANCH_REVISION_START,
3466                         (uint8_t *)&dp_hw_fw_revision,
3467                         sizeof(dp_hw_fw_revision));
3468
3469                 link->dpcd_caps.branch_hw_revision =
3470                         dp_hw_fw_revision.ieee_hw_rev;
3471
3472                 memmove(
3473                         link->dpcd_caps.branch_fw_revision,
3474                         dp_hw_fw_revision.ieee_fw_rev,
3475                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3476         }
3477 }
3478
3479 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3480                 int length)
3481 {
3482         int retry = 0;
3483
3484         if (!link->dpcd_caps.dpcd_rev.raw) {
3485                 do {
3486                         dp_receiver_power_ctrl(link, true);
3487                         core_link_read_dpcd(link, DP_DPCD_REV,
3488                                                         dpcd_data, length);
3489                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3490                                 DP_DPCD_REV -
3491                                 DP_DPCD_REV];
3492                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3493         }
3494
3495         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3496                 switch (link->dpcd_caps.branch_dev_id) {
3497                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3498                  * all internal circuits including AUX communication preventing
3499                  * reading DPCD table and EDID (spec violation).
3500                  * Encoder will skip DP RX power down on disable_output to
3501                  * keep receiver powered all the time.*/
3502                 case DP_BRANCH_DEVICE_ID_0010FA:
3503                 case DP_BRANCH_DEVICE_ID_0080E1:
3504                 case DP_BRANCH_DEVICE_ID_00E04C:
3505                         link->wa_flags.dp_keep_receiver_powered = true;
3506                         break;
3507
3508                 /* TODO: May need work around for other dongles. */
3509                 default:
3510                         link->wa_flags.dp_keep_receiver_powered = false;
3511                         break;
3512                 }
3513         } else
3514                 link->wa_flags.dp_keep_receiver_powered = false;
3515 }
3516
3517 /* Read additional sink caps defined in source specific DPCD area
3518  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3519  */
3520 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3521 {
3522         uint8_t dpcd_data;
3523
3524         if (!link)
3525                 return false;
3526
3527         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3528                 return false;
3529
3530         link->dpcd_sink_ext_caps.raw = dpcd_data;
3531         return true;
3532 }
3533
3534 static bool retrieve_link_cap(struct dc_link *link)
3535 {
3536         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3537          * which means size 16 will be good for both of those DPCD register block reads
3538          */
3539         uint8_t dpcd_data[16];
3540         uint8_t lttpr_dpcd_data[6];
3541
3542         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3543          */
3544         uint8_t dpcd_dprx_data = '\0';
3545         uint8_t dpcd_power_state = '\0';
3546
3547         struct dp_device_vendor_id sink_id;
3548         union down_stream_port_count down_strm_port_count;
3549         union edp_configuration_cap edp_config_cap;
3550         union dp_downstream_port_present ds_port = { 0 };
3551         enum dc_status status = DC_ERROR_UNEXPECTED;
3552         uint32_t read_dpcd_retry_cnt = 3;
3553         int i;
3554         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3555         bool is_lttpr_present = false;
3556         const uint32_t post_oui_delay = 30; // 30ms
3557         bool vbios_lttpr_enable = false;
3558         bool vbios_lttpr_interop = false;
3559         struct dc_bios *bios = link->dc->ctx->dc_bios;
3560
3561         memset(dpcd_data, '\0', sizeof(dpcd_data));
3562         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3563         memset(&down_strm_port_count,
3564                 '\0', sizeof(union down_stream_port_count));
3565         memset(&edp_config_cap, '\0',
3566                 sizeof(union edp_configuration_cap));
3567
3568         /* if extended timeout is supported in hardware,
3569          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3570          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3571          */
3572         dc_link_aux_try_to_configure_timeout(link->ddc,
3573                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3574
3575         status = core_link_read_dpcd(link, DP_SET_POWER,
3576                                 &dpcd_power_state, sizeof(dpcd_power_state));
3577
3578         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3579          * section 2.3.1.2, if AUX CH may be powered down due to
3580          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3581          * signal and may need up to 1 ms before being able to reply.
3582          */
3583         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3584                 udelay(1000);
3585
3586         dpcd_set_source_specific_data(link);
3587         /* Sink may need to configure internals based on vendor, so allow some
3588          * time before proceeding with possibly vendor specific transactions
3589          */
3590         msleep(post_oui_delay);
3591
3592         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3593                 status = core_link_read_dpcd(
3594                                 link,
3595                                 DP_DPCD_REV,
3596                                 dpcd_data,
3597                                 sizeof(dpcd_data));
3598                 if (status == DC_OK)
3599                         break;
3600         }
3601
3602         if (status != DC_OK) {
3603                 dm_error("%s: Read dpcd data failed.\n", __func__);
3604                 return false;
3605         }
3606
3607         /* Query BIOS to determine if LTTPR functionality is forced on by system */
3608         if (bios->funcs->get_lttpr_caps) {
3609                 enum bp_result bp_query_result;
3610                 uint8_t is_vbios_lttpr_enable = 0;
3611
3612                 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3613                 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3614         }
3615
3616         if (bios->funcs->get_lttpr_interop) {
3617                 enum bp_result bp_query_result;
3618                 uint8_t is_vbios_interop_enabled = 0;
3619
3620                 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3621                 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3622         }
3623
3624         /*
3625          * Logic to determine LTTPR mode
3626          */
3627         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3628         if (vbios_lttpr_enable && vbios_lttpr_interop)
3629                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3630         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3631                 if (link->dc->config.allow_lttpr_non_transparent_mode)
3632                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3633                 else
3634                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3635         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3636                 if (!link->dc->config.allow_lttpr_non_transparent_mode
3637                         || !link->dc->caps.extended_aux_timeout_support)
3638                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3639                 else
3640                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3641         }
3642
3643         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3644                 /* By reading LTTPR capability, RX assumes that we will enable
3645                  * LTTPR extended aux timeout if LTTPR is present.
3646                  */
3647                 status = core_link_read_dpcd(
3648                                 link,
3649                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3650                                 lttpr_dpcd_data,
3651                                 sizeof(lttpr_dpcd_data));
3652
3653                 link->dpcd_caps.lttpr_caps.revision.raw =
3654                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3655                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3656
3657                 link->dpcd_caps.lttpr_caps.max_link_rate =
3658                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3659                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3660
3661                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3662                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3663                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3664
3665                 link->dpcd_caps.lttpr_caps.max_lane_count =
3666                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3667                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3668
3669                 link->dpcd_caps.lttpr_caps.mode =
3670                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3671                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3672
3673                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3674                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3675                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3676
3677                 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3678                 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3679                                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff &&
3680                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3681                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3682                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3683                 if (is_lttpr_present)
3684                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3685                 else
3686                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3687         }
3688
3689         if (!is_lttpr_present)
3690                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3691
3692
3693         {
3694                 union training_aux_rd_interval aux_rd_interval;
3695
3696                 aux_rd_interval.raw =
3697                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3698
3699                 link->dpcd_caps.ext_receiver_cap_field_present =
3700                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3701
3702                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3703                         uint8_t ext_cap_data[16];
3704
3705                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3706                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3707                                 status = core_link_read_dpcd(
3708                                 link,
3709                                 DP_DP13_DPCD_REV,
3710                                 ext_cap_data,
3711                                 sizeof(ext_cap_data));
3712                                 if (status == DC_OK) {
3713                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3714                                         break;
3715                                 }
3716                         }
3717                         if (status != DC_OK)
3718                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3719                 }
3720         }
3721
3722         link->dpcd_caps.dpcd_rev.raw =
3723                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3724
3725         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3726                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3727                         status = core_link_read_dpcd(
3728                                         link,
3729                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3730                                         &dpcd_dprx_data,
3731                                         sizeof(dpcd_dprx_data));
3732                         if (status == DC_OK)
3733                                 break;
3734                 }
3735
3736                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3737
3738                 if (status != DC_OK)
3739                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3740         }
3741
3742         else {
3743                 link->dpcd_caps.dprx_feature.raw = 0;
3744         }
3745
3746
3747         /* Error condition checking...
3748          * It is impossible for Sink to report Max Lane Count = 0.
3749          * It is possible for Sink to report Max Link Rate = 0, if it is
3750          * an eDP device that is reporting specialized link rates in the
3751          * SUPPORTED_LINK_RATE table.
3752          */
3753         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3754                 return false;
3755
3756         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3757                                  DP_DPCD_REV];
3758
3759         read_dp_device_vendor_id(link);
3760
3761         get_active_converter_info(ds_port.byte, link);
3762
3763         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3764
3765         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3766                                  DP_DPCD_REV];
3767
3768         link->dpcd_caps.allow_invalid_MSA_timing_param =
3769                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3770
3771         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3772                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3773
3774         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3775                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3776
3777         link->reported_link_cap.lane_count =
3778                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3779         link->reported_link_cap.link_rate = dpcd_data[
3780                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3781         link->reported_link_cap.link_spread =
3782                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3783                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3784
3785         edp_config_cap.raw = dpcd_data[
3786                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3787         link->dpcd_caps.panel_mode_edp =
3788                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3789         link->dpcd_caps.dpcd_display_control_capable =
3790                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3791
3792         link->test_pattern_enabled = false;
3793         link->compliance_test_state.raw = 0;
3794
3795         /* read sink count */
3796         core_link_read_dpcd(link,
3797                         DP_SINK_COUNT,
3798                         &link->dpcd_caps.sink_count.raw,
3799                         sizeof(link->dpcd_caps.sink_count.raw));
3800
3801         /* read sink ieee oui */
3802         core_link_read_dpcd(link,
3803                         DP_SINK_OUI,
3804                         (uint8_t *)(&sink_id),
3805                         sizeof(sink_id));
3806
3807         link->dpcd_caps.sink_dev_id =
3808                         (sink_id.ieee_oui[0] << 16) +
3809                         (sink_id.ieee_oui[1] << 8) +
3810                         (sink_id.ieee_oui[2]);
3811
3812         memmove(
3813                 link->dpcd_caps.sink_dev_id_str,
3814                 sink_id.ieee_device_id,
3815                 sizeof(sink_id.ieee_device_id));
3816
3817         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3818         {
3819                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3820
3821                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3822                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3823                             sizeof(str_mbp_2017))) {
3824                         link->reported_link_cap.link_rate = 0x0c;
3825                 }
3826         }
3827
3828         core_link_read_dpcd(
3829                 link,
3830                 DP_SINK_HW_REVISION_START,
3831                 (uint8_t *)&dp_hw_fw_revision,
3832                 sizeof(dp_hw_fw_revision));
3833
3834         link->dpcd_caps.sink_hw_revision =
3835                 dp_hw_fw_revision.ieee_hw_rev;
3836
3837         memmove(
3838                 link->dpcd_caps.sink_fw_revision,
3839                 dp_hw_fw_revision.ieee_fw_rev,
3840                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3841
3842         memset(&link->dpcd_caps.dsc_caps, '\0',
3843                         sizeof(link->dpcd_caps.dsc_caps));
3844         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3845         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3846         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3847                 status = core_link_read_dpcd(
3848                                 link,
3849                                 DP_FEC_CAPABILITY,
3850                                 &link->dpcd_caps.fec_cap.raw,
3851                                 sizeof(link->dpcd_caps.fec_cap.raw));
3852                 status = core_link_read_dpcd(
3853                                 link,
3854                                 DP_DSC_SUPPORT,
3855                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3856                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3857                 status = core_link_read_dpcd(
3858                                 link,
3859                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3860                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3861                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3862         }
3863
3864         if (!dpcd_read_sink_ext_caps(link))
3865                 link->dpcd_sink_ext_caps.raw = 0;
3866
3867         /* Connectivity log: detection */
3868         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3869
3870         return true;
3871 }
3872
3873 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3874 {
3875         uint8_t dpcd_data[16];
3876         uint32_t read_dpcd_retry_cnt = 3;
3877         enum dc_status status = DC_ERROR_UNEXPECTED;
3878         union dp_downstream_port_present ds_port = { 0 };
3879         union down_stream_port_count down_strm_port_count;
3880         union edp_configuration_cap edp_config_cap;
3881
3882         int i;
3883
3884         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3885                 status = core_link_read_dpcd(
3886                                 link,
3887                                 DP_DPCD_REV,
3888                                 dpcd_data,
3889                                 sizeof(dpcd_data));
3890                 if (status == DC_OK)
3891                         break;
3892         }
3893
3894         link->dpcd_caps.dpcd_rev.raw =
3895                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3896
3897         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3898                 return false;
3899
3900         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3901                         DP_DPCD_REV];
3902
3903         get_active_converter_info(ds_port.byte, link);
3904
3905         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3906                         DP_DPCD_REV];
3907
3908         link->dpcd_caps.allow_invalid_MSA_timing_param =
3909                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3910
3911         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3912                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3913
3914         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3915                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3916
3917         link->reported_link_cap.lane_count =
3918                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3919         link->reported_link_cap.link_rate = dpcd_data[
3920                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3921         link->reported_link_cap.link_spread =
3922                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3923                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3924
3925         edp_config_cap.raw = dpcd_data[
3926                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3927         link->dpcd_caps.panel_mode_edp =
3928                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3929         link->dpcd_caps.dpcd_display_control_capable =
3930                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3931
3932         return true;
3933 }
3934
3935 bool detect_dp_sink_caps(struct dc_link *link)
3936 {
3937         return retrieve_link_cap(link);
3938
3939         /* dc init_hw has power encoder using default
3940          * signal for connector. For native DP, no
3941          * need to power up encoder again. If not native
3942          * DP, hw_init may need check signal or power up
3943          * encoder here.
3944          */
3945         /* TODO save sink caps in link->sink */
3946 }
3947
3948 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3949 {
3950         enum dc_link_rate link_rate;
3951         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3952         switch (link_rate_in_khz) {
3953         case 1620000:
3954                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
3955                 break;
3956         case 2160000:
3957                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
3958                 break;
3959         case 2430000:
3960                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
3961                 break;
3962         case 2700000:
3963                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
3964                 break;
3965         case 3240000:
3966                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
3967                 break;
3968         case 4320000:
3969                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
3970                 break;
3971         case 5400000:
3972                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
3973                 break;
3974         case 8100000:
3975                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
3976                 break;
3977         default:
3978                 link_rate = LINK_RATE_UNKNOWN;
3979                 break;
3980         }
3981         return link_rate;
3982 }
3983
3984 void detect_edp_sink_caps(struct dc_link *link)
3985 {
3986         uint8_t supported_link_rates[16];
3987         uint32_t entry;
3988         uint32_t link_rate_in_khz;
3989         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
3990         uint8_t backlight_adj_cap;
3991
3992         retrieve_link_cap(link);
3993         link->dpcd_caps.edp_supported_link_rates_count = 0;
3994         memset(supported_link_rates, 0, sizeof(supported_link_rates));
3995
3996         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
3997                         (link->dc->debug.optimize_edp_link_rate ||
3998                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
3999                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4000                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4001                                                         supported_link_rates, sizeof(supported_link_rates));
4002
4003                 for (entry = 0; entry < 16; entry += 2) {
4004                         // DPCD register reports per-lane link rate = 16-bit link rate capability
4005                         // value X 200 kHz. Need multiplier to find link rate in kHz.
4006                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4007                                                                                 supported_link_rates[entry]) * 200;
4008
4009                         if (link_rate_in_khz != 0) {
4010                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4011                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4012                                 link->dpcd_caps.edp_supported_link_rates_count++;
4013
4014                                 if (link->reported_link_cap.link_rate < link_rate)
4015                                         link->reported_link_cap.link_rate = link_rate;
4016                         }
4017                 }
4018         }
4019         link->verified_link_cap = link->reported_link_cap;
4020
4021         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4022                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
4023
4024         link->dpcd_caps.dynamic_backlight_capable_edp =
4025                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4026
4027         dc_link_set_default_brightness_aux(link);
4028 }
4029
4030 void dc_link_dp_enable_hpd(const struct dc_link *link)
4031 {
4032         struct link_encoder *encoder = link->link_enc;
4033
4034         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4035                 encoder->funcs->enable_hpd(encoder);
4036 }
4037
4038 void dc_link_dp_disable_hpd(const struct dc_link *link)
4039 {
4040         struct link_encoder *encoder = link->link_enc;
4041
4042         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4043                 encoder->funcs->disable_hpd(encoder);
4044 }
4045
4046 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4047 {
4048         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4049                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4050                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4051                 return true;
4052         else
4053                 return false;
4054 }
4055
4056 static void set_crtc_test_pattern(struct dc_link *link,
4057                                 struct pipe_ctx *pipe_ctx,
4058                                 enum dp_test_pattern test_pattern,
4059                                 enum dp_test_pattern_color_space test_pattern_color_space)
4060 {
4061         enum controller_dp_test_pattern controller_test_pattern;
4062         enum dc_color_depth color_depth = pipe_ctx->
4063                 stream->timing.display_color_depth;
4064         struct bit_depth_reduction_params params;
4065         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4066         int width = pipe_ctx->stream->timing.h_addressable +
4067                 pipe_ctx->stream->timing.h_border_left +
4068                 pipe_ctx->stream->timing.h_border_right;
4069         int height = pipe_ctx->stream->timing.v_addressable +
4070                 pipe_ctx->stream->timing.v_border_bottom +
4071                 pipe_ctx->stream->timing.v_border_top;
4072
4073         memset(&params, 0, sizeof(params));
4074
4075         switch (test_pattern) {
4076         case DP_TEST_PATTERN_COLOR_SQUARES:
4077                 controller_test_pattern =
4078                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4079         break;
4080         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4081                 controller_test_pattern =
4082                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4083         break;
4084         case DP_TEST_PATTERN_VERTICAL_BARS:
4085                 controller_test_pattern =
4086                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4087         break;
4088         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4089                 controller_test_pattern =
4090                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4091         break;
4092         case DP_TEST_PATTERN_COLOR_RAMP:
4093                 controller_test_pattern =
4094                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4095         break;
4096         default:
4097                 controller_test_pattern =
4098                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4099         break;
4100         }
4101
4102         switch (test_pattern) {
4103         case DP_TEST_PATTERN_COLOR_SQUARES:
4104         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4105         case DP_TEST_PATTERN_VERTICAL_BARS:
4106         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4107         case DP_TEST_PATTERN_COLOR_RAMP:
4108         {
4109                 /* disable bit depth reduction */
4110                 pipe_ctx->stream->bit_depth_params = params;
4111                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4112                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4113                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4114                                 controller_test_pattern, color_depth);
4115                 else if (link->dc->hwss.set_disp_pattern_generator) {
4116                         struct pipe_ctx *odm_pipe;
4117                         enum controller_dp_color_space controller_color_space;
4118                         int opp_cnt = 1;
4119                         int offset = 0;
4120                         int dpg_width = width;
4121
4122                         switch (test_pattern_color_space) {
4123                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4124                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4125                                 break;
4126                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4127                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4128                                 break;
4129                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4130                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4131                                 break;
4132                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4133                         default:
4134                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4135                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4136                                 ASSERT(0);
4137                                 break;
4138                         }
4139
4140                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4141                                 opp_cnt++;
4142                         dpg_width = width / opp_cnt;
4143                         offset = dpg_width;
4144
4145                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4146                                         pipe_ctx,
4147                                         controller_test_pattern,
4148                                         controller_color_space,
4149                                         color_depth,
4150                                         NULL,
4151                                         dpg_width,
4152                                         height,
4153                                         0);
4154
4155                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4156                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4157
4158                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4159                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4160                                                 odm_pipe,
4161                                                 controller_test_pattern,
4162                                                 controller_color_space,
4163                                                 color_depth,
4164                                                 NULL,
4165                                                 dpg_width,
4166                                                 height,
4167                                                 offset);
4168                                 offset += offset;
4169                         }
4170                 }
4171         }
4172         break;
4173         case DP_TEST_PATTERN_VIDEO_MODE:
4174         {
4175                 /* restore bitdepth reduction */
4176                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4177                 pipe_ctx->stream->bit_depth_params = params;
4178                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4179                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4180                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4181                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4182                                 color_depth);
4183                 else if (link->dc->hwss.set_disp_pattern_generator) {
4184                         struct pipe_ctx *odm_pipe;
4185                         int opp_cnt = 1;
4186                         int dpg_width = width;
4187
4188                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4189                                 opp_cnt++;
4190
4191                         dpg_width = width / opp_cnt;
4192                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4193                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4194
4195                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4196                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4197                                                 odm_pipe,
4198                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4199                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4200                                                 color_depth,
4201                                                 NULL,
4202                                                 dpg_width,
4203                                                 height,
4204                                                 0);
4205                         }
4206                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4207                                         pipe_ctx,
4208                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4209                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4210                                         color_depth,
4211                                         NULL,
4212                                         dpg_width,
4213                                         height,
4214                                         0);
4215                 }
4216         }
4217         break;
4218
4219         default:
4220         break;
4221         }
4222 }
4223
4224 bool dc_link_dp_set_test_pattern(
4225         struct dc_link *link,
4226         enum dp_test_pattern test_pattern,
4227         enum dp_test_pattern_color_space test_pattern_color_space,
4228         const struct link_training_settings *p_link_settings,
4229         const unsigned char *p_custom_pattern,
4230         unsigned int cust_pattern_size)
4231 {
4232         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4233         struct pipe_ctx *pipe_ctx = NULL;
4234         unsigned int lane;
4235         unsigned int i;
4236         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4237         union dpcd_training_pattern training_pattern;
4238         enum dpcd_phy_test_patterns pattern;
4239
4240         memset(&training_pattern, 0, sizeof(training_pattern));
4241
4242         for (i = 0; i < MAX_PIPES; i++) {
4243                 if (pipes[i].stream == NULL)
4244                         continue;
4245
4246                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4247                         pipe_ctx = &pipes[i];
4248                         break;
4249                 }
4250         }
4251
4252         if (pipe_ctx == NULL)
4253                 return false;
4254
4255         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4256         if (link->test_pattern_enabled && test_pattern ==
4257                         DP_TEST_PATTERN_VIDEO_MODE) {
4258                 /* Set CRTC Test Pattern */
4259                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4260                 dp_set_hw_test_pattern(link, test_pattern,
4261                                 (uint8_t *)p_custom_pattern,
4262                                 (uint32_t)cust_pattern_size);
4263
4264                 /* Unblank Stream */
4265                 link->dc->hwss.unblank_stream(
4266                         pipe_ctx,
4267                         &link->verified_link_cap);
4268                 /* TODO:m_pHwss->MuteAudioEndpoint
4269                  * (pPathMode->pDisplayPath, false);
4270                  */
4271
4272                 /* Reset Test Pattern state */
4273                 link->test_pattern_enabled = false;
4274
4275                 return true;
4276         }
4277
4278         /* Check for PHY Test Patterns */
4279         if (is_dp_phy_pattern(test_pattern)) {
4280                 /* Set DPCD Lane Settings before running test pattern */
4281                 if (p_link_settings != NULL) {
4282                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4283                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4284                 }
4285
4286                 /* Blank stream if running test pattern */
4287                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4288                         /*TODO:
4289                          * m_pHwss->
4290                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4291                          */
4292                         /* Blank stream */
4293                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4294                 }
4295
4296                 dp_set_hw_test_pattern(link, test_pattern,
4297                                 (uint8_t *)p_custom_pattern,
4298                                 (uint32_t)cust_pattern_size);
4299
4300                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4301                         /* Set Test Pattern state */
4302                         link->test_pattern_enabled = true;
4303                         if (p_link_settings != NULL)
4304                                 dpcd_set_link_settings(link,
4305                                                 p_link_settings);
4306                 }
4307
4308                 switch (test_pattern) {
4309                 case DP_TEST_PATTERN_VIDEO_MODE:
4310                         pattern = PHY_TEST_PATTERN_NONE;
4311                         break;
4312                 case DP_TEST_PATTERN_D102:
4313                         pattern = PHY_TEST_PATTERN_D10_2;
4314                         break;
4315                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4316                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4317                         break;
4318                 case DP_TEST_PATTERN_PRBS7:
4319                         pattern = PHY_TEST_PATTERN_PRBS7;
4320                         break;
4321                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4322                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4323                         break;
4324                 case DP_TEST_PATTERN_CP2520_1:
4325                         pattern = PHY_TEST_PATTERN_CP2520_1;
4326                         break;
4327                 case DP_TEST_PATTERN_CP2520_2:
4328                         pattern = PHY_TEST_PATTERN_CP2520_2;
4329                         break;
4330                 case DP_TEST_PATTERN_CP2520_3:
4331                         pattern = PHY_TEST_PATTERN_CP2520_3;
4332                         break;
4333                 default:
4334                         return false;
4335                 }
4336
4337                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4338                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4339                         return false;
4340
4341                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4342                         /* tell receiver that we are sending qualification
4343                          * pattern DP 1.2 or later - DP receiver's link quality
4344                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4345                          * register (0x10B~0x10E)\
4346                          */
4347                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4348                                 link_qual_pattern[lane] =
4349                                                 (unsigned char)(pattern);
4350
4351                         core_link_write_dpcd(link,
4352                                         DP_LINK_QUAL_LANE0_SET,
4353                                         link_qual_pattern,
4354                                         sizeof(link_qual_pattern));
4355                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4356                            link->dpcd_caps.dpcd_rev.raw == 0) {
4357                         /* tell receiver that we are sending qualification
4358                          * pattern DP 1.1a or earlier - DP receiver's link
4359                          * quality pattern is set using
4360                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4361                          * register (0x102). We will use v_1.3 when we are
4362                          * setting test pattern for DP 1.1.
4363                          */
4364                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4365                                             &training_pattern.raw,
4366                                             sizeof(training_pattern));
4367                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4368                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4369                                              &training_pattern.raw,
4370                                              sizeof(training_pattern));
4371                 }
4372         } else {
4373                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4374
4375                 switch (test_pattern_color_space) {
4376                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4377                         color_space = COLOR_SPACE_SRGB;
4378                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4379                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4380                         break;
4381
4382                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4383                         color_space = COLOR_SPACE_YCBCR601;
4384                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4385                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4386                         break;
4387                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4388                         color_space = COLOR_SPACE_YCBCR709;
4389                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4390                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4391                         break;
4392                 default:
4393                         break;
4394                 }
4395
4396                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4397                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4398                                 union dmub_hw_lock_flags hw_locks = { 0 };
4399                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4400
4401                                 hw_locks.bits.lock_dig = 1;
4402                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4403
4404                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4405                                                         true,
4406                                                         &hw_locks,
4407                                                         &inst_flags);
4408                         } else
4409                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4410                                                 pipe_ctx->stream_res.tg);
4411                 }
4412
4413                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4414                 /* update MSA to requested color space */
4415                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4416                                 &pipe_ctx->stream->timing,
4417                                 color_space,
4418                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4419                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4420
4421                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4422                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4423                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4424                         else
4425                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4426                         resource_build_info_frame(pipe_ctx);
4427                         link->dc->hwss.update_info_frame(pipe_ctx);
4428                 }
4429
4430                 /* CRTC Patterns */
4431                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4432                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4433                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4434                                 CRTC_STATE_VACTIVE);
4435                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4436                                 CRTC_STATE_VBLANK);
4437                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4438                                 CRTC_STATE_VACTIVE);
4439
4440                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4441                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4442                                 union dmub_hw_lock_flags hw_locks = { 0 };
4443                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4444
4445                                 hw_locks.bits.lock_dig = 1;
4446                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4447
4448                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4449                                                         false,
4450                                                         &hw_locks,
4451                                                         &inst_flags);
4452                         } else
4453                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4454                                                 pipe_ctx->stream_res.tg);
4455                 }
4456
4457                 /* Set Test Pattern state */
4458                 link->test_pattern_enabled = true;
4459         }
4460
4461         return true;
4462 }
4463
4464 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4465 {
4466         unsigned char mstmCntl;
4467
4468         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4469         if (enable)
4470                 mstmCntl |= DP_MST_EN;
4471         else
4472                 mstmCntl &= (~DP_MST_EN);
4473
4474         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4475 }
4476
4477 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4478 {
4479         union dpcd_edp_config edp_config_set;
4480         bool panel_mode_edp = false;
4481
4482         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4483
4484         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4485
4486                 switch (panel_mode) {
4487                 case DP_PANEL_MODE_EDP:
4488                 case DP_PANEL_MODE_SPECIAL:
4489                         panel_mode_edp = true;
4490                         break;
4491
4492                 default:
4493                                 break;
4494                 }
4495
4496                 /*set edp panel mode in receiver*/
4497                 core_link_read_dpcd(
4498                         link,
4499                         DP_EDP_CONFIGURATION_SET,
4500                         &edp_config_set.raw,
4501                         sizeof(edp_config_set.raw));
4502
4503                 if (edp_config_set.bits.PANEL_MODE_EDP
4504                         != panel_mode_edp) {
4505                         enum dc_status result;
4506
4507                         edp_config_set.bits.PANEL_MODE_EDP =
4508                         panel_mode_edp;
4509                         result = core_link_write_dpcd(
4510                                 link,
4511                                 DP_EDP_CONFIGURATION_SET,
4512                                 &edp_config_set.raw,
4513                                 sizeof(edp_config_set.raw));
4514
4515                         ASSERT(result == DC_OK);
4516                 }
4517         }
4518         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4519                  "eDP panel mode enabled: %d \n",
4520                  link->link_index,
4521                  link->dpcd_caps.panel_mode_edp,
4522                  panel_mode_edp);
4523 }
4524
4525 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4526 {
4527         /* We need to explicitly check that connector
4528          * is not DP. Some Travis_VGA get reported
4529          * by video bios as DP.
4530          */
4531         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4532
4533                 switch (link->dpcd_caps.branch_dev_id) {
4534                 case DP_BRANCH_DEVICE_ID_0022B9:
4535                         /* alternate scrambler reset is required for Travis
4536                          * for the case when external chip does not
4537                          * provide sink device id, alternate scrambler
4538                          * scheme will  be overriden later by querying
4539                          * Encoder features
4540                          */
4541                         if (strncmp(
4542                                 link->dpcd_caps.branch_dev_name,
4543                                 DP_VGA_LVDS_CONVERTER_ID_2,
4544                                 sizeof(
4545                                 link->dpcd_caps.
4546                                 branch_dev_name)) == 0) {
4547                                         return DP_PANEL_MODE_SPECIAL;
4548                         }
4549                         break;
4550                 case DP_BRANCH_DEVICE_ID_00001A:
4551                         /* alternate scrambler reset is required for Travis
4552                          * for the case when external chip does not provide
4553                          * sink device id, alternate scrambler scheme will
4554                          * be overriden later by querying Encoder feature
4555                          */
4556                         if (strncmp(link->dpcd_caps.branch_dev_name,
4557                                 DP_VGA_LVDS_CONVERTER_ID_3,
4558                                 sizeof(
4559                                 link->dpcd_caps.
4560                                 branch_dev_name)) == 0) {
4561                                         return DP_PANEL_MODE_SPECIAL;
4562                         }
4563                         break;
4564                 default:
4565                         break;
4566                 }
4567         }
4568
4569         if (link->dpcd_caps.panel_mode_edp) {
4570                 return DP_PANEL_MODE_EDP;
4571         }
4572
4573         return DP_PANEL_MODE_DEFAULT;
4574 }
4575
4576 void dp_set_fec_ready(struct dc_link *link, bool ready)
4577 {
4578         /* FEC has to be "set ready" before the link training.
4579          * The policy is to always train with FEC
4580          * if the sink supports it and leave it enabled on link.
4581          * If FEC is not supported, disable it.
4582          */
4583         struct link_encoder *link_enc = link->link_enc;
4584         uint8_t fec_config = 0;
4585
4586         if (!dc_link_should_enable_fec(link))
4587                 return;
4588
4589         if (link_enc->funcs->fec_set_ready &&
4590                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4591                 if (ready) {
4592                         fec_config = 1;
4593                         if (core_link_write_dpcd(link,
4594                                         DP_FEC_CONFIGURATION,
4595                                         &fec_config,
4596                                         sizeof(fec_config)) == DC_OK) {
4597                                 link_enc->funcs->fec_set_ready(link_enc, true);
4598                                 link->fec_state = dc_link_fec_ready;
4599                         } else {
4600                                 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4601                                 link->fec_state = dc_link_fec_not_ready;
4602                                 dm_error("dpcd write failed to set fec_ready");
4603                         }
4604                 } else if (link->fec_state == dc_link_fec_ready) {
4605                         fec_config = 0;
4606                         core_link_write_dpcd(link,
4607                                         DP_FEC_CONFIGURATION,
4608                                         &fec_config,
4609                                         sizeof(fec_config));
4610                         link->link_enc->funcs->fec_set_ready(
4611                                         link->link_enc, false);
4612                         link->fec_state = dc_link_fec_not_ready;
4613                 }
4614         }
4615 }
4616
4617 void dp_set_fec_enable(struct dc_link *link, bool enable)
4618 {
4619         struct link_encoder *link_enc = link->link_enc;
4620
4621         if (!dc_link_should_enable_fec(link))
4622                 return;
4623
4624         if (link_enc->funcs->fec_set_enable &&
4625                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4626                 if (link->fec_state == dc_link_fec_ready && enable) {
4627                         /* Accord to DP spec, FEC enable sequence can first
4628                          * be transmitted anytime after 1000 LL codes have
4629                          * been transmitted on the link after link training
4630                          * completion. Using 1 lane RBR should have the maximum
4631                          * time for transmitting 1000 LL codes which is 6.173 us.
4632                          * So use 7 microseconds delay instead.
4633                          */
4634                         udelay(7);
4635                         link_enc->funcs->fec_set_enable(link_enc, true);
4636                         link->fec_state = dc_link_fec_enabled;
4637                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4638                         link_enc->funcs->fec_set_enable(link_enc, false);
4639                         link->fec_state = dc_link_fec_ready;
4640                 }
4641         }
4642 }
4643
4644 void dpcd_set_source_specific_data(struct dc_link *link)
4645 {
4646         if (!link->dc->vendor_signature.is_valid) {
4647                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4648                 struct dpcd_amd_signature amd_signature = {0};
4649                 struct dpcd_amd_device_id amd_device_id = {0};
4650
4651                 amd_device_id.device_id_byte1 =
4652                                 (uint8_t)(link->ctx->asic_id.chip_id);
4653                 amd_device_id.device_id_byte2 =
4654                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4655                 amd_device_id.dce_version =
4656                                 (uint8_t)(link->ctx->dce_version);
4657                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4658                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4659
4660                 core_link_read_dpcd(link, DP_SOURCE_OUI,
4661                                 (uint8_t *)(&amd_signature),
4662                                 sizeof(amd_signature));
4663
4664                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4665                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4666                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4667
4668                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4669                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4670                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4671
4672                         core_link_write_dpcd(link, DP_SOURCE_OUI,
4673                                 (uint8_t *)(&amd_signature),
4674                                 sizeof(amd_signature));
4675                 }
4676
4677                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4678                                 (uint8_t *)(&amd_device_id),
4679                                 sizeof(amd_device_id));
4680
4681                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4682                         link->dc->caps.min_horizontal_blanking_period != 0) {
4683
4684                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4685
4686                         result_write_min_hblank = core_link_write_dpcd(link,
4687                                 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4688                                 sizeof(hblank_size));
4689                 }
4690                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4691                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4692                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4693                                                         result_write_min_hblank,
4694                                                         link->link_index,
4695                                                         link->ctx->dce_version,
4696                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4697                                                         link->dc->caps.min_horizontal_blanking_period,
4698                                                         link->dpcd_caps.branch_dev_id,
4699                                                         link->dpcd_caps.branch_dev_name[0],
4700                                                         link->dpcd_caps.branch_dev_name[1],
4701                                                         link->dpcd_caps.branch_dev_name[2],
4702                                                         link->dpcd_caps.branch_dev_name[3],
4703                                                         link->dpcd_caps.branch_dev_name[4],
4704                                                         link->dpcd_caps.branch_dev_name[5]);
4705         } else {
4706                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4707                                 link->dc->vendor_signature.data.raw,
4708                                 sizeof(link->dc->vendor_signature.data.raw));
4709         }
4710 }
4711
4712 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4713                 bool isHDR,
4714                 uint32_t backlight_millinits,
4715                 uint32_t transition_time_in_ms)
4716 {
4717         struct dpcd_source_backlight_set dpcd_backlight_set;
4718         uint8_t backlight_control = isHDR ? 1 : 0;
4719
4720         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4721                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4722                 return false;
4723
4724         // OLEDs have no PWM, they can only use AUX
4725         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4726                 backlight_control = 1;
4727
4728         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4729         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4730
4731
4732         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4733                         (uint8_t *)(&dpcd_backlight_set),
4734                         sizeof(dpcd_backlight_set)) != DC_OK)
4735                 return false;
4736
4737         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4738                         &backlight_control, 1) != DC_OK)
4739                 return false;
4740
4741         return true;
4742 }
4743
4744 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4745                 uint32_t *backlight_millinits_avg,
4746                 uint32_t *backlight_millinits_peak)
4747 {
4748         union dpcd_source_backlight_get dpcd_backlight_get;
4749
4750         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4751
4752         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4753                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4754                 return false;
4755
4756         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4757                         dpcd_backlight_get.raw,
4758                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4759                 return false;
4760
4761         *backlight_millinits_avg =
4762                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4763         *backlight_millinits_peak =
4764                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4765
4766         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4767         if (*backlight_millinits_avg == 0 ||
4768                         *backlight_millinits_avg > *backlight_millinits_peak)
4769                 return false;
4770
4771         return true;
4772 }
4773
4774 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4775 {
4776         uint8_t backlight_enable = enable ? 1 : 0;
4777
4778         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4779                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4780                 return false;
4781
4782         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4783                 &backlight_enable, 1) != DC_OK)
4784                 return false;
4785
4786         return true;
4787 }
4788
4789 // we read default from 0x320 because we expect BIOS wrote it there
4790 // regular get_backlight_nit reads from panel set at 0x326
4791 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4792 {
4793         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4794                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4795                 return false;
4796
4797         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4798                 (uint8_t *) backlight_millinits,
4799                 sizeof(uint32_t)) != DC_OK)
4800                 return false;
4801
4802         return true;
4803 }
4804
4805 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4806 {
4807         uint32_t default_backlight;
4808
4809         if (link &&
4810                 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4811                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4812                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4813                         default_backlight = 150000;
4814                 // if < 5 nits or > 5000, it might be wrong readback
4815                 if (default_backlight < 5000 || default_backlight > 5000000)
4816                         default_backlight = 150000; //
4817
4818                 return dc_link_set_backlight_level_nits(link, true,
4819                                 default_backlight, 0);
4820         }
4821         return false;
4822 }
4823
4824 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4825 {
4826         struct dc_link_settings link_setting;
4827         uint8_t link_bw_set;
4828         uint8_t link_rate_set;
4829         uint32_t req_bw;
4830         union lane_count_set lane_count_set = { {0} };
4831
4832         ASSERT(link || crtc_timing); // invalid input
4833
4834         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4835                         !link->dc->debug.optimize_edp_link_rate)
4836                 return false;
4837
4838
4839         // Read DPCD 00100h to find if standard link rates are set
4840         core_link_read_dpcd(link, DP_LINK_BW_SET,
4841                                 &link_bw_set, sizeof(link_bw_set));
4842
4843         if (link_bw_set) {
4844                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4845                 return true;
4846         }
4847
4848         // Read DPCD 00115h to find the edp link rate set used
4849         core_link_read_dpcd(link, DP_LINK_RATE_SET,
4850                             &link_rate_set, sizeof(link_rate_set));
4851
4852         // Read DPCD 00101h to find out the number of lanes currently set
4853         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4854                                 &lane_count_set.raw, sizeof(lane_count_set));
4855
4856         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4857
4858         decide_edp_link_settings(link, &link_setting, req_bw);
4859
4860         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4861                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4862                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4863                 return true;
4864         }
4865
4866         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4867         return false;
4868 }
4869
4870