drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/version.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include "dm_services.h"
  29 #include "amdgpu.h"
  30 #include "amdgpu_dm.h"
  31 #include "amdgpu_dm_mst_types.h"
  32
  33 #include "dc.h"
  34 #include "dm_helpers.h"
  35
  36 #include "dc_link_ddc.h"
  37
  38 #include "i2caux_interface.h"
  39
  40 /* #define TRACE_DPCD */
  41
  42 #ifdef TRACE_DPCD
  43 #define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
  44
  45 static inline char *side_band_msg_type_to_str(uint32_t address)
  46 {
  47         static char str[10] = {0};
  48
  49         if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
  50                 strcpy(str, "DOWN_REQ");
  51         else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
  52                 strcpy(str, "UP_REP");
  53         else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
  54                 strcpy(str, "DOWN_REP");
  55         else
  56                 strcpy(str, "UP_REQ");
  57
  58         return str;
  59 }
  60
  61 static void log_dpcd(uint8_t type,
  62                      uint32_t address,
  63                      uint8_t *data,
  64                      uint32_t size,
  65                      bool res)
  66 {
  67         DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
  68                         (type == DP_AUX_NATIVE_READ) ||
  69                         (type == DP_AUX_I2C_READ) ?
  70                                         "Read" : "Write",
  71                         address,
  72                         SIDE_BAND_MSG(address) ?
  73                                         side_band_msg_type_to_str(address) : "Nop",
  74                         res ? "OK" : "Fail");
  75
  76         if (res) {
  77                 print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
  78         }
  79 }
  80 #endif
  81
  82 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  83                                   struct drm_dp_aux_msg *msg)
  84 {
  85         ssize_t result = 0;
  86         struct aux_payload payload;
  87         enum aux_channel_operation_result operation_result;
  88
  89         if (WARN_ON(msg->size > 16))
  90                 return -E2BIG;
  91
  92         payload.address = msg->address;
  93         payload.data = msg->buffer;
  94         payload.length = msg->size;
  95         payload.reply = &msg->reply;
  96         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
  97         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
  98         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
  99         payload.defer_delay = 0;
 100
 101         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
 102                                       &operation_result);
 103
 104         if (payload.write)
 105                 result = msg->size;
 106
 107         if (result < 0)
 108                 switch (operation_result) {
 109                 case AUX_CHANNEL_OPERATION_SUCCEEDED:
 110                         break;
 111                 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
 112                 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
 113                         result = -EIO;
 114                         break;
 115                 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
 116                 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
 117                         result = -EBUSY;
 118                         break;
 119                 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
 120                         result = -ETIMEDOUT;
 121                         break;
 122                 }
 123
 124         return result;
 125 }
 126
 127 static void
 128 dm_dp_mst_connector_destroy(struct drm_connector *connector)
 129 {
 130         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
 131         struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
 132
 133         kfree(amdgpu_dm_connector->edid);
 134         amdgpu_dm_connector->edid = NULL;
 135
 136         drm_encoder_cleanup(&amdgpu_encoder->base);
 137         kfree(amdgpu_encoder);
 138         drm_connector_cleanup(connector);
 139         drm_dp_mst_put_port_malloc(amdgpu_dm_connector->port);
 140         kfree(amdgpu_dm_connector);
 141 }
 142
 143 static int
 144 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 145 {
 146         struct amdgpu_dm_connector *amdgpu_dm_connector =
 147                 to_amdgpu_dm_connector(connector);
 148         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 149
 150         return drm_dp_mst_connector_late_register(connector, port);
 151 }
 152
 153 static void
 154 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 155 {
 156         struct amdgpu_dm_connector *amdgpu_dm_connector =
 157                 to_amdgpu_dm_connector(connector);
 158         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 159
 160         drm_dp_mst_connector_early_unregister(connector, port);
 161 }
 162
 163 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 164         .fill_modes = drm_helper_probe_single_connector_modes,
 165         .destroy = dm_dp_mst_connector_destroy,
 166         .reset = amdgpu_dm_connector_funcs_reset,
 167         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 168         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 169         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 170         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 171         .late_register = amdgpu_dm_mst_connector_late_register,
 172         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 173 };
 174
 175 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 176 {
 177         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 178         int ret = 0;
 179
 180         if (!aconnector)
 181                 return drm_add_edid_modes(connector, NULL);
 182
 183         if (!aconnector->edid) {
 184                 struct edid *edid;
 185                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 186
 187                 if (!edid) {
 188                         drm_connector_update_edid_property(
 189                                 &aconnector->base,
 190                                 NULL);
 191                         return ret;
 192                 }
 193
 194                 aconnector->edid = edid;
 195         }
 196
 197         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 198                 dc_sink_release(aconnector->dc_sink);
 199                 aconnector->dc_sink = NULL;
 200         }
 201
 202         if (!aconnector->dc_sink) {
 203                 struct dc_sink *dc_sink;
 204                 struct dc_sink_init_data init_params = {
 205                                 .link = aconnector->dc_link,
 206                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 207                 dc_sink = dc_link_add_remote_sink(
 208                         aconnector->dc_link,
 209                         (uint8_t *)aconnector->edid,
 210                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 211                         &init_params);
 212
 213                 dc_sink->priv = aconnector;
 214                 /* dc_link_add_remote_sink returns a new reference */
 215                 aconnector->dc_sink = dc_sink;
 216
 217                 if (aconnector->dc_sink)
 218                         amdgpu_dm_update_freesync_caps(
 219                                         connector, aconnector->edid);
 220
 221         }
 222
 223         drm_connector_update_edid_property(
 224                                         &aconnector->base, aconnector->edid);
 225
 226         ret = drm_add_edid_modes(connector, aconnector->edid);
 227
 228         return ret;
 229 }
 230
 231 static struct drm_encoder *
 232 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 233                            struct drm_connector_state *connector_state)
 234 {
 235         return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
 236 }
 237
 238 static int
 239 dm_dp_mst_detect(struct drm_connector *connector,
 240                  struct drm_modeset_acquire_ctx *ctx, bool force)
 241 {
 242         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 243         struct amdgpu_dm_connector *master = aconnector->mst_port;
 244
 245         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 246                                       aconnector->port);
 247 }
 248
 249 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 250         .get_modes = dm_dp_mst_get_modes,
 251         .mode_valid = amdgpu_dm_connector_mode_valid,
 252         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 253         .detect_ctx = dm_dp_mst_detect,
 254 };
 255
 256 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 257 {
 258         drm_encoder_cleanup(encoder);
 259         kfree(encoder);
 260 }
 261
 262 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 263         .destroy = amdgpu_dm_encoder_destroy,
 264 };
 265
 266 static struct amdgpu_encoder *
 267 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
 268 {
 269         struct drm_device *dev = connector->base.dev;
 270         struct amdgpu_device *adev = dev->dev_private;
 271         struct amdgpu_encoder *amdgpu_encoder;
 272         struct drm_encoder *encoder;
 273
 274         amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
 275         if (!amdgpu_encoder)
 276                 return NULL;
 277
 278         encoder = &amdgpu_encoder->base;
 279         encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 280
 281         drm_encoder_init(
 282                 dev,
 283                 &amdgpu_encoder->base,
 284                 &amdgpu_dm_encoder_funcs,
 285                 DRM_MODE_ENCODER_DPMST,
 286                 NULL);
 287
 288         drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 289
 290         return amdgpu_encoder;
 291 }
 292
 293 static struct drm_connector *
 294 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 295                         struct drm_dp_mst_port *port,
 296                         const char *pathprop)
 297 {
 298         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 299         struct drm_device *dev = master->base.dev;
 300         struct amdgpu_device *adev = dev->dev_private;
 301         struct amdgpu_dm_connector *aconnector;
 302         struct drm_connector *connector;
 303
 304         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 305         if (!aconnector)
 306                 return NULL;
 307
 308         connector = &aconnector->base;
 309         aconnector->port = port;
 310         aconnector->mst_port = master;
 311
 312         if (drm_connector_init(
 313                 dev,
 314                 connector,
 315                 &dm_dp_mst_connector_funcs,
 316                 DRM_MODE_CONNECTOR_DisplayPort)) {
 317                 kfree(aconnector);
 318                 return NULL;
 319         }
 320         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 321
 322         amdgpu_dm_connector_init_helper(
 323                 &adev->dm,
 324                 aconnector,
 325                 DRM_MODE_CONNECTOR_DisplayPort,
 326                 master->dc_link,
 327                 master->connector_id);
 328
 329         aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
 330         drm_connector_attach_encoder(&aconnector->base,
 331                                      &aconnector->mst_encoder->base);
 332
 333         drm_object_attach_property(
 334                 &connector->base,
 335                 dev->mode_config.path_property,
 336                 0);
 337         drm_object_attach_property(
 338                 &connector->base,
 339                 dev->mode_config.tile_property,
 340                 0);
 341
 342         drm_connector_set_path_property(connector, pathprop);
 343
 344         /*
 345          * Initialize connector state before adding the connectror to drm and
 346          * framebuffer lists
 347          */
 348         amdgpu_dm_connector_funcs_reset(connector);
 349
 350         DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
 351                  aconnector, connector->base.id, aconnector->mst_port);
 352
 353         drm_dp_mst_get_port_malloc(port);
 354
 355         DRM_DEBUG_KMS(":%d\n", connector->base.id);
 356
 357         return connector;
 358 }
 359
 360 static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 361                                         struct drm_connector *connector)
 362 {
 363         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 364         struct drm_device *dev = master->base.dev;
 365         struct amdgpu_device *adev = dev->dev_private;
 366         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 367
 368         DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
 369                  aconnector, connector->base.id, aconnector->mst_port);
 370
 371         if (aconnector->dc_sink) {
 372                 amdgpu_dm_update_freesync_caps(connector, NULL);
 373                 dc_link_remove_remote_sink(aconnector->dc_link,
 374                                            aconnector->dc_sink);
 375                 dc_sink_release(aconnector->dc_sink);
 376                 aconnector->dc_sink = NULL;
 377         }
 378
 379         drm_connector_unregister(connector);
 380         if (adev->mode_info.rfbdev)
 381                 drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector);
 382         drm_connector_put(connector);
 383 }
 384
 385 static void dm_dp_mst_register_connector(struct drm_connector *connector)
 386 {
 387         struct drm_device *dev = connector->dev;
 388         struct amdgpu_device *adev = dev->dev_private;
 389
 390         if (adev->mode_info.rfbdev)
 391                 drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
 392         else
 393                 DRM_ERROR("adev->mode_info.rfbdev is NULL\n");
 394
 395         drm_connector_register(connector);
 396 }
 397
 398 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 399         .add_connector = dm_dp_add_mst_connector,
 400         .destroy_connector = dm_dp_destroy_mst_connector,
 401         .register_connector = dm_dp_mst_register_connector
 402 };
 403
 404 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 405                                        struct amdgpu_dm_connector *aconnector)
 406 {
 407         aconnector->dm_dp_aux.aux.name = "dmdc";
 408         aconnector->dm_dp_aux.aux.dev = aconnector->base.kdev;
 409         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 410         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 411
 412         drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
 413         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 414                                       &aconnector->base);
 415
 416         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 417                 return;
 418
 419         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 420         drm_dp_mst_topology_mgr_init(
 421                 &aconnector->mst_mgr,
 422                 dm->adev->ddev,
 423                 &aconnector->dm_dp_aux.aux,
 424                 16,
 425                 4,
 426                 aconnector->connector_id);
 427 }
 428