drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drm_fourcc.h>
  25 #include <drm/drm_modeset_helper.h>
  26 #include <drm/drm_modeset_helper_vtables.h>
  27 #include <drm/drm_vblank.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_i2c.h"
  32 #include "cikd.h"
  33 #include "atom.h"
  34 #include "amdgpu_atombios.h"
  35 #include "atombios_crtc.h"
  36 #include "atombios_encoders.h"
  37 #include "amdgpu_pll.h"
  38 #include "amdgpu_connectors.h"
  39 #include "amdgpu_display.h"
  40 #include "dce_v8_0.h"
  41
  42 #include "dce/dce_8_0_d.h"
  43 #include "dce/dce_8_0_sh_mask.h"
  44
  45 #include "gca/gfx_7_2_enum.h"
  46
  47 #include "gmc/gmc_7_1_d.h"
  48 #include "gmc/gmc_7_1_sh_mask.h"
  49
  50 #include "oss/oss_2_0_d.h"
  51 #include "oss/oss_2_0_sh_mask.h"
  52
  53 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
  54 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  55
  56 static const u32 crtc_offsets[6] =
  57 {
  58         CRTC0_REGISTER_OFFSET,
  59         CRTC1_REGISTER_OFFSET,
  60         CRTC2_REGISTER_OFFSET,
  61         CRTC3_REGISTER_OFFSET,
  62         CRTC4_REGISTER_OFFSET,
  63         CRTC5_REGISTER_OFFSET
  64 };
  65
  66 static const u32 hpd_offsets[] =
  67 {
  68         HPD0_REGISTER_OFFSET,
  69         HPD1_REGISTER_OFFSET,
  70         HPD2_REGISTER_OFFSET,
  71         HPD3_REGISTER_OFFSET,
  72         HPD4_REGISTER_OFFSET,
  73         HPD5_REGISTER_OFFSET
  74 };
  75
  76 static const uint32_t dig_offsets[] = {
  77         CRTC0_REGISTER_OFFSET,
  78         CRTC1_REGISTER_OFFSET,
  79         CRTC2_REGISTER_OFFSET,
  80         CRTC3_REGISTER_OFFSET,
  81         CRTC4_REGISTER_OFFSET,
  82         CRTC5_REGISTER_OFFSET,
  83         (0x13830 - 0x7030) >> 2,
  84 };
  85
  86 static const struct {
  87         uint32_t        reg;
  88         uint32_t        vblank;
  89         uint32_t        vline;
  90         uint32_t        hpd;
  91
  92 } interrupt_status_offsets[6] = { {
  93         .reg = mmDISP_INTERRUPT_STATUS,
  94         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  95         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  96         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  97 }, {
  98         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  99         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
 100         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
 101         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
 102 }, {
 103         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
 104         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
 105         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 106         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 107 }, {
 108         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 109         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 110         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 111         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 112 }, {
 113         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 114         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 115         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 116         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 117 }, {
 118         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 119         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 120         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 121         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 122 } };
 123
 124 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
 125                                      u32 block_offset, u32 reg)
 126 {
 127         unsigned long flags;
 128         u32 r;
 129
 130         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 131         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 132         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 133         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 134
 135         return r;
 136 }
 137
 138 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
 139                                       u32 block_offset, u32 reg, u32 v)
 140 {
 141         unsigned long flags;
 142
 143         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 144         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 145         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 146         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 147 }
 148
 149 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 150 {
 151         if (crtc >= adev->mode_info.num_crtc)
 152                 return 0;
 153         else
 154                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 155 }
 156
 157 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 158 {
 159         unsigned i;
 160
 161         /* Enable pflip interrupts */
 162         for (i = 0; i < adev->mode_info.num_crtc; i++)
 163                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 164 }
 165
 166 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 167 {
 168         unsigned i;
 169
 170         /* Disable pflip interrupts */
 171         for (i = 0; i < adev->mode_info.num_crtc; i++)
 172                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 173 }
 174
 175 /**
 176  * dce_v8_0_page_flip - pageflip callback.
 177  *
 178  * @adev: amdgpu_device pointer
 179  * @crtc_id: crtc to cleanup pageflip on
 180  * @crtc_base: new address of the crtc (GPU MC address)
 181  * @async: asynchronous flip
 182  *
 183  * Triggers the actual pageflip by updating the primary
 184  * surface base address.
 185  */
 186 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
 187                                int crtc_id, u64 crtc_base, bool async)
 188 {
 189         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 190         struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
 191
 192         /* flip at hsync for async, default is vsync */
 193         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
 194                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
 195         /* update pitch */
 196         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
 197                fb->pitches[0] / fb->format->cpp[0]);
 198         /* update the primary scanout addresses */
 199         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 200                upper_32_bits(crtc_base));
 201         /* writing to the low address triggers the update */
 202         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 203                lower_32_bits(crtc_base));
 204         /* post the write */
 205         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 206 }
 207
 208 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 209                                         u32 *vbl, u32 *position)
 210 {
 211         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 212                 return -EINVAL;
 213
 214         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 215         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 216
 217         return 0;
 218 }
 219
 220 /**
 221  * dce_v8_0_hpd_sense - hpd sense callback.
 222  *
 223  * @adev: amdgpu_device pointer
 224  * @hpd: hpd (hotplug detect) pin
 225  *
 226  * Checks if a digital monitor is connected (evergreen+).
 227  * Returns true if connected, false if not connected.
 228  */
 229 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
 230                                enum amdgpu_hpd_id hpd)
 231 {
 232         bool connected = false;
 233
 234         if (hpd >= adev->mode_info.num_hpd)
 235                 return connected;
 236
 237         if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
 238             DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 239                 connected = true;
 240
 241         return connected;
 242 }
 243
 244 /**
 245  * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
 246  *
 247  * @adev: amdgpu_device pointer
 248  * @hpd: hpd (hotplug detect) pin
 249  *
 250  * Set the polarity of the hpd pin (evergreen+).
 251  */
 252 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
 253                                       enum amdgpu_hpd_id hpd)
 254 {
 255         u32 tmp;
 256         bool connected = dce_v8_0_hpd_sense(adev, hpd);
 257
 258         if (hpd >= adev->mode_info.num_hpd)
 259                 return;
 260
 261         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
 262         if (connected)
 263                 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 264         else
 265                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 266         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
 267 }
 268
 269 /**
 270  * dce_v8_0_hpd_init - hpd setup callback.
 271  *
 272  * @adev: amdgpu_device pointer
 273  *
 274  * Setup the hpd pins used by the card (evergreen+).
 275  * Enable the pin, set the polarity, and enable the hpd interrupts.
 276  */
 277 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
 278 {
 279         struct drm_device *dev = adev_to_drm(adev);
 280         struct drm_connector *connector;
 281         struct drm_connector_list_iter iter;
 282         u32 tmp;
 283
 284         drm_connector_list_iter_begin(dev, &iter);
 285         drm_for_each_connector_iter(connector, &iter) {
 286                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 287
 288                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 289                         continue;
 290
 291                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 292                 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 293                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 294
 295                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 296                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 297                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 298                          * aux dp channel on imac and help (but not completely fix)
 299                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 300                          * also avoid interrupt storms during dpms.
 301                          */
 302                         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 303                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
 304                         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 305                         continue;
 306                 }
 307
 308                 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 309                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 310         }
 311         drm_connector_list_iter_end(&iter);
 312 }
 313
 314 /**
 315  * dce_v8_0_hpd_fini - hpd tear down callback.
 316  *
 317  * @adev: amdgpu_device pointer
 318  *
 319  * Tear down the hpd pins used by the card (evergreen+).
 320  * Disable the hpd interrupts.
 321  */
 322 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 323 {
 324         struct drm_device *dev = adev_to_drm(adev);
 325         struct drm_connector *connector;
 326         struct drm_connector_list_iter iter;
 327         u32 tmp;
 328
 329         drm_connector_list_iter_begin(dev, &iter);
 330         drm_for_each_connector_iter(connector, &iter) {
 331                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 332
 333                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 334                         continue;
 335
 336                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 337                 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 338                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 339
 340                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 341         }
 342         drm_connector_list_iter_end(&iter);
 343 }
 344
 345 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 346 {
 347         return mmDC_GPIO_HPD_A;
 348 }
 349
 350 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
 351 {
 352         u32 crtc_hung = 0;
 353         u32 crtc_status[6];
 354         u32 i, j, tmp;
 355
 356         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 357                 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
 358                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 359                         crtc_hung |= (1 << i);
 360                 }
 361         }
 362
 363         for (j = 0; j < 10; j++) {
 364                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 365                         if (crtc_hung & (1 << i)) {
 366                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 367                                 if (tmp != crtc_status[i])
 368                                         crtc_hung &= ~(1 << i);
 369                         }
 370                 }
 371                 if (crtc_hung == 0)
 372                         return false;
 373                 udelay(100);
 374         }
 375
 376         return true;
 377 }
 378
 379 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
 380                                           bool render)
 381 {
 382         u32 tmp;
 383
 384         /* Lockout access through VGA aperture*/
 385         tmp = RREG32(mmVGA_HDP_CONTROL);
 386         if (render)
 387                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 388         else
 389                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 390         WREG32(mmVGA_HDP_CONTROL, tmp);
 391
 392         /* disable VGA render */
 393         tmp = RREG32(mmVGA_RENDER_CONTROL);
 394         if (render)
 395                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 396         else
 397                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 398         WREG32(mmVGA_RENDER_CONTROL, tmp);
 399 }
 400
 401 static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
 402 {
 403         int num_crtc = 0;
 404
 405         switch (adev->asic_type) {
 406         case CHIP_BONAIRE:
 407         case CHIP_HAWAII:
 408                 num_crtc = 6;
 409                 break;
 410         case CHIP_KAVERI:
 411                 num_crtc = 4;
 412                 break;
 413         case CHIP_KABINI:
 414         case CHIP_MULLINS:
 415                 num_crtc = 2;
 416                 break;
 417         default:
 418                 num_crtc = 0;
 419         }
 420         return num_crtc;
 421 }
 422
 423 void dce_v8_0_disable_dce(struct amdgpu_device *adev)
 424 {
 425         /*Disable VGA render and enabled crtc, if has DCE engine*/
 426         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 427                 u32 tmp;
 428                 int crtc_enabled, i;
 429
 430                 dce_v8_0_set_vga_render_state(adev, false);
 431
 432                 /*Disable crtc*/
 433                 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) {
 434                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 435                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 436                         if (crtc_enabled) {
 437                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 438                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 439                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 440                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 441                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 442                         }
 443                 }
 444         }
 445 }
 446
 447 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
 448 {
 449         struct drm_device *dev = encoder->dev;
 450         struct amdgpu_device *adev = drm_to_adev(dev);
 451         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 452         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 453         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 454         int bpc = 0;
 455         u32 tmp = 0;
 456         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 457
 458         if (connector) {
 459                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 460                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 461                 dither = amdgpu_connector->dither;
 462         }
 463
 464         /* LVDS/eDP FMT is set up by atom */
 465         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 466                 return;
 467
 468         /* not needed for analog */
 469         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 470             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 471                 return;
 472
 473         if (bpc == 0)
 474                 return;
 475
 476         switch (bpc) {
 477         case 6:
 478                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 479                         /* XXX sort out optimal dither settings */
 480                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 481                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 482                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 483                                 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 484                 else
 485                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 486                         (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 487                 break;
 488         case 8:
 489                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 490                         /* XXX sort out optimal dither settings */
 491                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 492                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 493                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 494                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 495                                 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 496                 else
 497                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 498                         (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 499                 break;
 500         case 10:
 501                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 502                         /* XXX sort out optimal dither settings */
 503                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 504                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 505                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 506                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 507                                 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 508                 else
 509                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 510                         (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 511                 break;
 512         default:
 513                 /* not needed */
 514                 break;
 515         }
 516
 517         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 518 }
 519
 520
 521 /* display watermark setup */
 522 /**
 523  * dce_v8_0_line_buffer_adjust - Set up the line buffer
 524  *
 525  * @adev: amdgpu_device pointer
 526  * @amdgpu_crtc: the selected display controller
 527  * @mode: the current display mode on the selected display
 528  * controller
 529  *
 530  * Setup up the line buffer allocation for
 531  * the selected display controller (CIK).
 532  * Returns the line buffer size in pixels.
 533  */
 534 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
 535                                        struct amdgpu_crtc *amdgpu_crtc,
 536                                        struct drm_display_mode *mode)
 537 {
 538         u32 tmp, buffer_alloc, i;
 539         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
 540         /*
 541          * Line Buffer Setup
 542          * There are 6 line buffers, one for each display controllers.
 543          * There are 3 partitions per LB. Select the number of partitions
 544          * to enable based on the display width.  For display widths larger
 545          * than 4096, you need use to use 2 display controllers and combine
 546          * them using the stereo blender.
 547          */
 548         if (amdgpu_crtc->base.enabled && mode) {
 549                 if (mode->crtc_hdisplay < 1920) {
 550                         tmp = 1;
 551                         buffer_alloc = 2;
 552                 } else if (mode->crtc_hdisplay < 2560) {
 553                         tmp = 2;
 554                         buffer_alloc = 2;
 555                 } else if (mode->crtc_hdisplay < 4096) {
 556                         tmp = 0;
 557                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 558                 } else {
 559                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 560                         tmp = 0;
 561                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 562                 }
 563         } else {
 564                 tmp = 1;
 565                 buffer_alloc = 0;
 566         }
 567
 568         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
 569               (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
 570               (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
 571
 572         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
 573                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
 574         for (i = 0; i < adev->usec_timeout; i++) {
 575                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
 576                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
 577                         break;
 578                 udelay(1);
 579         }
 580
 581         if (amdgpu_crtc->base.enabled && mode) {
 582                 switch (tmp) {
 583                 case 0:
 584                 default:
 585                         return 4096 * 2;
 586                 case 1:
 587                         return 1920 * 2;
 588                 case 2:
 589                         return 2560 * 2;
 590                 }
 591         }
 592
 593         /* controller not enabled, so no lb used */
 594         return 0;
 595 }
 596
 597 /**
 598  * cik_get_number_of_dram_channels - get the number of dram channels
 599  *
 600  * @adev: amdgpu_device pointer
 601  *
 602  * Look up the number of video ram channels (CIK).
 603  * Used for display watermark bandwidth calculations
 604  * Returns the number of dram channels
 605  */
 606 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 607 {
 608         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 609
 610         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 611         case 0:
 612         default:
 613                 return 1;
 614         case 1:
 615                 return 2;
 616         case 2:
 617                 return 4;
 618         case 3:
 619                 return 8;
 620         case 4:
 621                 return 3;
 622         case 5:
 623                 return 6;
 624         case 6:
 625                 return 10;
 626         case 7:
 627                 return 12;
 628         case 8:
 629                 return 16;
 630         }
 631 }
 632
 633 struct dce8_wm_params {
 634         u32 dram_channels; /* number of dram channels */
 635         u32 yclk;          /* bandwidth per dram data pin in kHz */
 636         u32 sclk;          /* engine clock in kHz */
 637         u32 disp_clk;      /* display clock in kHz */
 638         u32 src_width;     /* viewport width */
 639         u32 active_time;   /* active display time in ns */
 640         u32 blank_time;    /* blank time in ns */
 641         bool interlaced;    /* mode is interlaced */
 642         fixed20_12 vsc;    /* vertical scale ratio */
 643         u32 num_heads;     /* number of active crtcs */
 644         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 645         u32 lb_size;       /* line buffer allocated to pipe */
 646         u32 vtaps;         /* vertical scaler taps */
 647 };
 648
 649 /**
 650  * dce_v8_0_dram_bandwidth - get the dram bandwidth
 651  *
 652  * @wm: watermark calculation data
 653  *
 654  * Calculate the raw dram bandwidth (CIK).
 655  * Used for display watermark bandwidth calculations
 656  * Returns the dram bandwidth in MBytes/s
 657  */
 658 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
 659 {
 660         /* Calculate raw DRAM Bandwidth */
 661         fixed20_12 dram_efficiency; /* 0.7 */
 662         fixed20_12 yclk, dram_channels, bandwidth;
 663         fixed20_12 a;
 664
 665         a.full = dfixed_const(1000);
 666         yclk.full = dfixed_const(wm->yclk);
 667         yclk.full = dfixed_div(yclk, a);
 668         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 669         a.full = dfixed_const(10);
 670         dram_efficiency.full = dfixed_const(7);
 671         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 672         bandwidth.full = dfixed_mul(dram_channels, yclk);
 673         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 674
 675         return dfixed_trunc(bandwidth);
 676 }
 677
 678 /**
 679  * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
 680  *
 681  * @wm: watermark calculation data
 682  *
 683  * Calculate the dram bandwidth used for display (CIK).
 684  * Used for display watermark bandwidth calculations
 685  * Returns the dram bandwidth for display in MBytes/s
 686  */
 687 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 688 {
 689         /* Calculate DRAM Bandwidth and the part allocated to display. */
 690         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 691         fixed20_12 yclk, dram_channels, bandwidth;
 692         fixed20_12 a;
 693
 694         a.full = dfixed_const(1000);
 695         yclk.full = dfixed_const(wm->yclk);
 696         yclk.full = dfixed_div(yclk, a);
 697         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 698         a.full = dfixed_const(10);
 699         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 700         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 701         bandwidth.full = dfixed_mul(dram_channels, yclk);
 702         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 703
 704         return dfixed_trunc(bandwidth);
 705 }
 706
 707 /**
 708  * dce_v8_0_data_return_bandwidth - get the data return bandwidth
 709  *
 710  * @wm: watermark calculation data
 711  *
 712  * Calculate the data return bandwidth used for display (CIK).
 713  * Used for display watermark bandwidth calculations
 714  * Returns the data return bandwidth in MBytes/s
 715  */
 716 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
 717 {
 718         /* Calculate the display Data return Bandwidth */
 719         fixed20_12 return_efficiency; /* 0.8 */
 720         fixed20_12 sclk, bandwidth;
 721         fixed20_12 a;
 722
 723         a.full = dfixed_const(1000);
 724         sclk.full = dfixed_const(wm->sclk);
 725         sclk.full = dfixed_div(sclk, a);
 726         a.full = dfixed_const(10);
 727         return_efficiency.full = dfixed_const(8);
 728         return_efficiency.full = dfixed_div(return_efficiency, a);
 729         a.full = dfixed_const(32);
 730         bandwidth.full = dfixed_mul(a, sclk);
 731         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 732
 733         return dfixed_trunc(bandwidth);
 734 }
 735
 736 /**
 737  * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
 738  *
 739  * @wm: watermark calculation data
 740  *
 741  * Calculate the dmif bandwidth used for display (CIK).
 742  * Used for display watermark bandwidth calculations
 743  * Returns the dmif bandwidth in MBytes/s
 744  */
 745 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
 746 {
 747         /* Calculate the DMIF Request Bandwidth */
 748         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 749         fixed20_12 disp_clk, bandwidth;
 750         fixed20_12 a, b;
 751
 752         a.full = dfixed_const(1000);
 753         disp_clk.full = dfixed_const(wm->disp_clk);
 754         disp_clk.full = dfixed_div(disp_clk, a);
 755         a.full = dfixed_const(32);
 756         b.full = dfixed_mul(a, disp_clk);
 757
 758         a.full = dfixed_const(10);
 759         disp_clk_request_efficiency.full = dfixed_const(8);
 760         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 761
 762         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 763
 764         return dfixed_trunc(bandwidth);
 765 }
 766
 767 /**
 768  * dce_v8_0_available_bandwidth - get the min available bandwidth
 769  *
 770  * @wm: watermark calculation data
 771  *
 772  * Calculate the min available bandwidth used for display (CIK).
 773  * Used for display watermark bandwidth calculations
 774  * Returns the min available bandwidth in MBytes/s
 775  */
 776 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
 777 {
 778         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 779         u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
 780         u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
 781         u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
 782
 783         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 784 }
 785
 786 /**
 787  * dce_v8_0_average_bandwidth - get the average available bandwidth
 788  *
 789  * @wm: watermark calculation data
 790  *
 791  * Calculate the average available bandwidth used for display (CIK).
 792  * Used for display watermark bandwidth calculations
 793  * Returns the average available bandwidth in MBytes/s
 794  */
 795 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
 796 {
 797         /* Calculate the display mode Average Bandwidth
 798          * DisplayMode should contain the source and destination dimensions,
 799          * timing, etc.
 800          */
 801         fixed20_12 bpp;
 802         fixed20_12 line_time;
 803         fixed20_12 src_width;
 804         fixed20_12 bandwidth;
 805         fixed20_12 a;
 806
 807         a.full = dfixed_const(1000);
 808         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 809         line_time.full = dfixed_div(line_time, a);
 810         bpp.full = dfixed_const(wm->bytes_per_pixel);
 811         src_width.full = dfixed_const(wm->src_width);
 812         bandwidth.full = dfixed_mul(src_width, bpp);
 813         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 814         bandwidth.full = dfixed_div(bandwidth, line_time);
 815
 816         return dfixed_trunc(bandwidth);
 817 }
 818
 819 /**
 820  * dce_v8_0_latency_watermark - get the latency watermark
 821  *
 822  * @wm: watermark calculation data
 823  *
 824  * Calculate the latency watermark (CIK).
 825  * Used for display watermark bandwidth calculations
 826  * Returns the latency watermark in ns
 827  */
 828 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
 829 {
 830         /* First calculate the latency in ns */
 831         u32 mc_latency = 2000; /* 2000 ns. */
 832         u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
 833         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 834         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 835         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 836         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 837                 (wm->num_heads * cursor_line_pair_return_time);
 838         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 839         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 840         u32 tmp, dmif_size = 12288;
 841         fixed20_12 a, b, c;
 842
 843         if (wm->num_heads == 0)
 844                 return 0;
 845
 846         a.full = dfixed_const(2);
 847         b.full = dfixed_const(1);
 848         if ((wm->vsc.full > a.full) ||
 849             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 850             (wm->vtaps >= 5) ||
 851             ((wm->vsc.full >= a.full) && wm->interlaced))
 852                 max_src_lines_per_dst_line = 4;
 853         else
 854                 max_src_lines_per_dst_line = 2;
 855
 856         a.full = dfixed_const(available_bandwidth);
 857         b.full = dfixed_const(wm->num_heads);
 858         a.full = dfixed_div(a, b);
 859         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 860         tmp = min(dfixed_trunc(a), tmp);
 861
 862         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 863
 864         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 865         b.full = dfixed_const(1000);
 866         c.full = dfixed_const(lb_fill_bw);
 867         b.full = dfixed_div(c, b);
 868         a.full = dfixed_div(a, b);
 869         line_fill_time = dfixed_trunc(a);
 870
 871         if (line_fill_time < wm->active_time)
 872                 return latency;
 873         else
 874                 return latency + (line_fill_time - wm->active_time);
 875
 876 }
 877
 878 /**
 879  * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 880  * average and available dram bandwidth
 881  *
 882  * @wm: watermark calculation data
 883  *
 884  * Check if the display average bandwidth fits in the display
 885  * dram bandwidth (CIK).
 886  * Used for display watermark bandwidth calculations
 887  * Returns true if the display fits, false if not.
 888  */
 889 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 890 {
 891         if (dce_v8_0_average_bandwidth(wm) <=
 892             (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 893                 return true;
 894         else
 895                 return false;
 896 }
 897
 898 /**
 899  * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
 900  * average and available bandwidth
 901  *
 902  * @wm: watermark calculation data
 903  *
 904  * Check if the display average bandwidth fits in the display
 905  * available bandwidth (CIK).
 906  * Used for display watermark bandwidth calculations
 907  * Returns true if the display fits, false if not.
 908  */
 909 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
 910 {
 911         if (dce_v8_0_average_bandwidth(wm) <=
 912             (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
 913                 return true;
 914         else
 915                 return false;
 916 }
 917
 918 /**
 919  * dce_v8_0_check_latency_hiding - check latency hiding
 920  *
 921  * @wm: watermark calculation data
 922  *
 923  * Check latency hiding (CIK).
 924  * Used for display watermark bandwidth calculations
 925  * Returns true if the display fits, false if not.
 926  */
 927 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
 928 {
 929         u32 lb_partitions = wm->lb_size / wm->src_width;
 930         u32 line_time = wm->active_time + wm->blank_time;
 931         u32 latency_tolerant_lines;
 932         u32 latency_hiding;
 933         fixed20_12 a;
 934
 935         a.full = dfixed_const(1);
 936         if (wm->vsc.full > a.full)
 937                 latency_tolerant_lines = 1;
 938         else {
 939                 if (lb_partitions <= (wm->vtaps + 1))
 940                         latency_tolerant_lines = 1;
 941                 else
 942                         latency_tolerant_lines = 2;
 943         }
 944
 945         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 946
 947         if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
 948                 return true;
 949         else
 950                 return false;
 951 }
 952
 953 /**
 954  * dce_v8_0_program_watermarks - program display watermarks
 955  *
 956  * @adev: amdgpu_device pointer
 957  * @amdgpu_crtc: the selected display controller
 958  * @lb_size: line buffer size
 959  * @num_heads: number of display controllers in use
 960  *
 961  * Calculate and program the display watermarks for the
 962  * selected display controller (CIK).
 963  */
 964 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
 965                                         struct amdgpu_crtc *amdgpu_crtc,
 966                                         u32 lb_size, u32 num_heads)
 967 {
 968         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 969         struct dce8_wm_params wm_low, wm_high;
 970         u32 active_time;
 971         u32 line_time = 0;
 972         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 973         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
 974
 975         if (amdgpu_crtc->base.enabled && num_heads && mode) {
 976                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
 977                                             (u32)mode->clock);
 978                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
 979                                           (u32)mode->clock);
 980                 line_time = min(line_time, (u32)65535);
 981
 982                 /* watermark for high clocks */
 983                 if (adev->pm.dpm_enabled) {
 984                         wm_high.yclk =
 985                                 amdgpu_dpm_get_mclk(adev, false) * 10;
 986                         wm_high.sclk =
 987                                 amdgpu_dpm_get_sclk(adev, false) * 10;
 988                 } else {
 989                         wm_high.yclk = adev->pm.current_mclk * 10;
 990                         wm_high.sclk = adev->pm.current_sclk * 10;
 991                 }
 992
 993                 wm_high.disp_clk = mode->clock;
 994                 wm_high.src_width = mode->crtc_hdisplay;
 995                 wm_high.active_time = active_time;
 996                 wm_high.blank_time = line_time - wm_high.active_time;
 997                 wm_high.interlaced = false;
 998                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 999                         wm_high.interlaced = true;
1000                 wm_high.vsc = amdgpu_crtc->vsc;
1001                 wm_high.vtaps = 1;
1002                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1003                         wm_high.vtaps = 2;
1004                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1005                 wm_high.lb_size = lb_size;
1006                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1007                 wm_high.num_heads = num_heads;
1008
1009                 /* set for high clocks */
1010                 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1011
1012                 /* possibly force display priority to high */
1013                 /* should really do this at mode validation time... */
1014                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1015                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1016                     !dce_v8_0_check_latency_hiding(&wm_high) ||
1017                     (adev->mode_info.disp_priority == 2)) {
1018                         DRM_DEBUG_KMS("force priority to high\n");
1019                 }
1020
1021                 /* watermark for low clocks */
1022                 if (adev->pm.dpm_enabled) {
1023                         wm_low.yclk =
1024                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1025                         wm_low.sclk =
1026                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1027                 } else {
1028                         wm_low.yclk = adev->pm.current_mclk * 10;
1029                         wm_low.sclk = adev->pm.current_sclk * 10;
1030                 }
1031
1032                 wm_low.disp_clk = mode->clock;
1033                 wm_low.src_width = mode->crtc_hdisplay;
1034                 wm_low.active_time = active_time;
1035                 wm_low.blank_time = line_time - wm_low.active_time;
1036                 wm_low.interlaced = false;
1037                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1038                         wm_low.interlaced = true;
1039                 wm_low.vsc = amdgpu_crtc->vsc;
1040                 wm_low.vtaps = 1;
1041                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1042                         wm_low.vtaps = 2;
1043                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1044                 wm_low.lb_size = lb_size;
1045                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1046                 wm_low.num_heads = num_heads;
1047
1048                 /* set for low clocks */
1049                 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1050
1051                 /* possibly force display priority to high */
1052                 /* should really do this at mode validation time... */
1053                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1054                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1055                     !dce_v8_0_check_latency_hiding(&wm_low) ||
1056                     (adev->mode_info.disp_priority == 2)) {
1057                         DRM_DEBUG_KMS("force priority to high\n");
1058                 }
1059                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1060         }
1061
1062         /* select wm A */
1063         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1064         tmp = wm_mask;
1065         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1066         tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1067         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1068         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1069                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1070                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1071         /* select wm B */
1072         tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1073         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1074         tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1075         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1076         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1077                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1078                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1079         /* restore original selection */
1080         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1081
1082         /* save values for DPM */
1083         amdgpu_crtc->line_time = line_time;
1084         amdgpu_crtc->wm_high = latency_watermark_a;
1085         amdgpu_crtc->wm_low = latency_watermark_b;
1086         /* Save number of lines the linebuffer leads before the scanout */
1087         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1088 }
1089
1090 /**
1091  * dce_v8_0_bandwidth_update - program display watermarks
1092  *
1093  * @adev: amdgpu_device pointer
1094  *
1095  * Calculate and program the display watermarks and line
1096  * buffer allocation (CIK).
1097  */
1098 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1099 {
1100         struct drm_display_mode *mode = NULL;
1101         u32 num_heads = 0, lb_size;
1102         int i;
1103
1104         amdgpu_display_update_priority(adev);
1105
1106         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1107                 if (adev->mode_info.crtcs[i]->base.enabled)
1108                         num_heads++;
1109         }
1110         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1111                 mode = &adev->mode_info.crtcs[i]->base.mode;
1112                 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1113                 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1114                                             lb_size, num_heads);
1115         }
1116 }
1117
1118 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1119 {
1120         int i;
1121         u32 offset, tmp;
1122
1123         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1124                 offset = adev->mode_info.audio.pin[i].offset;
1125                 tmp = RREG32_AUDIO_ENDPT(offset,
1126                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1127                 if (((tmp &
1128                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1129                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1130                         adev->mode_info.audio.pin[i].connected = false;
1131                 else
1132                         adev->mode_info.audio.pin[i].connected = true;
1133         }
1134 }
1135
1136 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1137 {
1138         int i;
1139
1140         dce_v8_0_audio_get_connected_pins(adev);
1141
1142         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1143                 if (adev->mode_info.audio.pin[i].connected)
1144                         return &adev->mode_info.audio.pin[i];
1145         }
1146         DRM_ERROR("No connected audio pins found!\n");
1147         return NULL;
1148 }
1149
1150 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1151 {
1152         struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1153         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1154         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1155         u32 offset;
1156
1157         if (!dig || !dig->afmt || !dig->afmt->pin)
1158                 return;
1159
1160         offset = dig->afmt->offset;
1161
1162         WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1163                (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1164 }
1165
1166 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1167                                                 struct drm_display_mode *mode)
1168 {
1169         struct drm_device *dev = encoder->dev;
1170         struct amdgpu_device *adev = drm_to_adev(dev);
1171         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1172         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1173         struct drm_connector *connector;
1174         struct drm_connector_list_iter iter;
1175         struct amdgpu_connector *amdgpu_connector = NULL;
1176         u32 tmp = 0, offset;
1177
1178         if (!dig || !dig->afmt || !dig->afmt->pin)
1179                 return;
1180
1181         offset = dig->afmt->pin->offset;
1182
1183         drm_connector_list_iter_begin(dev, &iter);
1184         drm_for_each_connector_iter(connector, &iter) {
1185                 if (connector->encoder == encoder) {
1186                         amdgpu_connector = to_amdgpu_connector(connector);
1187                         break;
1188                 }
1189         }
1190         drm_connector_list_iter_end(&iter);
1191
1192         if (!amdgpu_connector) {
1193                 DRM_ERROR("Couldn't find encoder's connector\n");
1194                 return;
1195         }
1196
1197         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1198                 if (connector->latency_present[1])
1199                         tmp =
1200                         (connector->video_latency[1] <<
1201                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1202                         (connector->audio_latency[1] <<
1203                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1204                 else
1205                         tmp =
1206                         (0 <<
1207                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1208                         (0 <<
1209                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1210         } else {
1211                 if (connector->latency_present[0])
1212                         tmp =
1213                         (connector->video_latency[0] <<
1214                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1215                         (connector->audio_latency[0] <<
1216                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1217                 else
1218                         tmp =
1219                         (0 <<
1220                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1221                         (0 <<
1222                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1223
1224         }
1225         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1226 }
1227
1228 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1229 {
1230         struct drm_device *dev = encoder->dev;
1231         struct amdgpu_device *adev = drm_to_adev(dev);
1232         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1233         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1234         struct drm_connector *connector;
1235         struct drm_connector_list_iter iter;
1236         struct amdgpu_connector *amdgpu_connector = NULL;
1237         u32 offset, tmp;
1238         u8 *sadb = NULL;
1239         int sad_count;
1240
1241         if (!dig || !dig->afmt || !dig->afmt->pin)
1242                 return;
1243
1244         offset = dig->afmt->pin->offset;
1245
1246         drm_connector_list_iter_begin(dev, &iter);
1247         drm_for_each_connector_iter(connector, &iter) {
1248                 if (connector->encoder == encoder) {
1249                         amdgpu_connector = to_amdgpu_connector(connector);
1250                         break;
1251                 }
1252         }
1253         drm_connector_list_iter_end(&iter);
1254
1255         if (!amdgpu_connector) {
1256                 DRM_ERROR("Couldn't find encoder's connector\n");
1257                 return;
1258         }
1259
1260         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1261         if (sad_count < 0) {
1262                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1263                 sad_count = 0;
1264         }
1265
1266         /* program the speaker allocation */
1267         tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1268         tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1269                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1270         /* set HDMI mode */
1271         tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1272         if (sad_count)
1273                 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1274         else
1275                 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1276         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1277
1278         kfree(sadb);
1279 }
1280
1281 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1282 {
1283         struct drm_device *dev = encoder->dev;
1284         struct amdgpu_device *adev = drm_to_adev(dev);
1285         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1286         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1287         u32 offset;
1288         struct drm_connector *connector;
1289         struct drm_connector_list_iter iter;
1290         struct amdgpu_connector *amdgpu_connector = NULL;
1291         struct cea_sad *sads;
1292         int i, sad_count;
1293
1294         static const u16 eld_reg_to_type[][2] = {
1295                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1296                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1297                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1298                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1299                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1300                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1301                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1302                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1303                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1304                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1305                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1306                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1307         };
1308
1309         if (!dig || !dig->afmt || !dig->afmt->pin)
1310                 return;
1311
1312         offset = dig->afmt->pin->offset;
1313
1314         drm_connector_list_iter_begin(dev, &iter);
1315         drm_for_each_connector_iter(connector, &iter) {
1316                 if (connector->encoder == encoder) {
1317                         amdgpu_connector = to_amdgpu_connector(connector);
1318                         break;
1319                 }
1320         }
1321         drm_connector_list_iter_end(&iter);
1322
1323         if (!amdgpu_connector) {
1324                 DRM_ERROR("Couldn't find encoder's connector\n");
1325                 return;
1326         }
1327
1328         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1329         if (sad_count < 0)
1330                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1331         if (sad_count <= 0)
1332                 return;
1333         BUG_ON(!sads);
1334
1335         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1336                 u32 value = 0;
1337                 u8 stereo_freqs = 0;
1338                 int max_channels = -1;
1339                 int j;
1340
1341                 for (j = 0; j < sad_count; j++) {
1342                         struct cea_sad *sad = &sads[j];
1343
1344                         if (sad->format == eld_reg_to_type[i][1]) {
1345                                 if (sad->channels > max_channels) {
1346                                         value = (sad->channels <<
1347                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1348                                                 (sad->byte2 <<
1349                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1350                                                 (sad->freq <<
1351                                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1352                                         max_channels = sad->channels;
1353                                 }
1354
1355                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1356                                         stereo_freqs |= sad->freq;
1357                                 else
1358                                         break;
1359                         }
1360                 }
1361
1362                 value |= (stereo_freqs <<
1363                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1364
1365                 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1366         }
1367
1368         kfree(sads);
1369 }
1370
1371 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1372                                   struct amdgpu_audio_pin *pin,
1373                                   bool enable)
1374 {
1375         if (!pin)
1376                 return;
1377
1378         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1379                 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1380 }
1381
1382 static const u32 pin_offsets[7] =
1383 {
1384         (0x1780 - 0x1780),
1385         (0x1786 - 0x1780),
1386         (0x178c - 0x1780),
1387         (0x1792 - 0x1780),
1388         (0x1798 - 0x1780),
1389         (0x179d - 0x1780),
1390         (0x17a4 - 0x1780),
1391 };
1392
1393 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1394 {
1395         int i;
1396
1397         if (!amdgpu_audio)
1398                 return 0;
1399
1400         adev->mode_info.audio.enabled = true;
1401
1402         if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1403                 adev->mode_info.audio.num_pins = 7;
1404         else if ((adev->asic_type == CHIP_KABINI) ||
1405                  (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1406                 adev->mode_info.audio.num_pins = 3;
1407         else if ((adev->asic_type == CHIP_BONAIRE) ||
1408                  (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1409                 adev->mode_info.audio.num_pins = 7;
1410         else
1411                 adev->mode_info.audio.num_pins = 3;
1412
1413         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1414                 adev->mode_info.audio.pin[i].channels = -1;
1415                 adev->mode_info.audio.pin[i].rate = -1;
1416                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1417                 adev->mode_info.audio.pin[i].status_bits = 0;
1418                 adev->mode_info.audio.pin[i].category_code = 0;
1419                 adev->mode_info.audio.pin[i].connected = false;
1420                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1421                 adev->mode_info.audio.pin[i].id = i;
1422                 /* disable audio.  it will be set up later */
1423                 /* XXX remove once we switch to ip funcs */
1424                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1425         }
1426
1427         return 0;
1428 }
1429
1430 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1431 {
1432         int i;
1433
1434         if (!amdgpu_audio)
1435                 return;
1436
1437         if (!adev->mode_info.audio.enabled)
1438                 return;
1439
1440         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1441                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1442
1443         adev->mode_info.audio.enabled = false;
1444 }
1445
1446 /*
1447  * update the N and CTS parameters for a given pixel clock rate
1448  */
1449 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1450 {
1451         struct drm_device *dev = encoder->dev;
1452         struct amdgpu_device *adev = drm_to_adev(dev);
1453         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1454         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1455         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1456         uint32_t offset = dig->afmt->offset;
1457
1458         WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
1459         WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1460
1461         WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1462         WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1463
1464         WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1465         WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1466 }
1467
1468 /*
1469  * build a HDMI Video Info Frame
1470  */
1471 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1472                                                void *buffer, size_t size)
1473 {
1474         struct drm_device *dev = encoder->dev;
1475         struct amdgpu_device *adev = drm_to_adev(dev);
1476         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1477         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1478         uint32_t offset = dig->afmt->offset;
1479         uint8_t *frame = buffer + 3;
1480         uint8_t *header = buffer;
1481
1482         WREG32(mmAFMT_AVI_INFO0 + offset,
1483                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1484         WREG32(mmAFMT_AVI_INFO1 + offset,
1485                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1486         WREG32(mmAFMT_AVI_INFO2 + offset,
1487                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1488         WREG32(mmAFMT_AVI_INFO3 + offset,
1489                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1490 }
1491
1492 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1493 {
1494         struct drm_device *dev = encoder->dev;
1495         struct amdgpu_device *adev = drm_to_adev(dev);
1496         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1497         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1498         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1499         u32 dto_phase = 24 * 1000;
1500         u32 dto_modulo = clock;
1501
1502         if (!dig || !dig->afmt)
1503                 return;
1504
1505         /* XXX two dtos; generally use dto0 for hdmi */
1506         /* Express [24MHz / target pixel clock] as an exact rational
1507          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1508          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1509          */
1510         WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1511         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1512         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1513 }
1514
1515 /*
1516  * update the info frames with the data from the current display mode
1517  */
1518 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1519                                   struct drm_display_mode *mode)
1520 {
1521         struct drm_device *dev = encoder->dev;
1522         struct amdgpu_device *adev = drm_to_adev(dev);
1523         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1524         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1525         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1526         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1527         struct hdmi_avi_infoframe frame;
1528         uint32_t offset, val;
1529         ssize_t err;
1530         int bpc = 8;
1531
1532         if (!dig || !dig->afmt)
1533                 return;
1534
1535         /* Silent, r600_hdmi_enable will raise WARN for us */
1536         if (!dig->afmt->enabled)
1537                 return;
1538
1539         offset = dig->afmt->offset;
1540
1541         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1542         if (encoder->crtc) {
1543                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1544                 bpc = amdgpu_crtc->bpc;
1545         }
1546
1547         /* disable audio prior to setting up hw */
1548         dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1549         dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1550
1551         dce_v8_0_audio_set_dto(encoder, mode->clock);
1552
1553         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1554                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1555
1556         WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1557
1558         val = RREG32(mmHDMI_CONTROL + offset);
1559         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1560         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1561
1562         switch (bpc) {
1563         case 0:
1564         case 6:
1565         case 8:
1566         case 16:
1567         default:
1568                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1569                           connector->name, bpc);
1570                 break;
1571         case 10:
1572                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1573                 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1574                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1575                           connector->name);
1576                 break;
1577         case 12:
1578                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1579                 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1580                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1581                           connector->name);
1582                 break;
1583         }
1584
1585         WREG32(mmHDMI_CONTROL + offset, val);
1586
1587         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1588                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1589                HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1590                HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1591
1592         WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1593                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1594                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1595
1596         WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1597                AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1598
1599         WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1600                (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1601
1602         WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1603
1604         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1605                (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1606                (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1607
1608         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1609                AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1610
1611         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1612
1613         if (bpc > 8)
1614                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1615                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1616         else
1617                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1618                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1619                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1620
1621         dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1622
1623         WREG32(mmAFMT_60958_0 + offset,
1624                (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1625
1626         WREG32(mmAFMT_60958_1 + offset,
1627                (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1628
1629         WREG32(mmAFMT_60958_2 + offset,
1630                (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1631                (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1632                (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1633                (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1634                (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1635                (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1636
1637         dce_v8_0_audio_write_speaker_allocation(encoder);
1638
1639
1640         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1641                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1642
1643         dce_v8_0_afmt_audio_select_pin(encoder);
1644         dce_v8_0_audio_write_sad_regs(encoder);
1645         dce_v8_0_audio_write_latency_fields(encoder, mode);
1646
1647         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1648         if (err < 0) {
1649                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1650                 return;
1651         }
1652
1653         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1654         if (err < 0) {
1655                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1656                 return;
1657         }
1658
1659         dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1660
1661         WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1662                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1663                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1664
1665         WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1666                  (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1667                  ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1668
1669         WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1670                   AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1671
1672         WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1673         WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1674         WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1675         WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1676
1677         /* enable audio after setting up hw */
1678         dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1679 }
1680
1681 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1682 {
1683         struct drm_device *dev = encoder->dev;
1684         struct amdgpu_device *adev = drm_to_adev(dev);
1685         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1686         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1687
1688         if (!dig || !dig->afmt)
1689                 return;
1690
1691         /* Silent, r600_hdmi_enable will raise WARN for us */
1692         if (enable && dig->afmt->enabled)
1693                 return;
1694         if (!enable && !dig->afmt->enabled)
1695                 return;
1696
1697         if (!enable && dig->afmt->pin) {
1698                 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1699                 dig->afmt->pin = NULL;
1700         }
1701
1702         dig->afmt->enabled = enable;
1703
1704         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1705                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1706 }
1707
1708 static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
1709 {
1710         int i;
1711
1712         for (i = 0; i < adev->mode_info.num_dig; i++)
1713                 adev->mode_info.afmt[i] = NULL;
1714
1715         /* DCE8 has audio blocks tied to DIG encoders */
1716         for (i = 0; i < adev->mode_info.num_dig; i++) {
1717                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1718                 if (adev->mode_info.afmt[i]) {
1719                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1720                         adev->mode_info.afmt[i]->id = i;
1721                 } else {
1722                         int j;
1723                         for (j = 0; j < i; j++) {
1724                                 kfree(adev->mode_info.afmt[j]);
1725                                 adev->mode_info.afmt[j] = NULL;
1726                         }
1727                         return -ENOMEM;
1728                 }
1729         }
1730         return 0;
1731 }
1732
1733 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1734 {
1735         int i;
1736
1737         for (i = 0; i < adev->mode_info.num_dig; i++) {
1738                 kfree(adev->mode_info.afmt[i]);
1739                 adev->mode_info.afmt[i] = NULL;
1740         }
1741 }
1742
1743 static const u32 vga_control_regs[6] =
1744 {
1745         mmD1VGA_CONTROL,
1746         mmD2VGA_CONTROL,
1747         mmD3VGA_CONTROL,
1748         mmD4VGA_CONTROL,
1749         mmD5VGA_CONTROL,
1750         mmD6VGA_CONTROL,
1751 };
1752
1753 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1754 {
1755         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1756         struct drm_device *dev = crtc->dev;
1757         struct amdgpu_device *adev = drm_to_adev(dev);
1758         u32 vga_control;
1759
1760         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1761         if (enable)
1762                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1763         else
1764                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1765 }
1766
1767 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1768 {
1769         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1770         struct drm_device *dev = crtc->dev;
1771         struct amdgpu_device *adev = drm_to_adev(dev);
1772
1773         if (enable)
1774                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1775         else
1776                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1777 }
1778
1779 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1780                                      struct drm_framebuffer *fb,
1781                                      int x, int y, int atomic)
1782 {
1783         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1784         struct drm_device *dev = crtc->dev;
1785         struct amdgpu_device *adev = drm_to_adev(dev);
1786         struct drm_framebuffer *target_fb;
1787         struct drm_gem_object *obj;
1788         struct amdgpu_bo *abo;
1789         uint64_t fb_location, tiling_flags;
1790         uint32_t fb_format, fb_pitch_pixels;
1791         u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1792         u32 pipe_config;
1793         u32 viewport_w, viewport_h;
1794         int r;
1795         bool bypass_lut = false;
1796
1797         /* no fb bound */
1798         if (!atomic && !crtc->primary->fb) {
1799                 DRM_DEBUG_KMS("No FB bound\n");
1800                 return 0;
1801         }
1802
1803         if (atomic)
1804                 target_fb = fb;
1805         else
1806                 target_fb = crtc->primary->fb;
1807
1808         /* If atomic, assume fb object is pinned & idle & fenced and
1809          * just update base pointers
1810          */
1811         obj = target_fb->obj[0];
1812         abo = gem_to_amdgpu_bo(obj);
1813         r = amdgpu_bo_reserve(abo, false);
1814         if (unlikely(r != 0))
1815                 return r;
1816
1817         if (!atomic) {
1818                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1819                 if (unlikely(r != 0)) {
1820                         amdgpu_bo_unreserve(abo);
1821                         return -EINVAL;
1822                 }
1823         }
1824         fb_location = amdgpu_bo_gpu_offset(abo);
1825
1826         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1827         amdgpu_bo_unreserve(abo);
1828
1829         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1830
1831         switch (target_fb->format->format) {
1832         case DRM_FORMAT_C8:
1833                 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1834                              (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1835                 break;
1836         case DRM_FORMAT_XRGB4444:
1837         case DRM_FORMAT_ARGB4444:
1838                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1839                              (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1840 #ifdef __BIG_ENDIAN
1841                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1842 #endif
1843                 break;
1844         case DRM_FORMAT_XRGB1555:
1845         case DRM_FORMAT_ARGB1555:
1846                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1847                              (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1848 #ifdef __BIG_ENDIAN
1849                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1850 #endif
1851                 break;
1852         case DRM_FORMAT_BGRX5551:
1853         case DRM_FORMAT_BGRA5551:
1854                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1855                              (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1856 #ifdef __BIG_ENDIAN
1857                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1858 #endif
1859                 break;
1860         case DRM_FORMAT_RGB565:
1861                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1862                              (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1863 #ifdef __BIG_ENDIAN
1864                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1865 #endif
1866                 break;
1867         case DRM_FORMAT_XRGB8888:
1868         case DRM_FORMAT_ARGB8888:
1869                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1870                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1871 #ifdef __BIG_ENDIAN
1872                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1873 #endif
1874                 break;
1875         case DRM_FORMAT_XRGB2101010:
1876         case DRM_FORMAT_ARGB2101010:
1877                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1878                              (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1879 #ifdef __BIG_ENDIAN
1880                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1881 #endif
1882                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1883                 bypass_lut = true;
1884                 break;
1885         case DRM_FORMAT_BGRX1010102:
1886         case DRM_FORMAT_BGRA1010102:
1887                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1888                              (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1889 #ifdef __BIG_ENDIAN
1890                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1891 #endif
1892                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1893                 bypass_lut = true;
1894                 break;
1895         case DRM_FORMAT_XBGR8888:
1896         case DRM_FORMAT_ABGR8888:
1897                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
1898                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
1899                 fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) |
1900                            (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT));
1901 #ifdef __BIG_ENDIAN
1902                 fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1903 #endif
1904                 break;
1905         default:
1906                 DRM_ERROR("Unsupported screen format %p4cc\n",
1907                           &target_fb->format->format);
1908                 return -EINVAL;
1909         }
1910
1911         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1912                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1913
1914                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1915                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1916                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1917                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1918                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1919
1920                 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
1921                 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1922                 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
1923                 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
1924                 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
1925                 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
1926                 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
1927         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1928                 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
1929         }
1930
1931         fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
1932
1933         dce_v8_0_vga_enable(crtc, false);
1934
1935         /* Make sure surface address is updated at vertical blank rather than
1936          * horizontal blank
1937          */
1938         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1939
1940         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1941                upper_32_bits(fb_location));
1942         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1943                upper_32_bits(fb_location));
1944         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1945                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1946         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1947                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
1948         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1949         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1950
1951         /*
1952          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1953          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1954          * retain the full precision throughout the pipeline.
1955          */
1956         WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
1957                  (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
1958                  ~LUT_10BIT_BYPASS_EN);
1959
1960         if (bypass_lut)
1961                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1962
1963         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1964         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1965         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1966         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1967         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1968         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1969
1970         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1971         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1972
1973         dce_v8_0_grph_enable(crtc, true);
1974
1975         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1976                target_fb->height);
1977
1978         x &= ~3;
1979         y &= ~1;
1980         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1981                (x << 16) | y);
1982         viewport_w = crtc->mode.hdisplay;
1983         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1984         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1985                (viewport_w << 16) | viewport_h);
1986
1987         /* set pageflip to happen anywhere in vblank interval */
1988         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1989
1990         if (!atomic && fb && fb != crtc->primary->fb) {
1991                 abo = gem_to_amdgpu_bo(fb->obj[0]);
1992                 r = amdgpu_bo_reserve(abo, true);
1993                 if (unlikely(r != 0))
1994                         return r;
1995                 amdgpu_bo_unpin(abo);
1996                 amdgpu_bo_unreserve(abo);
1997         }
1998
1999         /* Bytes per pixel may have changed */
2000         dce_v8_0_bandwidth_update(adev);
2001
2002         return 0;
2003 }
2004
2005 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2006                                     struct drm_display_mode *mode)
2007 {
2008         struct drm_device *dev = crtc->dev;
2009         struct amdgpu_device *adev = drm_to_adev(dev);
2010         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2011
2012         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2013                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2014                        LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2015         else
2016                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2017 }
2018
2019 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2020 {
2021         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2022         struct drm_device *dev = crtc->dev;
2023         struct amdgpu_device *adev = drm_to_adev(dev);
2024         u16 *r, *g, *b;
2025         int i;
2026
2027         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2028
2029         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2030                ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2031                 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2032         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2033                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2034         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2035                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2036         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2037                ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2038                 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2039
2040         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2041
2042         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2043         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2044         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2045
2046         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2047         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2048         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2049
2050         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2051         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2052
2053         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2054         r = crtc->gamma_store;
2055         g = r + crtc->gamma_size;
2056         b = g + crtc->gamma_size;
2057         for (i = 0; i < 256; i++) {
2058                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2059                        ((*r++ & 0xffc0) << 14) |
2060                        ((*g++ & 0xffc0) << 4) |
2061                        (*b++ >> 6));
2062         }
2063
2064         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2065                ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2066                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2067                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2068         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2069                ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2070                 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2071         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2072                ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2073                 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2074         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2075                ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2076                 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2077         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2078         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2079         /* XXX this only needs to be programmed once per crtc at startup,
2080          * not sure where the best place for it is
2081          */
2082         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2083                ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2084 }
2085
2086 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2087 {
2088         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2089         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2090
2091         switch (amdgpu_encoder->encoder_id) {
2092         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2093                 if (dig->linkb)
2094                         return 1;
2095                 else
2096                         return 0;
2097         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2098                 if (dig->linkb)
2099                         return 3;
2100                 else
2101                         return 2;
2102         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2103                 if (dig->linkb)
2104                         return 5;
2105                 else
2106                         return 4;
2107         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2108                 return 6;
2109         default:
2110                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2111                 return 0;
2112         }
2113 }
2114
2115 /**
2116  * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2117  *
2118  * @crtc: drm crtc
2119  *
2120  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2121  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2122  * monitors a dedicated PPLL must be used.  If a particular board has
2123  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2124  * as there is no need to program the PLL itself.  If we are not able to
2125  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2126  * avoid messing up an existing monitor.
2127  *
2128  * Asic specific PLL information
2129  *
2130  * DCE 8.x
2131  * KB/KV
2132  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2133  * CI
2134  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2135  *
2136  */
2137 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2138 {
2139         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2140         struct drm_device *dev = crtc->dev;
2141         struct amdgpu_device *adev = drm_to_adev(dev);
2142         u32 pll_in_use;
2143         int pll;
2144
2145         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2146                 if (adev->clock.dp_extclk)
2147                         /* skip PPLL programming if using ext clock */
2148                         return ATOM_PPLL_INVALID;
2149                 else {
2150                         /* use the same PPLL for all DP monitors */
2151                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2152                         if (pll != ATOM_PPLL_INVALID)
2153                                 return pll;
2154                 }
2155         } else {
2156                 /* use the same PPLL for all monitors with the same clock */
2157                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2158                 if (pll != ATOM_PPLL_INVALID)
2159                         return pll;
2160         }
2161         /* otherwise, pick one of the plls */
2162         if ((adev->asic_type == CHIP_KABINI) ||
2163             (adev->asic_type == CHIP_MULLINS)) {
2164                 /* KB/ML has PPLL1 and PPLL2 */
2165                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2166                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2167                         return ATOM_PPLL2;
2168                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2169                         return ATOM_PPLL1;
2170                 DRM_ERROR("unable to allocate a PPLL\n");
2171                 return ATOM_PPLL_INVALID;
2172         } else {
2173                 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2174                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2175                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2176                         return ATOM_PPLL2;
2177                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2178                         return ATOM_PPLL1;
2179                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2180                         return ATOM_PPLL0;
2181                 DRM_ERROR("unable to allocate a PPLL\n");
2182                 return ATOM_PPLL_INVALID;
2183         }
2184         return ATOM_PPLL_INVALID;
2185 }
2186
2187 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2188 {
2189         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2190         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2191         uint32_t cur_lock;
2192
2193         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2194         if (lock)
2195                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2196         else
2197                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2198         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2199 }
2200
2201 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2202 {
2203         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2204         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2205
2206         WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2207                (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2208                (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2209 }
2210
2211 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2212 {
2213         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2214         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2215
2216         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2217                upper_32_bits(amdgpu_crtc->cursor_addr));
2218         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2219                lower_32_bits(amdgpu_crtc->cursor_addr));
2220
2221         WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2222                CUR_CONTROL__CURSOR_EN_MASK |
2223                (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2224                (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2225 }
2226
2227 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2228                                        int x, int y)
2229 {
2230         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2231         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2232         int xorigin = 0, yorigin = 0;
2233
2234         amdgpu_crtc->cursor_x = x;
2235         amdgpu_crtc->cursor_y = y;
2236
2237         /* avivo cursor are offset into the total surface */
2238         x += crtc->x;
2239         y += crtc->y;
2240         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2241
2242         if (x < 0) {
2243                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2244                 x = 0;
2245         }
2246         if (y < 0) {
2247                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2248                 y = 0;
2249         }
2250
2251         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2252         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2253         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2254                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2255
2256         return 0;
2257 }
2258
2259 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2260                                      int x, int y)
2261 {
2262         int ret;
2263
2264         dce_v8_0_lock_cursor(crtc, true);
2265         ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2266         dce_v8_0_lock_cursor(crtc, false);
2267
2268         return ret;
2269 }
2270
2271 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2272                                      struct drm_file *file_priv,
2273                                      uint32_t handle,
2274                                      uint32_t width,
2275                                      uint32_t height,
2276                                      int32_t hot_x,
2277                                      int32_t hot_y)
2278 {
2279         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2280         struct drm_gem_object *obj;
2281         struct amdgpu_bo *aobj;
2282         int ret;
2283
2284         if (!handle) {
2285                 /* turn off cursor */
2286                 dce_v8_0_hide_cursor(crtc);
2287                 obj = NULL;
2288                 goto unpin;
2289         }
2290
2291         if ((width > amdgpu_crtc->max_cursor_width) ||
2292             (height > amdgpu_crtc->max_cursor_height)) {
2293                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2294                 return -EINVAL;
2295         }
2296
2297         obj = drm_gem_object_lookup(file_priv, handle);
2298         if (!obj) {
2299                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2300                 return -ENOENT;
2301         }
2302
2303         aobj = gem_to_amdgpu_bo(obj);
2304         ret = amdgpu_bo_reserve(aobj, false);
2305         if (ret != 0) {
2306                 drm_gem_object_put(obj);
2307                 return ret;
2308         }
2309
2310         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2311         amdgpu_bo_unreserve(aobj);
2312         if (ret) {
2313                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2314                 drm_gem_object_put(obj);
2315                 return ret;
2316         }
2317         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2318
2319         dce_v8_0_lock_cursor(crtc, true);
2320
2321         if (width != amdgpu_crtc->cursor_width ||
2322             height != amdgpu_crtc->cursor_height ||
2323             hot_x != amdgpu_crtc->cursor_hot_x ||
2324             hot_y != amdgpu_crtc->cursor_hot_y) {
2325                 int x, y;
2326
2327                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2328                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2329
2330                 dce_v8_0_cursor_move_locked(crtc, x, y);
2331
2332                 amdgpu_crtc->cursor_width = width;
2333                 amdgpu_crtc->cursor_height = height;
2334                 amdgpu_crtc->cursor_hot_x = hot_x;
2335                 amdgpu_crtc->cursor_hot_y = hot_y;
2336         }
2337
2338         dce_v8_0_show_cursor(crtc);
2339         dce_v8_0_lock_cursor(crtc, false);
2340
2341 unpin:
2342         if (amdgpu_crtc->cursor_bo) {
2343                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2344                 ret = amdgpu_bo_reserve(aobj, true);
2345                 if (likely(ret == 0)) {
2346                         amdgpu_bo_unpin(aobj);
2347                         amdgpu_bo_unreserve(aobj);
2348                 }
2349                 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2350         }
2351
2352         amdgpu_crtc->cursor_bo = obj;
2353         return 0;
2354 }
2355
2356 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2357 {
2358         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2359
2360         if (amdgpu_crtc->cursor_bo) {
2361                 dce_v8_0_lock_cursor(crtc, true);
2362
2363                 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2364                                             amdgpu_crtc->cursor_y);
2365
2366                 dce_v8_0_show_cursor(crtc);
2367
2368                 dce_v8_0_lock_cursor(crtc, false);
2369         }
2370 }
2371
2372 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2373                                    u16 *blue, uint32_t size,
2374                                    struct drm_modeset_acquire_ctx *ctx)
2375 {
2376         dce_v8_0_crtc_load_lut(crtc);
2377
2378         return 0;
2379 }
2380
2381 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2382 {
2383         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2384
2385         drm_crtc_cleanup(crtc);
2386         kfree(amdgpu_crtc);
2387 }
2388
2389 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2390         .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2391         .cursor_move = dce_v8_0_crtc_cursor_move,
2392         .gamma_set = dce_v8_0_crtc_gamma_set,
2393         .set_config = amdgpu_display_crtc_set_config,
2394         .destroy = dce_v8_0_crtc_destroy,
2395         .page_flip_target = amdgpu_display_crtc_page_flip_target,
2396         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2397         .enable_vblank = amdgpu_enable_vblank_kms,
2398         .disable_vblank = amdgpu_disable_vblank_kms,
2399         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2400 };
2401
2402 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2403 {
2404         struct drm_device *dev = crtc->dev;
2405         struct amdgpu_device *adev = drm_to_adev(dev);
2406         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2407         unsigned type;
2408
2409         switch (mode) {
2410         case DRM_MODE_DPMS_ON:
2411                 amdgpu_crtc->enabled = true;
2412                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2413                 dce_v8_0_vga_enable(crtc, true);
2414                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2415                 dce_v8_0_vga_enable(crtc, false);
2416                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2417                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2418                                                 amdgpu_crtc->crtc_id);
2419                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2420                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2421                 drm_crtc_vblank_on(crtc);
2422                 dce_v8_0_crtc_load_lut(crtc);
2423                 break;
2424         case DRM_MODE_DPMS_STANDBY:
2425         case DRM_MODE_DPMS_SUSPEND:
2426         case DRM_MODE_DPMS_OFF:
2427                 drm_crtc_vblank_off(crtc);
2428                 if (amdgpu_crtc->enabled) {
2429                         dce_v8_0_vga_enable(crtc, true);
2430                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2431                         dce_v8_0_vga_enable(crtc, false);
2432                 }
2433                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2434                 amdgpu_crtc->enabled = false;
2435                 break;
2436         }
2437         /* adjust pm to dpms */
2438         amdgpu_dpm_compute_clocks(adev);
2439 }
2440
2441 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2442 {
2443         /* disable crtc pair power gating before programming */
2444         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2445         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2446         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2447 }
2448
2449 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2450 {
2451         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2452         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2453 }
2454
2455 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2456 {
2457         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2458         struct drm_device *dev = crtc->dev;
2459         struct amdgpu_device *adev = drm_to_adev(dev);
2460         struct amdgpu_atom_ss ss;
2461         int i;
2462
2463         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2464         if (crtc->primary->fb) {
2465                 int r;
2466                 struct amdgpu_bo *abo;
2467
2468                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2469                 r = amdgpu_bo_reserve(abo, true);
2470                 if (unlikely(r))
2471                         DRM_ERROR("failed to reserve abo before unpin\n");
2472                 else {
2473                         amdgpu_bo_unpin(abo);
2474                         amdgpu_bo_unreserve(abo);
2475                 }
2476         }
2477         /* disable the GRPH */
2478         dce_v8_0_grph_enable(crtc, false);
2479
2480         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2481
2482         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2483                 if (adev->mode_info.crtcs[i] &&
2484                     adev->mode_info.crtcs[i]->enabled &&
2485                     i != amdgpu_crtc->crtc_id &&
2486                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2487                         /* one other crtc is using this pll don't turn
2488                          * off the pll
2489                          */
2490                         goto done;
2491                 }
2492         }
2493
2494         switch (amdgpu_crtc->pll_id) {
2495         case ATOM_PPLL1:
2496         case ATOM_PPLL2:
2497                 /* disable the ppll */
2498                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2499                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2500                 break;
2501         case ATOM_PPLL0:
2502                 /* disable the ppll */
2503                 if ((adev->asic_type == CHIP_KAVERI) ||
2504                     (adev->asic_type == CHIP_BONAIRE) ||
2505                     (adev->asic_type == CHIP_HAWAII))
2506                         amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2507                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2508                 break;
2509         default:
2510                 break;
2511         }
2512 done:
2513         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2514         amdgpu_crtc->adjusted_clock = 0;
2515         amdgpu_crtc->encoder = NULL;
2516         amdgpu_crtc->connector = NULL;
2517 }
2518
2519 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2520                                   struct drm_display_mode *mode,
2521                                   struct drm_display_mode *adjusted_mode,
2522                                   int x, int y, struct drm_framebuffer *old_fb)
2523 {
2524         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2525
2526         if (!amdgpu_crtc->adjusted_clock)
2527                 return -EINVAL;
2528
2529         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2530         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2531         dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2532         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2533         amdgpu_atombios_crtc_scaler_setup(crtc);
2534         dce_v8_0_cursor_reset(crtc);
2535         /* update the hw version fpr dpm */
2536         amdgpu_crtc->hw_mode = *adjusted_mode;
2537
2538         return 0;
2539 }
2540
2541 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2542                                      const struct drm_display_mode *mode,
2543                                      struct drm_display_mode *adjusted_mode)
2544 {
2545         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2546         struct drm_device *dev = crtc->dev;
2547         struct drm_encoder *encoder;
2548
2549         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2550         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2551                 if (encoder->crtc == crtc) {
2552                         amdgpu_crtc->encoder = encoder;
2553                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2554                         break;
2555                 }
2556         }
2557         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2558                 amdgpu_crtc->encoder = NULL;
2559                 amdgpu_crtc->connector = NULL;
2560                 return false;
2561         }
2562         if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2563                 return false;
2564         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2565                 return false;
2566         /* pick pll */
2567         amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2568         /* if we can't get a PPLL for a non-DP encoder, fail */
2569         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2570             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2571                 return false;
2572
2573         return true;
2574 }
2575
2576 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2577                                   struct drm_framebuffer *old_fb)
2578 {
2579         return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2580 }
2581
2582 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2583                                          struct drm_framebuffer *fb,
2584                                          int x, int y, enum mode_set_atomic state)
2585 {
2586         return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2587 }
2588
2589 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2590         .dpms = dce_v8_0_crtc_dpms,
2591         .mode_fixup = dce_v8_0_crtc_mode_fixup,
2592         .mode_set = dce_v8_0_crtc_mode_set,
2593         .mode_set_base = dce_v8_0_crtc_set_base,
2594         .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2595         .prepare = dce_v8_0_crtc_prepare,
2596         .commit = dce_v8_0_crtc_commit,
2597         .disable = dce_v8_0_crtc_disable,
2598         .get_scanout_position = amdgpu_crtc_get_scanout_position,
2599 };
2600
2601 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2602 {
2603         struct amdgpu_crtc *amdgpu_crtc;
2604
2605         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2606                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2607         if (amdgpu_crtc == NULL)
2608                 return -ENOMEM;
2609
2610         drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2611
2612         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2613         amdgpu_crtc->crtc_id = index;
2614         adev->mode_info.crtcs[index] = amdgpu_crtc;
2615
2616         amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2617         amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2618         adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2619         adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2620
2621         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2622
2623         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2624         amdgpu_crtc->adjusted_clock = 0;
2625         amdgpu_crtc->encoder = NULL;
2626         amdgpu_crtc->connector = NULL;
2627         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2628
2629         return 0;
2630 }
2631
2632 static int dce_v8_0_early_init(void *handle)
2633 {
2634         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2635
2636         adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2637         adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2638
2639         dce_v8_0_set_display_funcs(adev);
2640
2641         adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
2642
2643         switch (adev->asic_type) {
2644         case CHIP_BONAIRE:
2645         case CHIP_HAWAII:
2646                 adev->mode_info.num_hpd = 6;
2647                 adev->mode_info.num_dig = 6;
2648                 break;
2649         case CHIP_KAVERI:
2650                 adev->mode_info.num_hpd = 6;
2651                 adev->mode_info.num_dig = 7;
2652                 break;
2653         case CHIP_KABINI:
2654         case CHIP_MULLINS:
2655                 adev->mode_info.num_hpd = 6;
2656                 adev->mode_info.num_dig = 6; /* ? */
2657                 break;
2658         default:
2659                 /* FIXME: not supported yet */
2660                 return -EINVAL;
2661         }
2662
2663         dce_v8_0_set_irq_funcs(adev);
2664
2665         return 0;
2666 }
2667
2668 static int dce_v8_0_sw_init(void *handle)
2669 {
2670         int r, i;
2671         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2672
2673         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2674                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2675                 if (r)
2676                         return r;
2677         }
2678
2679         for (i = 8; i < 20; i += 2) {
2680                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2681                 if (r)
2682                         return r;
2683         }
2684
2685         /* HPD hotplug */
2686         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2687         if (r)
2688                 return r;
2689
2690         adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2691
2692         adev_to_drm(adev)->mode_config.async_page_flip = true;
2693
2694         adev_to_drm(adev)->mode_config.max_width = 16384;
2695         adev_to_drm(adev)->mode_config.max_height = 16384;
2696
2697         adev_to_drm(adev)->mode_config.preferred_depth = 24;
2698         if (adev->asic_type == CHIP_HAWAII)
2699                 /* disable prefer shadow for now due to hibernation issues */
2700                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
2701         else
2702                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2703
2704         adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2705
2706         r = amdgpu_display_modeset_create_props(adev);
2707         if (r)
2708                 return r;
2709
2710         adev_to_drm(adev)->mode_config.max_width = 16384;
2711         adev_to_drm(adev)->mode_config.max_height = 16384;
2712
2713         /* allocate crtcs */
2714         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2715                 r = dce_v8_0_crtc_init(adev, i);
2716                 if (r)
2717                         return r;
2718         }
2719
2720         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2721                 amdgpu_display_print_display_setup(adev_to_drm(adev));
2722         else
2723                 return -EINVAL;
2724
2725         /* setup afmt */
2726         r = dce_v8_0_afmt_init(adev);
2727         if (r)
2728                 return r;
2729
2730         r = dce_v8_0_audio_init(adev);
2731         if (r)
2732                 return r;
2733
2734         /* Disable vblank IRQs aggressively for power-saving */
2735         /* XXX: can this be enabled for DC? */
2736         adev_to_drm(adev)->vblank_disable_immediate = true;
2737
2738         r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2739         if (r)
2740                 return r;
2741
2742         /* Pre-DCE11 */
2743         INIT_DELAYED_WORK(&adev->hotplug_work,
2744                   amdgpu_display_hotplug_work_func);
2745
2746         drm_kms_helper_poll_init(adev_to_drm(adev));
2747
2748         adev->mode_info.mode_config_initialized = true;
2749         return 0;
2750 }
2751
2752 static int dce_v8_0_sw_fini(void *handle)
2753 {
2754         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2755
2756         kfree(adev->mode_info.bios_hardcoded_edid);
2757
2758         drm_kms_helper_poll_fini(adev_to_drm(adev));
2759
2760         dce_v8_0_audio_fini(adev);
2761
2762         dce_v8_0_afmt_fini(adev);
2763
2764         drm_mode_config_cleanup(adev_to_drm(adev));
2765         adev->mode_info.mode_config_initialized = false;
2766
2767         return 0;
2768 }
2769
2770 static int dce_v8_0_hw_init(void *handle)
2771 {
2772         int i;
2773         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2774
2775         /* disable vga render */
2776         dce_v8_0_set_vga_render_state(adev, false);
2777         /* init dig PHYs, disp eng pll */
2778         amdgpu_atombios_encoder_init_dig(adev);
2779         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2780
2781         /* initialize hpd */
2782         dce_v8_0_hpd_init(adev);
2783
2784         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2785                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2786         }
2787
2788         dce_v8_0_pageflip_interrupt_init(adev);
2789
2790         return 0;
2791 }
2792
2793 static int dce_v8_0_hw_fini(void *handle)
2794 {
2795         int i;
2796         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2797
2798         dce_v8_0_hpd_fini(adev);
2799
2800         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2801                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2802         }
2803
2804         dce_v8_0_pageflip_interrupt_fini(adev);
2805
2806         flush_delayed_work(&adev->hotplug_work);
2807
2808         return 0;
2809 }
2810
2811 static int dce_v8_0_suspend(void *handle)
2812 {
2813         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2814         int r;
2815
2816         r = amdgpu_display_suspend_helper(adev);
2817         if (r)
2818                 return r;
2819
2820         adev->mode_info.bl_level =
2821                 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2822
2823         return dce_v8_0_hw_fini(handle);
2824 }
2825
2826 static int dce_v8_0_resume(void *handle)
2827 {
2828         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2829         int ret;
2830
2831         amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2832                                                            adev->mode_info.bl_level);
2833
2834         ret = dce_v8_0_hw_init(handle);
2835
2836         /* turn on the BL */
2837         if (adev->mode_info.bl_encoder) {
2838                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2839                                                                   adev->mode_info.bl_encoder);
2840                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2841                                                     bl_level);
2842         }
2843         if (ret)
2844                 return ret;
2845
2846         return amdgpu_display_resume_helper(adev);
2847 }
2848
2849 static bool dce_v8_0_is_idle(void *handle)
2850 {
2851         return true;
2852 }
2853
2854 static int dce_v8_0_wait_for_idle(void *handle)
2855 {
2856         return 0;
2857 }
2858
2859 static int dce_v8_0_soft_reset(void *handle)
2860 {
2861         u32 srbm_soft_reset = 0, tmp;
2862         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2863
2864         if (dce_v8_0_is_display_hung(adev))
2865                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2866
2867         if (srbm_soft_reset) {
2868                 tmp = RREG32(mmSRBM_SOFT_RESET);
2869                 tmp |= srbm_soft_reset;
2870                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2871                 WREG32(mmSRBM_SOFT_RESET, tmp);
2872                 tmp = RREG32(mmSRBM_SOFT_RESET);
2873
2874                 udelay(50);
2875
2876                 tmp &= ~srbm_soft_reset;
2877                 WREG32(mmSRBM_SOFT_RESET, tmp);
2878                 tmp = RREG32(mmSRBM_SOFT_RESET);
2879
2880                 /* Wait a little for things to settle down */
2881                 udelay(50);
2882         }
2883         return 0;
2884 }
2885
2886 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2887                                                      int crtc,
2888                                                      enum amdgpu_interrupt_state state)
2889 {
2890         u32 reg_block, lb_interrupt_mask;
2891
2892         if (crtc >= adev->mode_info.num_crtc) {
2893                 DRM_DEBUG("invalid crtc %d\n", crtc);
2894                 return;
2895         }
2896
2897         switch (crtc) {
2898         case 0:
2899                 reg_block = CRTC0_REGISTER_OFFSET;
2900                 break;
2901         case 1:
2902                 reg_block = CRTC1_REGISTER_OFFSET;
2903                 break;
2904         case 2:
2905                 reg_block = CRTC2_REGISTER_OFFSET;
2906                 break;
2907         case 3:
2908                 reg_block = CRTC3_REGISTER_OFFSET;
2909                 break;
2910         case 4:
2911                 reg_block = CRTC4_REGISTER_OFFSET;
2912                 break;
2913         case 5:
2914                 reg_block = CRTC5_REGISTER_OFFSET;
2915                 break;
2916         default:
2917                 DRM_DEBUG("invalid crtc %d\n", crtc);
2918                 return;
2919         }
2920
2921         switch (state) {
2922         case AMDGPU_IRQ_STATE_DISABLE:
2923                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2924                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2925                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2926                 break;
2927         case AMDGPU_IRQ_STATE_ENABLE:
2928                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2929                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2930                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2931                 break;
2932         default:
2933                 break;
2934         }
2935 }
2936
2937 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2938                                                     int crtc,
2939                                                     enum amdgpu_interrupt_state state)
2940 {
2941         u32 reg_block, lb_interrupt_mask;
2942
2943         if (crtc >= adev->mode_info.num_crtc) {
2944                 DRM_DEBUG("invalid crtc %d\n", crtc);
2945                 return;
2946         }
2947
2948         switch (crtc) {
2949         case 0:
2950                 reg_block = CRTC0_REGISTER_OFFSET;
2951                 break;
2952         case 1:
2953                 reg_block = CRTC1_REGISTER_OFFSET;
2954                 break;
2955         case 2:
2956                 reg_block = CRTC2_REGISTER_OFFSET;
2957                 break;
2958         case 3:
2959                 reg_block = CRTC3_REGISTER_OFFSET;
2960                 break;
2961         case 4:
2962                 reg_block = CRTC4_REGISTER_OFFSET;
2963                 break;
2964         case 5:
2965                 reg_block = CRTC5_REGISTER_OFFSET;
2966                 break;
2967         default:
2968                 DRM_DEBUG("invalid crtc %d\n", crtc);
2969                 return;
2970         }
2971
2972         switch (state) {
2973         case AMDGPU_IRQ_STATE_DISABLE:
2974                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2975                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2976                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2977                 break;
2978         case AMDGPU_IRQ_STATE_ENABLE:
2979                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2980                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
2981                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2982                 break;
2983         default:
2984                 break;
2985         }
2986 }
2987
2988 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2989                                             struct amdgpu_irq_src *src,
2990                                             unsigned type,
2991                                             enum amdgpu_interrupt_state state)
2992 {
2993         u32 dc_hpd_int_cntl;
2994
2995         if (type >= adev->mode_info.num_hpd) {
2996                 DRM_DEBUG("invalid hdp %d\n", type);
2997                 return 0;
2998         }
2999
3000         switch (state) {
3001         case AMDGPU_IRQ_STATE_DISABLE:
3002                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3003                 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3004                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3005                 break;
3006         case AMDGPU_IRQ_STATE_ENABLE:
3007                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
3008                 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3009                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
3010                 break;
3011         default:
3012                 break;
3013         }
3014
3015         return 0;
3016 }
3017
3018 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3019                                              struct amdgpu_irq_src *src,
3020                                              unsigned type,
3021                                              enum amdgpu_interrupt_state state)
3022 {
3023         switch (type) {
3024         case AMDGPU_CRTC_IRQ_VBLANK1:
3025                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3026                 break;
3027         case AMDGPU_CRTC_IRQ_VBLANK2:
3028                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3029                 break;
3030         case AMDGPU_CRTC_IRQ_VBLANK3:
3031                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3032                 break;
3033         case AMDGPU_CRTC_IRQ_VBLANK4:
3034                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3035                 break;
3036         case AMDGPU_CRTC_IRQ_VBLANK5:
3037                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3038                 break;
3039         case AMDGPU_CRTC_IRQ_VBLANK6:
3040                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3041                 break;
3042         case AMDGPU_CRTC_IRQ_VLINE1:
3043                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3044                 break;
3045         case AMDGPU_CRTC_IRQ_VLINE2:
3046                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3047                 break;
3048         case AMDGPU_CRTC_IRQ_VLINE3:
3049                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3050                 break;
3051         case AMDGPU_CRTC_IRQ_VLINE4:
3052                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3053                 break;
3054         case AMDGPU_CRTC_IRQ_VLINE5:
3055                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3056                 break;
3057         case AMDGPU_CRTC_IRQ_VLINE6:
3058                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3059                 break;
3060         default:
3061                 break;
3062         }
3063         return 0;
3064 }
3065
3066 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3067                              struct amdgpu_irq_src *source,
3068                              struct amdgpu_iv_entry *entry)
3069 {
3070         unsigned crtc = entry->src_id - 1;
3071         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3072         unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3073                                                                     crtc);
3074
3075         switch (entry->src_data[0]) {
3076         case 0: /* vblank */
3077                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3078                         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3079                 else
3080                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3081
3082                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3083                         drm_handle_vblank(adev_to_drm(adev), crtc);
3084                 }
3085                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3086                 break;
3087         case 1: /* vline */
3088                 if (disp_int & interrupt_status_offsets[crtc].vline)
3089                         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3090                 else
3091                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3092
3093                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3094                 break;
3095         default:
3096                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3097                 break;
3098         }
3099
3100         return 0;
3101 }
3102
3103 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3104                                                  struct amdgpu_irq_src *src,
3105                                                  unsigned type,
3106                                                  enum amdgpu_interrupt_state state)
3107 {
3108         u32 reg;
3109
3110         if (type >= adev->mode_info.num_crtc) {
3111                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3112                 return -EINVAL;
3113         }
3114
3115         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3116         if (state == AMDGPU_IRQ_STATE_DISABLE)
3117                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3118                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3119         else
3120                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3121                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3122
3123         return 0;
3124 }
3125
3126 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3127                                 struct amdgpu_irq_src *source,
3128                                 struct amdgpu_iv_entry *entry)
3129 {
3130         unsigned long flags;
3131         unsigned crtc_id;
3132         struct amdgpu_crtc *amdgpu_crtc;
3133         struct amdgpu_flip_work *works;
3134
3135         crtc_id = (entry->src_id - 8) >> 1;
3136         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3137
3138         if (crtc_id >= adev->mode_info.num_crtc) {
3139                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3140                 return -EINVAL;
3141         }
3142
3143         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3144             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3145                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3146                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3147
3148         /* IRQ could occur when in initial stage */
3149         if (amdgpu_crtc == NULL)
3150                 return 0;
3151
3152         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3153         works = amdgpu_crtc->pflip_works;
3154         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3155                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3156                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3157                                                 amdgpu_crtc->pflip_status,
3158                                                 AMDGPU_FLIP_SUBMITTED);
3159                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3160                 return 0;
3161         }
3162
3163         /* page flip completed. clean up */
3164         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3165         amdgpu_crtc->pflip_works = NULL;
3166
3167         /* wakeup usersapce */
3168         if (works->event)
3169                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3170
3171         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3172
3173         drm_crtc_vblank_put(&amdgpu_crtc->base);
3174         schedule_work(&works->unpin_work);
3175
3176         return 0;
3177 }
3178
3179 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3180                             struct amdgpu_irq_src *source,
3181                             struct amdgpu_iv_entry *entry)
3182 {
3183         uint32_t disp_int, mask, tmp;
3184         unsigned hpd;
3185
3186         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3187                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3188                 return 0;
3189         }
3190
3191         hpd = entry->src_data[0];
3192         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3193         mask = interrupt_status_offsets[hpd].hpd;
3194
3195         if (disp_int & mask) {
3196                 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
3197                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3198                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
3199                 schedule_delayed_work(&adev->hotplug_work, 0);
3200                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3201         }
3202
3203         return 0;
3204
3205 }
3206
3207 static int dce_v8_0_set_clockgating_state(void *handle,
3208                                           enum amd_clockgating_state state)
3209 {
3210         return 0;
3211 }
3212
3213 static int dce_v8_0_set_powergating_state(void *handle,
3214                                           enum amd_powergating_state state)
3215 {
3216         return 0;
3217 }
3218
3219 static const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3220         .name = "dce_v8_0",
3221         .early_init = dce_v8_0_early_init,
3222         .late_init = NULL,
3223         .sw_init = dce_v8_0_sw_init,
3224         .sw_fini = dce_v8_0_sw_fini,
3225         .hw_init = dce_v8_0_hw_init,
3226         .hw_fini = dce_v8_0_hw_fini,
3227         .suspend = dce_v8_0_suspend,
3228         .resume = dce_v8_0_resume,
3229         .is_idle = dce_v8_0_is_idle,
3230         .wait_for_idle = dce_v8_0_wait_for_idle,
3231         .soft_reset = dce_v8_0_soft_reset,
3232         .set_clockgating_state = dce_v8_0_set_clockgating_state,
3233         .set_powergating_state = dce_v8_0_set_powergating_state,
3234 };
3235
3236 static void
3237 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3238                           struct drm_display_mode *mode,
3239                           struct drm_display_mode *adjusted_mode)
3240 {
3241         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3242
3243         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3244
3245         /* need to call this here rather than in prepare() since we need some crtc info */
3246         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3247
3248         /* set scaler clears this on some chips */
3249         dce_v8_0_set_interleave(encoder->crtc, mode);
3250
3251         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3252                 dce_v8_0_afmt_enable(encoder, true);
3253                 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3254         }
3255 }
3256
3257 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3258 {
3259         struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3260         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3261         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3262
3263         if ((amdgpu_encoder->active_device &
3264              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3265             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3266              ENCODER_OBJECT_ID_NONE)) {
3267                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3268                 if (dig) {
3269                         dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3270                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3271                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3272                 }
3273         }
3274
3275         amdgpu_atombios_scratch_regs_lock(adev, true);
3276
3277         if (connector) {
3278                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3279
3280                 /* select the clock/data port if it uses a router */
3281                 if (amdgpu_connector->router.cd_valid)
3282                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3283
3284                 /* turn eDP panel on for mode set */
3285                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3286                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3287                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3288         }
3289
3290         /* this is needed for the pll/ss setup to work correctly in some cases */
3291         amdgpu_atombios_encoder_set_crtc_source(encoder);
3292         /* set up the FMT blocks */
3293         dce_v8_0_program_fmt(encoder);
3294 }
3295
3296 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3297 {
3298         struct drm_device *dev = encoder->dev;
3299         struct amdgpu_device *adev = drm_to_adev(dev);
3300
3301         /* need to call this here as we need the crtc set up */
3302         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3303         amdgpu_atombios_scratch_regs_lock(adev, false);
3304 }
3305
3306 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3307 {
3308         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3309         struct amdgpu_encoder_atom_dig *dig;
3310
3311         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3312
3313         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3314                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3315                         dce_v8_0_afmt_enable(encoder, false);
3316                 dig = amdgpu_encoder->enc_priv;
3317                 dig->dig_encoder = -1;
3318         }
3319         amdgpu_encoder->active_device = 0;
3320 }
3321
3322 /* these are handled by the primary encoders */
3323 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3324 {
3325
3326 }
3327
3328 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3329 {
3330
3331 }
3332
3333 static void
3334 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3335                       struct drm_display_mode *mode,
3336                       struct drm_display_mode *adjusted_mode)
3337 {
3338
3339 }
3340
3341 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3342 {
3343
3344 }
3345
3346 static void
3347 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3348 {
3349
3350 }
3351
3352 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3353         .dpms = dce_v8_0_ext_dpms,
3354         .prepare = dce_v8_0_ext_prepare,
3355         .mode_set = dce_v8_0_ext_mode_set,
3356         .commit = dce_v8_0_ext_commit,
3357         .disable = dce_v8_0_ext_disable,
3358         /* no detect for TMDS/LVDS yet */
3359 };
3360
3361 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3362         .dpms = amdgpu_atombios_encoder_dpms,
3363         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3364         .prepare = dce_v8_0_encoder_prepare,
3365         .mode_set = dce_v8_0_encoder_mode_set,
3366         .commit = dce_v8_0_encoder_commit,
3367         .disable = dce_v8_0_encoder_disable,
3368         .detect = amdgpu_atombios_encoder_dig_detect,
3369 };
3370
3371 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3372         .dpms = amdgpu_atombios_encoder_dpms,
3373         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3374         .prepare = dce_v8_0_encoder_prepare,
3375         .mode_set = dce_v8_0_encoder_mode_set,
3376         .commit = dce_v8_0_encoder_commit,
3377         .detect = amdgpu_atombios_encoder_dac_detect,
3378 };
3379
3380 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3381 {
3382         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3383         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3384                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3385         kfree(amdgpu_encoder->enc_priv);
3386         drm_encoder_cleanup(encoder);
3387         kfree(amdgpu_encoder);
3388 }
3389
3390 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3391         .destroy = dce_v8_0_encoder_destroy,
3392 };
3393
3394 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3395                                  uint32_t encoder_enum,
3396                                  uint32_t supported_device,
3397                                  u16 caps)
3398 {
3399         struct drm_device *dev = adev_to_drm(adev);
3400         struct drm_encoder *encoder;
3401         struct amdgpu_encoder *amdgpu_encoder;
3402
3403         /* see if we already added it */
3404         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3405                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3406                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3407                         amdgpu_encoder->devices |= supported_device;
3408                         return;
3409                 }
3410
3411         }
3412
3413         /* add a new one */
3414         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3415         if (!amdgpu_encoder)
3416                 return;
3417
3418         encoder = &amdgpu_encoder->base;
3419         switch (adev->mode_info.num_crtc) {
3420         case 1:
3421                 encoder->possible_crtcs = 0x1;
3422                 break;
3423         case 2:
3424         default:
3425                 encoder->possible_crtcs = 0x3;
3426                 break;
3427         case 4:
3428                 encoder->possible_crtcs = 0xf;
3429                 break;
3430         case 6:
3431                 encoder->possible_crtcs = 0x3f;
3432                 break;
3433         }
3434
3435         amdgpu_encoder->enc_priv = NULL;
3436
3437         amdgpu_encoder->encoder_enum = encoder_enum;
3438         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3439         amdgpu_encoder->devices = supported_device;
3440         amdgpu_encoder->rmx_type = RMX_OFF;
3441         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3442         amdgpu_encoder->is_ext_encoder = false;
3443         amdgpu_encoder->caps = caps;
3444
3445         switch (amdgpu_encoder->encoder_id) {
3446         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3447         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3448                 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3449                                  DRM_MODE_ENCODER_DAC, NULL);
3450                 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3451                 break;
3452         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3453         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3454         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3455         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3456         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3457                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3458                         amdgpu_encoder->rmx_type = RMX_FULL;
3459                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3460                                          DRM_MODE_ENCODER_LVDS, NULL);
3461                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3462                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3463                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3464                                          DRM_MODE_ENCODER_DAC, NULL);
3465                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3466                 } else {
3467                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3468                                          DRM_MODE_ENCODER_TMDS, NULL);
3469                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3470                 }
3471                 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3472                 break;
3473         case ENCODER_OBJECT_ID_SI170B:
3474         case ENCODER_OBJECT_ID_CH7303:
3475         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3476         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3477         case ENCODER_OBJECT_ID_TITFP513:
3478         case ENCODER_OBJECT_ID_VT1623:
3479         case ENCODER_OBJECT_ID_HDMI_SI1930:
3480         case ENCODER_OBJECT_ID_TRAVIS:
3481         case ENCODER_OBJECT_ID_NUTMEG:
3482                 /* these are handled by the primary encoders */
3483                 amdgpu_encoder->is_ext_encoder = true;
3484                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3485                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3486                                          DRM_MODE_ENCODER_LVDS, NULL);
3487                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3488                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3489                                          DRM_MODE_ENCODER_DAC, NULL);
3490                 else
3491                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3492                                          DRM_MODE_ENCODER_TMDS, NULL);
3493                 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3494                 break;
3495         }
3496 }
3497
3498 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3499         .bandwidth_update = &dce_v8_0_bandwidth_update,
3500         .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3501         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3502         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3503         .hpd_sense = &dce_v8_0_hpd_sense,
3504         .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3505         .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3506         .page_flip = &dce_v8_0_page_flip,
3507         .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3508         .add_encoder = &dce_v8_0_encoder_add,
3509         .add_connector = &amdgpu_connector_add,
3510 };
3511
3512 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3513 {
3514         adev->mode_info.funcs = &dce_v8_0_display_funcs;
3515 }
3516
3517 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3518         .set = dce_v8_0_set_crtc_interrupt_state,
3519         .process = dce_v8_0_crtc_irq,
3520 };
3521
3522 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3523         .set = dce_v8_0_set_pageflip_interrupt_state,
3524         .process = dce_v8_0_pageflip_irq,
3525 };
3526
3527 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3528         .set = dce_v8_0_set_hpd_interrupt_state,
3529         .process = dce_v8_0_hpd_irq,
3530 };
3531
3532 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3533 {
3534         if (adev->mode_info.num_crtc > 0)
3535                 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3536         else
3537                 adev->crtc_irq.num_types = 0;
3538         adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3539
3540         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3541         adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3542
3543         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3544         adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3545 }
3546
3547 const struct amdgpu_ip_block_version dce_v8_0_ip_block =
3548 {
3549         .type = AMD_IP_BLOCK_TYPE_DCE,
3550         .major = 8,
3551         .minor = 0,
3552         .rev = 0,
3553         .funcs = &dce_v8_0_ip_funcs,
3554 };
3555
3556 const struct amdgpu_ip_block_version dce_v8_1_ip_block =
3557 {
3558         .type = AMD_IP_BLOCK_TYPE_DCE,
3559         .major = 8,
3560         .minor = 1,
3561         .rev = 0,
3562         .funcs = &dce_v8_0_ip_funcs,
3563 };
3564
3565 const struct amdgpu_ip_block_version dce_v8_2_ip_block =
3566 {
3567         .type = AMD_IP_BLOCK_TYPE_DCE,
3568         .major = 8,
3569         .minor = 2,
3570         .rev = 0,
3571         .funcs = &dce_v8_0_ip_funcs,
3572 };
3573
3574 const struct amdgpu_ip_block_version dce_v8_3_ip_block =
3575 {
3576         .type = AMD_IP_BLOCK_TYPE_DCE,
3577         .major = 8,
3578         .minor = 3,
3579         .rev = 0,
3580         .funcs = &dce_v8_0_ip_funcs,
3581 };
3582
3583 const struct amdgpu_ip_block_version dce_v8_5_ip_block =
3584 {
3585         .type = AMD_IP_BLOCK_TYPE_DCE,
3586         .major = 8,
3587         .minor = 5,
3588         .rev = 0,
3589         .funcs = &dce_v8_0_ip_funcs,
3590 };