drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "amdgpu_atomfirmware.h"
  62 #include "bif/bif_4_1_d.h"
  63
  64 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  65
  66 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
  67                                    struct ttm_tt *ttm,
  68                                    struct ttm_resource *bo_mem);
  69 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
  70                                       struct ttm_tt *ttm);
  71
  72 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  73                                     unsigned int type,
  74                                     uint64_t size)
  75 {
  76         return ttm_range_man_init(&adev->mman.bdev, type,
  77                                   false, size >> PAGE_SHIFT);
  78 }
  79
  80 /**
  81  * amdgpu_evict_flags - Compute placement flags
  82  *
  83  * @bo: The buffer object to evict
  84  * @placement: Possible destination(s) for evicted BO
  85  *
  86  * Fill in placement data when ttm_bo_evict() is called
  87  */
  88 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  89                                 struct ttm_placement *placement)
  90 {
  91         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  92         struct amdgpu_bo *abo;
  93         static const struct ttm_place placements = {
  94                 .fpfn = 0,
  95                 .lpfn = 0,
  96                 .mem_type = TTM_PL_SYSTEM,
  97                 .flags = 0
  98         };
  99
 100         /* Don't handle scatter gather BOs */
 101         if (bo->type == ttm_bo_type_sg) {
 102                 placement->num_placement = 0;
 103                 placement->num_busy_placement = 0;
 104                 return;
 105         }
 106
 107         /* Object isn't an AMDGPU object so ignore */
 108         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 109                 placement->placement = &placements;
 110                 placement->busy_placement = &placements;
 111                 placement->num_placement = 1;
 112                 placement->num_busy_placement = 1;
 113                 return;
 114         }
 115
 116         abo = ttm_to_amdgpu_bo(bo);
 117         switch (bo->mem.mem_type) {
 118         case AMDGPU_PL_GDS:
 119         case AMDGPU_PL_GWS:
 120         case AMDGPU_PL_OA:
 121                 placement->num_placement = 0;
 122                 placement->num_busy_placement = 0;
 123                 return;
 124
 125         case TTM_PL_VRAM:
 126                 if (!adev->mman.buffer_funcs_enabled) {
 127                         /* Move to system memory */
 128                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 129                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 130                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 131                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 132
 133                         /* Try evicting to the CPU inaccessible part of VRAM
 134                          * first, but only set GTT as busy placement, so this
 135                          * BO will be evicted to GTT rather than causing other
 136                          * BOs to be evicted from VRAM
 137                          */
 138                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 139                                                          AMDGPU_GEM_DOMAIN_GTT);
 140                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 141                         abo->placements[0].lpfn = 0;
 142                         abo->placement.busy_placement = &abo->placements[1];
 143                         abo->placement.num_busy_placement = 1;
 144                 } else {
 145                         /* Move to GTT memory */
 146                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 147                 }
 148                 break;
 149         case TTM_PL_TT:
 150         default:
 151                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 152                 break;
 153         }
 154         *placement = abo->placement;
 155 }
 156
 157 /**
 158  * amdgpu_verify_access - Verify access for a mmap call
 159  *
 160  * @bo: The buffer object to map
 161  * @filp: The file pointer from the process performing the mmap
 162  *
 163  * This is called by ttm_bo_mmap() to verify whether a process
 164  * has the right to mmap a BO to their process space.
 165  */
 166 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 167 {
 168         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 169
 170         /*
 171          * Don't verify access for KFD BOs. They don't have a GEM
 172          * object associated with them.
 173          */
 174         if (abo->kfd_bo)
 175                 return 0;
 176
 177         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 178                 return -EPERM;
 179         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 180                                           filp->private_data);
 181 }
 182
 183 /**
 184  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 185  *
 186  * @bo: The bo to assign the memory to.
 187  * @mm_node: Memory manager node for drm allocator.
 188  * @mem: The region where the bo resides.
 189  *
 190  */
 191 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 192                                     struct drm_mm_node *mm_node,
 193                                     struct ttm_resource *mem)
 194 {
 195         uint64_t addr = 0;
 196
 197         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 198                 addr = mm_node->start << PAGE_SHIFT;
 199                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 200                                                 mem->mem_type);
 201         }
 202         return addr;
 203 }
 204
 205 /**
 206  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 207  * @offset. It also modifies the offset to be within the drm_mm_node returned
 208  *
 209  * @mem: The region where the bo resides.
 210  * @offset: The offset that drm_mm_node is used for finding.
 211  *
 212  */
 213 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 214                                                uint64_t *offset)
 215 {
 216         struct drm_mm_node *mm_node = mem->mm_node;
 217
 218         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 219                 *offset -= (mm_node->size << PAGE_SHIFT);
 220                 ++mm_node;
 221         }
 222         return mm_node;
 223 }
 224
 225 /**
 226  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 227  * @bo: buffer object to map
 228  * @mem: memory object to map
 229  * @mm_node: drm_mm node object to map
 230  * @num_pages: number of pages to map
 231  * @offset: offset into @mm_node where to start
 232  * @window: which GART window to use
 233  * @ring: DMA ring to use for the copy
 234  * @tmz: if we should setup a TMZ enabled mapping
 235  * @addr: resulting address inside the MC address space
 236  *
 237  * Setup one of the GART windows to access a specific piece of memory or return
 238  * the physical address for local memory.
 239  */
 240 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 241                                  struct ttm_resource *mem,
 242                                  struct drm_mm_node *mm_node,
 243                                  unsigned num_pages, uint64_t offset,
 244                                  unsigned window, struct amdgpu_ring *ring,
 245                                  bool tmz, uint64_t *addr)
 246 {
 247         struct amdgpu_device *adev = ring->adev;
 248         struct amdgpu_job *job;
 249         unsigned num_dw, num_bytes;
 250         struct dma_fence *fence;
 251         uint64_t src_addr, dst_addr;
 252         void *cpu_addr;
 253         uint64_t flags;
 254         unsigned int i;
 255         int r;
 256
 257         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 258                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 259
 260         /* Map only what can't be accessed directly */
 261         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 262                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 263                 return 0;
 264         }
 265
 266         *addr = adev->gmc.gart_start;
 267         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 268                 AMDGPU_GPU_PAGE_SIZE;
 269         *addr += offset & ~PAGE_MASK;
 270
 271         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 272         num_bytes = num_pages * 8;
 273
 274         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 275                                      AMDGPU_IB_POOL_DELAYED, &job);
 276         if (r)
 277                 return r;
 278
 279         src_addr = num_dw * 4;
 280         src_addr += job->ibs[0].gpu_addr;
 281
 282         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 283         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 284         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 285                                 dst_addr, num_bytes, false);
 286
 287         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 288         WARN_ON(job->ibs[0].length_dw > num_dw);
 289
 290         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 291         if (tmz)
 292                 flags |= AMDGPU_PTE_TMZ;
 293
 294         cpu_addr = &job->ibs[0].ptr[num_dw];
 295
 296         if (mem->mem_type == TTM_PL_TT) {
 297                 dma_addr_t *dma_address;
 298
 299                 dma_address = &bo->ttm->dma_address[offset >> PAGE_SHIFT];
 300                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 301                                     cpu_addr);
 302                 if (r)
 303                         goto error_free;
 304         } else {
 305                 dma_addr_t dma_address;
 306
 307                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 308                 dma_address += adev->vm_manager.vram_base_offset;
 309
 310                 for (i = 0; i < num_pages; ++i) {
 311                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 312                                             &dma_address, flags, cpu_addr);
 313                         if (r)
 314                                 goto error_free;
 315
 316                         dma_address += PAGE_SIZE;
 317                 }
 318         }
 319
 320         r = amdgpu_job_submit(job, &adev->mman.entity,
 321                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 322         if (r)
 323                 goto error_free;
 324
 325         dma_fence_put(fence);
 326
 327         return r;
 328
 329 error_free:
 330         amdgpu_job_free(job);
 331         return r;
 332 }
 333
 334 /**
 335  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 336  * @adev: amdgpu device
 337  * @src: buffer/address where to read from
 338  * @dst: buffer/address where to write to
 339  * @size: number of bytes to copy
 340  * @tmz: if a secure copy should be used
 341  * @resv: resv object to sync to
 342  * @f: Returns the last fence if multiple jobs are submitted.
 343  *
 344  * The function copies @size bytes from {src->mem + src->offset} to
 345  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 346  * move and different for a BO to BO copy.
 347  *
 348  */
 349 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 350                                const struct amdgpu_copy_mem *src,
 351                                const struct amdgpu_copy_mem *dst,
 352                                uint64_t size, bool tmz,
 353                                struct dma_resv *resv,
 354                                struct dma_fence **f)
 355 {
 356         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 357                                         AMDGPU_GPU_PAGE_SIZE);
 358
 359         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 360         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 361         struct drm_mm_node *src_mm, *dst_mm;
 362         struct dma_fence *fence = NULL;
 363         int r = 0;
 364
 365         if (!adev->mman.buffer_funcs_enabled) {
 366                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 367                 return -EINVAL;
 368         }
 369
 370         src_offset = src->offset;
 371         if (src->mem->mm_node) {
 372                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 373                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 374         } else {
 375                 src_mm = NULL;
 376                 src_node_size = ULLONG_MAX;
 377         }
 378
 379         dst_offset = dst->offset;
 380         if (dst->mem->mm_node) {
 381                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 382                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 383         } else {
 384                 dst_mm = NULL;
 385                 dst_node_size = ULLONG_MAX;
 386         }
 387
 388         mutex_lock(&adev->mman.gtt_window_lock);
 389
 390         while (size) {
 391                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 392                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 393                 struct dma_fence *next;
 394                 uint32_t cur_size;
 395                 uint64_t from, to;
 396
 397                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 398                  * begins at an offset, then adjust the size accordingly
 399                  */
 400                 cur_size = max(src_page_offset, dst_page_offset);
 401                 cur_size = min(min3(src_node_size, dst_node_size, size),
 402                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 403
 404                 /* Map src to window 0 and dst to window 1. */
 405                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 406                                           PFN_UP(cur_size + src_page_offset),
 407                                           src_offset, 0, ring, tmz, &from);
 408                 if (r)
 409                         goto error;
 410
 411                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 412                                           PFN_UP(cur_size + dst_page_offset),
 413                                           dst_offset, 1, ring, tmz, &to);
 414                 if (r)
 415                         goto error;
 416
 417                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 418                                        resv, &next, false, true, tmz);
 419                 if (r)
 420                         goto error;
 421
 422                 dma_fence_put(fence);
 423                 fence = next;
 424
 425                 size -= cur_size;
 426                 if (!size)
 427                         break;
 428
 429                 src_node_size -= cur_size;
 430                 if (!src_node_size) {
 431                         ++src_mm;
 432                         src_node_size = src_mm->size << PAGE_SHIFT;
 433                         src_offset = 0;
 434                 } else {
 435                         src_offset += cur_size;
 436                 }
 437
 438                 dst_node_size -= cur_size;
 439                 if (!dst_node_size) {
 440                         ++dst_mm;
 441                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 442                         dst_offset = 0;
 443                 } else {
 444                         dst_offset += cur_size;
 445                 }
 446         }
 447 error:
 448         mutex_unlock(&adev->mman.gtt_window_lock);
 449         if (f)
 450                 *f = dma_fence_get(fence);
 451         dma_fence_put(fence);
 452         return r;
 453 }
 454
 455 /**
 456  * amdgpu_move_blit - Copy an entire buffer to another buffer
 457  *
 458  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 459  * help move buffers to and from VRAM.
 460  */
 461 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 462                             bool evict,
 463                             struct ttm_resource *new_mem,
 464                             struct ttm_resource *old_mem)
 465 {
 466         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 467         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 468         struct amdgpu_copy_mem src, dst;
 469         struct dma_fence *fence = NULL;
 470         int r;
 471
 472         src.bo = bo;
 473         dst.bo = bo;
 474         src.mem = old_mem;
 475         dst.mem = new_mem;
 476         src.offset = 0;
 477         dst.offset = 0;
 478
 479         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 480                                        new_mem->num_pages << PAGE_SHIFT,
 481                                        amdgpu_bo_encrypted(abo),
 482                                        bo->base.resv, &fence);
 483         if (r)
 484                 goto error;
 485
 486         /* clear the space being freed */
 487         if (old_mem->mem_type == TTM_PL_VRAM &&
 488             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 489                 struct dma_fence *wipe_fence = NULL;
 490
 491                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 492                                        NULL, &wipe_fence);
 493                 if (r) {
 494                         goto error;
 495                 } else if (wipe_fence) {
 496                         dma_fence_put(fence);
 497                         fence = wipe_fence;
 498                 }
 499         }
 500
 501         /* Always block for VM page tables before committing the new location */
 502         if (bo->type == ttm_bo_type_kernel)
 503                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 504         else
 505                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 506         dma_fence_put(fence);
 507         return r;
 508
 509 error:
 510         if (fence)
 511                 dma_fence_wait(fence, false);
 512         dma_fence_put(fence);
 513         return r;
 514 }
 515
 516 /**
 517  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 518  *
 519  * Called by amdgpu_bo_move().
 520  */
 521 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 522                                 struct ttm_operation_ctx *ctx,
 523                                 struct ttm_resource *new_mem)
 524 {
 525         struct ttm_resource *old_mem = &bo->mem;
 526         struct ttm_resource tmp_mem;
 527         struct ttm_place placements;
 528         struct ttm_placement placement;
 529         int r;
 530
 531         /* create space/pages for new_mem in GTT space */
 532         tmp_mem = *new_mem;
 533         tmp_mem.mm_node = NULL;
 534         placement.num_placement = 1;
 535         placement.placement = &placements;
 536         placement.num_busy_placement = 1;
 537         placement.busy_placement = &placements;
 538         placements.fpfn = 0;
 539         placements.lpfn = 0;
 540         placements.mem_type = TTM_PL_TT;
 541         placements.flags = 0;
 542         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 543         if (unlikely(r)) {
 544                 pr_err("Failed to find GTT space for blit from VRAM\n");
 545                 return r;
 546         }
 547
 548         r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
 549         if (unlikely(r))
 550                 goto out_cleanup;
 551
 552         /* Bind the memory to the GTT space */
 553         r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
 554         if (unlikely(r)) {
 555                 goto out_cleanup;
 556         }
 557
 558         /* blit VRAM to GTT */
 559         r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
 560         if (unlikely(r)) {
 561                 goto out_cleanup;
 562         }
 563
 564         r = ttm_bo_wait_ctx(bo, ctx);
 565         if (unlikely(r))
 566                 goto out_cleanup;
 567
 568         amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 569         ttm_resource_free(bo, &bo->mem);
 570         ttm_bo_assign_mem(bo, new_mem);
 571 out_cleanup:
 572         ttm_resource_free(bo, &tmp_mem);
 573         return r;
 574 }
 575
 576 /**
 577  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 578  *
 579  * Called by amdgpu_bo_move().
 580  */
 581 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 582                                 struct ttm_operation_ctx *ctx,
 583                                 struct ttm_resource *new_mem)
 584 {
 585         struct ttm_resource *old_mem = &bo->mem;
 586         struct ttm_resource tmp_mem;
 587         struct ttm_placement placement;
 588         struct ttm_place placements;
 589         int r;
 590
 591         /* make space in GTT for old_mem buffer */
 592         tmp_mem = *new_mem;
 593         tmp_mem.mm_node = NULL;
 594         placement.num_placement = 1;
 595         placement.placement = &placements;
 596         placement.num_busy_placement = 1;
 597         placement.busy_placement = &placements;
 598         placements.fpfn = 0;
 599         placements.lpfn = 0;
 600         placements.mem_type = TTM_PL_TT;
 601         placements.flags = 0;
 602         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 603         if (unlikely(r)) {
 604                 pr_err("Failed to find GTT space for blit to VRAM\n");
 605                 return r;
 606         }
 607
 608         /* move/bind old memory to GTT space */
 609         r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
 610         if (unlikely(r))
 611                 return r;
 612
 613         r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
 614         if (unlikely(r)) {
 615                 goto out_cleanup;
 616         }
 617
 618         ttm_bo_assign_mem(bo, &tmp_mem);
 619         /* copy to VRAM */
 620         r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 621         if (unlikely(r)) {
 622                 goto out_cleanup;
 623         }
 624 out_cleanup:
 625         ttm_resource_free(bo, &tmp_mem);
 626         return r;
 627 }
 628
 629 /**
 630  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 631  *
 632  * Called by amdgpu_bo_move()
 633  */
 634 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 635                                struct ttm_resource *mem)
 636 {
 637         struct drm_mm_node *nodes = mem->mm_node;
 638
 639         if (mem->mem_type == TTM_PL_SYSTEM ||
 640             mem->mem_type == TTM_PL_TT)
 641                 return true;
 642         if (mem->mem_type != TTM_PL_VRAM)
 643                 return false;
 644
 645         /* ttm_resource_ioremap only supports contiguous memory */
 646         if (nodes->size != mem->num_pages)
 647                 return false;
 648
 649         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 650                 <= adev->gmc.visible_vram_size;
 651 }
 652
 653 /**
 654  * amdgpu_bo_move - Move a buffer object to a new memory location
 655  *
 656  * Called by ttm_bo_handle_move_mem()
 657  */
 658 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 659                           struct ttm_operation_ctx *ctx,
 660                           struct ttm_resource *new_mem)
 661 {
 662         struct amdgpu_device *adev;
 663         struct amdgpu_bo *abo;
 664         struct ttm_resource *old_mem = &bo->mem;
 665         int r;
 666
 667         if (new_mem->mem_type == TTM_PL_TT) {
 668                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 669                 if (r)
 670                         return r;
 671         }
 672
 673         amdgpu_bo_move_notify(bo, evict, new_mem);
 674
 675         /* Can't move a pinned BO */
 676         abo = ttm_to_amdgpu_bo(bo);
 677         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 678                 return -EINVAL;
 679
 680         adev = amdgpu_ttm_adev(bo->bdev);
 681
 682         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 683                 ttm_bo_move_null(bo, new_mem);
 684                 return 0;
 685         }
 686         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 687             new_mem->mem_type == TTM_PL_TT) {
 688                 ttm_bo_move_null(bo, new_mem);
 689                 return 0;
 690         }
 691
 692         if (old_mem->mem_type == TTM_PL_TT &&
 693             new_mem->mem_type == TTM_PL_SYSTEM) {
 694                 r = ttm_bo_wait_ctx(bo, ctx);
 695                 if (r)
 696                         goto fail;
 697
 698                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 699                 ttm_resource_free(bo, &bo->mem);
 700                 ttm_bo_assign_mem(bo, new_mem);
 701                 return 0;
 702         }
 703
 704         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 705             old_mem->mem_type == AMDGPU_PL_GWS ||
 706             old_mem->mem_type == AMDGPU_PL_OA ||
 707             new_mem->mem_type == AMDGPU_PL_GDS ||
 708             new_mem->mem_type == AMDGPU_PL_GWS ||
 709             new_mem->mem_type == AMDGPU_PL_OA) {
 710                 /* Nothing to save here */
 711                 ttm_bo_move_null(bo, new_mem);
 712                 return 0;
 713         }
 714
 715         if (!adev->mman.buffer_funcs_enabled) {
 716                 r = -ENODEV;
 717                 goto memcpy;
 718         }
 719
 720         if (old_mem->mem_type == TTM_PL_VRAM &&
 721             new_mem->mem_type == TTM_PL_SYSTEM) {
 722                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 723         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 724                    new_mem->mem_type == TTM_PL_VRAM) {
 725                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 726         } else {
 727                 r = amdgpu_move_blit(bo, evict,
 728                                      new_mem, old_mem);
 729         }
 730
 731         if (r) {
 732 memcpy:
 733                 /* Check that all memory is CPU accessible */
 734                 if (!amdgpu_mem_visible(adev, old_mem) ||
 735                     !amdgpu_mem_visible(adev, new_mem)) {
 736                         pr_err("Move buffer fallback to memcpy unavailable\n");
 737                         goto fail;
 738                 }
 739
 740                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 741                 if (r)
 742                         goto fail;
 743         }
 744
 745         if (bo->type == ttm_bo_type_device &&
 746             new_mem->mem_type == TTM_PL_VRAM &&
 747             old_mem->mem_type != TTM_PL_VRAM) {
 748                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 749                  * accesses the BO after it's moved.
 750                  */
 751                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 752         }
 753
 754         /* update statistics */
 755         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 756         return 0;
 757 fail:
 758         swap(*new_mem, bo->mem);
 759         amdgpu_bo_move_notify(bo, false, new_mem);
 760         swap(*new_mem, bo->mem);
 761         return r;
 762 }
 763
 764 /**
 765  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 766  *
 767  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 768  */
 769 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 770 {
 771         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 772         struct drm_mm_node *mm_node = mem->mm_node;
 773         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 774
 775         switch (mem->mem_type) {
 776         case TTM_PL_SYSTEM:
 777                 /* system memory */
 778                 return 0;
 779         case TTM_PL_TT:
 780                 break;
 781         case TTM_PL_VRAM:
 782                 mem->bus.offset = mem->start << PAGE_SHIFT;
 783                 /* check if it's visible */
 784                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 785                         return -EINVAL;
 786                 /* Only physically contiguous buffers apply. In a contiguous
 787                  * buffer, size of the first mm_node would match the number of
 788                  * pages in ttm_resource.
 789                  */
 790                 if (adev->mman.aper_base_kaddr &&
 791                     (mm_node->size == mem->num_pages))
 792                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 793                                         mem->bus.offset;
 794
 795                 mem->bus.offset += adev->gmc.aper_base;
 796                 mem->bus.is_iomem = true;
 797                 mem->bus.caching = ttm_write_combined;
 798                 break;
 799         default:
 800                 return -EINVAL;
 801         }
 802         return 0;
 803 }
 804
 805 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 806                                            unsigned long page_offset)
 807 {
 808         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 809         uint64_t offset = (page_offset << PAGE_SHIFT);
 810         struct drm_mm_node *mm;
 811
 812         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 813         offset += adev->gmc.aper_base;
 814         return mm->start + (offset >> PAGE_SHIFT);
 815 }
 816
 817 /**
 818  * amdgpu_ttm_domain_start - Returns GPU start address
 819  * @adev: amdgpu device object
 820  * @type: type of the memory
 821  *
 822  * Returns:
 823  * GPU start address of a memory domain
 824  */
 825
 826 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 827 {
 828         switch (type) {
 829         case TTM_PL_TT:
 830                 return adev->gmc.gart_start;
 831         case TTM_PL_VRAM:
 832                 return adev->gmc.vram_start;
 833         }
 834
 835         return 0;
 836 }
 837
 838 /*
 839  * TTM backend functions.
 840  */
 841 struct amdgpu_ttm_tt {
 842         struct ttm_tt   ttm;
 843         struct drm_gem_object   *gobj;
 844         u64                     offset;
 845         uint64_t                userptr;
 846         struct task_struct      *usertask;
 847         uint32_t                userflags;
 848         bool                    bound;
 849 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 850         struct hmm_range        *range;
 851 #endif
 852 };
 853
 854 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 855 /**
 856  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 857  * memory and start HMM tracking CPU page table update
 858  *
 859  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 860  * once afterwards to stop HMM tracking
 861  */
 862 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 863 {
 864         struct ttm_tt *ttm = bo->tbo.ttm;
 865         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 866         unsigned long start = gtt->userptr;
 867         struct vm_area_struct *vma;
 868         struct hmm_range *range;
 869         unsigned long timeout;
 870         struct mm_struct *mm;
 871         unsigned long i;
 872         int r = 0;
 873
 874         mm = bo->notifier.mm;
 875         if (unlikely(!mm)) {
 876                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 877                 return -EFAULT;
 878         }
 879
 880         /* Another get_user_pages is running at the same time?? */
 881         if (WARN_ON(gtt->range))
 882                 return -EFAULT;
 883
 884         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 885                 return -ESRCH;
 886
 887         range = kzalloc(sizeof(*range), GFP_KERNEL);
 888         if (unlikely(!range)) {
 889                 r = -ENOMEM;
 890                 goto out;
 891         }
 892         range->notifier = &bo->notifier;
 893         range->start = bo->notifier.interval_tree.start;
 894         range->end = bo->notifier.interval_tree.last + 1;
 895         range->default_flags = HMM_PFN_REQ_FAULT;
 896         if (!amdgpu_ttm_tt_is_readonly(ttm))
 897                 range->default_flags |= HMM_PFN_REQ_WRITE;
 898
 899         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 900                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 901         if (unlikely(!range->hmm_pfns)) {
 902                 r = -ENOMEM;
 903                 goto out_free_ranges;
 904         }
 905
 906         mmap_read_lock(mm);
 907         vma = find_vma(mm, start);
 908         if (unlikely(!vma || start < vma->vm_start)) {
 909                 r = -EFAULT;
 910                 goto out_unlock;
 911         }
 912         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 913                 vma->vm_file)) {
 914                 r = -EPERM;
 915                 goto out_unlock;
 916         }
 917         mmap_read_unlock(mm);
 918         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 919
 920 retry:
 921         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 922
 923         mmap_read_lock(mm);
 924         r = hmm_range_fault(range);
 925         mmap_read_unlock(mm);
 926         if (unlikely(r)) {
 927                 /*
 928                  * FIXME: This timeout should encompass the retry from
 929                  * mmu_interval_read_retry() as well.
 930                  */
 931                 if (r == -EBUSY && !time_after(jiffies, timeout))
 932                         goto retry;
 933                 goto out_free_pfns;
 934         }
 935
 936         /*
 937          * Due to default_flags, all pages are HMM_PFN_VALID or
 938          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 939          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 940          */
 941         for (i = 0; i < ttm->num_pages; i++)
 942                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 943
 944         gtt->range = range;
 945         mmput(mm);
 946
 947         return 0;
 948
 949 out_unlock:
 950         mmap_read_unlock(mm);
 951 out_free_pfns:
 952         kvfree(range->hmm_pfns);
 953 out_free_ranges:
 954         kfree(range);
 955 out:
 956         mmput(mm);
 957         return r;
 958 }
 959
 960 /**
 961  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 962  * Check if the pages backing this ttm range have been invalidated
 963  *
 964  * Returns: true if pages are still valid
 965  */
 966 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 967 {
 968         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 969         bool r = false;
 970
 971         if (!gtt || !gtt->userptr)
 972                 return false;
 973
 974         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 975                 gtt->userptr, ttm->num_pages);
 976
 977         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 978                 "No user pages to check\n");
 979
 980         if (gtt->range) {
 981                 /*
 982                  * FIXME: Must always hold notifier_lock for this, and must
 983                  * not ignore the return code.
 984                  */
 985                 r = mmu_interval_read_retry(gtt->range->notifier,
 986                                          gtt->range->notifier_seq);
 987                 kvfree(gtt->range->hmm_pfns);
 988                 kfree(gtt->range);
 989                 gtt->range = NULL;
 990         }
 991
 992         return !r;
 993 }
 994 #endif
 995
 996 /**
 997  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 998  *
 999  * Called by amdgpu_cs_list_validate(). This creates the page list
1000  * that backs user memory and will ultimately be mapped into the device
1001  * address space.
1002  */
1003 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1004 {
1005         unsigned long i;
1006
1007         for (i = 0; i < ttm->num_pages; ++i)
1008                 ttm->pages[i] = pages ? pages[i] : NULL;
1009 }
1010
1011 /**
1012  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
1013  *
1014  * Called by amdgpu_ttm_backend_bind()
1015  **/
1016 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
1017                                      struct ttm_tt *ttm)
1018 {
1019         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1020         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1021         int r;
1022
1023         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1024         enum dma_data_direction direction = write ?
1025                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1026
1027         /* Allocate an SG array and squash pages into it */
1028         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1029                                       ttm->num_pages << PAGE_SHIFT,
1030                                       GFP_KERNEL);
1031         if (r)
1032                 goto release_sg;
1033
1034         /* Map SG to device */
1035         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1036         if (r)
1037                 goto release_sg;
1038
1039         /* convert SG to linear array of pages and dma addresses */
1040         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1041                                          gtt->ttm.dma_address, ttm->num_pages);
1042
1043         return 0;
1044
1045 release_sg:
1046         kfree(ttm->sg);
1047         ttm->sg = NULL;
1048         return r;
1049 }
1050
1051 /**
1052  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1053  */
1054 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
1055                                         struct ttm_tt *ttm)
1056 {
1057         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1058         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1059
1060         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1061         enum dma_data_direction direction = write ?
1062                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1063
1064         /* double check that we don't free the table twice */
1065         if (!ttm->sg->sgl)
1066                 return;
1067
1068         /* unmap the pages mapped to the device */
1069         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1070         sg_free_table(ttm->sg);
1071
1072 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1073         if (gtt->range) {
1074                 unsigned long i;
1075
1076                 for (i = 0; i < ttm->num_pages; i++) {
1077                         if (ttm->pages[i] !=
1078                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1079                                 break;
1080                 }
1081
1082                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1083         }
1084 #endif
1085 }
1086
1087 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1088                                 struct ttm_buffer_object *tbo,
1089                                 uint64_t flags)
1090 {
1091         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1092         struct ttm_tt *ttm = tbo->ttm;
1093         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1094         int r;
1095
1096         if (amdgpu_bo_encrypted(abo))
1097                 flags |= AMDGPU_PTE_TMZ;
1098
1099         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1100                 uint64_t page_idx = 1;
1101
1102                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1103                                 ttm->pages, gtt->ttm.dma_address, flags);
1104                 if (r)
1105                         goto gart_bind_fail;
1106
1107                 /* The memory type of the first page defaults to UC. Now
1108                  * modify the memory type to NC from the second page of
1109                  * the BO onward.
1110                  */
1111                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1112                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1113
1114                 r = amdgpu_gart_bind(adev,
1115                                 gtt->offset + (page_idx << PAGE_SHIFT),
1116                                 ttm->num_pages - page_idx,
1117                                 &ttm->pages[page_idx],
1118                                 &(gtt->ttm.dma_address[page_idx]), flags);
1119         } else {
1120                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1121                                      ttm->pages, gtt->ttm.dma_address, flags);
1122         }
1123
1124 gart_bind_fail:
1125         if (r)
1126                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1127                           ttm->num_pages, gtt->offset);
1128
1129         return r;
1130 }
1131
1132 /**
1133  * amdgpu_ttm_backend_bind - Bind GTT memory
1134  *
1135  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1136  * This handles binding GTT memory to the device address space.
1137  */
1138 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
1139                                    struct ttm_tt *ttm,
1140                                    struct ttm_resource *bo_mem)
1141 {
1142         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1143         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1144         uint64_t flags;
1145         int r = 0;
1146
1147         if (!bo_mem)
1148                 return -EINVAL;
1149
1150         if (gtt->bound)
1151                 return 0;
1152
1153         if (gtt->userptr) {
1154                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1155                 if (r) {
1156                         DRM_ERROR("failed to pin userptr\n");
1157                         return r;
1158                 }
1159         }
1160         if (!ttm->num_pages) {
1161                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
1162                      ttm->num_pages, bo_mem, ttm);
1163         }
1164
1165         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1166             bo_mem->mem_type == AMDGPU_PL_GWS ||
1167             bo_mem->mem_type == AMDGPU_PL_OA)
1168                 return -EINVAL;
1169
1170         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1171                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1172                 return 0;
1173         }
1174
1175         /* compute PTE flags relevant to this BO memory */
1176         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1177
1178         /* bind pages into GART page tables */
1179         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1180         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1181                 ttm->pages, gtt->ttm.dma_address, flags);
1182
1183         if (r)
1184                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1185                           ttm->num_pages, gtt->offset);
1186         gtt->bound = true;
1187         return r;
1188 }
1189
1190 /**
1191  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
1192  * through AGP or GART aperture.
1193  *
1194  * If bo is accessible through AGP aperture, then use AGP aperture
1195  * to access bo; otherwise allocate logical space in GART aperture
1196  * and map bo to GART aperture.
1197  */
1198 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1199 {
1200         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1201         struct ttm_operation_ctx ctx = { false, false };
1202         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1203         struct ttm_resource tmp;
1204         struct ttm_placement placement;
1205         struct ttm_place placements;
1206         uint64_t addr, flags;
1207         int r;
1208
1209         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1210                 return 0;
1211
1212         addr = amdgpu_gmc_agp_addr(bo);
1213         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1214                 bo->mem.start = addr >> PAGE_SHIFT;
1215         } else {
1216
1217                 /* allocate GART space */
1218                 tmp = bo->mem;
1219                 tmp.mm_node = NULL;
1220                 placement.num_placement = 1;
1221                 placement.placement = &placements;
1222                 placement.num_busy_placement = 1;
1223                 placement.busy_placement = &placements;
1224                 placements.fpfn = 0;
1225                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1226                 placements.mem_type = TTM_PL_TT;
1227                 placements.flags = bo->mem.placement;
1228
1229                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1230                 if (unlikely(r))
1231                         return r;
1232
1233                 /* compute PTE flags for this buffer object */
1234                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1235
1236                 /* Bind pages */
1237                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1238                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1239                 if (unlikely(r)) {
1240                         ttm_resource_free(bo, &tmp);
1241                         return r;
1242                 }
1243
1244                 ttm_resource_free(bo, &bo->mem);
1245                 bo->mem = tmp;
1246         }
1247
1248         return 0;
1249 }
1250
1251 /**
1252  * amdgpu_ttm_recover_gart - Rebind GTT pages
1253  *
1254  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1255  * rebind GTT pages during a GPU reset.
1256  */
1257 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1258 {
1259         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1260         uint64_t flags;
1261         int r;
1262
1263         if (!tbo->ttm)
1264                 return 0;
1265
1266         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1267         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1268
1269         return r;
1270 }
1271
1272 /**
1273  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1274  *
1275  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1276  * ttm_tt_destroy().
1277  */
1278 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1279                                       struct ttm_tt *ttm)
1280 {
1281         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1282         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1283         int r;
1284
1285         if (!gtt->bound)
1286                 return;
1287
1288         /* if the pages have userptr pinning then clear that first */
1289         if (gtt->userptr)
1290                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1291
1292         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1293                 return;
1294
1295         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1296         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1297         if (r)
1298                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1299                           gtt->ttm.num_pages, gtt->offset);
1300         gtt->bound = false;
1301 }
1302
1303 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1304                                        struct ttm_tt *ttm)
1305 {
1306         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1307
1308         amdgpu_ttm_backend_unbind(bdev, ttm);
1309         ttm_tt_destroy_common(bdev, ttm);
1310         if (gtt->usertask)
1311                 put_task_struct(gtt->usertask);
1312
1313         ttm_tt_fini(&gtt->ttm);
1314         kfree(gtt);
1315 }
1316
1317 /**
1318  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1319  *
1320  * @bo: The buffer object to create a GTT ttm_tt object around
1321  *
1322  * Called by ttm_tt_create().
1323  */
1324 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1325                                            uint32_t page_flags)
1326 {
1327         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1328         struct amdgpu_ttm_tt *gtt;
1329         enum ttm_caching caching;
1330
1331         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1332         if (gtt == NULL) {
1333                 return NULL;
1334         }
1335         gtt->gobj = &bo->base;
1336
1337         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1338                 caching = ttm_write_combined;
1339         else
1340                 caching = ttm_cached;
1341
1342         /* allocate space for the uninitialized page entries */
1343         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1344                 kfree(gtt);
1345                 return NULL;
1346         }
1347         return &gtt->ttm;
1348 }
1349
1350 /**
1351  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1352  *
1353  * Map the pages of a ttm_tt object to an address space visible
1354  * to the underlying device.
1355  */
1356 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1357                                   struct ttm_tt *ttm,
1358                                   struct ttm_operation_ctx *ctx)
1359 {
1360         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1361         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1362
1363         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1364         if (gtt && gtt->userptr) {
1365                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1366                 if (!ttm->sg)
1367                         return -ENOMEM;
1368
1369                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1370                 return 0;
1371         }
1372
1373         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1374                 if (!ttm->sg) {
1375                         struct dma_buf_attachment *attach;
1376                         struct sg_table *sgt;
1377
1378                         attach = gtt->gobj->import_attach;
1379                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1380                         if (IS_ERR(sgt))
1381                                 return PTR_ERR(sgt);
1382
1383                         ttm->sg = sgt;
1384                 }
1385
1386                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1387                                                  gtt->ttm.dma_address,
1388                                                  ttm->num_pages);
1389                 return 0;
1390         }
1391
1392 #ifdef CONFIG_SWIOTLB
1393         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1394                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1395         }
1396 #endif
1397
1398         /* fall back to generic helper to populate the page array
1399          * and map them to the device */
1400         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1401 }
1402
1403 /**
1404  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1405  *
1406  * Unmaps pages of a ttm_tt object from the device address space and
1407  * unpopulates the page array backing it.
1408  */
1409 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
1410 {
1411         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1412         struct amdgpu_device *adev;
1413
1414         if (gtt && gtt->userptr) {
1415                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1416                 kfree(ttm->sg);
1417                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1418                 return;
1419         }
1420
1421         if (ttm->sg && gtt->gobj->import_attach) {
1422                 struct dma_buf_attachment *attach;
1423
1424                 attach = gtt->gobj->import_attach;
1425                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1426                 ttm->sg = NULL;
1427                 return;
1428         }
1429
1430         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1431                 return;
1432
1433         adev = amdgpu_ttm_adev(bdev);
1434
1435 #ifdef CONFIG_SWIOTLB
1436         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1437                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1438                 return;
1439         }
1440 #endif
1441
1442         /* fall back to generic helper to unmap and unpopulate array */
1443         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1444 }
1445
1446 /**
1447  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1448  * task
1449  *
1450  * @bo: The ttm_buffer_object to bind this userptr to
1451  * @addr:  The address in the current tasks VM space to use
1452  * @flags: Requirements of userptr object.
1453  *
1454  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1455  * to current task
1456  */
1457 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1458                               uint64_t addr, uint32_t flags)
1459 {
1460         struct amdgpu_ttm_tt *gtt;
1461
1462         if (!bo->ttm) {
1463                 /* TODO: We want a separate TTM object type for userptrs */
1464                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1465                 if (bo->ttm == NULL)
1466                         return -ENOMEM;
1467         }
1468
1469         gtt = (void*)bo->ttm;
1470         gtt->userptr = addr;
1471         gtt->userflags = flags;
1472
1473         if (gtt->usertask)
1474                 put_task_struct(gtt->usertask);
1475         gtt->usertask = current->group_leader;
1476         get_task_struct(gtt->usertask);
1477
1478         return 0;
1479 }
1480
1481 /**
1482  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1483  */
1484 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1485 {
1486         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1487
1488         if (gtt == NULL)
1489                 return NULL;
1490
1491         if (gtt->usertask == NULL)
1492                 return NULL;
1493
1494         return gtt->usertask->mm;
1495 }
1496
1497 /**
1498  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1499  * address range for the current task.
1500  *
1501  */
1502 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1503                                   unsigned long end)
1504 {
1505         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1506         unsigned long size;
1507
1508         if (gtt == NULL || !gtt->userptr)
1509                 return false;
1510
1511         /* Return false if no part of the ttm_tt object lies within
1512          * the range
1513          */
1514         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1515         if (gtt->userptr > end || gtt->userptr + size <= start)
1516                 return false;
1517
1518         return true;
1519 }
1520
1521 /**
1522  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1523  */
1524 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1525 {
1526         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1527
1528         if (gtt == NULL || !gtt->userptr)
1529                 return false;
1530
1531         return true;
1532 }
1533
1534 /**
1535  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1536  */
1537 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1538 {
1539         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1540
1541         if (gtt == NULL)
1542                 return false;
1543
1544         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1545 }
1546
1547 /**
1548  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1549  *
1550  * @ttm: The ttm_tt object to compute the flags for
1551  * @mem: The memory registry backing this ttm_tt object
1552  *
1553  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1554  */
1555 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1556 {
1557         uint64_t flags = 0;
1558
1559         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1560                 flags |= AMDGPU_PTE_VALID;
1561
1562         if (mem && mem->mem_type == TTM_PL_TT) {
1563                 flags |= AMDGPU_PTE_SYSTEM;
1564
1565                 if (ttm->caching == ttm_cached)
1566                         flags |= AMDGPU_PTE_SNOOPED;
1567         }
1568
1569         return flags;
1570 }
1571
1572 /**
1573  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1574  *
1575  * @ttm: The ttm_tt object to compute the flags for
1576  * @mem: The memory registry backing this ttm_tt object
1577
1578  * Figure out the flags to use for a VM PTE (Page Table Entry).
1579  */
1580 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1581                                  struct ttm_resource *mem)
1582 {
1583         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1584
1585         flags |= adev->gart.gart_pte_flags;
1586         flags |= AMDGPU_PTE_READABLE;
1587
1588         if (!amdgpu_ttm_tt_is_readonly(ttm))
1589                 flags |= AMDGPU_PTE_WRITEABLE;
1590
1591         return flags;
1592 }
1593
1594 /**
1595  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1596  * object.
1597  *
1598  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1599  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1600  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1601  * used to clean out a memory space.
1602  */
1603 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1604                                             const struct ttm_place *place)
1605 {
1606         unsigned long num_pages = bo->mem.num_pages;
1607         struct drm_mm_node *node = bo->mem.mm_node;
1608         struct dma_resv_list *flist;
1609         struct dma_fence *f;
1610         int i;
1611
1612         if (bo->type == ttm_bo_type_kernel &&
1613             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1614                 return false;
1615
1616         /* If bo is a KFD BO, check if the bo belongs to the current process.
1617          * If true, then return false as any KFD process needs all its BOs to
1618          * be resident to run successfully
1619          */
1620         flist = dma_resv_get_list(bo->base.resv);
1621         if (flist) {
1622                 for (i = 0; i < flist->shared_count; ++i) {
1623                         f = rcu_dereference_protected(flist->shared[i],
1624                                 dma_resv_held(bo->base.resv));
1625                         if (amdkfd_fence_check_mm(f, current->mm))
1626                                 return false;
1627                 }
1628         }
1629
1630         switch (bo->mem.mem_type) {
1631         case TTM_PL_TT:
1632                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1633                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1634                         return false;
1635                 return true;
1636
1637         case TTM_PL_VRAM:
1638                 /* Check each drm MM node individually */
1639                 while (num_pages) {
1640                         if (place->fpfn < (node->start + node->size) &&
1641                             !(place->lpfn && place->lpfn <= node->start))
1642                                 return true;
1643
1644                         num_pages -= node->size;
1645                         ++node;
1646                 }
1647                 return false;
1648
1649         default:
1650                 break;
1651         }
1652
1653         return ttm_bo_eviction_valuable(bo, place);
1654 }
1655
1656 /**
1657  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1658  *
1659  * @bo:  The buffer object to read/write
1660  * @offset:  Offset into buffer object
1661  * @buf:  Secondary buffer to write/read from
1662  * @len: Length in bytes of access
1663  * @write:  true if writing
1664  *
1665  * This is used to access VRAM that backs a buffer object via MMIO
1666  * access for debugging purposes.
1667  */
1668 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1669                                     unsigned long offset,
1670                                     void *buf, int len, int write)
1671 {
1672         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1673         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1674         struct drm_mm_node *nodes;
1675         uint32_t value = 0;
1676         int ret = 0;
1677         uint64_t pos;
1678         unsigned long flags;
1679
1680         if (bo->mem.mem_type != TTM_PL_VRAM)
1681                 return -EIO;
1682
1683         pos = offset;
1684         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1685         pos += (nodes->start << PAGE_SHIFT);
1686
1687         while (len && pos < adev->gmc.mc_vram_size) {
1688                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1689                 uint64_t bytes = 4 - (pos & 3);
1690                 uint32_t shift = (pos & 3) * 8;
1691                 uint32_t mask = 0xffffffff << shift;
1692
1693                 if (len < bytes) {
1694                         mask &= 0xffffffff >> (bytes - len) * 8;
1695                         bytes = len;
1696                 }
1697
1698                 if (mask != 0xffffffff) {
1699                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1700                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1701                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1702                         if (!write || mask != 0xffffffff)
1703                                 value = RREG32_NO_KIQ(mmMM_DATA);
1704                         if (write) {
1705                                 value &= ~mask;
1706                                 value |= (*(uint32_t *)buf << shift) & mask;
1707                                 WREG32_NO_KIQ(mmMM_DATA, value);
1708                         }
1709                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1710                         if (!write) {
1711                                 value = (value & mask) >> shift;
1712                                 memcpy(buf, &value, bytes);
1713                         }
1714                 } else {
1715                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1716                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1717
1718                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1719                                                   bytes, write);
1720                 }
1721
1722                 ret += bytes;
1723                 buf = (uint8_t *)buf + bytes;
1724                 pos += bytes;
1725                 len -= bytes;
1726                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1727                         ++nodes;
1728                         pos = (nodes->start << PAGE_SHIFT);
1729                 }
1730         }
1731
1732         return ret;
1733 }
1734
1735 static void
1736 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1737 {
1738         amdgpu_bo_move_notify(bo, false, NULL);
1739 }
1740
1741 static struct ttm_bo_driver amdgpu_bo_driver = {
1742         .ttm_tt_create = &amdgpu_ttm_tt_create,
1743         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1744         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1745         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1746         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1747         .evict_flags = &amdgpu_evict_flags,
1748         .move = &amdgpu_bo_move,
1749         .verify_access = &amdgpu_verify_access,
1750         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1751         .release_notify = &amdgpu_bo_release_notify,
1752         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1753         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1754         .access_memory = &amdgpu_ttm_access_memory,
1755         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1756 };
1757
1758 /*
1759  * Firmware Reservation functions
1760  */
1761 /**
1762  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1763  *
1764  * @adev: amdgpu_device pointer
1765  *
1766  * free fw reserved vram if it has been reserved.
1767  */
1768 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1769 {
1770         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1771                 NULL, &adev->mman.fw_vram_usage_va);
1772 }
1773
1774 /**
1775  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1776  *
1777  * @adev: amdgpu_device pointer
1778  *
1779  * create bo vram reservation from fw.
1780  */
1781 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1782 {
1783         uint64_t vram_size = adev->gmc.visible_vram_size;
1784
1785         adev->mman.fw_vram_usage_va = NULL;
1786         adev->mman.fw_vram_usage_reserved_bo = NULL;
1787
1788         if (adev->mman.fw_vram_usage_size == 0 ||
1789             adev->mman.fw_vram_usage_size > vram_size)
1790                 return 0;
1791
1792         return amdgpu_bo_create_kernel_at(adev,
1793                                           adev->mman.fw_vram_usage_start_offset,
1794                                           adev->mman.fw_vram_usage_size,
1795                                           AMDGPU_GEM_DOMAIN_VRAM,
1796                                           &adev->mman.fw_vram_usage_reserved_bo,
1797                                           &adev->mman.fw_vram_usage_va);
1798 }
1799
1800 /*
1801  * Memoy training reservation functions
1802  */
1803
1804 /**
1805  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1806  *
1807  * @adev: amdgpu_device pointer
1808  *
1809  * free memory training reserved vram if it has been reserved.
1810  */
1811 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1812 {
1813         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1814
1815         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1816         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1817         ctx->c2p_bo = NULL;
1818
1819         return 0;
1820 }
1821
1822 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1823 {
1824         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1825
1826         memset(ctx, 0, sizeof(*ctx));
1827
1828         ctx->c2p_train_data_offset =
1829                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1830         ctx->p2c_train_data_offset =
1831                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1832         ctx->train_data_size =
1833                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1834
1835         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1836                         ctx->train_data_size,
1837                         ctx->p2c_train_data_offset,
1838                         ctx->c2p_train_data_offset);
1839 }
1840
1841 /*
1842  * reserve TMR memory at the top of VRAM which holds
1843  * IP Discovery data and is protected by PSP.
1844  */
1845 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1846 {
1847         int ret;
1848         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1849         bool mem_train_support = false;
1850
1851         if (!amdgpu_sriov_vf(adev)) {
1852                 ret = amdgpu_mem_train_support(adev);
1853                 if (ret == 1)
1854                         mem_train_support = true;
1855                 else if (ret == -1)
1856                         return -EINVAL;
1857                 else
1858                         DRM_DEBUG("memory training does not support!\n");
1859         }
1860
1861         /*
1862          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1863          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1864          *
1865          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1866          * discovery data and G6 memory training data respectively
1867          */
1868         adev->mman.discovery_tmr_size =
1869                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1870         if (!adev->mman.discovery_tmr_size)
1871                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1872
1873         if (mem_train_support) {
1874                 /* reserve vram for mem train according to TMR location */
1875                 amdgpu_ttm_training_data_block_init(adev);
1876                 ret = amdgpu_bo_create_kernel_at(adev,
1877                                          ctx->c2p_train_data_offset,
1878                                          ctx->train_data_size,
1879                                          AMDGPU_GEM_DOMAIN_VRAM,
1880                                          &ctx->c2p_bo,
1881                                          NULL);
1882                 if (ret) {
1883                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1884                         amdgpu_ttm_training_reserve_vram_fini(adev);
1885                         return ret;
1886                 }
1887                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1888         }
1889
1890         ret = amdgpu_bo_create_kernel_at(adev,
1891                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1892                                 adev->mman.discovery_tmr_size,
1893                                 AMDGPU_GEM_DOMAIN_VRAM,
1894                                 &adev->mman.discovery_memory,
1895                                 NULL);
1896         if (ret) {
1897                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1898                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1899                 return ret;
1900         }
1901
1902         return 0;
1903 }
1904
1905 /**
1906  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1907  * gtt/vram related fields.
1908  *
1909  * This initializes all of the memory space pools that the TTM layer
1910  * will need such as the GTT space (system memory mapped to the device),
1911  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1912  * can be mapped per VMID.
1913  */
1914 int amdgpu_ttm_init(struct amdgpu_device *adev)
1915 {
1916         uint64_t gtt_size;
1917         int r;
1918         u64 vis_vram_limit;
1919
1920         mutex_init(&adev->mman.gtt_window_lock);
1921
1922         /* No others user of address space so set it to 0 */
1923         r = ttm_bo_device_init(&adev->mman.bdev,
1924                                &amdgpu_bo_driver,
1925                                adev_to_drm(adev)->anon_inode->i_mapping,
1926                                adev_to_drm(adev)->vma_offset_manager,
1927                                dma_addressing_limited(adev->dev));
1928         if (r) {
1929                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1930                 return r;
1931         }
1932         adev->mman.initialized = true;
1933
1934         /* We opt to avoid OOM on system pages allocations */
1935         adev->mman.bdev.no_retry = true;
1936
1937         /* Initialize VRAM pool with all of VRAM divided into pages */
1938         r = amdgpu_vram_mgr_init(adev);
1939         if (r) {
1940                 DRM_ERROR("Failed initializing VRAM heap.\n");
1941                 return r;
1942         }
1943
1944         /* Reduce size of CPU-visible VRAM if requested */
1945         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1946         if (amdgpu_vis_vram_limit > 0 &&
1947             vis_vram_limit <= adev->gmc.visible_vram_size)
1948                 adev->gmc.visible_vram_size = vis_vram_limit;
1949
1950         /* Change the size here instead of the init above so only lpfn is affected */
1951         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1952 #ifdef CONFIG_64BIT
1953         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1954                                                 adev->gmc.visible_vram_size);
1955 #endif
1956
1957         /*
1958          *The reserved vram for firmware must be pinned to the specified
1959          *place on the VRAM, so reserve it early.
1960          */
1961         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1962         if (r) {
1963                 return r;
1964         }
1965
1966         /*
1967          * only NAVI10 and onwards ASIC support for IP discovery.
1968          * If IP discovery enabled, a block of memory should be
1969          * reserved for IP discovey.
1970          */
1971         if (adev->mman.discovery_bin) {
1972                 r = amdgpu_ttm_reserve_tmr(adev);
1973                 if (r)
1974                         return r;
1975         }
1976
1977         /* allocate memory as required for VGA
1978          * This is used for VGA emulation and pre-OS scanout buffers to
1979          * avoid display artifacts while transitioning between pre-OS
1980          * and driver.  */
1981         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1982                                        AMDGPU_GEM_DOMAIN_VRAM,
1983                                        &adev->mman.stolen_vga_memory,
1984                                        NULL);
1985         if (r)
1986                 return r;
1987         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1988                                        adev->mman.stolen_extended_size,
1989                                        AMDGPU_GEM_DOMAIN_VRAM,
1990                                        &adev->mman.stolen_extended_memory,
1991                                        NULL);
1992         if (r)
1993                 return r;
1994
1995         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1996                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1997
1998         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1999          * or whatever the user passed on module init */
2000         if (amdgpu_gtt_size == -1) {
2001                 struct sysinfo si;
2002
2003                 si_meminfo(&si);
2004                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
2005                                adev->gmc.mc_vram_size),
2006                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
2007         }
2008         else
2009                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
2010
2011         /* Initialize GTT memory pool */
2012         r = amdgpu_gtt_mgr_init(adev, gtt_size);
2013         if (r) {
2014                 DRM_ERROR("Failed initializing GTT heap.\n");
2015                 return r;
2016         }
2017         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
2018                  (unsigned)(gtt_size / (1024 * 1024)));
2019
2020         /* Initialize various on-chip memory pools */
2021         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
2022         if (r) {
2023                 DRM_ERROR("Failed initializing GDS heap.\n");
2024                 return r;
2025         }
2026
2027         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
2028         if (r) {
2029                 DRM_ERROR("Failed initializing gws heap.\n");
2030                 return r;
2031         }
2032
2033         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
2034         if (r) {
2035                 DRM_ERROR("Failed initializing oa heap.\n");
2036                 return r;
2037         }
2038
2039         return 0;
2040 }
2041
2042 /**
2043  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2044  */
2045 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2046 {
2047         /* return the VGA stolen memory (if any) back to VRAM */
2048         if (!adev->mman.keep_stolen_vga_memory)
2049                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2050         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2051 }
2052
2053 /**
2054  * amdgpu_ttm_fini - De-initialize the TTM memory pools
2055  */
2056 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2057 {
2058         if (!adev->mman.initialized)
2059                 return;
2060
2061         amdgpu_ttm_training_reserve_vram_fini(adev);
2062         /* return the stolen vga memory back to VRAM */
2063         if (adev->mman.keep_stolen_vga_memory)
2064                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2065         /* return the IP Discovery TMR memory back to VRAM */
2066         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
2067         amdgpu_ttm_fw_reserve_vram_fini(adev);
2068
2069         if (adev->mman.aper_base_kaddr)
2070                 iounmap(adev->mman.aper_base_kaddr);
2071         adev->mman.aper_base_kaddr = NULL;
2072
2073         amdgpu_vram_mgr_fini(adev);
2074         amdgpu_gtt_mgr_fini(adev);
2075         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2076         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2077         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2078         ttm_bo_device_release(&adev->mman.bdev);
2079         adev->mman.initialized = false;
2080         DRM_INFO("amdgpu: ttm finalized\n");
2081 }
2082
2083 /**
2084  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2085  *
2086  * @adev: amdgpu_device pointer
2087  * @enable: true when we can use buffer functions.
2088  *
2089  * Enable/disable use of buffer functions during suspend/resume. This should
2090  * only be called at bootup or when userspace isn't running.
2091  */
2092 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2093 {
2094         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2095         uint64_t size;
2096         int r;
2097
2098         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2099             adev->mman.buffer_funcs_enabled == enable)
2100                 return;
2101
2102         if (enable) {
2103                 struct amdgpu_ring *ring;
2104                 struct drm_gpu_scheduler *sched;
2105
2106                 ring = adev->mman.buffer_funcs_ring;
2107                 sched = &ring->sched;
2108                 r = drm_sched_entity_init(&adev->mman.entity,
2109                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2110                                           1, NULL);
2111                 if (r) {
2112                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2113                                   r);
2114                         return;
2115                 }
2116         } else {
2117                 drm_sched_entity_destroy(&adev->mman.entity);
2118                 dma_fence_put(man->move);
2119                 man->move = NULL;
2120         }
2121
2122         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2123         if (enable)
2124                 size = adev->gmc.real_vram_size;
2125         else
2126                 size = adev->gmc.visible_vram_size;
2127         man->size = size >> PAGE_SHIFT;
2128         adev->mman.buffer_funcs_enabled = enable;
2129 }
2130
2131 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
2132 {
2133         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
2134         vm_fault_t ret;
2135
2136         ret = ttm_bo_vm_reserve(bo, vmf);
2137         if (ret)
2138                 return ret;
2139
2140         ret = amdgpu_bo_fault_reserve_notify(bo);
2141         if (ret)
2142                 goto unlock;
2143
2144         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
2145                                        TTM_BO_VM_NUM_PREFAULT, 1);
2146         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
2147                 return ret;
2148
2149 unlock:
2150         dma_resv_unlock(bo->base.resv);
2151         return ret;
2152 }
2153
2154 static struct vm_operations_struct amdgpu_ttm_vm_ops = {
2155         .fault = amdgpu_ttm_fault,
2156         .open = ttm_bo_vm_open,
2157         .close = ttm_bo_vm_close,
2158         .access = ttm_bo_vm_access
2159 };
2160
2161 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2162 {
2163         struct drm_file *file_priv = filp->private_data;
2164         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2165         int r;
2166
2167         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2168         if (unlikely(r != 0))
2169                 return r;
2170
2171         vma->vm_ops = &amdgpu_ttm_vm_ops;
2172         return 0;
2173 }
2174
2175 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2176                        uint64_t dst_offset, uint32_t byte_count,
2177                        struct dma_resv *resv,
2178                        struct dma_fence **fence, bool direct_submit,
2179                        bool vm_needs_flush, bool tmz)
2180 {
2181         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2182                 AMDGPU_IB_POOL_DELAYED;
2183         struct amdgpu_device *adev = ring->adev;
2184         struct amdgpu_job *job;
2185
2186         uint32_t max_bytes;
2187         unsigned num_loops, num_dw;
2188         unsigned i;
2189         int r;
2190
2191         if (direct_submit && !ring->sched.ready) {
2192                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2193                 return -EINVAL;
2194         }
2195
2196         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2197         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2198         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2199
2200         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2201         if (r)
2202                 return r;
2203
2204         if (vm_needs_flush) {
2205                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2206                 job->vm_needs_flush = true;
2207         }
2208         if (resv) {
2209                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2210                                      AMDGPU_SYNC_ALWAYS,
2211                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2212                 if (r) {
2213                         DRM_ERROR("sync failed (%d).\n", r);
2214                         goto error_free;
2215                 }
2216         }
2217
2218         for (i = 0; i < num_loops; i++) {
2219                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2220
2221                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2222                                         dst_offset, cur_size_in_bytes, tmz);
2223
2224                 src_offset += cur_size_in_bytes;
2225                 dst_offset += cur_size_in_bytes;
2226                 byte_count -= cur_size_in_bytes;
2227         }
2228
2229         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2230         WARN_ON(job->ibs[0].length_dw > num_dw);
2231         if (direct_submit)
2232                 r = amdgpu_job_submit_direct(job, ring, fence);
2233         else
2234                 r = amdgpu_job_submit(job, &adev->mman.entity,
2235                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2236         if (r)
2237                 goto error_free;
2238
2239         return r;
2240
2241 error_free:
2242         amdgpu_job_free(job);
2243         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2244         return r;
2245 }
2246
2247 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2248                        uint32_t src_data,
2249                        struct dma_resv *resv,
2250                        struct dma_fence **fence)
2251 {
2252         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2253         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2254         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2255
2256         struct drm_mm_node *mm_node;
2257         unsigned long num_pages;
2258         unsigned int num_loops, num_dw;
2259
2260         struct amdgpu_job *job;
2261         int r;
2262
2263         if (!adev->mman.buffer_funcs_enabled) {
2264                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2265                 return -EINVAL;
2266         }
2267
2268         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2269                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2270                 if (r)
2271                         return r;
2272         }
2273
2274         num_pages = bo->tbo.num_pages;
2275         mm_node = bo->tbo.mem.mm_node;
2276         num_loops = 0;
2277         while (num_pages) {
2278                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2279
2280                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2281                 num_pages -= mm_node->size;
2282                 ++mm_node;
2283         }
2284         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2285
2286         /* for IB padding */
2287         num_dw += 64;
2288
2289         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2290                                      &job);
2291         if (r)
2292                 return r;
2293
2294         if (resv) {
2295                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2296                                      AMDGPU_SYNC_ALWAYS,
2297                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2298                 if (r) {
2299                         DRM_ERROR("sync failed (%d).\n", r);
2300                         goto error_free;
2301                 }
2302         }
2303
2304         num_pages = bo->tbo.num_pages;
2305         mm_node = bo->tbo.mem.mm_node;
2306
2307         while (num_pages) {
2308                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2309                 uint64_t dst_addr;
2310
2311                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2312                 while (byte_count) {
2313                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2314                                                            max_bytes);
2315
2316                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2317                                                 dst_addr, cur_size_in_bytes);
2318
2319                         dst_addr += cur_size_in_bytes;
2320                         byte_count -= cur_size_in_bytes;
2321                 }
2322
2323                 num_pages -= mm_node->size;
2324                 ++mm_node;
2325         }
2326
2327         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2328         WARN_ON(job->ibs[0].length_dw > num_dw);
2329         r = amdgpu_job_submit(job, &adev->mman.entity,
2330                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2331         if (r)
2332                 goto error_free;
2333
2334         return 0;
2335
2336 error_free:
2337         amdgpu_job_free(job);
2338         return r;
2339 }
2340
2341 #if defined(CONFIG_DEBUG_FS)
2342
2343 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2344 {
2345         struct drm_info_node *node = (struct drm_info_node *)m->private;
2346         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2347         struct drm_device *dev = node->minor->dev;
2348         struct amdgpu_device *adev = drm_to_adev(dev);
2349         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2350         struct drm_printer p = drm_seq_file_printer(m);
2351
2352         man->func->debug(man, &p);
2353         return 0;
2354 }
2355
2356 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2357         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2358         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2359         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2360         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2361         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2362         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2363 #ifdef CONFIG_SWIOTLB
2364         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2365 #endif
2366 };
2367
2368 /**
2369  * amdgpu_ttm_vram_read - Linear read access to VRAM
2370  *
2371  * Accesses VRAM via MMIO for debugging purposes.
2372  */
2373 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2374                                     size_t size, loff_t *pos)
2375 {
2376         struct amdgpu_device *adev = file_inode(f)->i_private;
2377         ssize_t result = 0;
2378
2379         if (size & 0x3 || *pos & 0x3)
2380                 return -EINVAL;
2381
2382         if (*pos >= adev->gmc.mc_vram_size)
2383                 return -ENXIO;
2384
2385         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2386         while (size) {
2387                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2388                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2389
2390                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2391                 if (copy_to_user(buf, value, bytes))
2392                         return -EFAULT;
2393
2394                 result += bytes;
2395                 buf += bytes;
2396                 *pos += bytes;
2397                 size -= bytes;
2398         }
2399
2400         return result;
2401 }
2402
2403 /**
2404  * amdgpu_ttm_vram_write - Linear write access to VRAM
2405  *
2406  * Accesses VRAM via MMIO for debugging purposes.
2407  */
2408 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2409                                     size_t size, loff_t *pos)
2410 {
2411         struct amdgpu_device *adev = file_inode(f)->i_private;
2412         ssize_t result = 0;
2413         int r;
2414
2415         if (size & 0x3 || *pos & 0x3)
2416                 return -EINVAL;
2417
2418         if (*pos >= adev->gmc.mc_vram_size)
2419                 return -ENXIO;
2420
2421         while (size) {
2422                 unsigned long flags;
2423                 uint32_t value;
2424
2425                 if (*pos >= adev->gmc.mc_vram_size)
2426                         return result;
2427
2428                 r = get_user(value, (uint32_t *)buf);
2429                 if (r)
2430                         return r;
2431
2432                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2433                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2434                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2435                 WREG32_NO_KIQ(mmMM_DATA, value);
2436                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2437
2438                 result += 4;
2439                 buf += 4;
2440                 *pos += 4;
2441                 size -= 4;
2442         }
2443
2444         return result;
2445 }
2446
2447 static const struct file_operations amdgpu_ttm_vram_fops = {
2448         .owner = THIS_MODULE,
2449         .read = amdgpu_ttm_vram_read,
2450         .write = amdgpu_ttm_vram_write,
2451         .llseek = default_llseek,
2452 };
2453
2454 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2455
2456 /**
2457  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2458  */
2459 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2460                                    size_t size, loff_t *pos)
2461 {
2462         struct amdgpu_device *adev = file_inode(f)->i_private;
2463         ssize_t result = 0;
2464         int r;
2465
2466         while (size) {
2467                 loff_t p = *pos / PAGE_SIZE;
2468                 unsigned off = *pos & ~PAGE_MASK;
2469                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2470                 struct page *page;
2471                 void *ptr;
2472
2473                 if (p >= adev->gart.num_cpu_pages)
2474                         return result;
2475
2476                 page = adev->gart.pages[p];
2477                 if (page) {
2478                         ptr = kmap(page);
2479                         ptr += off;
2480
2481                         r = copy_to_user(buf, ptr, cur_size);
2482                         kunmap(adev->gart.pages[p]);
2483                 } else
2484                         r = clear_user(buf, cur_size);
2485
2486                 if (r)
2487                         return -EFAULT;
2488
2489                 result += cur_size;
2490                 buf += cur_size;
2491                 *pos += cur_size;
2492                 size -= cur_size;
2493         }
2494
2495         return result;
2496 }
2497
2498 static const struct file_operations amdgpu_ttm_gtt_fops = {
2499         .owner = THIS_MODULE,
2500         .read = amdgpu_ttm_gtt_read,
2501         .llseek = default_llseek
2502 };
2503
2504 #endif
2505
2506 /**
2507  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2508  *
2509  * This function is used to read memory that has been mapped to the
2510  * GPU and the known addresses are not physical addresses but instead
2511  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2512  */
2513 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2514                                  size_t size, loff_t *pos)
2515 {
2516         struct amdgpu_device *adev = file_inode(f)->i_private;
2517         struct iommu_domain *dom;
2518         ssize_t result = 0;
2519         int r;
2520
2521         /* retrieve the IOMMU domain if any for this device */
2522         dom = iommu_get_domain_for_dev(adev->dev);
2523
2524         while (size) {
2525                 phys_addr_t addr = *pos & PAGE_MASK;
2526                 loff_t off = *pos & ~PAGE_MASK;
2527                 size_t bytes = PAGE_SIZE - off;
2528                 unsigned long pfn;
2529                 struct page *p;
2530                 void *ptr;
2531
2532                 bytes = bytes < size ? bytes : size;
2533
2534                 /* Translate the bus address to a physical address.  If
2535                  * the domain is NULL it means there is no IOMMU active
2536                  * and the address translation is the identity
2537                  */
2538                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2539
2540                 pfn = addr >> PAGE_SHIFT;
2541                 if (!pfn_valid(pfn))
2542                         return -EPERM;
2543
2544                 p = pfn_to_page(pfn);
2545                 if (p->mapping != adev->mman.bdev.dev_mapping)
2546                         return -EPERM;
2547
2548                 ptr = kmap(p);
2549                 r = copy_to_user(buf, ptr + off, bytes);
2550                 kunmap(p);
2551                 if (r)
2552                         return -EFAULT;
2553
2554                 size -= bytes;
2555                 *pos += bytes;
2556                 result += bytes;
2557         }
2558
2559         return result;
2560 }
2561
2562 /**
2563  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2564  *
2565  * This function is used to write memory that has been mapped to the
2566  * GPU and the known addresses are not physical addresses but instead
2567  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2568  */
2569 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2570                                  size_t size, loff_t *pos)
2571 {
2572         struct amdgpu_device *adev = file_inode(f)->i_private;
2573         struct iommu_domain *dom;
2574         ssize_t result = 0;
2575         int r;
2576
2577         dom = iommu_get_domain_for_dev(adev->dev);
2578
2579         while (size) {
2580                 phys_addr_t addr = *pos & PAGE_MASK;
2581                 loff_t off = *pos & ~PAGE_MASK;
2582                 size_t bytes = PAGE_SIZE - off;
2583                 unsigned long pfn;
2584                 struct page *p;
2585                 void *ptr;
2586
2587                 bytes = bytes < size ? bytes : size;
2588
2589                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2590
2591                 pfn = addr >> PAGE_SHIFT;
2592                 if (!pfn_valid(pfn))
2593                         return -EPERM;
2594
2595                 p = pfn_to_page(pfn);
2596                 if (p->mapping != adev->mman.bdev.dev_mapping)
2597                         return -EPERM;
2598
2599                 ptr = kmap(p);
2600                 r = copy_from_user(ptr + off, buf, bytes);
2601                 kunmap(p);
2602                 if (r)
2603                         return -EFAULT;
2604
2605                 size -= bytes;
2606                 *pos += bytes;
2607                 result += bytes;
2608         }
2609
2610         return result;
2611 }
2612
2613 static const struct file_operations amdgpu_ttm_iomem_fops = {
2614         .owner = THIS_MODULE,
2615         .read = amdgpu_iomem_read,
2616         .write = amdgpu_iomem_write,
2617         .llseek = default_llseek
2618 };
2619
2620 static const struct {
2621         char *name;
2622         const struct file_operations *fops;
2623         int domain;
2624 } ttm_debugfs_entries[] = {
2625         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2626 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2627         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2628 #endif
2629         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2630 };
2631
2632 #endif
2633
2634 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2635 {
2636 #if defined(CONFIG_DEBUG_FS)
2637         unsigned count;
2638
2639         struct drm_minor *minor = adev_to_drm(adev)->primary;
2640         struct dentry *ent, *root = minor->debugfs_root;
2641
2642         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2643                 ent = debugfs_create_file(
2644                                 ttm_debugfs_entries[count].name,
2645                                 S_IFREG | S_IRUGO, root,
2646                                 adev,
2647                                 ttm_debugfs_entries[count].fops);
2648                 if (IS_ERR(ent))
2649                         return PTR_ERR(ent);
2650                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2651                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2652                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2653                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2654                 adev->mman.debugfs_entries[count] = ent;
2655         }
2656
2657         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2658
2659 #ifdef CONFIG_SWIOTLB
2660         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2661                 --count;
2662 #endif
2663
2664         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2665 #else
2666         return 0;
2667 #endif
2668 }