drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/list.h>
  25 #include <linux/slab.h>
  26 #include <linux/pci.h>
  27 #include <linux/acpi.h>
  28 #include <drm/drmP.h>
  29 #include <linux/firmware.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32 #include "cgs_linux.h"
  33 #include "atom.h"
  34 #include "amdgpu_ucode.h"
  35
  36 struct amdgpu_cgs_device {
  37         struct cgs_device base;
  38         struct amdgpu_device *adev;
  39 };
  40
  41 #define CGS_FUNC_ADEV                                                   \
  42         struct amdgpu_device *adev =                                    \
  43                 ((struct amdgpu_cgs_device *)cgs_device)->adev
  44
  45 static void *amdgpu_cgs_register_pp_handle(struct cgs_device *cgs_device,
  46                         int (*call_back_func)(struct amd_pp_init *, void **))
  47 {
  48         CGS_FUNC_ADEV;
  49         struct amd_pp_init pp_init;
  50         struct amd_powerplay *amd_pp;
  51
  52         if (call_back_func == NULL)
  53                 return NULL;
  54
  55         amd_pp = &(adev->powerplay);
  56         pp_init.chip_family = adev->family;
  57         pp_init.chip_id = adev->asic_type;
  58         pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
  59         pp_init.feature_mask = amdgpu_pp_feature_mask;
  60         pp_init.device = cgs_device;
  61         if (call_back_func(&pp_init, &(amd_pp->pp_handle)))
  62                 return NULL;
  63
  64         return adev->powerplay.pp_handle;
  65 }
  66
  67 static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
  68                                     enum cgs_gpu_mem_type type,
  69                                     uint64_t size, uint64_t align,
  70                                     cgs_handle_t *handle)
  71 {
  72         CGS_FUNC_ADEV;
  73         uint16_t flags = 0;
  74         int ret = 0;
  75         uint32_t domain = 0;
  76         struct amdgpu_bo *obj;
  77
  78         /* fail if the alignment is not a power of 2 */
  79         if (((align != 1) && (align & (align - 1)))
  80             || size == 0 || align == 0)
  81                 return -EINVAL;
  82
  83
  84         switch(type) {
  85         case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
  86         case CGS_GPU_MEM_TYPE__VISIBLE_FB:
  87                 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
  88                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
  89                 domain = AMDGPU_GEM_DOMAIN_VRAM;
  90                 break;
  91         case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
  92         case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
  93                 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
  94                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
  95                 domain = AMDGPU_GEM_DOMAIN_VRAM;
  96                 break;
  97         case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
  98                 domain = AMDGPU_GEM_DOMAIN_GTT;
  99                 break;
 100         case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
 101                 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 102                 domain = AMDGPU_GEM_DOMAIN_GTT;
 103                 break;
 104         default:
 105                 return -EINVAL;
 106         }
 107
 108
 109         *handle = 0;
 110
 111         ret = amdgpu_bo_create(adev, size, align, true, domain, flags,
 112                                NULL, NULL, 0, &obj);
 113         if (ret) {
 114                 DRM_ERROR("(%d) bo create failed\n", ret);
 115                 return ret;
 116         }
 117         *handle = (cgs_handle_t)obj;
 118
 119         return ret;
 120 }
 121
 122 static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
 123 {
 124         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 125
 126         if (obj) {
 127                 int r = amdgpu_bo_reserve(obj, true);
 128                 if (likely(r == 0)) {
 129                         amdgpu_bo_kunmap(obj);
 130                         amdgpu_bo_unpin(obj);
 131                         amdgpu_bo_unreserve(obj);
 132                 }
 133                 amdgpu_bo_unref(&obj);
 134
 135         }
 136         return 0;
 137 }
 138
 139 static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
 140                                    uint64_t *mcaddr)
 141 {
 142         int r;
 143         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 144
 145         WARN_ON_ONCE(obj->placement.num_placement > 1);
 146
 147         r = amdgpu_bo_reserve(obj, true);
 148         if (unlikely(r != 0))
 149                 return r;
 150         r = amdgpu_bo_pin(obj, obj->preferred_domains, mcaddr);
 151         amdgpu_bo_unreserve(obj);
 152         return r;
 153 }
 154
 155 static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
 156 {
 157         int r;
 158         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 159         r = amdgpu_bo_reserve(obj, true);
 160         if (unlikely(r != 0))
 161                 return r;
 162         r = amdgpu_bo_unpin(obj);
 163         amdgpu_bo_unreserve(obj);
 164         return r;
 165 }
 166
 167 static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
 168                                    void **map)
 169 {
 170         int r;
 171         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 172         r = amdgpu_bo_reserve(obj, true);
 173         if (unlikely(r != 0))
 174                 return r;
 175         r = amdgpu_bo_kmap(obj, map);
 176         amdgpu_bo_unreserve(obj);
 177         return r;
 178 }
 179
 180 static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
 181 {
 182         int r;
 183         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 184         r = amdgpu_bo_reserve(obj, true);
 185         if (unlikely(r != 0))
 186                 return r;
 187         amdgpu_bo_kunmap(obj);
 188         amdgpu_bo_unreserve(obj);
 189         return r;
 190 }
 191
 192 static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
 193 {
 194         CGS_FUNC_ADEV;
 195         return RREG32(offset);
 196 }
 197
 198 static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
 199                                       uint32_t value)
 200 {
 201         CGS_FUNC_ADEV;
 202         WREG32(offset, value);
 203 }
 204
 205 static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
 206                                              enum cgs_ind_reg space,
 207                                              unsigned index)
 208 {
 209         CGS_FUNC_ADEV;
 210         switch (space) {
 211         case CGS_IND_REG__MMIO:
 212                 return RREG32_IDX(index);
 213         case CGS_IND_REG__PCIE:
 214                 return RREG32_PCIE(index);
 215         case CGS_IND_REG__SMC:
 216                 return RREG32_SMC(index);
 217         case CGS_IND_REG__UVD_CTX:
 218                 return RREG32_UVD_CTX(index);
 219         case CGS_IND_REG__DIDT:
 220                 return RREG32_DIDT(index);
 221         case CGS_IND_REG_GC_CAC:
 222                 return RREG32_GC_CAC(index);
 223         case CGS_IND_REG_SE_CAC:
 224                 return RREG32_SE_CAC(index);
 225         case CGS_IND_REG__AUDIO_ENDPT:
 226                 DRM_ERROR("audio endpt register access not implemented.\n");
 227                 return 0;
 228         }
 229         WARN(1, "Invalid indirect register space");
 230         return 0;
 231 }
 232
 233 static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
 234                                           enum cgs_ind_reg space,
 235                                           unsigned index, uint32_t value)
 236 {
 237         CGS_FUNC_ADEV;
 238         switch (space) {
 239         case CGS_IND_REG__MMIO:
 240                 return WREG32_IDX(index, value);
 241         case CGS_IND_REG__PCIE:
 242                 return WREG32_PCIE(index, value);
 243         case CGS_IND_REG__SMC:
 244                 return WREG32_SMC(index, value);
 245         case CGS_IND_REG__UVD_CTX:
 246                 return WREG32_UVD_CTX(index, value);
 247         case CGS_IND_REG__DIDT:
 248                 return WREG32_DIDT(index, value);
 249         case CGS_IND_REG_GC_CAC:
 250                 return WREG32_GC_CAC(index, value);
 251         case CGS_IND_REG_SE_CAC:
 252                 return WREG32_SE_CAC(index, value);
 253         case CGS_IND_REG__AUDIO_ENDPT:
 254                 DRM_ERROR("audio endpt register access not implemented.\n");
 255                 return;
 256         }
 257         WARN(1, "Invalid indirect register space");
 258 }
 259
 260 static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
 261                                        enum cgs_resource_type resource_type,
 262                                        uint64_t size,
 263                                        uint64_t offset,
 264                                        uint64_t *resource_base)
 265 {
 266         CGS_FUNC_ADEV;
 267
 268         if (resource_base == NULL)
 269                 return -EINVAL;
 270
 271         switch (resource_type) {
 272         case CGS_RESOURCE_TYPE_MMIO:
 273                 if (adev->rmmio_size == 0)
 274                         return -ENOENT;
 275                 if ((offset + size) > adev->rmmio_size)
 276                         return -EINVAL;
 277                 *resource_base = adev->rmmio_base;
 278                 return 0;
 279         case CGS_RESOURCE_TYPE_DOORBELL:
 280                 if (adev->doorbell.size == 0)
 281                         return -ENOENT;
 282                 if ((offset + size) > adev->doorbell.size)
 283                         return -EINVAL;
 284                 *resource_base = adev->doorbell.base;
 285                 return 0;
 286         case CGS_RESOURCE_TYPE_FB:
 287         case CGS_RESOURCE_TYPE_IO:
 288         case CGS_RESOURCE_TYPE_ROM:
 289         default:
 290                 return -EINVAL;
 291         }
 292 }
 293
 294 static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
 295                                                   unsigned table, uint16_t *size,
 296                                                   uint8_t *frev, uint8_t *crev)
 297 {
 298         CGS_FUNC_ADEV;
 299         uint16_t data_start;
 300
 301         if (amdgpu_atom_parse_data_header(
 302                     adev->mode_info.atom_context, table, size,
 303                     frev, crev, &data_start))
 304                 return (uint8_t*)adev->mode_info.atom_context->bios +
 305                         data_start;
 306
 307         return NULL;
 308 }
 309
 310 static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
 311                                               uint8_t *frev, uint8_t *crev)
 312 {
 313         CGS_FUNC_ADEV;
 314
 315         if (amdgpu_atom_parse_cmd_header(
 316                     adev->mode_info.atom_context, table,
 317                     frev, crev))
 318                 return 0;
 319
 320         return -EINVAL;
 321 }
 322
 323 static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
 324                                           void *args)
 325 {
 326         CGS_FUNC_ADEV;
 327
 328         return amdgpu_atom_execute_table(
 329                 adev->mode_info.atom_context, table, args);
 330 }
 331
 332 struct cgs_irq_params {
 333         unsigned src_id;
 334         cgs_irq_source_set_func_t set;
 335         cgs_irq_handler_func_t handler;
 336         void *private_data;
 337 };
 338
 339 static int cgs_set_irq_state(struct amdgpu_device *adev,
 340                              struct amdgpu_irq_src *src,
 341                              unsigned type,
 342                              enum amdgpu_interrupt_state state)
 343 {
 344         struct cgs_irq_params *irq_params =
 345                 (struct cgs_irq_params *)src->data;
 346         if (!irq_params)
 347                 return -EINVAL;
 348         if (!irq_params->set)
 349                 return -EINVAL;
 350         return irq_params->set(irq_params->private_data,
 351                                irq_params->src_id,
 352                                type,
 353                                (int)state);
 354 }
 355
 356 static int cgs_process_irq(struct amdgpu_device *adev,
 357                            struct amdgpu_irq_src *source,
 358                            struct amdgpu_iv_entry *entry)
 359 {
 360         struct cgs_irq_params *irq_params =
 361                 (struct cgs_irq_params *)source->data;
 362         if (!irq_params)
 363                 return -EINVAL;
 364         if (!irq_params->handler)
 365                 return -EINVAL;
 366         return irq_params->handler(irq_params->private_data,
 367                                    irq_params->src_id,
 368                                    entry->iv_entry);
 369 }
 370
 371 static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
 372         .set = cgs_set_irq_state,
 373         .process = cgs_process_irq,
 374 };
 375
 376 static int amdgpu_cgs_add_irq_source(void *cgs_device,
 377                                      unsigned client_id,
 378                                      unsigned src_id,
 379                                      unsigned num_types,
 380                                      cgs_irq_source_set_func_t set,
 381                                      cgs_irq_handler_func_t handler,
 382                                      void *private_data)
 383 {
 384         CGS_FUNC_ADEV;
 385         int ret = 0;
 386         struct cgs_irq_params *irq_params;
 387         struct amdgpu_irq_src *source =
 388                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
 389         if (!source)
 390                 return -ENOMEM;
 391         irq_params =
 392                 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
 393         if (!irq_params) {
 394                 kfree(source);
 395                 return -ENOMEM;
 396         }
 397         source->num_types = num_types;
 398         source->funcs = &cgs_irq_funcs;
 399         irq_params->src_id = src_id;
 400         irq_params->set = set;
 401         irq_params->handler = handler;
 402         irq_params->private_data = private_data;
 403         source->data = (void *)irq_params;
 404         ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
 405         if (ret) {
 406                 kfree(irq_params);
 407                 kfree(source);
 408         }
 409
 410         return ret;
 411 }
 412
 413 static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
 414                               unsigned src_id, unsigned type)
 415 {
 416         CGS_FUNC_ADEV;
 417
 418         if (!adev->irq.client[client_id].sources)
 419                 return -EINVAL;
 420
 421         return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type);
 422 }
 423
 424 static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id,
 425                               unsigned src_id, unsigned type)
 426 {
 427         CGS_FUNC_ADEV;
 428
 429         if (!adev->irq.client[client_id].sources)
 430                 return -EINVAL;
 431
 432         return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type);
 433 }
 434
 435 static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
 436                                   enum amd_ip_block_type block_type,
 437                                   enum amd_clockgating_state state)
 438 {
 439         CGS_FUNC_ADEV;
 440         int i, r = -1;
 441
 442         for (i = 0; i < adev->num_ip_blocks; i++) {
 443                 if (!adev->ip_blocks[i].status.valid)
 444                         continue;
 445
 446                 if (adev->ip_blocks[i].version->type == block_type) {
 447                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
 448                                                                 (void *)adev,
 449                                                                         state);
 450                         break;
 451                 }
 452         }
 453         return r;
 454 }
 455
 456 static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
 457                                   enum amd_ip_block_type block_type,
 458                                   enum amd_powergating_state state)
 459 {
 460         CGS_FUNC_ADEV;
 461         int i, r = -1;
 462
 463         for (i = 0; i < adev->num_ip_blocks; i++) {
 464                 if (!adev->ip_blocks[i].status.valid)
 465                         continue;
 466
 467                 if (adev->ip_blocks[i].version->type == block_type) {
 468                         r = adev->ip_blocks[i].version->funcs->set_powergating_state(
 469                                                                 (void *)adev,
 470                                                                         state);
 471                         break;
 472                 }
 473         }
 474         return r;
 475 }
 476
 477
 478 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
 479 {
 480         CGS_FUNC_ADEV;
 481         enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
 482
 483         switch (fw_type) {
 484         case CGS_UCODE_ID_SDMA0:
 485                 result = AMDGPU_UCODE_ID_SDMA0;
 486                 break;
 487         case CGS_UCODE_ID_SDMA1:
 488                 result = AMDGPU_UCODE_ID_SDMA1;
 489                 break;
 490         case CGS_UCODE_ID_CP_CE:
 491                 result = AMDGPU_UCODE_ID_CP_CE;
 492                 break;
 493         case CGS_UCODE_ID_CP_PFP:
 494                 result = AMDGPU_UCODE_ID_CP_PFP;
 495                 break;
 496         case CGS_UCODE_ID_CP_ME:
 497                 result = AMDGPU_UCODE_ID_CP_ME;
 498                 break;
 499         case CGS_UCODE_ID_CP_MEC:
 500         case CGS_UCODE_ID_CP_MEC_JT1:
 501                 result = AMDGPU_UCODE_ID_CP_MEC1;
 502                 break;
 503         case CGS_UCODE_ID_CP_MEC_JT2:
 504                 /* for VI. JT2 should be the same as JT1, because:
 505                         1, MEC2 and MEC1 use exactly same FW.
 506                         2, JT2 is not pached but JT1 is.
 507                 */
 508                 if (adev->asic_type >= CHIP_TOPAZ)
 509                         result = AMDGPU_UCODE_ID_CP_MEC1;
 510                 else
 511                         result = AMDGPU_UCODE_ID_CP_MEC2;
 512                 break;
 513         case CGS_UCODE_ID_RLC_G:
 514                 result = AMDGPU_UCODE_ID_RLC_G;
 515                 break;
 516         case CGS_UCODE_ID_STORAGE:
 517                 result = AMDGPU_UCODE_ID_STORAGE;
 518                 break;
 519         default:
 520                 DRM_ERROR("Firmware type not supported\n");
 521         }
 522         return result;
 523 }
 524
 525 static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
 526 {
 527         CGS_FUNC_ADEV;
 528         if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
 529                 release_firmware(adev->pm.fw);
 530                 adev->pm.fw = NULL;
 531                 return 0;
 532         }
 533         /* cannot release other firmware because they are not created by cgs */
 534         return -EINVAL;
 535 }
 536
 537 static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
 538                                         enum cgs_ucode_id type)
 539 {
 540         CGS_FUNC_ADEV;
 541         uint16_t fw_version = 0;
 542
 543         switch (type) {
 544                 case CGS_UCODE_ID_SDMA0:
 545                         fw_version = adev->sdma.instance[0].fw_version;
 546                         break;
 547                 case CGS_UCODE_ID_SDMA1:
 548                         fw_version = adev->sdma.instance[1].fw_version;
 549                         break;
 550                 case CGS_UCODE_ID_CP_CE:
 551                         fw_version = adev->gfx.ce_fw_version;
 552                         break;
 553                 case CGS_UCODE_ID_CP_PFP:
 554                         fw_version = adev->gfx.pfp_fw_version;
 555                         break;
 556                 case CGS_UCODE_ID_CP_ME:
 557                         fw_version = adev->gfx.me_fw_version;
 558                         break;
 559                 case CGS_UCODE_ID_CP_MEC:
 560                         fw_version = adev->gfx.mec_fw_version;
 561                         break;
 562                 case CGS_UCODE_ID_CP_MEC_JT1:
 563                         fw_version = adev->gfx.mec_fw_version;
 564                         break;
 565                 case CGS_UCODE_ID_CP_MEC_JT2:
 566                         fw_version = adev->gfx.mec_fw_version;
 567                         break;
 568                 case CGS_UCODE_ID_RLC_G:
 569                         fw_version = adev->gfx.rlc_fw_version;
 570                         break;
 571                 case CGS_UCODE_ID_STORAGE:
 572                         break;
 573                 default:
 574                         DRM_ERROR("firmware type %d do not have version\n", type);
 575                         break;
 576         }
 577         return fw_version;
 578 }
 579
 580 static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device,
 581                                         bool en)
 582 {
 583         CGS_FUNC_ADEV;
 584
 585         if (adev->gfx.rlc.funcs->enter_safe_mode == NULL ||
 586                 adev->gfx.rlc.funcs->exit_safe_mode == NULL)
 587                 return 0;
 588
 589         if (en)
 590                 adev->gfx.rlc.funcs->enter_safe_mode(adev);
 591         else
 592                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 593
 594         return 0;
 595 }
 596
 597 static void amdgpu_cgs_lock_grbm_idx(struct cgs_device *cgs_device,
 598                                         bool lock)
 599 {
 600         CGS_FUNC_ADEV;
 601
 602         if (lock)
 603                 mutex_lock(&adev->grbm_idx_mutex);
 604         else
 605                 mutex_unlock(&adev->grbm_idx_mutex);
 606 }
 607
 608 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
 609                                         enum cgs_ucode_id type,
 610                                         struct cgs_firmware_info *info)
 611 {
 612         CGS_FUNC_ADEV;
 613
 614         if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
 615                 uint64_t gpu_addr;
 616                 uint32_t data_size;
 617                 const struct gfx_firmware_header_v1_0 *header;
 618                 enum AMDGPU_UCODE_ID id;
 619                 struct amdgpu_firmware_info *ucode;
 620
 621                 id = fw_type_convert(cgs_device, type);
 622                 ucode = &adev->firmware.ucode[id];
 623                 if (ucode->fw == NULL)
 624                         return -EINVAL;
 625
 626                 gpu_addr  = ucode->mc_addr;
 627                 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 628                 data_size = le32_to_cpu(header->header.ucode_size_bytes);
 629
 630                 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
 631                     (type == CGS_UCODE_ID_CP_MEC_JT2)) {
 632                         gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
 633                         data_size = le32_to_cpu(header->jt_size) << 2;
 634                 }
 635
 636                 info->kptr = ucode->kaddr;
 637                 info->image_size = data_size;
 638                 info->mc_addr = gpu_addr;
 639                 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
 640
 641                 if (CGS_UCODE_ID_CP_MEC == type)
 642                         info->image_size = le32_to_cpu(header->jt_offset) << 2;
 643
 644                 info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
 645                 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
 646         } else {
 647                 char fw_name[30] = {0};
 648                 int err = 0;
 649                 uint32_t ucode_size;
 650                 uint32_t ucode_start_address;
 651                 const uint8_t *src;
 652                 const struct smc_firmware_header_v1_0 *hdr;
 653                 const struct common_firmware_header *header;
 654                 struct amdgpu_firmware_info *ucode = NULL;
 655
 656                 if (!adev->pm.fw) {
 657                         switch (adev->asic_type) {
 658                         case CHIP_TAHITI:
 659                                 strcpy(fw_name, "radeon/tahiti_smc.bin");
 660                                 break;
 661                         case CHIP_PITCAIRN:
 662                                 if ((adev->pdev->revision == 0x81) &&
 663                                     ((adev->pdev->device == 0x6810) ||
 664                                     (adev->pdev->device == 0x6811))) {
 665                                         info->is_kicker = true;
 666                                         strcpy(fw_name, "radeon/pitcairn_k_smc.bin");
 667                                 } else {
 668                                         strcpy(fw_name, "radeon/pitcairn_smc.bin");
 669                                 }
 670                                 break;
 671                         case CHIP_VERDE:
 672                                 if (((adev->pdev->device == 0x6820) &&
 673                                         ((adev->pdev->revision == 0x81) ||
 674                                         (adev->pdev->revision == 0x83))) ||
 675                                     ((adev->pdev->device == 0x6821) &&
 676                                         ((adev->pdev->revision == 0x83) ||
 677                                         (adev->pdev->revision == 0x87))) ||
 678                                     ((adev->pdev->revision == 0x87) &&
 679                                         ((adev->pdev->device == 0x6823) ||
 680                                         (adev->pdev->device == 0x682b)))) {
 681                                         info->is_kicker = true;
 682                                         strcpy(fw_name, "radeon/verde_k_smc.bin");
 683                                 } else {
 684                                         strcpy(fw_name, "radeon/verde_smc.bin");
 685                                 }
 686                                 break;
 687                         case CHIP_OLAND:
 688                                 if (((adev->pdev->revision == 0x81) &&
 689                                         ((adev->pdev->device == 0x6600) ||
 690                                         (adev->pdev->device == 0x6604) ||
 691                                         (adev->pdev->device == 0x6605) ||
 692                                         (adev->pdev->device == 0x6610))) ||
 693                                     ((adev->pdev->revision == 0x83) &&
 694                                         (adev->pdev->device == 0x6610))) {
 695                                         info->is_kicker = true;
 696                                         strcpy(fw_name, "radeon/oland_k_smc.bin");
 697                                 } else {
 698                                         strcpy(fw_name, "radeon/oland_smc.bin");
 699                                 }
 700                                 break;
 701                         case CHIP_HAINAN:
 702                                 if (((adev->pdev->revision == 0x81) &&
 703                                         (adev->pdev->device == 0x6660)) ||
 704                                     ((adev->pdev->revision == 0x83) &&
 705                                         ((adev->pdev->device == 0x6660) ||
 706                                         (adev->pdev->device == 0x6663) ||
 707                                         (adev->pdev->device == 0x6665) ||
 708                                          (adev->pdev->device == 0x6667)))) {
 709                                         info->is_kicker = true;
 710                                         strcpy(fw_name, "radeon/hainan_k_smc.bin");
 711                                 } else if ((adev->pdev->revision == 0xc3) &&
 712                                          (adev->pdev->device == 0x6665)) {
 713                                         info->is_kicker = true;
 714                                         strcpy(fw_name, "radeon/banks_k_2_smc.bin");
 715                                 } else {
 716                                         strcpy(fw_name, "radeon/hainan_smc.bin");
 717                                 }
 718                                 break;
 719                         case CHIP_BONAIRE:
 720                                 if ((adev->pdev->revision == 0x80) ||
 721                                         (adev->pdev->revision == 0x81) ||
 722                                         (adev->pdev->device == 0x665f)) {
 723                                         info->is_kicker = true;
 724                                         strcpy(fw_name, "radeon/bonaire_k_smc.bin");
 725                                 } else {
 726                                         strcpy(fw_name, "radeon/bonaire_smc.bin");
 727                                 }
 728                                 break;
 729                         case CHIP_HAWAII:
 730                                 if (adev->pdev->revision == 0x80) {
 731                                         info->is_kicker = true;
 732                                         strcpy(fw_name, "radeon/hawaii_k_smc.bin");
 733                                 } else {
 734                                         strcpy(fw_name, "radeon/hawaii_smc.bin");
 735                                 }
 736                                 break;
 737                         case CHIP_TOPAZ:
 738                                 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
 739                                     ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
 740                                     ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) {
 741                                         info->is_kicker = true;
 742                                         strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
 743                                 } else
 744                                         strcpy(fw_name, "amdgpu/topaz_smc.bin");
 745                                 break;
 746                         case CHIP_TONGA:
 747                                 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
 748                                     ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
 749                                         info->is_kicker = true;
 750                                         strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
 751                                 } else
 752                                         strcpy(fw_name, "amdgpu/tonga_smc.bin");
 753                                 break;
 754                         case CHIP_FIJI:
 755                                 strcpy(fw_name, "amdgpu/fiji_smc.bin");
 756                                 break;
 757                         case CHIP_POLARIS11:
 758                                 if (type == CGS_UCODE_ID_SMU) {
 759                                         if (((adev->pdev->device == 0x67ef) &&
 760                                              ((adev->pdev->revision == 0xe0) ||
 761                                               (adev->pdev->revision == 0xe2) ||
 762                                               (adev->pdev->revision == 0xe5))) ||
 763                                             ((adev->pdev->device == 0x67ff) &&
 764                                              ((adev->pdev->revision == 0xcf) ||
 765                                               (adev->pdev->revision == 0xef) ||
 766                                               (adev->pdev->revision == 0xff)))) {
 767                                                 info->is_kicker = true;
 768                                                 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
 769                                         } else
 770                                                 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
 771                                 } else if (type == CGS_UCODE_ID_SMU_SK) {
 772                                         strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
 773                                 }
 774                                 break;
 775                         case CHIP_POLARIS10:
 776                                 if (type == CGS_UCODE_ID_SMU) {
 777                                         if ((adev->pdev->device == 0x67df) &&
 778                                             ((adev->pdev->revision == 0xe0) ||
 779                                              (adev->pdev->revision == 0xe3) ||
 780                                              (adev->pdev->revision == 0xe4) ||
 781                                              (adev->pdev->revision == 0xe5) ||
 782                                              (adev->pdev->revision == 0xe7) ||
 783                                              (adev->pdev->revision == 0xef))) {
 784                                                 info->is_kicker = true;
 785                                                 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
 786                                         } else
 787                                                 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
 788                                 } else if (type == CGS_UCODE_ID_SMU_SK) {
 789                                         strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
 790                                 }
 791                                 break;
 792                         case CHIP_POLARIS12:
 793                                 strcpy(fw_name, "amdgpu/polaris12_smc.bin");
 794                                 break;
 795                         case CHIP_VEGA10:
 796                                 if ((adev->pdev->device == 0x687f) &&
 797                                         ((adev->pdev->revision == 0xc0) ||
 798                                         (adev->pdev->revision == 0xc1) ||
 799                                         (adev->pdev->revision == 0xc3)))
 800                                         strcpy(fw_name, "amdgpu/vega10_acg_smc.bin");
 801                                 else
 802                                         strcpy(fw_name, "amdgpu/vega10_smc.bin");
 803                                 break;
 804                         default:
 805                                 DRM_ERROR("SMC firmware not supported\n");
 806                                 return -EINVAL;
 807                         }
 808
 809                         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 810                         if (err) {
 811                                 DRM_ERROR("Failed to request firmware\n");
 812                                 return err;
 813                         }
 814
 815                         err = amdgpu_ucode_validate(adev->pm.fw);
 816                         if (err) {
 817                                 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
 818                                 release_firmware(adev->pm.fw);
 819                                 adev->pm.fw = NULL;
 820                                 return err;
 821                         }
 822
 823                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 824                                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 825                                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 826                                 ucode->fw = adev->pm.fw;
 827                                 header = (const struct common_firmware_header *)ucode->fw->data;
 828                                 adev->firmware.fw_size +=
 829                                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 830                         }
 831                 }
 832
 833                 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 834                 amdgpu_ucode_print_smc_hdr(&hdr->header);
 835                 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 836                 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 837                 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
 838                 src = (const uint8_t *)(adev->pm.fw->data +
 839                        le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 840
 841                 info->version = adev->pm.fw_version;
 842                 info->image_size = ucode_size;
 843                 info->ucode_start_address = ucode_start_address;
 844                 info->kptr = (void *)src;
 845         }
 846         return 0;
 847 }
 848
 849 static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
 850 {
 851         CGS_FUNC_ADEV;
 852         return amdgpu_sriov_vf(adev);
 853 }
 854
 855 static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
 856                                         struct cgs_system_info *sys_info)
 857 {
 858         CGS_FUNC_ADEV;
 859
 860         if (NULL == sys_info)
 861                 return -ENODEV;
 862
 863         if (sizeof(struct cgs_system_info) != sys_info->size)
 864                 return -ENODEV;
 865
 866         switch (sys_info->info_id) {
 867         case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
 868                 sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
 869                 break;
 870         case CGS_SYSTEM_INFO_PCIE_GEN_INFO:
 871                 sys_info->value = adev->pm.pcie_gen_mask;
 872                 break;
 873         case CGS_SYSTEM_INFO_PCIE_MLW:
 874                 sys_info->value = adev->pm.pcie_mlw_mask;
 875                 break;
 876         case CGS_SYSTEM_INFO_PCIE_DEV:
 877                 sys_info->value = adev->pdev->device;
 878                 break;
 879         case CGS_SYSTEM_INFO_PCIE_REV:
 880                 sys_info->value = adev->pdev->revision;
 881                 break;
 882         case CGS_SYSTEM_INFO_CG_FLAGS:
 883                 sys_info->value = adev->cg_flags;
 884                 break;
 885         case CGS_SYSTEM_INFO_PG_FLAGS:
 886                 sys_info->value = adev->pg_flags;
 887                 break;
 888         case CGS_SYSTEM_INFO_GFX_CU_INFO:
 889                 sys_info->value = adev->gfx.cu_info.number;
 890                 break;
 891         case CGS_SYSTEM_INFO_GFX_SE_INFO:
 892                 sys_info->value = adev->gfx.config.max_shader_engines;
 893                 break;
 894         case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID:
 895                 sys_info->value = adev->pdev->subsystem_device;
 896                 break;
 897         case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:
 898                 sys_info->value = adev->pdev->subsystem_vendor;
 899                 break;
 900         case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:
 901                 sys_info->value = adev->pdev->devfn;
 902                 break;
 903         default:
 904                 return -ENODEV;
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
 911                                           struct cgs_display_info *info)
 912 {
 913         CGS_FUNC_ADEV;
 914         struct cgs_mode_info *mode_info;
 915
 916         if (info == NULL)
 917                 return -EINVAL;
 918
 919         mode_info = info->mode_info;
 920         if (mode_info) {
 921                 /* if the displays are off, vblank time is max */
 922                 mode_info->vblank_time_us = 0xffffffff;
 923                 /* always set the reference clock */
 924                 mode_info->ref_clock = adev->clock.spll.reference_freq;
 925         }
 926
 927         if (!amdgpu_device_has_dc_support(adev)) {
 928                 struct amdgpu_crtc *amdgpu_crtc;
 929                 struct drm_device *ddev = adev->ddev;
 930                 struct drm_crtc *crtc;
 931                 uint32_t line_time_us, vblank_lines;
 932
 933                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
 934                         list_for_each_entry(crtc,
 935                                         &ddev->mode_config.crtc_list, head) {
 936                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 937                                 if (crtc->enabled) {
 938                                         info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
 939                                         info->display_count++;
 940                                 }
 941                                 if (mode_info != NULL &&
 942                                         crtc->enabled && amdgpu_crtc->enabled &&
 943                                         amdgpu_crtc->hw_mode.clock) {
 944                                         line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
 945                                                                 amdgpu_crtc->hw_mode.clock;
 946                                         vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
 947                                                                 amdgpu_crtc->hw_mode.crtc_vdisplay +
 948                                                                 (amdgpu_crtc->v_border * 2);
 949                                         mode_info->vblank_time_us = vblank_lines * line_time_us;
 950                                         mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
 951                                         mode_info->ref_clock = adev->clock.spll.reference_freq;
 952                                         mode_info = NULL;
 953                                 }
 954                         }
 955                 }
 956         } else {
 957                 info->display_count = adev->pm.pm_display_cfg.num_display;
 958                 if (mode_info != NULL) {
 959                         mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;
 960                         mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;
 961                         mode_info->ref_clock = adev->clock.spll.reference_freq;
 962                 }
 963         }
 964         return 0;
 965 }
 966
 967
 968 static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
 969 {
 970         CGS_FUNC_ADEV;
 971
 972         adev->pm.dpm_enabled = enabled;
 973
 974         return 0;
 975 }
 976
 977 /** \brief evaluate acpi namespace object, handle or pathname must be valid
 978  *  \param cgs_device
 979  *  \param info input/output arguments for the control method
 980  *  \return status
 981  */
 982
 983 #if defined(CONFIG_ACPI)
 984 static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
 985                                     struct cgs_acpi_method_info *info)
 986 {
 987         CGS_FUNC_ADEV;
 988         acpi_handle handle;
 989         struct acpi_object_list input;
 990         struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
 991         union acpi_object *params, *obj;
 992         uint8_t name[5] = {'\0'};
 993         struct cgs_acpi_method_argument *argument;
 994         uint32_t i, count;
 995         acpi_status status;
 996         int result;
 997
 998         handle = ACPI_HANDLE(&adev->pdev->dev);
 999         if (!handle)
1000                 return -ENODEV;
1001
1002         memset(&input, 0, sizeof(struct acpi_object_list));
1003
1004         /* validate input info */
1005         if (info->size != sizeof(struct cgs_acpi_method_info))
1006                 return -EINVAL;
1007
1008         input.count = info->input_count;
1009         if (info->input_count > 0) {
1010                 if (info->pinput_argument == NULL)
1011                         return -EINVAL;
1012                 argument = info->pinput_argument;
1013                 for (i = 0; i < info->input_count; i++) {
1014                         if (((argument->type == ACPI_TYPE_STRING) ||
1015                              (argument->type == ACPI_TYPE_BUFFER)) &&
1016                             (argument->pointer == NULL))
1017                                 return -EINVAL;
1018                         argument++;
1019                 }
1020         }
1021
1022         if (info->output_count > 0) {
1023                 if (info->poutput_argument == NULL)
1024                         return -EINVAL;
1025                 argument = info->poutput_argument;
1026                 for (i = 0; i < info->output_count; i++) {
1027                         if (((argument->type == ACPI_TYPE_STRING) ||
1028                                 (argument->type == ACPI_TYPE_BUFFER))
1029                                 && (argument->pointer == NULL))
1030                                 return -EINVAL;
1031                         argument++;
1032                 }
1033         }
1034
1035         /* The path name passed to acpi_evaluate_object should be null terminated */
1036         if ((info->field & CGS_ACPI_FIELD_METHOD_NAME) != 0) {
1037                 strncpy(name, (char *)&(info->name), sizeof(uint32_t));
1038                 name[4] = '\0';
1039         }
1040
1041         /* parse input parameters */
1042         if (input.count > 0) {
1043                 input.pointer = params =
1044                                 kzalloc(sizeof(union acpi_object) * input.count, GFP_KERNEL);
1045                 if (params == NULL)
1046                         return -EINVAL;
1047
1048                 argument = info->pinput_argument;
1049
1050                 for (i = 0; i < input.count; i++) {
1051                         params->type = argument->type;
1052                         switch (params->type) {
1053                         case ACPI_TYPE_INTEGER:
1054                                 params->integer.value = argument->value;
1055                                 break;
1056                         case ACPI_TYPE_STRING:
1057                                 params->string.length = argument->data_length;
1058                                 params->string.pointer = argument->pointer;
1059                                 break;
1060                         case ACPI_TYPE_BUFFER:
1061                                 params->buffer.length = argument->data_length;
1062                                 params->buffer.pointer = argument->pointer;
1063                                 break;
1064                         default:
1065                                 break;
1066                         }
1067                         params++;
1068                         argument++;
1069                 }
1070         }
1071
1072         /* parse output info */
1073         count = info->output_count;
1074         argument = info->poutput_argument;
1075
1076         /* evaluate the acpi method */
1077         status = acpi_evaluate_object(handle, name, &input, &output);
1078
1079         if (ACPI_FAILURE(status)) {
1080                 result = -EIO;
1081                 goto free_input;
1082         }
1083
1084         /* return the output info */
1085         obj = output.pointer;
1086
1087         if (count > 1) {
1088                 if ((obj->type != ACPI_TYPE_PACKAGE) ||
1089                         (obj->package.count != count)) {
1090                         result = -EIO;
1091                         goto free_obj;
1092                 }
1093                 params = obj->package.elements;
1094         } else
1095                 params = obj;
1096
1097         if (params == NULL) {
1098                 result = -EIO;
1099                 goto free_obj;
1100         }
1101
1102         for (i = 0; i < count; i++) {
1103                 if (argument->type != params->type) {
1104                         result = -EIO;
1105                         goto free_obj;
1106                 }
1107                 switch (params->type) {
1108                 case ACPI_TYPE_INTEGER:
1109                         argument->value = params->integer.value;
1110                         break;
1111                 case ACPI_TYPE_STRING:
1112                         if ((params->string.length != argument->data_length) ||
1113                                 (params->string.pointer == NULL)) {
1114                                 result = -EIO;
1115                                 goto free_obj;
1116                         }
1117                         strncpy(argument->pointer,
1118                                 params->string.pointer,
1119                                 params->string.length);
1120                         break;
1121                 case ACPI_TYPE_BUFFER:
1122                         if (params->buffer.pointer == NULL) {
1123                                 result = -EIO;
1124                                 goto free_obj;
1125                         }
1126                         memcpy(argument->pointer,
1127                                 params->buffer.pointer,
1128                                 argument->data_length);
1129                         break;
1130                 default:
1131                         break;
1132                 }
1133                 argument++;
1134                 params++;
1135         }
1136
1137         result = 0;
1138 free_obj:
1139         kfree(obj);
1140 free_input:
1141         kfree((void *)input.pointer);
1142         return result;
1143 }
1144 #else
1145 static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
1146                                 struct cgs_acpi_method_info *info)
1147 {
1148         return -EIO;
1149 }
1150 #endif
1151
1152 static int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
1153                                         uint32_t acpi_method,
1154                                         uint32_t acpi_function,
1155                                         void *pinput, void *poutput,
1156                                         uint32_t output_count,
1157                                         uint32_t input_size,
1158                                         uint32_t output_size)
1159 {
1160         struct cgs_acpi_method_argument acpi_input[2] = { {0}, {0} };
1161         struct cgs_acpi_method_argument acpi_output = {0};
1162         struct cgs_acpi_method_info info = {0};
1163
1164         acpi_input[0].type = CGS_ACPI_TYPE_INTEGER;
1165         acpi_input[0].data_length = sizeof(uint32_t);
1166         acpi_input[0].value = acpi_function;
1167
1168         acpi_input[1].type = CGS_ACPI_TYPE_BUFFER;
1169         acpi_input[1].data_length = input_size;
1170         acpi_input[1].pointer = pinput;
1171
1172         acpi_output.type = CGS_ACPI_TYPE_BUFFER;
1173         acpi_output.data_length = output_size;
1174         acpi_output.pointer = poutput;
1175
1176         info.size = sizeof(struct cgs_acpi_method_info);
1177         info.field = CGS_ACPI_FIELD_METHOD_NAME | CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT;
1178         info.input_count = 2;
1179         info.name = acpi_method;
1180         info.pinput_argument = acpi_input;
1181         info.output_count = output_count;
1182         info.poutput_argument = &acpi_output;
1183
1184         return amdgpu_cgs_acpi_eval_object(cgs_device, &info);
1185 }
1186
1187 static const struct cgs_ops amdgpu_cgs_ops = {
1188         .alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,
1189         .free_gpu_mem = amdgpu_cgs_free_gpu_mem,
1190         .gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,
1191         .gunmap_gpu_mem = amdgpu_cgs_gunmap_gpu_mem,
1192         .kmap_gpu_mem = amdgpu_cgs_kmap_gpu_mem,
1193         .kunmap_gpu_mem = amdgpu_cgs_kunmap_gpu_mem,
1194         .read_register = amdgpu_cgs_read_register,
1195         .write_register = amdgpu_cgs_write_register,
1196         .read_ind_register = amdgpu_cgs_read_ind_register,
1197         .write_ind_register = amdgpu_cgs_write_ind_register,
1198         .get_pci_resource = amdgpu_cgs_get_pci_resource,
1199         .atom_get_data_table = amdgpu_cgs_atom_get_data_table,
1200         .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
1201         .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
1202         .get_firmware_info = amdgpu_cgs_get_firmware_info,
1203         .rel_firmware = amdgpu_cgs_rel_firmware,
1204         .set_powergating_state = amdgpu_cgs_set_powergating_state,
1205         .set_clockgating_state = amdgpu_cgs_set_clockgating_state,
1206         .get_active_displays_info = amdgpu_cgs_get_active_displays_info,
1207         .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
1208         .call_acpi_method = amdgpu_cgs_call_acpi_method,
1209         .query_system_info = amdgpu_cgs_query_system_info,
1210         .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
1211         .enter_safe_mode = amdgpu_cgs_enter_safe_mode,
1212         .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
1213         .register_pp_handle = amdgpu_cgs_register_pp_handle,
1214 };
1215
1216 static const struct cgs_os_ops amdgpu_cgs_os_ops = {
1217         .add_irq_source = amdgpu_cgs_add_irq_source,
1218         .irq_get = amdgpu_cgs_irq_get,
1219         .irq_put = amdgpu_cgs_irq_put
1220 };
1221
1222 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
1223 {
1224         struct amdgpu_cgs_device *cgs_device =
1225                 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
1226
1227         if (!cgs_device) {
1228                 DRM_ERROR("Couldn't allocate CGS device structure\n");
1229                 return NULL;
1230         }
1231
1232         cgs_device->base.ops = &amdgpu_cgs_ops;
1233         cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
1234         cgs_device->adev = adev;
1235
1236         return (struct cgs_device *)cgs_device;
1237 }
1238
1239 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
1240 {
1241         kfree(cgs_device);
1242 }