drivers/clk/qcom/gcc-msm8996.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  26
  27 #include "common.h"
  28 #include "clk-regmap.h"
  29 #include "clk-alpha-pll.h"
  30 #include "clk-rcg.h"
  31 #include "clk-branch.h"
  32 #include "reset.h"
  33 #include "gdsc.h"
  34
  35 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  36
  37 enum {
  38         P_XO,
  39         P_GPLL0,
  40         P_GPLL2,
  41         P_GPLL3,
  42         P_GPLL1,
  43         P_GPLL2_EARLY,
  44         P_GPLL0_EARLY_DIV,
  45         P_SLEEP_CLK,
  46         P_GPLL4,
  47         P_AUD_REF_CLK,
  48         P_GPLL1_EARLY_DIV
  49 };
  50
  51 static const struct parent_map gcc_sleep_clk_map[] = {
  52         { P_SLEEP_CLK, 5 }
  53 };
  54
  55 static const char * const gcc_sleep_clk[] = {
  56         "sleep_clk"
  57 };
  58
  59 static const struct parent_map gcc_xo_gpll0_map[] = {
  60         { P_XO, 0 },
  61         { P_GPLL0, 1 }
  62 };
  63
  64 static const char * const gcc_xo_gpll0[] = {
  65         "xo",
  66         "gpll0"
  67 };
  68
  69 static const struct parent_map gcc_xo_sleep_clk_map[] = {
  70         { P_XO, 0 },
  71         { P_SLEEP_CLK, 5 }
  72 };
  73
  74 static const char * const gcc_xo_sleep_clk[] = {
  75         "xo",
  76         "sleep_clk"
  77 };
  78
  79 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
  80         { P_XO, 0 },
  81         { P_GPLL0, 1 },
  82         { P_GPLL0_EARLY_DIV, 6 }
  83 };
  84
  85 static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
  86         "xo",
  87         "gpll0",
  88         "gpll0_early_div"
  89 };
  90
  91 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  92         { P_XO, 0 },
  93         { P_GPLL0, 1 },
  94         { P_GPLL4, 5 }
  95 };
  96
  97 static const char * const gcc_xo_gpll0_gpll4[] = {
  98         "xo",
  99         "gpll0",
 100         "gpll4"
 101 };
 102
 103 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
 104         { P_XO, 0 },
 105         { P_GPLL0, 1 },
 106         { P_AUD_REF_CLK, 2 }
 107 };
 108
 109 static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
 110         "xo",
 111         "gpll0",
 112         "aud_ref_clk"
 113 };
 114
 115 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
 116         { P_XO, 0 },
 117         { P_GPLL0, 1 },
 118         { P_SLEEP_CLK, 5 },
 119         { P_GPLL0_EARLY_DIV, 6 }
 120 };
 121
 122 static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
 123         "xo",
 124         "gpll0",
 125         "sleep_clk",
 126         "gpll0_early_div"
 127 };
 128
 129 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 130         { P_XO, 0 },
 131         { P_GPLL0, 1 },
 132         { P_GPLL4, 5 },
 133         { P_GPLL0_EARLY_DIV, 6 }
 134 };
 135
 136 static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 137         "xo",
 138         "gpll0",
 139         "gpll4",
 140         "gpll0_early_div"
 141 };
 142
 143 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = {
 144         { P_XO, 0 },
 145         { P_GPLL0, 1 },
 146         { P_GPLL2, 2 },
 147         { P_GPLL3, 3 },
 148         { P_GPLL0_EARLY_DIV, 6 }
 149 };
 150
 151 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = {
 152         "xo",
 153         "gpll0",
 154         "gpll2",
 155         "gpll3",
 156         "gpll0_early_div"
 157 };
 158
 159 static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
 160         { P_XO, 0 },
 161         { P_GPLL0, 1 },
 162         { P_GPLL1_EARLY_DIV, 3 },
 163         { P_GPLL1, 4 },
 164         { P_GPLL4, 5 },
 165         { P_GPLL0_EARLY_DIV, 6 }
 166 };
 167
 168 static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
 169         "xo",
 170         "gpll0",
 171         "gpll1_early_div",
 172         "gpll1",
 173         "gpll4",
 174         "gpll0_early_div"
 175 };
 176
 177 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
 178         { P_XO, 0 },
 179         { P_GPLL0, 1 },
 180         { P_GPLL2, 2 },
 181         { P_GPLL3, 3 },
 182         { P_GPLL1, 4 },
 183         { P_GPLL2_EARLY, 5 },
 184         { P_GPLL0_EARLY_DIV, 6 }
 185 };
 186
 187 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
 188         "xo",
 189         "gpll0",
 190         "gpll2",
 191         "gpll3",
 192         "gpll1",
 193         "gpll2_early",
 194         "gpll0_early_div"
 195 };
 196
 197 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = {
 198         { P_XO, 0 },
 199         { P_GPLL0, 1 },
 200         { P_GPLL2, 2 },
 201         { P_GPLL3, 3 },
 202         { P_GPLL1, 4 },
 203         { P_GPLL4, 5 },
 204         { P_GPLL0_EARLY_DIV, 6 }
 205 };
 206
 207 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {
 208         "xo",
 209         "gpll0",
 210         "gpll2",
 211         "gpll3",
 212         "gpll1",
 213         "gpll4",
 214         "gpll0_early_div"
 215 };
 216
 217 static struct clk_fixed_factor xo = {
 218         .mult = 1,
 219         .div = 1,
 220         .hw.init = &(struct clk_init_data){
 221                 .name = "xo",
 222                 .parent_names = (const char *[]){ "xo_board" },
 223                 .num_parents = 1,
 224                 .ops = &clk_fixed_factor_ops,
 225         },
 226 };
 227
 228 static struct clk_alpha_pll gpll0_early = {
 229         .offset = 0x00000,
 230         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 231         .clkr = {
 232                 .enable_reg = 0x52000,
 233                 .enable_mask = BIT(0),
 234                 .hw.init = &(struct clk_init_data){
 235                         .name = "gpll0_early",
 236                         .parent_names = (const char *[]){ "xo" },
 237                         .num_parents = 1,
 238                         .ops = &clk_alpha_pll_ops,
 239                 },
 240         },
 241 };
 242
 243 static struct clk_fixed_factor gpll0_early_div = {
 244         .mult = 1,
 245         .div = 2,
 246         .hw.init = &(struct clk_init_data){
 247                 .name = "gpll0_early_div",
 248                 .parent_names = (const char *[]){ "gpll0_early" },
 249                 .num_parents = 1,
 250                 .ops = &clk_fixed_factor_ops,
 251         },
 252 };
 253
 254 static struct clk_alpha_pll_postdiv gpll0 = {
 255         .offset = 0x00000,
 256         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 257         .clkr.hw.init = &(struct clk_init_data){
 258                 .name = "gpll0",
 259                 .parent_names = (const char *[]){ "gpll0_early" },
 260                 .num_parents = 1,
 261                 .ops = &clk_alpha_pll_postdiv_ops,
 262         },
 263 };
 264
 265 static struct clk_alpha_pll gpll4_early = {
 266         .offset = 0x77000,
 267         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 268         .clkr = {
 269                 .enable_reg = 0x52000,
 270                 .enable_mask = BIT(4),
 271                 .hw.init = &(struct clk_init_data){
 272                         .name = "gpll4_early",
 273                         .parent_names = (const char *[]){ "xo" },
 274                         .num_parents = 1,
 275                         .ops = &clk_alpha_pll_ops,
 276                 },
 277         },
 278 };
 279
 280 static struct clk_alpha_pll_postdiv gpll4 = {
 281         .offset = 0x77000,
 282         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 283         .clkr.hw.init = &(struct clk_init_data){
 284                 .name = "gpll4",
 285                 .parent_names = (const char *[]){ "gpll4_early" },
 286                 .num_parents = 1,
 287                 .ops = &clk_alpha_pll_postdiv_ops,
 288         },
 289 };
 290
 291 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 292         F(19200000, P_XO, 1, 0, 0),
 293         F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
 294         F(100000000, P_GPLL0, 6, 0, 0),
 295         F(150000000, P_GPLL0, 4, 0, 0),
 296         F(200000000, P_GPLL0, 3, 0, 0),
 297         F(240000000, P_GPLL0, 2.5, 0, 0),
 298         { }
 299 };
 300
 301 static struct clk_rcg2 system_noc_clk_src = {
 302         .cmd_rcgr = 0x0401c,
 303         .hid_width = 5,
 304         .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
 305         .freq_tbl = ftbl_system_noc_clk_src,
 306         .clkr.hw.init = &(struct clk_init_data){
 307                 .name = "system_noc_clk_src",
 308                 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
 309                 .num_parents = 7,
 310                 .ops = &clk_rcg2_ops,
 311         },
 312 };
 313
 314 static const struct freq_tbl ftbl_config_noc_clk_src[] = {
 315         F(19200000, P_XO, 1, 0, 0),
 316         F(37500000, P_GPLL0, 16, 0, 0),
 317         F(75000000, P_GPLL0, 8, 0, 0),
 318         { }
 319 };
 320
 321 static struct clk_rcg2 config_noc_clk_src = {
 322         .cmd_rcgr = 0x0500c,
 323         .hid_width = 5,
 324         .parent_map = gcc_xo_gpll0_map,
 325         .freq_tbl = ftbl_config_noc_clk_src,
 326         .clkr.hw.init = &(struct clk_init_data){
 327                 .name = "config_noc_clk_src",
 328                 .parent_names = gcc_xo_gpll0,
 329                 .num_parents = 2,
 330                 .ops = &clk_rcg2_ops,
 331         },
 332 };
 333
 334 static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
 335         F(19200000, P_XO, 1, 0, 0),
 336         F(37500000, P_GPLL0, 16, 0, 0),
 337         F(50000000, P_GPLL0, 12, 0, 0),
 338         F(75000000, P_GPLL0, 8, 0, 0),
 339         F(100000000, P_GPLL0, 6, 0, 0),
 340         { }
 341 };
 342
 343 static struct clk_rcg2 periph_noc_clk_src = {
 344         .cmd_rcgr = 0x06014,
 345         .hid_width = 5,
 346         .parent_map = gcc_xo_gpll0_map,
 347         .freq_tbl = ftbl_periph_noc_clk_src,
 348         .clkr.hw.init = &(struct clk_init_data){
 349                 .name = "periph_noc_clk_src",
 350                 .parent_names = gcc_xo_gpll0,
 351                 .num_parents = 2,
 352                 .ops = &clk_rcg2_ops,
 353         },
 354 };
 355
 356 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
 357         F(19200000, P_XO, 1, 0, 0),
 358         F(120000000, P_GPLL0, 5, 0, 0),
 359         F(150000000, P_GPLL0, 4, 0, 0),
 360         { }
 361 };
 362
 363 static struct clk_rcg2 usb30_master_clk_src = {
 364         .cmd_rcgr = 0x0f014,
 365         .mnd_width = 8,
 366         .hid_width = 5,
 367         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 368         .freq_tbl = ftbl_usb30_master_clk_src,
 369         .clkr.hw.init = &(struct clk_init_data){
 370                 .name = "usb30_master_clk_src",
 371                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 372                 .num_parents = 3,
 373                 .ops = &clk_rcg2_ops,
 374         },
 375 };
 376
 377 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 378         F(19200000, P_XO, 1, 0, 0),
 379         { }
 380 };
 381
 382 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 383         .cmd_rcgr = 0x0f028,
 384         .hid_width = 5,
 385         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 386         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 387         .clkr.hw.init = &(struct clk_init_data){
 388                 .name = "usb30_mock_utmi_clk_src",
 389                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 390                 .num_parents = 3,
 391                 .ops = &clk_rcg2_ops,
 392         },
 393 };
 394
 395 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
 396         F(1200000, P_XO, 16, 0, 0),
 397         { }
 398 };
 399
 400 static struct clk_rcg2 usb3_phy_aux_clk_src = {
 401         .cmd_rcgr = 0x5000c,
 402         .hid_width = 5,
 403         .parent_map = gcc_xo_sleep_clk_map,
 404         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
 405         .clkr.hw.init = &(struct clk_init_data){
 406                 .name = "usb3_phy_aux_clk_src",
 407                 .parent_names = gcc_xo_sleep_clk,
 408                 .num_parents = 2,
 409                 .ops = &clk_rcg2_ops,
 410         },
 411 };
 412
 413 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
 414         F(120000000, P_GPLL0, 5, 0, 0),
 415         { }
 416 };
 417
 418 static struct clk_rcg2 usb20_master_clk_src = {
 419         .cmd_rcgr = 0x12010,
 420         .mnd_width = 8,
 421         .hid_width = 5,
 422         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 423         .freq_tbl = ftbl_usb20_master_clk_src,
 424         .clkr.hw.init = &(struct clk_init_data){
 425                 .name = "usb20_master_clk_src",
 426                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 427                 .num_parents = 3,
 428                 .ops = &clk_rcg2_ops,
 429         },
 430 };
 431
 432 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 433         .cmd_rcgr = 0x12024,
 434         .hid_width = 5,
 435         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 436         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 437         .clkr.hw.init = &(struct clk_init_data){
 438                 .name = "usb20_mock_utmi_clk_src",
 439                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 440                 .num_parents = 3,
 441                 .ops = &clk_rcg2_ops,
 442         },
 443 };
 444
 445 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 446         F(144000, P_XO, 16, 3, 25),
 447         F(400000, P_XO, 12, 1, 4),
 448         F(20000000, P_GPLL0, 15, 1, 2),
 449         F(25000000, P_GPLL0, 12, 1, 2),
 450         F(50000000, P_GPLL0, 12, 0, 0),
 451         F(96000000, P_GPLL4, 4, 0, 0),
 452         F(192000000, P_GPLL4, 2, 0, 0),
 453         F(384000000, P_GPLL4, 1, 0, 0),
 454         { }
 455 };
 456
 457 static struct clk_rcg2 sdcc1_apps_clk_src = {
 458         .cmd_rcgr = 0x13010,
 459         .mnd_width = 8,
 460         .hid_width = 5,
 461         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 462         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 463         .clkr.hw.init = &(struct clk_init_data){
 464                 .name = "sdcc1_apps_clk_src",
 465                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 466                 .num_parents = 4,
 467                 .ops = &clk_rcg2_floor_ops,
 468         },
 469 };
 470
 471 static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
 472         F(19200000, P_XO, 1, 0, 0),
 473         F(150000000, P_GPLL0, 4, 0, 0),
 474         F(300000000, P_GPLL0, 2, 0, 0),
 475         { }
 476 };
 477
 478 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 479         .cmd_rcgr = 0x13024,
 480         .hid_width = 5,
 481         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 482         .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 483         .clkr.hw.init = &(struct clk_init_data){
 484                 .name = "sdcc1_ice_core_clk_src",
 485                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 486                 .num_parents = 4,
 487                 .ops = &clk_rcg2_ops,
 488         },
 489 };
 490
 491 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
 492         F(144000, P_XO, 16, 3, 25),
 493         F(400000, P_XO, 12, 1, 4),
 494         F(20000000, P_GPLL0, 15, 1, 2),
 495         F(25000000, P_GPLL0, 12, 1, 2),
 496         F(50000000, P_GPLL0, 12, 0, 0),
 497         F(100000000, P_GPLL0, 6, 0, 0),
 498         F(200000000, P_GPLL0, 3, 0, 0),
 499         { }
 500 };
 501
 502 static struct clk_rcg2 sdcc2_apps_clk_src = {
 503         .cmd_rcgr = 0x14010,
 504         .mnd_width = 8,
 505         .hid_width = 5,
 506         .parent_map = gcc_xo_gpll0_gpll4_map,
 507         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 508         .clkr.hw.init = &(struct clk_init_data){
 509                 .name = "sdcc2_apps_clk_src",
 510                 .parent_names = gcc_xo_gpll0_gpll4,
 511                 .num_parents = 3,
 512                 .ops = &clk_rcg2_floor_ops,
 513         },
 514 };
 515
 516 static struct clk_rcg2 sdcc3_apps_clk_src = {
 517         .cmd_rcgr = 0x15010,
 518         .mnd_width = 8,
 519         .hid_width = 5,
 520         .parent_map = gcc_xo_gpll0_gpll4_map,
 521         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 522         .clkr.hw.init = &(struct clk_init_data){
 523                 .name = "sdcc3_apps_clk_src",
 524                 .parent_names = gcc_xo_gpll0_gpll4,
 525                 .num_parents = 3,
 526                 .ops = &clk_rcg2_floor_ops,
 527         },
 528 };
 529
 530 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
 531         F(144000, P_XO, 16, 3, 25),
 532         F(400000, P_XO, 12, 1, 4),
 533         F(20000000, P_GPLL0, 15, 1, 2),
 534         F(25000000, P_GPLL0, 12, 1, 2),
 535         F(50000000, P_GPLL0, 12, 0, 0),
 536         F(100000000, P_GPLL0, 6, 0, 0),
 537         { }
 538 };
 539
 540 static struct clk_rcg2 sdcc4_apps_clk_src = {
 541         .cmd_rcgr = 0x16010,
 542         .mnd_width = 8,
 543         .hid_width = 5,
 544         .parent_map = gcc_xo_gpll0_map,
 545         .freq_tbl = ftbl_sdcc4_apps_clk_src,
 546         .clkr.hw.init = &(struct clk_init_data){
 547                 .name = "sdcc4_apps_clk_src",
 548                 .parent_names = gcc_xo_gpll0,
 549                 .num_parents = 2,
 550                 .ops = &clk_rcg2_floor_ops,
 551         },
 552 };
 553
 554 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 555         F(960000, P_XO, 10, 1, 2),
 556         F(4800000, P_XO, 4, 0, 0),
 557         F(9600000, P_XO, 2, 0, 0),
 558         F(15000000, P_GPLL0, 10, 1, 4),
 559         F(19200000, P_XO, 1, 0, 0),
 560         F(25000000, P_GPLL0, 12, 1, 2),
 561         F(50000000, P_GPLL0, 12, 0, 0),
 562         { }
 563 };
 564
 565 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 566         .cmd_rcgr = 0x1900c,
 567         .mnd_width = 8,
 568         .hid_width = 5,
 569         .parent_map = gcc_xo_gpll0_map,
 570         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 571         .clkr.hw.init = &(struct clk_init_data){
 572                 .name = "blsp1_qup1_spi_apps_clk_src",
 573                 .parent_names = gcc_xo_gpll0,
 574                 .num_parents = 2,
 575                 .ops = &clk_rcg2_ops,
 576         },
 577 };
 578
 579 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 580         F(19200000, P_XO, 1, 0, 0),
 581         F(50000000, P_GPLL0, 12, 0, 0),
 582         { }
 583 };
 584
 585 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 586         .cmd_rcgr = 0x19020,
 587         .hid_width = 5,
 588         .parent_map = gcc_xo_gpll0_map,
 589         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 590         .clkr.hw.init = &(struct clk_init_data){
 591                 .name = "blsp1_qup1_i2c_apps_clk_src",
 592                 .parent_names = gcc_xo_gpll0,
 593                 .num_parents = 2,
 594                 .ops = &clk_rcg2_ops,
 595         },
 596 };
 597
 598 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 599         F(3686400, P_GPLL0, 1, 96, 15625),
 600         F(7372800, P_GPLL0, 1, 192, 15625),
 601         F(14745600, P_GPLL0, 1, 384, 15625),
 602         F(16000000, P_GPLL0, 5, 2, 15),
 603         F(19200000, P_XO, 1, 0, 0),
 604         F(24000000, P_GPLL0, 5, 1, 5),
 605         F(32000000, P_GPLL0, 1, 4, 75),
 606         F(40000000, P_GPLL0, 15, 0, 0),
 607         F(46400000, P_GPLL0, 1, 29, 375),
 608         F(48000000, P_GPLL0, 12.5, 0, 0),
 609         F(51200000, P_GPLL0, 1, 32, 375),
 610         F(56000000, P_GPLL0, 1, 7, 75),
 611         F(58982400, P_GPLL0, 1, 1536, 15625),
 612         F(60000000, P_GPLL0, 10, 0, 0),
 613         F(63157895, P_GPLL0, 9.5, 0, 0),
 614         { }
 615 };
 616
 617 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 618         .cmd_rcgr = 0x1a00c,
 619         .mnd_width = 16,
 620         .hid_width = 5,
 621         .parent_map = gcc_xo_gpll0_map,
 622         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 623         .clkr.hw.init = &(struct clk_init_data){
 624                 .name = "blsp1_uart1_apps_clk_src",
 625                 .parent_names = gcc_xo_gpll0,
 626                 .num_parents = 2,
 627                 .ops = &clk_rcg2_ops,
 628         },
 629 };
 630
 631 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 632         .cmd_rcgr = 0x1b00c,
 633         .mnd_width = 8,
 634         .hid_width = 5,
 635         .parent_map = gcc_xo_gpll0_map,
 636         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 637         .clkr.hw.init = &(struct clk_init_data){
 638                 .name = "blsp1_qup2_spi_apps_clk_src",
 639                 .parent_names = gcc_xo_gpll0,
 640                 .num_parents = 2,
 641                 .ops = &clk_rcg2_ops,
 642         },
 643 };
 644
 645 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 646         .cmd_rcgr = 0x1b020,
 647         .hid_width = 5,
 648         .parent_map = gcc_xo_gpll0_map,
 649         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 650         .clkr.hw.init = &(struct clk_init_data){
 651                 .name = "blsp1_qup2_i2c_apps_clk_src",
 652                 .parent_names = gcc_xo_gpll0,
 653                 .num_parents = 2,
 654                 .ops = &clk_rcg2_ops,
 655         },
 656 };
 657
 658 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 659         .cmd_rcgr = 0x1c00c,
 660         .mnd_width = 16,
 661         .hid_width = 5,
 662         .parent_map = gcc_xo_gpll0_map,
 663         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 664         .clkr.hw.init = &(struct clk_init_data){
 665                 .name = "blsp1_uart2_apps_clk_src",
 666                 .parent_names = gcc_xo_gpll0,
 667                 .num_parents = 2,
 668                 .ops = &clk_rcg2_ops,
 669         },
 670 };
 671
 672 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 673         .cmd_rcgr = 0x1d00c,
 674         .mnd_width = 8,
 675         .hid_width = 5,
 676         .parent_map = gcc_xo_gpll0_map,
 677         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 678         .clkr.hw.init = &(struct clk_init_data){
 679                 .name = "blsp1_qup3_spi_apps_clk_src",
 680                 .parent_names = gcc_xo_gpll0,
 681                 .num_parents = 2,
 682                 .ops = &clk_rcg2_ops,
 683         },
 684 };
 685
 686 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 687         .cmd_rcgr = 0x1d020,
 688         .hid_width = 5,
 689         .parent_map = gcc_xo_gpll0_map,
 690         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 691         .clkr.hw.init = &(struct clk_init_data){
 692                 .name = "blsp1_qup3_i2c_apps_clk_src",
 693                 .parent_names = gcc_xo_gpll0,
 694                 .num_parents = 2,
 695                 .ops = &clk_rcg2_ops,
 696         },
 697 };
 698
 699 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 700         .cmd_rcgr = 0x1e00c,
 701         .mnd_width = 16,
 702         .hid_width = 5,
 703         .parent_map = gcc_xo_gpll0_map,
 704         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 705         .clkr.hw.init = &(struct clk_init_data){
 706                 .name = "blsp1_uart3_apps_clk_src",
 707                 .parent_names = gcc_xo_gpll0,
 708                 .num_parents = 2,
 709                 .ops = &clk_rcg2_ops,
 710         },
 711 };
 712
 713 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 714         .cmd_rcgr = 0x1f00c,
 715         .mnd_width = 8,
 716         .hid_width = 5,
 717         .parent_map = gcc_xo_gpll0_map,
 718         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 719         .clkr.hw.init = &(struct clk_init_data){
 720                 .name = "blsp1_qup4_spi_apps_clk_src",
 721                 .parent_names = gcc_xo_gpll0,
 722                 .num_parents = 2,
 723                 .ops = &clk_rcg2_ops,
 724         },
 725 };
 726
 727 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 728         .cmd_rcgr = 0x1f020,
 729         .hid_width = 5,
 730         .parent_map = gcc_xo_gpll0_map,
 731         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 732         .clkr.hw.init = &(struct clk_init_data){
 733                 .name = "blsp1_qup4_i2c_apps_clk_src",
 734                 .parent_names = gcc_xo_gpll0,
 735                 .num_parents = 2,
 736                 .ops = &clk_rcg2_ops,
 737         },
 738 };
 739
 740 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 741         .cmd_rcgr = 0x2000c,
 742         .mnd_width = 16,
 743         .hid_width = 5,
 744         .parent_map = gcc_xo_gpll0_map,
 745         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 746         .clkr.hw.init = &(struct clk_init_data){
 747                 .name = "blsp1_uart4_apps_clk_src",
 748                 .parent_names = gcc_xo_gpll0,
 749                 .num_parents = 2,
 750                 .ops = &clk_rcg2_ops,
 751         },
 752 };
 753
 754 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 755         .cmd_rcgr = 0x2100c,
 756         .mnd_width = 8,
 757         .hid_width = 5,
 758         .parent_map = gcc_xo_gpll0_map,
 759         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 760         .clkr.hw.init = &(struct clk_init_data){
 761                 .name = "blsp1_qup5_spi_apps_clk_src",
 762                 .parent_names = gcc_xo_gpll0,
 763                 .num_parents = 2,
 764                 .ops = &clk_rcg2_ops,
 765         },
 766 };
 767
 768 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 769         .cmd_rcgr = 0x21020,
 770         .hid_width = 5,
 771         .parent_map = gcc_xo_gpll0_map,
 772         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 773         .clkr.hw.init = &(struct clk_init_data){
 774                 .name = "blsp1_qup5_i2c_apps_clk_src",
 775                 .parent_names = gcc_xo_gpll0,
 776                 .num_parents = 2,
 777                 .ops = &clk_rcg2_ops,
 778         },
 779 };
 780
 781 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 782         .cmd_rcgr = 0x2200c,
 783         .mnd_width = 16,
 784         .hid_width = 5,
 785         .parent_map = gcc_xo_gpll0_map,
 786         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 787         .clkr.hw.init = &(struct clk_init_data){
 788                 .name = "blsp1_uart5_apps_clk_src",
 789                 .parent_names = gcc_xo_gpll0,
 790                 .num_parents = 2,
 791                 .ops = &clk_rcg2_ops,
 792         },
 793 };
 794
 795 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 796         .cmd_rcgr = 0x2300c,
 797         .mnd_width = 8,
 798         .hid_width = 5,
 799         .parent_map = gcc_xo_gpll0_map,
 800         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "blsp1_qup6_spi_apps_clk_src",
 803                 .parent_names = gcc_xo_gpll0,
 804                 .num_parents = 2,
 805                 .ops = &clk_rcg2_ops,
 806         },
 807 };
 808
 809 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 810         .cmd_rcgr = 0x23020,
 811         .hid_width = 5,
 812         .parent_map = gcc_xo_gpll0_map,
 813         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 814         .clkr.hw.init = &(struct clk_init_data){
 815                 .name = "blsp1_qup6_i2c_apps_clk_src",
 816                 .parent_names = gcc_xo_gpll0,
 817                 .num_parents = 2,
 818                 .ops = &clk_rcg2_ops,
 819         },
 820 };
 821
 822 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 823         .cmd_rcgr = 0x2400c,
 824         .mnd_width = 16,
 825         .hid_width = 5,
 826         .parent_map = gcc_xo_gpll0_map,
 827         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 828         .clkr.hw.init = &(struct clk_init_data){
 829                 .name = "blsp1_uart6_apps_clk_src",
 830                 .parent_names = gcc_xo_gpll0,
 831                 .num_parents = 2,
 832                 .ops = &clk_rcg2_ops,
 833         },
 834 };
 835
 836 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 837         .cmd_rcgr = 0x2600c,
 838         .mnd_width = 8,
 839         .hid_width = 5,
 840         .parent_map = gcc_xo_gpll0_map,
 841         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 842         .clkr.hw.init = &(struct clk_init_data){
 843                 .name = "blsp2_qup1_spi_apps_clk_src",
 844                 .parent_names = gcc_xo_gpll0,
 845                 .num_parents = 2,
 846                 .ops = &clk_rcg2_ops,
 847         },
 848 };
 849
 850 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 851         .cmd_rcgr = 0x26020,
 852         .hid_width = 5,
 853         .parent_map = gcc_xo_gpll0_map,
 854         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 855         .clkr.hw.init = &(struct clk_init_data){
 856                 .name = "blsp2_qup1_i2c_apps_clk_src",
 857                 .parent_names = gcc_xo_gpll0,
 858                 .num_parents = 2,
 859                 .ops = &clk_rcg2_ops,
 860         },
 861 };
 862
 863 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 864         .cmd_rcgr = 0x2700c,
 865         .mnd_width = 16,
 866         .hid_width = 5,
 867         .parent_map = gcc_xo_gpll0_map,
 868         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 869         .clkr.hw.init = &(struct clk_init_data){
 870                 .name = "blsp2_uart1_apps_clk_src",
 871                 .parent_names = gcc_xo_gpll0,
 872                 .num_parents = 2,
 873                 .ops = &clk_rcg2_ops,
 874         },
 875 };
 876
 877 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 878         .cmd_rcgr = 0x2800c,
 879         .mnd_width = 8,
 880         .hid_width = 5,
 881         .parent_map = gcc_xo_gpll0_map,
 882         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 883         .clkr.hw.init = &(struct clk_init_data){
 884                 .name = "blsp2_qup2_spi_apps_clk_src",
 885                 .parent_names = gcc_xo_gpll0,
 886                 .num_parents = 2,
 887                 .ops = &clk_rcg2_ops,
 888         },
 889 };
 890
 891 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 892         .cmd_rcgr = 0x28020,
 893         .hid_width = 5,
 894         .parent_map = gcc_xo_gpll0_map,
 895         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 896         .clkr.hw.init = &(struct clk_init_data){
 897                 .name = "blsp2_qup2_i2c_apps_clk_src",
 898                 .parent_names = gcc_xo_gpll0,
 899                 .num_parents = 2,
 900                 .ops = &clk_rcg2_ops,
 901         },
 902 };
 903
 904 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 905         .cmd_rcgr = 0x2900c,
 906         .mnd_width = 16,
 907         .hid_width = 5,
 908         .parent_map = gcc_xo_gpll0_map,
 909         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 910         .clkr.hw.init = &(struct clk_init_data){
 911                 .name = "blsp2_uart2_apps_clk_src",
 912                 .parent_names = gcc_xo_gpll0,
 913                 .num_parents = 2,
 914                 .ops = &clk_rcg2_ops,
 915         },
 916 };
 917
 918 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 919         .cmd_rcgr = 0x2a00c,
 920         .mnd_width = 8,
 921         .hid_width = 5,
 922         .parent_map = gcc_xo_gpll0_map,
 923         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 924         .clkr.hw.init = &(struct clk_init_data){
 925                 .name = "blsp2_qup3_spi_apps_clk_src",
 926                 .parent_names = gcc_xo_gpll0,
 927                 .num_parents = 2,
 928                 .ops = &clk_rcg2_ops,
 929         },
 930 };
 931
 932 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 933         .cmd_rcgr = 0x2a020,
 934         .hid_width = 5,
 935         .parent_map = gcc_xo_gpll0_map,
 936         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 937         .clkr.hw.init = &(struct clk_init_data){
 938                 .name = "blsp2_qup3_i2c_apps_clk_src",
 939                 .parent_names = gcc_xo_gpll0,
 940                 .num_parents = 2,
 941                 .ops = &clk_rcg2_ops,
 942         },
 943 };
 944
 945 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 946         .cmd_rcgr = 0x2b00c,
 947         .mnd_width = 16,
 948         .hid_width = 5,
 949         .parent_map = gcc_xo_gpll0_map,
 950         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 951         .clkr.hw.init = &(struct clk_init_data){
 952                 .name = "blsp2_uart3_apps_clk_src",
 953                 .parent_names = gcc_xo_gpll0,
 954                 .num_parents = 2,
 955                 .ops = &clk_rcg2_ops,
 956         },
 957 };
 958
 959 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 960         .cmd_rcgr = 0x2c00c,
 961         .mnd_width = 8,
 962         .hid_width = 5,
 963         .parent_map = gcc_xo_gpll0_map,
 964         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 965         .clkr.hw.init = &(struct clk_init_data){
 966                 .name = "blsp2_qup4_spi_apps_clk_src",
 967                 .parent_names = gcc_xo_gpll0,
 968                 .num_parents = 2,
 969                 .ops = &clk_rcg2_ops,
 970         },
 971 };
 972
 973 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 974         .cmd_rcgr = 0x2c020,
 975         .hid_width = 5,
 976         .parent_map = gcc_xo_gpll0_map,
 977         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 978         .clkr.hw.init = &(struct clk_init_data){
 979                 .name = "blsp2_qup4_i2c_apps_clk_src",
 980                 .parent_names = gcc_xo_gpll0,
 981                 .num_parents = 2,
 982                 .ops = &clk_rcg2_ops,
 983         },
 984 };
 985
 986 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 987         .cmd_rcgr = 0x2d00c,
 988         .mnd_width = 16,
 989         .hid_width = 5,
 990         .parent_map = gcc_xo_gpll0_map,
 991         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 992         .clkr.hw.init = &(struct clk_init_data){
 993                 .name = "blsp2_uart4_apps_clk_src",
 994                 .parent_names = gcc_xo_gpll0,
 995                 .num_parents = 2,
 996                 .ops = &clk_rcg2_ops,
 997         },
 998 };
 999
1000 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
1001         .cmd_rcgr = 0x2e00c,
1002         .mnd_width = 8,
1003         .hid_width = 5,
1004         .parent_map = gcc_xo_gpll0_map,
1005         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1006         .clkr.hw.init = &(struct clk_init_data){
1007                 .name = "blsp2_qup5_spi_apps_clk_src",
1008                 .parent_names = gcc_xo_gpll0,
1009                 .num_parents = 2,
1010                 .ops = &clk_rcg2_ops,
1011         },
1012 };
1013
1014 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
1015         .cmd_rcgr = 0x2e020,
1016         .hid_width = 5,
1017         .parent_map = gcc_xo_gpll0_map,
1018         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1019         .clkr.hw.init = &(struct clk_init_data){
1020                 .name = "blsp2_qup5_i2c_apps_clk_src",
1021                 .parent_names = gcc_xo_gpll0,
1022                 .num_parents = 2,
1023                 .ops = &clk_rcg2_ops,
1024         },
1025 };
1026
1027 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
1028         .cmd_rcgr = 0x2f00c,
1029         .mnd_width = 16,
1030         .hid_width = 5,
1031         .parent_map = gcc_xo_gpll0_map,
1032         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1033         .clkr.hw.init = &(struct clk_init_data){
1034                 .name = "blsp2_uart5_apps_clk_src",
1035                 .parent_names = gcc_xo_gpll0,
1036                 .num_parents = 2,
1037                 .ops = &clk_rcg2_ops,
1038         },
1039 };
1040
1041 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1042         .cmd_rcgr = 0x3000c,
1043         .mnd_width = 8,
1044         .hid_width = 5,
1045         .parent_map = gcc_xo_gpll0_map,
1046         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1047         .clkr.hw.init = &(struct clk_init_data){
1048                 .name = "blsp2_qup6_spi_apps_clk_src",
1049                 .parent_names = gcc_xo_gpll0,
1050                 .num_parents = 2,
1051                 .ops = &clk_rcg2_ops,
1052         },
1053 };
1054
1055 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1056         .cmd_rcgr = 0x30020,
1057         .hid_width = 5,
1058         .parent_map = gcc_xo_gpll0_map,
1059         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1060         .clkr.hw.init = &(struct clk_init_data){
1061                 .name = "blsp2_qup6_i2c_apps_clk_src",
1062                 .parent_names = gcc_xo_gpll0,
1063                 .num_parents = 2,
1064                 .ops = &clk_rcg2_ops,
1065         },
1066 };
1067
1068 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1069         .cmd_rcgr = 0x3100c,
1070         .mnd_width = 16,
1071         .hid_width = 5,
1072         .parent_map = gcc_xo_gpll0_map,
1073         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1074         .clkr.hw.init = &(struct clk_init_data){
1075                 .name = "blsp2_uart6_apps_clk_src",
1076                 .parent_names = gcc_xo_gpll0,
1077                 .num_parents = 2,
1078                 .ops = &clk_rcg2_ops,
1079         },
1080 };
1081
1082 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1083         F(60000000, P_GPLL0, 10, 0, 0),
1084         { }
1085 };
1086
1087 static struct clk_rcg2 pdm2_clk_src = {
1088         .cmd_rcgr = 0x33010,
1089         .hid_width = 5,
1090         .parent_map = gcc_xo_gpll0_map,
1091         .freq_tbl = ftbl_pdm2_clk_src,
1092         .clkr.hw.init = &(struct clk_init_data){
1093                 .name = "pdm2_clk_src",
1094                 .parent_names = gcc_xo_gpll0,
1095                 .num_parents = 2,
1096                 .ops = &clk_rcg2_ops,
1097         },
1098 };
1099
1100 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1101         F(105495, P_XO, 1, 1, 182),
1102         { }
1103 };
1104
1105 static struct clk_rcg2 tsif_ref_clk_src = {
1106         .cmd_rcgr = 0x36010,
1107         .mnd_width = 8,
1108         .hid_width = 5,
1109         .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1110         .freq_tbl = ftbl_tsif_ref_clk_src,
1111         .clkr.hw.init = &(struct clk_init_data){
1112                 .name = "tsif_ref_clk_src",
1113                 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1114                 .num_parents = 3,
1115                 .ops = &clk_rcg2_ops,
1116         },
1117 };
1118
1119 static struct clk_rcg2 gcc_sleep_clk_src = {
1120         .cmd_rcgr = 0x43014,
1121         .hid_width = 5,
1122         .parent_map = gcc_sleep_clk_map,
1123         .clkr.hw.init = &(struct clk_init_data){
1124                 .name = "gcc_sleep_clk_src",
1125                 .parent_names = gcc_sleep_clk,
1126                 .num_parents = 1,
1127                 .ops = &clk_rcg2_ops,
1128         },
1129 };
1130
1131 static struct clk_rcg2 hmss_rbcpr_clk_src = {
1132         .cmd_rcgr = 0x48040,
1133         .hid_width = 5,
1134         .parent_map = gcc_xo_gpll0_map,
1135         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1136         .clkr.hw.init = &(struct clk_init_data){
1137                 .name = "hmss_rbcpr_clk_src",
1138                 .parent_names = gcc_xo_gpll0,
1139                 .num_parents = 2,
1140                 .ops = &clk_rcg2_ops,
1141         },
1142 };
1143
1144 static struct clk_rcg2 hmss_gpll0_clk_src = {
1145         .cmd_rcgr = 0x48058,
1146         .hid_width = 5,
1147         .parent_map = gcc_xo_gpll0_map,
1148         .clkr.hw.init = &(struct clk_init_data){
1149                 .name = "hmss_gpll0_clk_src",
1150                 .parent_names = gcc_xo_gpll0,
1151                 .num_parents = 2,
1152                 .ops = &clk_rcg2_ops,
1153         },
1154 };
1155
1156 static const struct freq_tbl ftbl_gp1_clk_src[] = {
1157         F(19200000, P_XO, 1, 0, 0),
1158         F(100000000, P_GPLL0, 6, 0, 0),
1159         F(200000000, P_GPLL0, 3, 0, 0),
1160         { }
1161 };
1162
1163 static struct clk_rcg2 gp1_clk_src = {
1164         .cmd_rcgr = 0x64004,
1165         .mnd_width = 8,
1166         .hid_width = 5,
1167         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1168         .freq_tbl = ftbl_gp1_clk_src,
1169         .clkr.hw.init = &(struct clk_init_data){
1170                 .name = "gp1_clk_src",
1171                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1172                 .num_parents = 4,
1173                 .ops = &clk_rcg2_ops,
1174         },
1175 };
1176
1177 static struct clk_rcg2 gp2_clk_src = {
1178         .cmd_rcgr = 0x65004,
1179         .mnd_width = 8,
1180         .hid_width = 5,
1181         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1182         .freq_tbl = ftbl_gp1_clk_src,
1183         .clkr.hw.init = &(struct clk_init_data){
1184                 .name = "gp2_clk_src",
1185                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1186                 .num_parents = 4,
1187                 .ops = &clk_rcg2_ops,
1188         },
1189 };
1190
1191 static struct clk_rcg2 gp3_clk_src = {
1192         .cmd_rcgr = 0x66004,
1193         .mnd_width = 8,
1194         .hid_width = 5,
1195         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1196         .freq_tbl = ftbl_gp1_clk_src,
1197         .clkr.hw.init = &(struct clk_init_data){
1198                 .name = "gp3_clk_src",
1199                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1200                 .num_parents = 4,
1201                 .ops = &clk_rcg2_ops,
1202         },
1203 };
1204
1205 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1206         F(1010526, P_XO, 1, 1, 19),
1207         { }
1208 };
1209
1210 static struct clk_rcg2 pcie_aux_clk_src = {
1211         .cmd_rcgr = 0x6c000,
1212         .mnd_width = 16,
1213         .hid_width = 5,
1214         .parent_map = gcc_xo_sleep_clk_map,
1215         .freq_tbl = ftbl_pcie_aux_clk_src,
1216         .clkr.hw.init = &(struct clk_init_data){
1217                 .name = "pcie_aux_clk_src",
1218                 .parent_names = gcc_xo_sleep_clk,
1219                 .num_parents = 2,
1220                 .ops = &clk_rcg2_ops,
1221         },
1222 };
1223
1224 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1225         F(100000000, P_GPLL0, 6, 0, 0),
1226         F(200000000, P_GPLL0, 3, 0, 0),
1227         F(240000000, P_GPLL0, 2.5, 0, 0),
1228         { }
1229 };
1230
1231 static struct clk_rcg2 ufs_axi_clk_src = {
1232         .cmd_rcgr = 0x75024,
1233         .mnd_width = 8,
1234         .hid_width = 5,
1235         .parent_map = gcc_xo_gpll0_map,
1236         .freq_tbl = ftbl_ufs_axi_clk_src,
1237         .clkr.hw.init = &(struct clk_init_data){
1238                 .name = "ufs_axi_clk_src",
1239                 .parent_names = gcc_xo_gpll0,
1240                 .num_parents = 2,
1241                 .ops = &clk_rcg2_ops,
1242         },
1243 };
1244
1245 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
1246         F(19200000, P_XO, 1, 0, 0),
1247         F(150000000, P_GPLL0, 4, 0, 0),
1248         F(300000000, P_GPLL0, 2, 0, 0),
1249         { }
1250 };
1251
1252 static struct clk_rcg2 ufs_ice_core_clk_src = {
1253         .cmd_rcgr = 0x76014,
1254         .hid_width = 5,
1255         .parent_map = gcc_xo_gpll0_map,
1256         .freq_tbl = ftbl_ufs_ice_core_clk_src,
1257         .clkr.hw.init = &(struct clk_init_data){
1258                 .name = "ufs_ice_core_clk_src",
1259                 .parent_names = gcc_xo_gpll0,
1260                 .num_parents = 2,
1261                 .ops = &clk_rcg2_ops,
1262         },
1263 };
1264
1265 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
1266         F(75000000, P_GPLL0, 8, 0, 0),
1267         F(150000000, P_GPLL0, 4, 0, 0),
1268         F(256000000, P_GPLL4, 1.5, 0, 0),
1269         F(300000000, P_GPLL0, 2, 0, 0),
1270         { }
1271 };
1272
1273 static struct clk_rcg2 qspi_ser_clk_src = {
1274         .cmd_rcgr = 0x8b00c,
1275         .hid_width = 5,
1276         .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1277         .freq_tbl = ftbl_qspi_ser_clk_src,
1278         .clkr.hw.init = &(struct clk_init_data){
1279                 .name = "qspi_ser_clk_src",
1280                 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1281                 .num_parents = 6,
1282                 .ops = &clk_rcg2_ops,
1283         },
1284 };
1285
1286 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1287         .halt_reg = 0x0f03c,
1288         .clkr = {
1289                 .enable_reg = 0x0f03c,
1290                 .enable_mask = BIT(0),
1291                 .hw.init = &(struct clk_init_data){
1292                         .name = "gcc_sys_noc_usb3_axi_clk",
1293                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1294                         .num_parents = 1,
1295                         .flags = CLK_SET_RATE_PARENT,
1296                         .ops = &clk_branch2_ops,
1297                 },
1298         },
1299 };
1300
1301 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1302         .halt_reg = 0x75038,
1303         .clkr = {
1304                 .enable_reg = 0x75038,
1305                 .enable_mask = BIT(0),
1306                 .hw.init = &(struct clk_init_data){
1307                         .name = "gcc_sys_noc_ufs_axi_clk",
1308                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1309                         .num_parents = 1,
1310                         .flags = CLK_SET_RATE_PARENT,
1311                         .ops = &clk_branch2_ops,
1312                 },
1313         },
1314 };
1315
1316 static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1317         .halt_reg = 0x6010,
1318         .clkr = {
1319                 .enable_reg = 0x6010,
1320                 .enable_mask = BIT(0),
1321                 .hw.init = &(struct clk_init_data){
1322                         .name = "gcc_periph_noc_usb20_ahb_clk",
1323                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1324                         .num_parents = 1,
1325                         .flags = CLK_SET_RATE_PARENT,
1326                         .ops = &clk_branch2_ops,
1327                 },
1328         },
1329 };
1330
1331 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1332         .halt_reg = 0x9008,
1333         .clkr = {
1334                 .enable_reg = 0x9008,
1335                 .enable_mask = BIT(0),
1336                 .hw.init = &(struct clk_init_data){
1337                         .name = "gcc_mmss_noc_cfg_ahb_clk",
1338                         .parent_names = (const char *[]){ "config_noc_clk_src" },
1339                         .num_parents = 1,
1340                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1341                         .ops = &clk_branch2_ops,
1342                 },
1343         },
1344 };
1345
1346 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1347         .halt_reg = 0x9010,
1348         .clkr = {
1349                 .enable_reg = 0x9010,
1350                 .enable_mask = BIT(0),
1351                 .hw.init = &(struct clk_init_data){
1352                         .name = "gcc_mmss_bimc_gfx_clk",
1353                         .flags = CLK_SET_RATE_PARENT,
1354                         .ops = &clk_branch2_ops,
1355                 },
1356         },
1357 };
1358
1359 static struct clk_branch gcc_usb30_master_clk = {
1360         .halt_reg = 0x0f008,
1361         .clkr = {
1362                 .enable_reg = 0x0f008,
1363                 .enable_mask = BIT(0),
1364                 .hw.init = &(struct clk_init_data){
1365                         .name = "gcc_usb30_master_clk",
1366                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1367                         .num_parents = 1,
1368                         .flags = CLK_SET_RATE_PARENT,
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gcc_usb30_sleep_clk = {
1375         .halt_reg = 0x0f00c,
1376         .clkr = {
1377                 .enable_reg = 0x0f00c,
1378                 .enable_mask = BIT(0),
1379                 .hw.init = &(struct clk_init_data){
1380                         .name = "gcc_usb30_sleep_clk",
1381                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1382                         .num_parents = 1,
1383                         .flags = CLK_SET_RATE_PARENT,
1384                         .ops = &clk_branch2_ops,
1385                 },
1386         },
1387 };
1388
1389 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1390         .halt_reg = 0x0f010,
1391         .clkr = {
1392                 .enable_reg = 0x0f010,
1393                 .enable_mask = BIT(0),
1394                 .hw.init = &(struct clk_init_data){
1395                         .name = "gcc_usb30_mock_utmi_clk",
1396                         .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1397                         .num_parents = 1,
1398                         .flags = CLK_SET_RATE_PARENT,
1399                         .ops = &clk_branch2_ops,
1400                 },
1401         },
1402 };
1403
1404 static struct clk_branch gcc_usb3_phy_aux_clk = {
1405         .halt_reg = 0x50000,
1406         .clkr = {
1407                 .enable_reg = 0x50000,
1408                 .enable_mask = BIT(0),
1409                 .hw.init = &(struct clk_init_data){
1410                         .name = "gcc_usb3_phy_aux_clk",
1411                         .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1412                         .num_parents = 1,
1413                         .flags = CLK_SET_RATE_PARENT,
1414                         .ops = &clk_branch2_ops,
1415                 },
1416         },
1417 };
1418
1419 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1420         .halt_reg = 0x50004,
1421         .halt_check = BRANCH_HALT_SKIP,
1422         .clkr = {
1423                 .enable_reg = 0x50004,
1424                 .enable_mask = BIT(0),
1425                 .hw.init = &(struct clk_init_data){
1426                         .name = "gcc_usb3_phy_pipe_clk",
1427                         .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1428                         .num_parents = 1,
1429                         .flags = CLK_SET_RATE_PARENT,
1430                         .ops = &clk_branch2_ops,
1431                 },
1432         },
1433 };
1434
1435 static struct clk_branch gcc_usb20_master_clk = {
1436         .halt_reg = 0x12004,
1437         .clkr = {
1438                 .enable_reg = 0x12004,
1439                 .enable_mask = BIT(0),
1440                 .hw.init = &(struct clk_init_data){
1441                         .name = "gcc_usb20_master_clk",
1442                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1443                         .num_parents = 1,
1444                         .flags = CLK_SET_RATE_PARENT,
1445                         .ops = &clk_branch2_ops,
1446                 },
1447         },
1448 };
1449
1450 static struct clk_branch gcc_usb20_sleep_clk = {
1451         .halt_reg = 0x12008,
1452         .clkr = {
1453                 .enable_reg = 0x12008,
1454                 .enable_mask = BIT(0),
1455                 .hw.init = &(struct clk_init_data){
1456                         .name = "gcc_usb20_sleep_clk",
1457                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1458                         .num_parents = 1,
1459                         .flags = CLK_SET_RATE_PARENT,
1460                         .ops = &clk_branch2_ops,
1461                 },
1462         },
1463 };
1464
1465 static struct clk_branch gcc_usb20_mock_utmi_clk = {
1466         .halt_reg = 0x1200c,
1467         .clkr = {
1468                 .enable_reg = 0x1200c,
1469                 .enable_mask = BIT(0),
1470                 .hw.init = &(struct clk_init_data){
1471                         .name = "gcc_usb20_mock_utmi_clk",
1472                         .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1473                         .num_parents = 1,
1474                         .flags = CLK_SET_RATE_PARENT,
1475                         .ops = &clk_branch2_ops,
1476                 },
1477         },
1478 };
1479
1480 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1481         .halt_reg = 0x6a004,
1482         .clkr = {
1483                 .enable_reg = 0x6a004,
1484                 .enable_mask = BIT(0),
1485                 .hw.init = &(struct clk_init_data){
1486                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1487                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1488                         .num_parents = 1,
1489                         .flags = CLK_SET_RATE_PARENT,
1490                         .ops = &clk_branch2_ops,
1491                 },
1492         },
1493 };
1494
1495 static struct clk_branch gcc_sdcc1_apps_clk = {
1496         .halt_reg = 0x13004,
1497         .clkr = {
1498                 .enable_reg = 0x13004,
1499                 .enable_mask = BIT(0),
1500                 .hw.init = &(struct clk_init_data){
1501                         .name = "gcc_sdcc1_apps_clk",
1502                         .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1503                         .num_parents = 1,
1504                         .flags = CLK_SET_RATE_PARENT,
1505                         .ops = &clk_branch2_ops,
1506                 },
1507         },
1508 };
1509
1510 static struct clk_branch gcc_sdcc1_ahb_clk = {
1511         .halt_reg = 0x13008,
1512         .clkr = {
1513                 .enable_reg = 0x13008,
1514                 .enable_mask = BIT(0),
1515                 .hw.init = &(struct clk_init_data){
1516                         .name = "gcc_sdcc1_ahb_clk",
1517                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1518                         .num_parents = 1,
1519                         .flags = CLK_SET_RATE_PARENT,
1520                         .ops = &clk_branch2_ops,
1521                 },
1522         },
1523 };
1524
1525 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1526         .halt_reg = 0x13038,
1527         .clkr = {
1528                 .enable_reg = 0x13038,
1529                 .enable_mask = BIT(0),
1530                 .hw.init = &(struct clk_init_data){
1531                         .name = "gcc_sdcc1_ice_core_clk",
1532                         .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1533                         .num_parents = 1,
1534                         .flags = CLK_SET_RATE_PARENT,
1535                         .ops = &clk_branch2_ops,
1536                 },
1537         },
1538 };
1539
1540 static struct clk_branch gcc_sdcc2_apps_clk = {
1541         .halt_reg = 0x14004,
1542         .clkr = {
1543                 .enable_reg = 0x14004,
1544                 .enable_mask = BIT(0),
1545                 .hw.init = &(struct clk_init_data){
1546                         .name = "gcc_sdcc2_apps_clk",
1547                         .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1548                         .num_parents = 1,
1549                         .flags = CLK_SET_RATE_PARENT,
1550                         .ops = &clk_branch2_ops,
1551                 },
1552         },
1553 };
1554
1555 static struct clk_branch gcc_sdcc2_ahb_clk = {
1556         .halt_reg = 0x14008,
1557         .clkr = {
1558                 .enable_reg = 0x14008,
1559                 .enable_mask = BIT(0),
1560                 .hw.init = &(struct clk_init_data){
1561                         .name = "gcc_sdcc2_ahb_clk",
1562                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1563                         .num_parents = 1,
1564                         .flags = CLK_SET_RATE_PARENT,
1565                         .ops = &clk_branch2_ops,
1566                 },
1567         },
1568 };
1569
1570 static struct clk_branch gcc_sdcc3_apps_clk = {
1571         .halt_reg = 0x15004,
1572         .clkr = {
1573                 .enable_reg = 0x15004,
1574                 .enable_mask = BIT(0),
1575                 .hw.init = &(struct clk_init_data){
1576                         .name = "gcc_sdcc3_apps_clk",
1577                         .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1578                         .num_parents = 1,
1579                         .flags = CLK_SET_RATE_PARENT,
1580                         .ops = &clk_branch2_ops,
1581                 },
1582         },
1583 };
1584
1585 static struct clk_branch gcc_sdcc3_ahb_clk = {
1586         .halt_reg = 0x15008,
1587         .clkr = {
1588                 .enable_reg = 0x15008,
1589                 .enable_mask = BIT(0),
1590                 .hw.init = &(struct clk_init_data){
1591                         .name = "gcc_sdcc3_ahb_clk",
1592                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1593                         .num_parents = 1,
1594                         .flags = CLK_SET_RATE_PARENT,
1595                         .ops = &clk_branch2_ops,
1596                 },
1597         },
1598 };
1599
1600 static struct clk_branch gcc_sdcc4_apps_clk = {
1601         .halt_reg = 0x16004,
1602         .clkr = {
1603                 .enable_reg = 0x16004,
1604                 .enable_mask = BIT(0),
1605                 .hw.init = &(struct clk_init_data){
1606                         .name = "gcc_sdcc4_apps_clk",
1607                         .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1608                         .num_parents = 1,
1609                         .flags = CLK_SET_RATE_PARENT,
1610                         .ops = &clk_branch2_ops,
1611                 },
1612         },
1613 };
1614
1615 static struct clk_branch gcc_sdcc4_ahb_clk = {
1616         .halt_reg = 0x16008,
1617         .clkr = {
1618                 .enable_reg = 0x16008,
1619                 .enable_mask = BIT(0),
1620                 .hw.init = &(struct clk_init_data){
1621                         .name = "gcc_sdcc4_ahb_clk",
1622                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1623                         .num_parents = 1,
1624                         .flags = CLK_SET_RATE_PARENT,
1625                         .ops = &clk_branch2_ops,
1626                 },
1627         },
1628 };
1629
1630 static struct clk_branch gcc_blsp1_ahb_clk = {
1631         .halt_reg = 0x17004,
1632         .halt_check = BRANCH_HALT_VOTED,
1633         .clkr = {
1634                 .enable_reg = 0x52004,
1635                 .enable_mask = BIT(17),
1636                 .hw.init = &(struct clk_init_data){
1637                         .name = "gcc_blsp1_ahb_clk",
1638                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1639                         .num_parents = 1,
1640                         .flags = CLK_SET_RATE_PARENT,
1641                         .ops = &clk_branch2_ops,
1642                 },
1643         },
1644 };
1645
1646 static struct clk_branch gcc_blsp1_sleep_clk = {
1647         .halt_reg = 0x17008,
1648         .halt_check = BRANCH_HALT_VOTED,
1649         .clkr = {
1650                 .enable_reg = 0x52004,
1651                 .enable_mask = BIT(16),
1652                 .hw.init = &(struct clk_init_data){
1653                         .name = "gcc_blsp1_sleep_clk",
1654                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1655                         .num_parents = 1,
1656                         .flags = CLK_SET_RATE_PARENT,
1657                         .ops = &clk_branch2_ops,
1658                 },
1659         },
1660 };
1661
1662 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1663         .halt_reg = 0x19004,
1664         .clkr = {
1665                 .enable_reg = 0x19004,
1666                 .enable_mask = BIT(0),
1667                 .hw.init = &(struct clk_init_data){
1668                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1669                         .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1670                         .num_parents = 1,
1671                         .flags = CLK_SET_RATE_PARENT,
1672                         .ops = &clk_branch2_ops,
1673                 },
1674         },
1675 };
1676
1677 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1678         .halt_reg = 0x19008,
1679         .clkr = {
1680                 .enable_reg = 0x19008,
1681                 .enable_mask = BIT(0),
1682                 .hw.init = &(struct clk_init_data){
1683                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1684                         .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1685                         .num_parents = 1,
1686                         .flags = CLK_SET_RATE_PARENT,
1687                         .ops = &clk_branch2_ops,
1688                 },
1689         },
1690 };
1691
1692 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1693         .halt_reg = 0x1a004,
1694         .clkr = {
1695                 .enable_reg = 0x1a004,
1696                 .enable_mask = BIT(0),
1697                 .hw.init = &(struct clk_init_data){
1698                         .name = "gcc_blsp1_uart1_apps_clk",
1699                         .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1700                         .num_parents = 1,
1701                         .flags = CLK_SET_RATE_PARENT,
1702                         .ops = &clk_branch2_ops,
1703                 },
1704         },
1705 };
1706
1707 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1708         .halt_reg = 0x1b004,
1709         .clkr = {
1710                 .enable_reg = 0x1b004,
1711                 .enable_mask = BIT(0),
1712                 .hw.init = &(struct clk_init_data){
1713                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1714                         .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1715                         .num_parents = 1,
1716                         .flags = CLK_SET_RATE_PARENT,
1717                         .ops = &clk_branch2_ops,
1718                 },
1719         },
1720 };
1721
1722 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1723         .halt_reg = 0x1b008,
1724         .clkr = {
1725                 .enable_reg = 0x1b008,
1726                 .enable_mask = BIT(0),
1727                 .hw.init = &(struct clk_init_data){
1728                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1729                         .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1730                         .num_parents = 1,
1731                         .flags = CLK_SET_RATE_PARENT,
1732                         .ops = &clk_branch2_ops,
1733                 },
1734         },
1735 };
1736
1737 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1738         .halt_reg = 0x1c004,
1739         .clkr = {
1740                 .enable_reg = 0x1c004,
1741                 .enable_mask = BIT(0),
1742                 .hw.init = &(struct clk_init_data){
1743                         .name = "gcc_blsp1_uart2_apps_clk",
1744                         .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1745                         .num_parents = 1,
1746                         .flags = CLK_SET_RATE_PARENT,
1747                         .ops = &clk_branch2_ops,
1748                 },
1749         },
1750 };
1751
1752 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1753         .halt_reg = 0x1d004,
1754         .clkr = {
1755                 .enable_reg = 0x1d004,
1756                 .enable_mask = BIT(0),
1757                 .hw.init = &(struct clk_init_data){
1758                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1759                         .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1760                         .num_parents = 1,
1761                         .flags = CLK_SET_RATE_PARENT,
1762                         .ops = &clk_branch2_ops,
1763                 },
1764         },
1765 };
1766
1767 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1768         .halt_reg = 0x1d008,
1769         .clkr = {
1770                 .enable_reg = 0x1d008,
1771                 .enable_mask = BIT(0),
1772                 .hw.init = &(struct clk_init_data){
1773                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1774                         .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1775                         .num_parents = 1,
1776                         .flags = CLK_SET_RATE_PARENT,
1777                         .ops = &clk_branch2_ops,
1778                 },
1779         },
1780 };
1781
1782 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1783         .halt_reg = 0x1e004,
1784         .clkr = {
1785                 .enable_reg = 0x1e004,
1786                 .enable_mask = BIT(0),
1787                 .hw.init = &(struct clk_init_data){
1788                         .name = "gcc_blsp1_uart3_apps_clk",
1789                         .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1790                         .num_parents = 1,
1791                         .flags = CLK_SET_RATE_PARENT,
1792                         .ops = &clk_branch2_ops,
1793                 },
1794         },
1795 };
1796
1797 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1798         .halt_reg = 0x1f004,
1799         .clkr = {
1800                 .enable_reg = 0x1f004,
1801                 .enable_mask = BIT(0),
1802                 .hw.init = &(struct clk_init_data){
1803                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1804                         .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1805                         .num_parents = 1,
1806                         .flags = CLK_SET_RATE_PARENT,
1807                         .ops = &clk_branch2_ops,
1808                 },
1809         },
1810 };
1811
1812 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1813         .halt_reg = 0x1f008,
1814         .clkr = {
1815                 .enable_reg = 0x1f008,
1816                 .enable_mask = BIT(0),
1817                 .hw.init = &(struct clk_init_data){
1818                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1819                         .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1820                         .num_parents = 1,
1821                         .flags = CLK_SET_RATE_PARENT,
1822                         .ops = &clk_branch2_ops,
1823                 },
1824         },
1825 };
1826
1827 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1828         .halt_reg = 0x20004,
1829         .clkr = {
1830                 .enable_reg = 0x20004,
1831                 .enable_mask = BIT(0),
1832                 .hw.init = &(struct clk_init_data){
1833                         .name = "gcc_blsp1_uart4_apps_clk",
1834                         .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1835                         .num_parents = 1,
1836                         .flags = CLK_SET_RATE_PARENT,
1837                         .ops = &clk_branch2_ops,
1838                 },
1839         },
1840 };
1841
1842 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1843         .halt_reg = 0x21004,
1844         .clkr = {
1845                 .enable_reg = 0x21004,
1846                 .enable_mask = BIT(0),
1847                 .hw.init = &(struct clk_init_data){
1848                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1849                         .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1850                         .num_parents = 1,
1851                         .flags = CLK_SET_RATE_PARENT,
1852                         .ops = &clk_branch2_ops,
1853                 },
1854         },
1855 };
1856
1857 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1858         .halt_reg = 0x21008,
1859         .clkr = {
1860                 .enable_reg = 0x21008,
1861                 .enable_mask = BIT(0),
1862                 .hw.init = &(struct clk_init_data){
1863                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1864                         .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1865                         .num_parents = 1,
1866                         .flags = CLK_SET_RATE_PARENT,
1867                         .ops = &clk_branch2_ops,
1868                 },
1869         },
1870 };
1871
1872 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1873         .halt_reg = 0x22004,
1874         .clkr = {
1875                 .enable_reg = 0x22004,
1876                 .enable_mask = BIT(0),
1877                 .hw.init = &(struct clk_init_data){
1878                         .name = "gcc_blsp1_uart5_apps_clk",
1879                         .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1880                         .num_parents = 1,
1881                         .flags = CLK_SET_RATE_PARENT,
1882                         .ops = &clk_branch2_ops,
1883                 },
1884         },
1885 };
1886
1887 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1888         .halt_reg = 0x23004,
1889         .clkr = {
1890                 .enable_reg = 0x23004,
1891                 .enable_mask = BIT(0),
1892                 .hw.init = &(struct clk_init_data){
1893                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1894                         .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1895                         .num_parents = 1,
1896                         .flags = CLK_SET_RATE_PARENT,
1897                         .ops = &clk_branch2_ops,
1898                 },
1899         },
1900 };
1901
1902 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1903         .halt_reg = 0x23008,
1904         .clkr = {
1905                 .enable_reg = 0x23008,
1906                 .enable_mask = BIT(0),
1907                 .hw.init = &(struct clk_init_data){
1908                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1909                         .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1910                         .num_parents = 1,
1911                         .flags = CLK_SET_RATE_PARENT,
1912                         .ops = &clk_branch2_ops,
1913                 },
1914         },
1915 };
1916
1917 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1918         .halt_reg = 0x24004,
1919         .clkr = {
1920                 .enable_reg = 0x24004,
1921                 .enable_mask = BIT(0),
1922                 .hw.init = &(struct clk_init_data){
1923                         .name = "gcc_blsp1_uart6_apps_clk",
1924                         .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1925                         .num_parents = 1,
1926                         .flags = CLK_SET_RATE_PARENT,
1927                         .ops = &clk_branch2_ops,
1928                 },
1929         },
1930 };
1931
1932 static struct clk_branch gcc_blsp2_ahb_clk = {
1933         .halt_reg = 0x25004,
1934         .halt_check = BRANCH_HALT_VOTED,
1935         .clkr = {
1936                 .enable_reg = 0x52004,
1937                 .enable_mask = BIT(15),
1938                 .hw.init = &(struct clk_init_data){
1939                         .name = "gcc_blsp2_ahb_clk",
1940                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1941                         .num_parents = 1,
1942                         .flags = CLK_SET_RATE_PARENT,
1943                         .ops = &clk_branch2_ops,
1944                 },
1945         },
1946 };
1947
1948 static struct clk_branch gcc_blsp2_sleep_clk = {
1949         .halt_reg = 0x25008,
1950         .halt_check = BRANCH_HALT_VOTED,
1951         .clkr = {
1952                 .enable_reg = 0x52004,
1953                 .enable_mask = BIT(14),
1954                 .hw.init = &(struct clk_init_data){
1955                         .name = "gcc_blsp2_sleep_clk",
1956                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1957                         .num_parents = 1,
1958                         .flags = CLK_SET_RATE_PARENT,
1959                         .ops = &clk_branch2_ops,
1960                 },
1961         },
1962 };
1963
1964 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1965         .halt_reg = 0x26004,
1966         .clkr = {
1967                 .enable_reg = 0x26004,
1968                 .enable_mask = BIT(0),
1969                 .hw.init = &(struct clk_init_data){
1970                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1971                         .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
1972                         .num_parents = 1,
1973                         .flags = CLK_SET_RATE_PARENT,
1974                         .ops = &clk_branch2_ops,
1975                 },
1976         },
1977 };
1978
1979 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1980         .halt_reg = 0x26008,
1981         .clkr = {
1982                 .enable_reg = 0x26008,
1983                 .enable_mask = BIT(0),
1984                 .hw.init = &(struct clk_init_data){
1985                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1986                         .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
1987                         .num_parents = 1,
1988                         .flags = CLK_SET_RATE_PARENT,
1989                         .ops = &clk_branch2_ops,
1990                 },
1991         },
1992 };
1993
1994 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1995         .halt_reg = 0x27004,
1996         .clkr = {
1997                 .enable_reg = 0x27004,
1998                 .enable_mask = BIT(0),
1999                 .hw.init = &(struct clk_init_data){
2000                         .name = "gcc_blsp2_uart1_apps_clk",
2001                         .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
2002                         .num_parents = 1,
2003                         .flags = CLK_SET_RATE_PARENT,
2004                         .ops = &clk_branch2_ops,
2005                 },
2006         },
2007 };
2008
2009 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
2010         .halt_reg = 0x28004,
2011         .clkr = {
2012                 .enable_reg = 0x28004,
2013                 .enable_mask = BIT(0),
2014                 .hw.init = &(struct clk_init_data){
2015                         .name = "gcc_blsp2_qup2_spi_apps_clk",
2016                         .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
2017                         .num_parents = 1,
2018                         .flags = CLK_SET_RATE_PARENT,
2019                         .ops = &clk_branch2_ops,
2020                 },
2021         },
2022 };
2023
2024 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
2025         .halt_reg = 0x28008,
2026         .clkr = {
2027                 .enable_reg = 0x28008,
2028                 .enable_mask = BIT(0),
2029                 .hw.init = &(struct clk_init_data){
2030                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
2031                         .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
2032                         .num_parents = 1,
2033                         .flags = CLK_SET_RATE_PARENT,
2034                         .ops = &clk_branch2_ops,
2035                 },
2036         },
2037 };
2038
2039 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2040         .halt_reg = 0x29004,
2041         .clkr = {
2042                 .enable_reg = 0x29004,
2043                 .enable_mask = BIT(0),
2044                 .hw.init = &(struct clk_init_data){
2045                         .name = "gcc_blsp2_uart2_apps_clk",
2046                         .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2047                         .num_parents = 1,
2048                         .flags = CLK_SET_RATE_PARENT,
2049                         .ops = &clk_branch2_ops,
2050                 },
2051         },
2052 };
2053
2054 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2055         .halt_reg = 0x2a004,
2056         .clkr = {
2057                 .enable_reg = 0x2a004,
2058                 .enable_mask = BIT(0),
2059                 .hw.init = &(struct clk_init_data){
2060                         .name = "gcc_blsp2_qup3_spi_apps_clk",
2061                         .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2062                         .num_parents = 1,
2063                         .flags = CLK_SET_RATE_PARENT,
2064                         .ops = &clk_branch2_ops,
2065                 },
2066         },
2067 };
2068
2069 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2070         .halt_reg = 0x2a008,
2071         .clkr = {
2072                 .enable_reg = 0x2a008,
2073                 .enable_mask = BIT(0),
2074                 .hw.init = &(struct clk_init_data){
2075                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
2076                         .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2077                         .num_parents = 1,
2078                         .flags = CLK_SET_RATE_PARENT,
2079                         .ops = &clk_branch2_ops,
2080                 },
2081         },
2082 };
2083
2084 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2085         .halt_reg = 0x2b004,
2086         .clkr = {
2087                 .enable_reg = 0x2b004,
2088                 .enable_mask = BIT(0),
2089                 .hw.init = &(struct clk_init_data){
2090                         .name = "gcc_blsp2_uart3_apps_clk",
2091                         .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2092                         .num_parents = 1,
2093                         .flags = CLK_SET_RATE_PARENT,
2094                         .ops = &clk_branch2_ops,
2095                 },
2096         },
2097 };
2098
2099 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2100         .halt_reg = 0x2c004,
2101         .clkr = {
2102                 .enable_reg = 0x2c004,
2103                 .enable_mask = BIT(0),
2104                 .hw.init = &(struct clk_init_data){
2105                         .name = "gcc_blsp2_qup4_spi_apps_clk",
2106                         .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2107                         .num_parents = 1,
2108                         .flags = CLK_SET_RATE_PARENT,
2109                         .ops = &clk_branch2_ops,
2110                 },
2111         },
2112 };
2113
2114 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2115         .halt_reg = 0x2c008,
2116         .clkr = {
2117                 .enable_reg = 0x2c008,
2118                 .enable_mask = BIT(0),
2119                 .hw.init = &(struct clk_init_data){
2120                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
2121                         .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2122                         .num_parents = 1,
2123                         .flags = CLK_SET_RATE_PARENT,
2124                         .ops = &clk_branch2_ops,
2125                 },
2126         },
2127 };
2128
2129 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2130         .halt_reg = 0x2d004,
2131         .clkr = {
2132                 .enable_reg = 0x2d004,
2133                 .enable_mask = BIT(0),
2134                 .hw.init = &(struct clk_init_data){
2135                         .name = "gcc_blsp2_uart4_apps_clk",
2136                         .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2137                         .num_parents = 1,
2138                         .flags = CLK_SET_RATE_PARENT,
2139                         .ops = &clk_branch2_ops,
2140                 },
2141         },
2142 };
2143
2144 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2145         .halt_reg = 0x2e004,
2146         .clkr = {
2147                 .enable_reg = 0x2e004,
2148                 .enable_mask = BIT(0),
2149                 .hw.init = &(struct clk_init_data){
2150                         .name = "gcc_blsp2_qup5_spi_apps_clk",
2151                         .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2152                         .num_parents = 1,
2153                         .flags = CLK_SET_RATE_PARENT,
2154                         .ops = &clk_branch2_ops,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2160         .halt_reg = 0x2e008,
2161         .clkr = {
2162                 .enable_reg = 0x2e008,
2163                 .enable_mask = BIT(0),
2164                 .hw.init = &(struct clk_init_data){
2165                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
2166                         .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2167                         .num_parents = 1,
2168                         .flags = CLK_SET_RATE_PARENT,
2169                         .ops = &clk_branch2_ops,
2170                 },
2171         },
2172 };
2173
2174 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2175         .halt_reg = 0x2f004,
2176         .clkr = {
2177                 .enable_reg = 0x2f004,
2178                 .enable_mask = BIT(0),
2179                 .hw.init = &(struct clk_init_data){
2180                         .name = "gcc_blsp2_uart5_apps_clk",
2181                         .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2182                         .num_parents = 1,
2183                         .flags = CLK_SET_RATE_PARENT,
2184                         .ops = &clk_branch2_ops,
2185                 },
2186         },
2187 };
2188
2189 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2190         .halt_reg = 0x30004,
2191         .clkr = {
2192                 .enable_reg = 0x30004,
2193                 .enable_mask = BIT(0),
2194                 .hw.init = &(struct clk_init_data){
2195                         .name = "gcc_blsp2_qup6_spi_apps_clk",
2196                         .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2197                         .num_parents = 1,
2198                         .flags = CLK_SET_RATE_PARENT,
2199                         .ops = &clk_branch2_ops,
2200                 },
2201         },
2202 };
2203
2204 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2205         .halt_reg = 0x30008,
2206         .clkr = {
2207                 .enable_reg = 0x30008,
2208                 .enable_mask = BIT(0),
2209                 .hw.init = &(struct clk_init_data){
2210                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
2211                         .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2212                         .num_parents = 1,
2213                         .flags = CLK_SET_RATE_PARENT,
2214                         .ops = &clk_branch2_ops,
2215                 },
2216         },
2217 };
2218
2219 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2220         .halt_reg = 0x31004,
2221         .clkr = {
2222                 .enable_reg = 0x31004,
2223                 .enable_mask = BIT(0),
2224                 .hw.init = &(struct clk_init_data){
2225                         .name = "gcc_blsp2_uart6_apps_clk",
2226                         .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2227                         .num_parents = 1,
2228                         .flags = CLK_SET_RATE_PARENT,
2229                         .ops = &clk_branch2_ops,
2230                 },
2231         },
2232 };
2233
2234 static struct clk_branch gcc_pdm_ahb_clk = {
2235         .halt_reg = 0x33004,
2236         .clkr = {
2237                 .enable_reg = 0x33004,
2238                 .enable_mask = BIT(0),
2239                 .hw.init = &(struct clk_init_data){
2240                         .name = "gcc_pdm_ahb_clk",
2241                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2242                         .num_parents = 1,
2243                         .flags = CLK_SET_RATE_PARENT,
2244                         .ops = &clk_branch2_ops,
2245                 },
2246         },
2247 };
2248
2249 static struct clk_branch gcc_pdm2_clk = {
2250         .halt_reg = 0x3300c,
2251         .clkr = {
2252                 .enable_reg = 0x3300c,
2253                 .enable_mask = BIT(0),
2254                 .hw.init = &(struct clk_init_data){
2255                         .name = "gcc_pdm2_clk",
2256                         .parent_names = (const char *[]){ "pdm2_clk_src" },
2257                         .num_parents = 1,
2258                         .flags = CLK_SET_RATE_PARENT,
2259                         .ops = &clk_branch2_ops,
2260                 },
2261         },
2262 };
2263
2264 static struct clk_branch gcc_prng_ahb_clk = {
2265         .halt_reg = 0x34004,
2266         .halt_check = BRANCH_HALT_VOTED,
2267         .clkr = {
2268                 .enable_reg = 0x52004,
2269                 .enable_mask = BIT(13),
2270                 .hw.init = &(struct clk_init_data){
2271                         .name = "gcc_prng_ahb_clk",
2272                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2273                         .num_parents = 1,
2274                         .flags = CLK_SET_RATE_PARENT,
2275                         .ops = &clk_branch2_ops,
2276                 },
2277         },
2278 };
2279
2280 static struct clk_branch gcc_tsif_ahb_clk = {
2281         .halt_reg = 0x36004,
2282         .clkr = {
2283                 .enable_reg = 0x36004,
2284                 .enable_mask = BIT(0),
2285                 .hw.init = &(struct clk_init_data){
2286                         .name = "gcc_tsif_ahb_clk",
2287                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2288                         .num_parents = 1,
2289                         .flags = CLK_SET_RATE_PARENT,
2290                         .ops = &clk_branch2_ops,
2291                 },
2292         },
2293 };
2294
2295 static struct clk_branch gcc_tsif_ref_clk = {
2296         .halt_reg = 0x36008,
2297         .clkr = {
2298                 .enable_reg = 0x36008,
2299                 .enable_mask = BIT(0),
2300                 .hw.init = &(struct clk_init_data){
2301                         .name = "gcc_tsif_ref_clk",
2302                         .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2303                         .num_parents = 1,
2304                         .flags = CLK_SET_RATE_PARENT,
2305                         .ops = &clk_branch2_ops,
2306                 },
2307         },
2308 };
2309
2310 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2311         .halt_reg = 0x3600c,
2312         .clkr = {
2313                 .enable_reg = 0x3600c,
2314                 .enable_mask = BIT(0),
2315                 .hw.init = &(struct clk_init_data){
2316                         .name = "gcc_tsif_inactivity_timers_clk",
2317                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2318                         .num_parents = 1,
2319                         .flags = CLK_SET_RATE_PARENT,
2320                         .ops = &clk_branch2_ops,
2321                 },
2322         },
2323 };
2324
2325 static struct clk_branch gcc_boot_rom_ahb_clk = {
2326         .halt_reg = 0x38004,
2327         .halt_check = BRANCH_HALT_VOTED,
2328         .clkr = {
2329                 .enable_reg = 0x52004,
2330                 .enable_mask = BIT(10),
2331                 .hw.init = &(struct clk_init_data){
2332                         .name = "gcc_boot_rom_ahb_clk",
2333                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2334                         .num_parents = 1,
2335                         .flags = CLK_SET_RATE_PARENT,
2336                         .ops = &clk_branch2_ops,
2337                 },
2338         },
2339 };
2340
2341 static struct clk_branch gcc_bimc_gfx_clk = {
2342         .halt_reg = 0x46018,
2343         .clkr = {
2344                 .enable_reg = 0x46018,
2345                 .enable_mask = BIT(0),
2346                 .hw.init = &(struct clk_init_data){
2347                         .name = "gcc_bimc_gfx_clk",
2348                         .flags = CLK_SET_RATE_PARENT,
2349                         .ops = &clk_branch2_ops,
2350                 },
2351         },
2352 };
2353
2354 static struct clk_branch gcc_hmss_rbcpr_clk = {
2355         .halt_reg = 0x4800c,
2356         .clkr = {
2357                 .enable_reg = 0x4800c,
2358                 .enable_mask = BIT(0),
2359                 .hw.init = &(struct clk_init_data){
2360                         .name = "gcc_hmss_rbcpr_clk",
2361                         .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2362                         .num_parents = 1,
2363                         .flags = CLK_SET_RATE_PARENT,
2364                         .ops = &clk_branch2_ops,
2365                 },
2366         },
2367 };
2368
2369 static struct clk_branch gcc_gp1_clk = {
2370         .halt_reg = 0x64000,
2371         .clkr = {
2372                 .enable_reg = 0x64000,
2373                 .enable_mask = BIT(0),
2374                 .hw.init = &(struct clk_init_data){
2375                         .name = "gcc_gp1_clk",
2376                         .parent_names = (const char *[]){ "gp1_clk_src" },
2377                         .num_parents = 1,
2378                         .flags = CLK_SET_RATE_PARENT,
2379                         .ops = &clk_branch2_ops,
2380                 },
2381         },
2382 };
2383
2384 static struct clk_branch gcc_gp2_clk = {
2385         .halt_reg = 0x65000,
2386         .clkr = {
2387                 .enable_reg = 0x65000,
2388                 .enable_mask = BIT(0),
2389                 .hw.init = &(struct clk_init_data){
2390                         .name = "gcc_gp2_clk",
2391                         .parent_names = (const char *[]){ "gp2_clk_src" },
2392                         .num_parents = 1,
2393                         .flags = CLK_SET_RATE_PARENT,
2394                         .ops = &clk_branch2_ops,
2395                 },
2396         },
2397 };
2398
2399 static struct clk_branch gcc_gp3_clk = {
2400         .halt_reg = 0x66000,
2401         .clkr = {
2402                 .enable_reg = 0x66000,
2403                 .enable_mask = BIT(0),
2404                 .hw.init = &(struct clk_init_data){
2405                         .name = "gcc_gp3_clk",
2406                         .parent_names = (const char *[]){ "gp3_clk_src" },
2407                         .num_parents = 1,
2408                         .flags = CLK_SET_RATE_PARENT,
2409                         .ops = &clk_branch2_ops,
2410                 },
2411         },
2412 };
2413
2414 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2415         .halt_reg = 0x6b008,
2416         .clkr = {
2417                 .enable_reg = 0x6b008,
2418                 .enable_mask = BIT(0),
2419                 .hw.init = &(struct clk_init_data){
2420                         .name = "gcc_pcie_0_slv_axi_clk",
2421                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2422                         .num_parents = 1,
2423                         .flags = CLK_SET_RATE_PARENT,
2424                         .ops = &clk_branch2_ops,
2425                 },
2426         },
2427 };
2428
2429 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2430         .halt_reg = 0x6b00c,
2431         .clkr = {
2432                 .enable_reg = 0x6b00c,
2433                 .enable_mask = BIT(0),
2434                 .hw.init = &(struct clk_init_data){
2435                         .name = "gcc_pcie_0_mstr_axi_clk",
2436                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2437                         .num_parents = 1,
2438                         .flags = CLK_SET_RATE_PARENT,
2439                         .ops = &clk_branch2_ops,
2440                 },
2441         },
2442 };
2443
2444 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2445         .halt_reg = 0x6b010,
2446         .clkr = {
2447                 .enable_reg = 0x6b010,
2448                 .enable_mask = BIT(0),
2449                 .hw.init = &(struct clk_init_data){
2450                         .name = "gcc_pcie_0_cfg_ahb_clk",
2451                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2452                         .num_parents = 1,
2453                         .flags = CLK_SET_RATE_PARENT,
2454                         .ops = &clk_branch2_ops,
2455                 },
2456         },
2457 };
2458
2459 static struct clk_branch gcc_pcie_0_aux_clk = {
2460         .halt_reg = 0x6b014,
2461         .clkr = {
2462                 .enable_reg = 0x6b014,
2463                 .enable_mask = BIT(0),
2464                 .hw.init = &(struct clk_init_data){
2465                         .name = "gcc_pcie_0_aux_clk",
2466                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2467                         .num_parents = 1,
2468                         .flags = CLK_SET_RATE_PARENT,
2469                         .ops = &clk_branch2_ops,
2470                 },
2471         },
2472 };
2473
2474 static struct clk_branch gcc_pcie_0_pipe_clk = {
2475         .halt_reg = 0x6b018,
2476         .halt_check = BRANCH_HALT_SKIP,
2477         .clkr = {
2478                 .enable_reg = 0x6b018,
2479                 .enable_mask = BIT(0),
2480                 .hw.init = &(struct clk_init_data){
2481                         .name = "gcc_pcie_0_pipe_clk",
2482                         .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2483                         .num_parents = 1,
2484                         .flags = CLK_SET_RATE_PARENT,
2485                         .ops = &clk_branch2_ops,
2486                 },
2487         },
2488 };
2489
2490 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2491         .halt_reg = 0x6d008,
2492         .clkr = {
2493                 .enable_reg = 0x6d008,
2494                 .enable_mask = BIT(0),
2495                 .hw.init = &(struct clk_init_data){
2496                         .name = "gcc_pcie_1_slv_axi_clk",
2497                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2498                         .num_parents = 1,
2499                         .flags = CLK_SET_RATE_PARENT,
2500                         .ops = &clk_branch2_ops,
2501                 },
2502         },
2503 };
2504
2505 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2506         .halt_reg = 0x6d00c,
2507         .clkr = {
2508                 .enable_reg = 0x6d00c,
2509                 .enable_mask = BIT(0),
2510                 .hw.init = &(struct clk_init_data){
2511                         .name = "gcc_pcie_1_mstr_axi_clk",
2512                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2513                         .num_parents = 1,
2514                         .flags = CLK_SET_RATE_PARENT,
2515                         .ops = &clk_branch2_ops,
2516                 },
2517         },
2518 };
2519
2520 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2521         .halt_reg = 0x6d010,
2522         .clkr = {
2523                 .enable_reg = 0x6d010,
2524                 .enable_mask = BIT(0),
2525                 .hw.init = &(struct clk_init_data){
2526                         .name = "gcc_pcie_1_cfg_ahb_clk",
2527                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2528                         .num_parents = 1,
2529                         .flags = CLK_SET_RATE_PARENT,
2530                         .ops = &clk_branch2_ops,
2531                 },
2532         },
2533 };
2534
2535 static struct clk_branch gcc_pcie_1_aux_clk = {
2536         .halt_reg = 0x6d014,
2537         .clkr = {
2538                 .enable_reg = 0x6d014,
2539                 .enable_mask = BIT(0),
2540                 .hw.init = &(struct clk_init_data){
2541                         .name = "gcc_pcie_1_aux_clk",
2542                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2543                         .num_parents = 1,
2544                         .flags = CLK_SET_RATE_PARENT,
2545                         .ops = &clk_branch2_ops,
2546                 },
2547         },
2548 };
2549
2550 static struct clk_branch gcc_pcie_1_pipe_clk = {
2551         .halt_reg = 0x6d018,
2552         .halt_check = BRANCH_HALT_SKIP,
2553         .clkr = {
2554                 .enable_reg = 0x6d018,
2555                 .enable_mask = BIT(0),
2556                 .hw.init = &(struct clk_init_data){
2557                         .name = "gcc_pcie_1_pipe_clk",
2558                         .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2559                         .num_parents = 1,
2560                         .flags = CLK_SET_RATE_PARENT,
2561                         .ops = &clk_branch2_ops,
2562                 },
2563         },
2564 };
2565
2566 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2567         .halt_reg = 0x6e008,
2568         .clkr = {
2569                 .enable_reg = 0x6e008,
2570                 .enable_mask = BIT(0),
2571                 .hw.init = &(struct clk_init_data){
2572                         .name = "gcc_pcie_2_slv_axi_clk",
2573                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2574                         .num_parents = 1,
2575                         .flags = CLK_SET_RATE_PARENT,
2576                         .ops = &clk_branch2_ops,
2577                 },
2578         },
2579 };
2580
2581 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2582         .halt_reg = 0x6e00c,
2583         .clkr = {
2584                 .enable_reg = 0x6e00c,
2585                 .enable_mask = BIT(0),
2586                 .hw.init = &(struct clk_init_data){
2587                         .name = "gcc_pcie_2_mstr_axi_clk",
2588                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2589                         .num_parents = 1,
2590                         .flags = CLK_SET_RATE_PARENT,
2591                         .ops = &clk_branch2_ops,
2592                 },
2593         },
2594 };
2595
2596 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2597         .halt_reg = 0x6e010,
2598         .clkr = {
2599                 .enable_reg = 0x6e010,
2600                 .enable_mask = BIT(0),
2601                 .hw.init = &(struct clk_init_data){
2602                         .name = "gcc_pcie_2_cfg_ahb_clk",
2603                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2604                         .num_parents = 1,
2605                         .flags = CLK_SET_RATE_PARENT,
2606                         .ops = &clk_branch2_ops,
2607                 },
2608         },
2609 };
2610
2611 static struct clk_branch gcc_pcie_2_aux_clk = {
2612         .halt_reg = 0x6e014,
2613         .clkr = {
2614                 .enable_reg = 0x6e014,
2615                 .enable_mask = BIT(0),
2616                 .hw.init = &(struct clk_init_data){
2617                         .name = "gcc_pcie_2_aux_clk",
2618                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2619                         .num_parents = 1,
2620                         .flags = CLK_SET_RATE_PARENT,
2621                         .ops = &clk_branch2_ops,
2622                 },
2623         },
2624 };
2625
2626 static struct clk_branch gcc_pcie_2_pipe_clk = {
2627         .halt_reg = 0x6e018,
2628         .halt_check = BRANCH_HALT_SKIP,
2629         .clkr = {
2630                 .enable_reg = 0x6e018,
2631                 .enable_mask = BIT(0),
2632                 .hw.init = &(struct clk_init_data){
2633                         .name = "gcc_pcie_2_pipe_clk",
2634                         .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2635                         .num_parents = 1,
2636                         .flags = CLK_SET_RATE_PARENT,
2637                         .ops = &clk_branch2_ops,
2638                 },
2639         },
2640 };
2641
2642 static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2643         .halt_reg = 0x6f004,
2644         .clkr = {
2645                 .enable_reg = 0x6f004,
2646                 .enable_mask = BIT(0),
2647                 .hw.init = &(struct clk_init_data){
2648                         .name = "gcc_pcie_phy_cfg_ahb_clk",
2649                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2650                         .num_parents = 1,
2651                         .flags = CLK_SET_RATE_PARENT,
2652                         .ops = &clk_branch2_ops,
2653                 },
2654         },
2655 };
2656
2657 static struct clk_branch gcc_pcie_phy_aux_clk = {
2658         .halt_reg = 0x6f008,
2659         .clkr = {
2660                 .enable_reg = 0x6f008,
2661                 .enable_mask = BIT(0),
2662                 .hw.init = &(struct clk_init_data){
2663                         .name = "gcc_pcie_phy_aux_clk",
2664                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2665                         .num_parents = 1,
2666                         .flags = CLK_SET_RATE_PARENT,
2667                         .ops = &clk_branch2_ops,
2668                 },
2669         },
2670 };
2671
2672 static struct clk_branch gcc_ufs_axi_clk = {
2673         .halt_reg = 0x75008,
2674         .clkr = {
2675                 .enable_reg = 0x75008,
2676                 .enable_mask = BIT(0),
2677                 .hw.init = &(struct clk_init_data){
2678                         .name = "gcc_ufs_axi_clk",
2679                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2680                         .num_parents = 1,
2681                         .flags = CLK_SET_RATE_PARENT,
2682                         .ops = &clk_branch2_ops,
2683                 },
2684         },
2685 };
2686
2687 static struct clk_branch gcc_ufs_ahb_clk = {
2688         .halt_reg = 0x7500c,
2689         .clkr = {
2690                 .enable_reg = 0x7500c,
2691                 .enable_mask = BIT(0),
2692                 .hw.init = &(struct clk_init_data){
2693                         .name = "gcc_ufs_ahb_clk",
2694                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2695                         .num_parents = 1,
2696                         .flags = CLK_SET_RATE_PARENT,
2697                         .ops = &clk_branch2_ops,
2698                 },
2699         },
2700 };
2701
2702 static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2703         .mult = 1,
2704         .div = 16,
2705         .hw.init = &(struct clk_init_data){
2706                 .name = "ufs_tx_cfg_clk_src",
2707                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2708                 .num_parents = 1,
2709                 .flags = CLK_SET_RATE_PARENT,
2710                 .ops = &clk_fixed_factor_ops,
2711         },
2712 };
2713
2714 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2715         .halt_reg = 0x75010,
2716         .clkr = {
2717                 .enable_reg = 0x75010,
2718                 .enable_mask = BIT(0),
2719                 .hw.init = &(struct clk_init_data){
2720                         .name = "gcc_ufs_tx_cfg_clk",
2721                         .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2722                         .num_parents = 1,
2723                         .flags = CLK_SET_RATE_PARENT,
2724                         .ops = &clk_branch2_ops,
2725                 },
2726         },
2727 };
2728
2729 static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2730         .mult = 1,
2731         .div = 16,
2732         .hw.init = &(struct clk_init_data){
2733                 .name = "ufs_rx_cfg_clk_src",
2734                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2735                 .num_parents = 1,
2736                 .flags = CLK_SET_RATE_PARENT,
2737                 .ops = &clk_fixed_factor_ops,
2738         },
2739 };
2740
2741 static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
2742         .halt_reg = 0x7d010,
2743         .halt_check = BRANCH_HALT_VOTED,
2744         .clkr = {
2745                 .enable_reg = 0x7d010,
2746                 .enable_mask = BIT(0),
2747                 .hw.init = &(struct clk_init_data){
2748                         .name = "hlos1_vote_lpass_core_smmu_clk",
2749                         .ops = &clk_branch2_ops,
2750                 },
2751         },
2752 };
2753
2754 static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
2755         .halt_reg = 0x7d014,
2756         .halt_check = BRANCH_HALT_VOTED,
2757         .clkr = {
2758                 .enable_reg = 0x7d014,
2759                 .enable_mask = BIT(0),
2760                 .hw.init = &(struct clk_init_data){
2761                         .name = "hlos1_vote_lpass_adsp_smmu_clk",
2762                         .ops = &clk_branch2_ops,
2763                 },
2764         },
2765 };
2766
2767 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2768         .halt_reg = 0x75014,
2769         .clkr = {
2770                 .enable_reg = 0x75014,
2771                 .enable_mask = BIT(0),
2772                 .hw.init = &(struct clk_init_data){
2773                         .name = "gcc_ufs_rx_cfg_clk",
2774                         .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2775                         .num_parents = 1,
2776                         .flags = CLK_SET_RATE_PARENT,
2777                         .ops = &clk_branch2_ops,
2778                 },
2779         },
2780 };
2781
2782 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2783         .halt_reg = 0x75018,
2784         .clkr = {
2785                 .enable_reg = 0x75018,
2786                 .enable_mask = BIT(0),
2787                 .hw.init = &(struct clk_init_data){
2788                         .name = "gcc_ufs_tx_symbol_0_clk",
2789                         .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2790                         .num_parents = 1,
2791                         .flags = CLK_SET_RATE_PARENT,
2792                         .ops = &clk_branch2_ops,
2793                 },
2794         },
2795 };
2796
2797 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2798         .halt_reg = 0x7501c,
2799         .halt_check = BRANCH_HALT_SKIP,
2800         .clkr = {
2801                 .enable_reg = 0x7501c,
2802                 .enable_mask = BIT(0),
2803                 .hw.init = &(struct clk_init_data){
2804                         .name = "gcc_ufs_rx_symbol_0_clk",
2805                         .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2806                         .num_parents = 1,
2807                         .flags = CLK_SET_RATE_PARENT,
2808                         .ops = &clk_branch2_ops,
2809                 },
2810         },
2811 };
2812
2813 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2814         .halt_reg = 0x75020,
2815         .halt_check = BRANCH_HALT_SKIP,
2816         .clkr = {
2817                 .enable_reg = 0x75020,
2818                 .enable_mask = BIT(0),
2819                 .hw.init = &(struct clk_init_data){
2820                         .name = "gcc_ufs_rx_symbol_1_clk",
2821                         .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2822                         .num_parents = 1,
2823                         .flags = CLK_SET_RATE_PARENT,
2824                         .ops = &clk_branch2_ops,
2825                 },
2826         },
2827 };
2828
2829 static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2830         .mult = 1,
2831         .div = 2,
2832         .hw.init = &(struct clk_init_data){
2833                 .name = "ufs_ice_core_postdiv_clk_src",
2834                 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2835                 .num_parents = 1,
2836                 .flags = CLK_SET_RATE_PARENT,
2837                 .ops = &clk_fixed_factor_ops,
2838         },
2839 };
2840
2841 static struct clk_branch gcc_ufs_unipro_core_clk = {
2842         .halt_reg = 0x7600c,
2843         .clkr = {
2844                 .enable_reg = 0x7600c,
2845                 .enable_mask = BIT(0),
2846                 .hw.init = &(struct clk_init_data){
2847                         .name = "gcc_ufs_unipro_core_clk",
2848                         .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2849                         .num_parents = 1,
2850                         .flags = CLK_SET_RATE_PARENT,
2851                         .ops = &clk_branch2_ops,
2852                 },
2853         },
2854 };
2855
2856 static struct clk_branch gcc_ufs_ice_core_clk = {
2857         .halt_reg = 0x76010,
2858         .clkr = {
2859                 .enable_reg = 0x76010,
2860                 .enable_mask = BIT(0),
2861                 .hw.init = &(struct clk_init_data){
2862                         .name = "gcc_ufs_ice_core_clk",
2863                         .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2864                         .num_parents = 1,
2865                         .flags = CLK_SET_RATE_PARENT,
2866                         .ops = &clk_branch2_ops,
2867                 },
2868         },
2869 };
2870
2871 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2872         .halt_check = BRANCH_HALT_DELAY,
2873         .clkr = {
2874                 .enable_reg = 0x76030,
2875                 .enable_mask = BIT(0),
2876                 .hw.init = &(struct clk_init_data){
2877                         .name = "gcc_ufs_sys_clk_core_clk",
2878                         .ops = &clk_branch2_ops,
2879                 },
2880         },
2881 };
2882
2883 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2884         .halt_check = BRANCH_HALT_DELAY,
2885         .clkr = {
2886                 .enable_reg = 0x76034,
2887                 .enable_mask = BIT(0),
2888                 .hw.init = &(struct clk_init_data){
2889                         .name = "gcc_ufs_tx_symbol_clk_core_clk",
2890                         .ops = &clk_branch2_ops,
2891                 },
2892         },
2893 };
2894
2895 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2896         .halt_reg = 0x81008,
2897         .clkr = {
2898                 .enable_reg = 0x81008,
2899                 .enable_mask = BIT(0),
2900                 .hw.init = &(struct clk_init_data){
2901                         .name = "gcc_aggre0_snoc_axi_clk",
2902                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2903                         .num_parents = 1,
2904                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2905                         .ops = &clk_branch2_ops,
2906                 },
2907         },
2908 };
2909
2910 static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2911         .halt_reg = 0x8100c,
2912         .clkr = {
2913                 .enable_reg = 0x8100c,
2914                 .enable_mask = BIT(0),
2915                 .hw.init = &(struct clk_init_data){
2916                         .name = "gcc_aggre0_cnoc_ahb_clk",
2917                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2918                         .num_parents = 1,
2919                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2920                         .ops = &clk_branch2_ops,
2921                 },
2922         },
2923 };
2924
2925 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2926         .halt_reg = 0x81014,
2927         .clkr = {
2928                 .enable_reg = 0x81014,
2929                 .enable_mask = BIT(0),
2930                 .hw.init = &(struct clk_init_data){
2931                         .name = "gcc_smmu_aggre0_axi_clk",
2932                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2933                         .num_parents = 1,
2934                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2935                         .ops = &clk_branch2_ops,
2936                 },
2937         },
2938 };
2939
2940 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2941         .halt_reg = 0x81018,
2942         .clkr = {
2943                 .enable_reg = 0x81018,
2944                 .enable_mask = BIT(0),
2945                 .hw.init = &(struct clk_init_data){
2946                         .name = "gcc_smmu_aggre0_ahb_clk",
2947                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2948                         .num_parents = 1,
2949                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2950                         .ops = &clk_branch2_ops,
2951                 },
2952         },
2953 };
2954
2955 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2956         .halt_reg = 0x83014,
2957         .clkr = {
2958                 .enable_reg = 0x83014,
2959                 .enable_mask = BIT(0),
2960                 .hw.init = &(struct clk_init_data){
2961                         .name = "gcc_aggre2_ufs_axi_clk",
2962                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2963                         .num_parents = 1,
2964                         .flags = CLK_SET_RATE_PARENT,
2965                         .ops = &clk_branch2_ops,
2966                 },
2967         },
2968 };
2969
2970 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
2971         .halt_reg = 0x83018,
2972         .clkr = {
2973                 .enable_reg = 0x83018,
2974                 .enable_mask = BIT(0),
2975                 .hw.init = &(struct clk_init_data){
2976                         .name = "gcc_aggre2_usb3_axi_clk",
2977                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
2978                         .num_parents = 1,
2979                         .flags = CLK_SET_RATE_PARENT,
2980                         .ops = &clk_branch2_ops,
2981                 },
2982         },
2983 };
2984
2985 static struct clk_branch gcc_qspi_ahb_clk = {
2986         .halt_reg = 0x8b004,
2987         .clkr = {
2988                 .enable_reg = 0x8b004,
2989                 .enable_mask = BIT(0),
2990                 .hw.init = &(struct clk_init_data){
2991                         .name = "gcc_qspi_ahb_clk",
2992                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2993                         .num_parents = 1,
2994                         .flags = CLK_SET_RATE_PARENT,
2995                         .ops = &clk_branch2_ops,
2996                 },
2997         },
2998 };
2999
3000 static struct clk_branch gcc_qspi_ser_clk = {
3001         .halt_reg = 0x8b008,
3002         .clkr = {
3003                 .enable_reg = 0x8b008,
3004                 .enable_mask = BIT(0),
3005                 .hw.init = &(struct clk_init_data){
3006                         .name = "gcc_qspi_ser_clk",
3007                         .parent_names = (const char *[]){ "qspi_ser_clk_src" },
3008                         .num_parents = 1,
3009                         .flags = CLK_SET_RATE_PARENT,
3010                         .ops = &clk_branch2_ops,
3011                 },
3012         },
3013 };
3014
3015 static struct clk_branch gcc_usb3_clkref_clk = {
3016         .halt_reg = 0x8800C,
3017         .clkr = {
3018                 .enable_reg = 0x8800C,
3019                 .enable_mask = BIT(0),
3020                 .hw.init = &(struct clk_init_data){
3021                         .name = "gcc_usb3_clkref_clk",
3022                         .parent_names = (const char *[]){ "xo" },
3023                         .num_parents = 1,
3024                         .ops = &clk_branch2_ops,
3025                 },
3026         },
3027 };
3028
3029 static struct clk_branch gcc_hdmi_clkref_clk = {
3030         .halt_reg = 0x88000,
3031         .clkr = {
3032                 .enable_reg = 0x88000,
3033                 .enable_mask = BIT(0),
3034                 .hw.init = &(struct clk_init_data){
3035                         .name = "gcc_hdmi_clkref_clk",
3036                         .parent_names = (const char *[]){ "xo" },
3037                         .num_parents = 1,
3038                         .ops = &clk_branch2_ops,
3039                 },
3040         },
3041 };
3042
3043 static struct clk_branch gcc_ufs_clkref_clk = {
3044         .halt_reg = 0x88008,
3045         .clkr = {
3046                 .enable_reg = 0x88008,
3047                 .enable_mask = BIT(0),
3048                 .hw.init = &(struct clk_init_data){
3049                         .name = "gcc_ufs_clkref_clk",
3050                         .parent_names = (const char *[]){ "xo" },
3051                         .num_parents = 1,
3052                         .ops = &clk_branch2_ops,
3053                 },
3054         },
3055 };
3056
3057 static struct clk_branch gcc_pcie_clkref_clk = {
3058         .halt_reg = 0x88010,
3059         .clkr = {
3060                 .enable_reg = 0x88010,
3061                 .enable_mask = BIT(0),
3062                 .hw.init = &(struct clk_init_data){
3063                         .name = "gcc_pcie_clkref_clk",
3064                         .parent_names = (const char *[]){ "xo" },
3065                         .num_parents = 1,
3066                         .ops = &clk_branch2_ops,
3067                 },
3068         },
3069 };
3070
3071 static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3072         .halt_reg = 0x88014,
3073         .clkr = {
3074                 .enable_reg = 0x88014,
3075                 .enable_mask = BIT(0),
3076                 .hw.init = &(struct clk_init_data){
3077                         .name = "gcc_rx2_usb2_clkref_clk",
3078                         .parent_names = (const char *[]){ "xo" },
3079                         .num_parents = 1,
3080                         .ops = &clk_branch2_ops,
3081                 },
3082         },
3083 };
3084
3085 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3086         .halt_reg = 0x88018,
3087         .clkr = {
3088                 .enable_reg = 0x88018,
3089                 .enable_mask = BIT(0),
3090                 .hw.init = &(struct clk_init_data){
3091                         .name = "gcc_rx1_usb2_clkref_clk",
3092                         .parent_names = (const char *[]){ "xo" },
3093                         .num_parents = 1,
3094                         .ops = &clk_branch2_ops,
3095                 },
3096         },
3097 };
3098
3099 static struct clk_hw *gcc_msm8996_hws[] = {
3100         &xo.hw,
3101         &gpll0_early_div.hw,
3102         &ufs_tx_cfg_clk_src.hw,
3103         &ufs_rx_cfg_clk_src.hw,
3104         &ufs_ice_core_postdiv_clk_src.hw,
3105 };
3106
3107 static struct gdsc aggre0_noc_gdsc = {
3108         .gdscr = 0x81004,
3109         .gds_hw_ctrl = 0x81028,
3110         .pd = {
3111                 .name = "aggre0_noc",
3112         },
3113         .pwrsts = PWRSTS_OFF_ON,
3114         .flags = VOTABLE | ALWAYS_ON,
3115 };
3116
3117 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3118         .gdscr = 0x7d024,
3119         .pd = {
3120                 .name = "hlos1_vote_aggre0_noc",
3121         },
3122         .pwrsts = PWRSTS_OFF_ON,
3123         .flags = VOTABLE,
3124 };
3125
3126 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3127         .gdscr = 0x7d034,
3128         .pd = {
3129                 .name = "hlos1_vote_lpass_adsp",
3130         },
3131         .pwrsts = PWRSTS_OFF_ON,
3132         .flags = VOTABLE,
3133 };
3134
3135 static struct gdsc hlos1_vote_lpass_core_gdsc = {
3136         .gdscr = 0x7d038,
3137         .pd = {
3138                 .name = "hlos1_vote_lpass_core",
3139         },
3140         .pwrsts = PWRSTS_OFF_ON,
3141         .flags = VOTABLE,
3142 };
3143
3144 static struct gdsc usb30_gdsc = {
3145         .gdscr = 0xf004,
3146         .pd = {
3147                 .name = "usb30",
3148         },
3149         .pwrsts = PWRSTS_OFF_ON,
3150 };
3151
3152 static struct gdsc pcie0_gdsc = {
3153         .gdscr = 0x6b004,
3154         .pd = {
3155                 .name = "pcie0",
3156         },
3157         .pwrsts = PWRSTS_OFF_ON,
3158 };
3159
3160 static struct gdsc pcie1_gdsc = {
3161         .gdscr = 0x6d004,
3162         .pd = {
3163                 .name = "pcie1",
3164         },
3165         .pwrsts = PWRSTS_OFF_ON,
3166 };
3167
3168 static struct gdsc pcie2_gdsc = {
3169         .gdscr = 0x6e004,
3170         .pd = {
3171                 .name = "pcie2",
3172         },
3173         .pwrsts = PWRSTS_OFF_ON,
3174 };
3175
3176 static struct gdsc ufs_gdsc = {
3177         .gdscr = 0x75004,
3178         .pd = {
3179                 .name = "ufs",
3180         },
3181         .pwrsts = PWRSTS_OFF_ON,
3182 };
3183
3184 static struct clk_regmap *gcc_msm8996_clocks[] = {
3185         [GPLL0_EARLY] = &gpll0_early.clkr,
3186         [GPLL0] = &gpll0.clkr,
3187         [GPLL4_EARLY] = &gpll4_early.clkr,
3188         [GPLL4] = &gpll4.clkr,
3189         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3190         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3191         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3192         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3193         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3194         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3195         [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3196         [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3197         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3198         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3199         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3200         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3201         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3202         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3203         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3204         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3205         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3206         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3207         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3208         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3209         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3210         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3211         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3212         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3213         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3214         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3215         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3216         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3217         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3218         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3219         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3220         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3221         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3222         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3223         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3224         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3225         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3226         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3227         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3228         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3229         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3230         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3231         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3232         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3233         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3234         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3235         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3236         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3237         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3238         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3239         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3240         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3241         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3242         [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3243         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3244         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3245         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3246         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3247         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3248         [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3249         [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3250         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3251         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3252         [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3253         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3254         [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3255         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3256         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3257         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3258         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3259         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3260         [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3261         [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3262         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3263         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3264         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3265         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3266         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3267         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3268         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3269         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3270         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3271         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3272         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3273         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3274         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3275         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3276         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3277         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3278         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3279         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3280         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3281         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3282         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3283         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3284         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3285         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3286         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3287         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3288         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3289         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3290         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3291         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3292         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3293         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3294         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3295         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3296         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3297         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3298         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3299         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3300         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3301         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3302         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3303         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3304         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3305         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3306         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3307         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3308         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3309         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3310         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3311         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3312         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3313         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3314         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3315         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3316         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3317         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3318         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3319         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3320         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3321         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3322         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3323         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3324         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3325         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3326         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3327         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3328         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3329         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3330         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3331         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3332         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3333         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3334         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3335         [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3336         [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3337         [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3338         [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3339         [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3340         [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3341         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3342         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3343         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3344         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3345         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3346         [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
3347         [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
3348         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3349         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3350         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3351         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3352         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3353         [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3354         [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3355         [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3356         [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3357         [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3358         [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3359         [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3360         [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3361         [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3362         [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3363         [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3364         [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3365         [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3366         [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3367         [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3368         [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3369 };
3370
3371 static struct gdsc *gcc_msm8996_gdscs[] = {
3372         [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3373         [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3374         [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3375         [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3376         [USB30_GDSC] = &usb30_gdsc,
3377         [PCIE0_GDSC] = &pcie0_gdsc,
3378         [PCIE1_GDSC] = &pcie1_gdsc,
3379         [PCIE2_GDSC] = &pcie2_gdsc,
3380         [UFS_GDSC] = &ufs_gdsc,
3381 };
3382
3383 static const struct qcom_reset_map gcc_msm8996_resets[] = {
3384         [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3385         [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3386         [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3387         [GCC_IMEM_BCR] = { 0x8000 },
3388         [GCC_MMSS_BCR] = { 0x9000 },
3389         [GCC_PIMEM_BCR] = { 0x0a000 },
3390         [GCC_QDSS_BCR] = { 0x0c000 },
3391         [GCC_USB_30_BCR] = { 0x0f000 },
3392         [GCC_USB_20_BCR] = { 0x12000 },
3393         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3394         [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3395         [GCC_USB3_PHY_BCR] = { 0x50020 },
3396         [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3397         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3398         [GCC_SDCC1_BCR] = { 0x13000 },
3399         [GCC_SDCC2_BCR] = { 0x14000 },
3400         [GCC_SDCC3_BCR] = { 0x15000 },
3401         [GCC_SDCC4_BCR] = { 0x16000 },
3402         [GCC_BLSP1_BCR] = { 0x17000 },
3403         [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3404         [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3405         [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3406         [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3407         [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3408         [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3409         [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3410         [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3411         [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3412         [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3413         [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3414         [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3415         [GCC_BLSP2_BCR] = { 0x25000 },
3416         [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3417         [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3418         [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3419         [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3420         [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3421         [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3422         [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3423         [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3424         [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3425         [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3426         [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3427         [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3428         [GCC_PDM_BCR] = { 0x33000 },
3429         [GCC_PRNG_BCR] = { 0x34000 },
3430         [GCC_TSIF_BCR] = { 0x36000 },
3431         [GCC_TCSR_BCR] = { 0x37000 },
3432         [GCC_BOOT_ROM_BCR] = { 0x38000 },
3433         [GCC_MSG_RAM_BCR] = { 0x39000 },
3434         [GCC_TLMM_BCR] = { 0x3a000 },
3435         [GCC_MPM_BCR] = { 0x3b000 },
3436         [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3437         [GCC_SPMI_BCR] = { 0x3f000 },
3438         [GCC_SPDM_BCR] = { 0x40000 },
3439         [GCC_CE1_BCR] = { 0x41000 },
3440         [GCC_BIMC_BCR] = { 0x44000 },
3441         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3442         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3443         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3444         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3445         [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3446         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3447         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3448         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3449         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3450         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3451         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3452         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3453         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3454         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3455         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3456         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3457         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3458         [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3459         [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3460         [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3461         [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3462         [GCC_APB2JTAG_BCR] = { 0x4c000 },
3463         [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3464         [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3465         [GCC_PCIE_0_BCR] = { 0x6b000 },
3466         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3467         [GCC_PCIE_1_BCR] = { 0x6d000 },
3468         [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3469         [GCC_PCIE_2_BCR] = { 0x6e000 },
3470         [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3471         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3472         [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3473         [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3474         [GCC_DCD_BCR] = { 0x70000 },
3475         [GCC_OBT_ODT_BCR] = { 0x73000 },
3476         [GCC_UFS_BCR] = { 0x75000 },
3477         [GCC_SSC_BCR] = { 0x63000 },
3478         [GCC_VS_BCR] = { 0x7a000 },
3479         [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3480         [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3481         [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3482         [GCC_DCC_BCR] = { 0x84000 },
3483         [GCC_IPA_BCR] = { 0x89000 },
3484         [GCC_QSPI_BCR] = { 0x8b000 },
3485         [GCC_SKL_BCR] = { 0x8c000 },
3486         [GCC_MSMPU_BCR] = { 0x8d000 },
3487         [GCC_MSS_Q6_BCR] = { 0x8e000 },
3488         [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3489         [GCC_MSS_RESTART] = { 0x8f008 },
3490 };
3491
3492 static const struct regmap_config gcc_msm8996_regmap_config = {
3493         .reg_bits       = 32,
3494         .reg_stride     = 4,
3495         .val_bits       = 32,
3496         .max_register   = 0x8f010,
3497         .fast_io        = true,
3498 };
3499
3500 static const struct qcom_cc_desc gcc_msm8996_desc = {
3501         .config = &gcc_msm8996_regmap_config,
3502         .clks = gcc_msm8996_clocks,
3503         .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3504         .resets = gcc_msm8996_resets,
3505         .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3506         .gdscs = gcc_msm8996_gdscs,
3507         .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3508 };
3509
3510 static const struct of_device_id gcc_msm8996_match_table[] = {
3511         { .compatible = "qcom,gcc-msm8996" },
3512         { }
3513 };
3514 MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3515
3516 static int gcc_msm8996_probe(struct platform_device *pdev)
3517 {
3518         struct device *dev = &pdev->dev;
3519         int i, ret;
3520         struct regmap *regmap;
3521
3522         regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3523         if (IS_ERR(regmap))
3524                 return PTR_ERR(regmap);
3525
3526         /*
3527          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3528          * turned off by hardware during certain apps low power modes.
3529          */
3530         regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3531
3532         for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3533                 ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
3534                 if (ret)
3535                         return ret;
3536         }
3537
3538         return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3539 }
3540
3541 static struct platform_driver gcc_msm8996_driver = {
3542         .probe          = gcc_msm8996_probe,
3543         .driver         = {
3544                 .name   = "gcc-msm8996",
3545                 .of_match_table = gcc_msm8996_match_table,
3546         },
3547 };
3548
3549 static int __init gcc_msm8996_init(void)
3550 {
3551         return platform_driver_register(&gcc_msm8996_driver);
3552 }
3553 core_initcall(gcc_msm8996_init);
3554
3555 static void __exit gcc_msm8996_exit(void)
3556 {
3557         platform_driver_unregister(&gcc_msm8996_driver);
3558 }
3559 module_exit(gcc_msm8996_exit);
3560
3561 MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3562 MODULE_LICENSE("GPL v2");
3563 MODULE_ALIAS("platform:gcc-msm8996");