drivers/clk/imx/clk-imx5.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   4  */
   5 #include <linux/mm.h>
   6 #include <linux/delay.h>
   7 #include <linux/clk.h>
   8 #include <linux/io.h>
   9 #include <linux/clkdev.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/err.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/sizes.h>
  16 #include <soc/imx/revision.h>
  17 #include <dt-bindings/clock/imx5-clock.h>
  18
  19 #include "clk.h"
  20
  21 #define MX51_DPLL1_BASE         0x83f80000
  22 #define MX51_DPLL2_BASE         0x83f84000
  23 #define MX51_DPLL3_BASE         0x83f88000
  24
  25 #define MX53_DPLL1_BASE         0x63f80000
  26 #define MX53_DPLL2_BASE         0x63f84000
  27 #define MX53_DPLL3_BASE         0x63f88000
  28 #define MX53_DPLL4_BASE         0x63f8c000
  29
  30 #define MXC_CCM_CCR             (ccm_base + 0x00)
  31 #define MXC_CCM_CCDR            (ccm_base + 0x04)
  32 #define MXC_CCM_CSR             (ccm_base + 0x08)
  33 #define MXC_CCM_CCSR            (ccm_base + 0x0c)
  34 #define MXC_CCM_CACRR           (ccm_base + 0x10)
  35 #define MXC_CCM_CBCDR           (ccm_base + 0x14)
  36 #define MXC_CCM_CBCMR           (ccm_base + 0x18)
  37 #define MXC_CCM_CSCMR1          (ccm_base + 0x1c)
  38 #define MXC_CCM_CSCMR2          (ccm_base + 0x20)
  39 #define MXC_CCM_CSCDR1          (ccm_base + 0x24)
  40 #define MXC_CCM_CS1CDR          (ccm_base + 0x28)
  41 #define MXC_CCM_CS2CDR          (ccm_base + 0x2c)
  42 #define MXC_CCM_CDCDR           (ccm_base + 0x30)
  43 #define MXC_CCM_CHSCDR          (ccm_base + 0x34)
  44 #define MXC_CCM_CSCDR2          (ccm_base + 0x38)
  45 #define MXC_CCM_CSCDR3          (ccm_base + 0x3c)
  46 #define MXC_CCM_CSCDR4          (ccm_base + 0x40)
  47 #define MXC_CCM_CWDR            (ccm_base + 0x44)
  48 #define MXC_CCM_CDHIPR          (ccm_base + 0x48)
  49 #define MXC_CCM_CDCR            (ccm_base + 0x4c)
  50 #define MXC_CCM_CTOR            (ccm_base + 0x50)
  51 #define MXC_CCM_CLPCR           (ccm_base + 0x54)
  52 #define MXC_CCM_CISR            (ccm_base + 0x58)
  53 #define MXC_CCM_CIMR            (ccm_base + 0x5c)
  54 #define MXC_CCM_CCOSR           (ccm_base + 0x60)
  55 #define MXC_CCM_CGPR            (ccm_base + 0x64)
  56 #define MXC_CCM_CCGR0           (ccm_base + 0x68)
  57 #define MXC_CCM_CCGR1           (ccm_base + 0x6c)
  58 #define MXC_CCM_CCGR2           (ccm_base + 0x70)
  59 #define MXC_CCM_CCGR3           (ccm_base + 0x74)
  60 #define MXC_CCM_CCGR4           (ccm_base + 0x78)
  61 #define MXC_CCM_CCGR5           (ccm_base + 0x7c)
  62 #define MXC_CCM_CCGR6           (ccm_base + 0x80)
  63 #define MXC_CCM_CCGR7           (ccm_base + 0x84)
  64
  65 /* Low-power Audio Playback Mode clock */
  66 static const char *lp_apm_sel[] = { "osc", };
  67
  68 /* This is used multiple times */
  69 static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
  70 static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
  71 static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
  72 static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
  73 static const char *per_root_sel[] = { "per_podf", "ipg", };
  74 static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
  75 static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
  76 static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
  77 static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
  78 static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
  79 static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
  80 static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
  81 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
  82 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
  83 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
  84 static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
  85 static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
  86 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
  87 static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
  88 static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
  89 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
  90 static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
  91 static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
  92 static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
  93 static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
  94 static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
  95 static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
  96 static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
  97 static const char *mx53_cko1_sel[] = {
  98         "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
  99         "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
 100         "di_pred", "dummy", "dummy", "ahb",
 101         "ipg", "per_root", "ckil", "dummy",};
 102 static const char *mx53_cko2_sel[] = {
 103         "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
 104         "dummy", "esdhc_a_podf",
 105         "usboh3_podf", "dummy"/* wrck_clk_root */,
 106         "ecspi_podf", "dummy"/* pll1_ref_clk */,
 107         "esdhc_b_podf", "dummy"/* ddr_clk_root */,
 108         "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
 109         "vpu_sel", "ipu_sel",
 110         "osc", "ckih1",
 111         "dummy", "esdhc_c_sel",
 112         "ssi1_root_podf", "ssi2_root_podf",
 113         "dummy", "dummy",
 114         "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
 115         "dummy"/* tve_out */, "usb_phy_sel",
 116         "tve_sel", "lp_apm",
 117         "uart_root", "dummy"/* spdif0_clk_root */,
 118         "dummy", "dummy", };
 119 static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
 120 static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
 121 static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
 122 static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
 123 static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
 124 static const char *step_sels[] = { "lp_apm", };
 125 static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
 126 static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_clk */, "dummy" /* fec_phy_clk */ };
 127
 128 static struct clk *clk[IMX5_CLK_END];
 129 static struct clk_onecell_data clk_data;
 130
 131 static struct clk ** const uart_clks_mx51[] __initconst = {
 132         &clk[IMX5_CLK_UART1_IPG_GATE],
 133         &clk[IMX5_CLK_UART1_PER_GATE],
 134         &clk[IMX5_CLK_UART2_IPG_GATE],
 135         &clk[IMX5_CLK_UART2_PER_GATE],
 136         &clk[IMX5_CLK_UART3_IPG_GATE],
 137         &clk[IMX5_CLK_UART3_PER_GATE],
 138         NULL
 139 };
 140
 141 static struct clk ** const uart_clks_mx50_mx53[] __initconst = {
 142         &clk[IMX5_CLK_UART1_IPG_GATE],
 143         &clk[IMX5_CLK_UART1_PER_GATE],
 144         &clk[IMX5_CLK_UART2_IPG_GATE],
 145         &clk[IMX5_CLK_UART2_PER_GATE],
 146         &clk[IMX5_CLK_UART3_IPG_GATE],
 147         &clk[IMX5_CLK_UART3_PER_GATE],
 148         &clk[IMX5_CLK_UART4_IPG_GATE],
 149         &clk[IMX5_CLK_UART4_PER_GATE],
 150         &clk[IMX5_CLK_UART5_IPG_GATE],
 151         &clk[IMX5_CLK_UART5_PER_GATE],
 152         NULL
 153 };
 154
 155 static void __init mx5_clocks_common_init(void __iomem *ccm_base)
 156 {
 157         clk[IMX5_CLK_DUMMY]             = imx_clk_fixed("dummy", 0);
 158         clk[IMX5_CLK_CKIL]              = imx_obtain_fixed_clock("ckil", 0);
 159         clk[IMX5_CLK_OSC]               = imx_obtain_fixed_clock("osc", 0);
 160         clk[IMX5_CLK_CKIH1]             = imx_obtain_fixed_clock("ckih1", 0);
 161         clk[IMX5_CLK_CKIH2]             = imx_obtain_fixed_clock("ckih2", 0);
 162
 163         clk[IMX5_CLK_PER_LP_APM]        = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
 164                                                 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
 165         clk[IMX5_CLK_PER_PRED1]         = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
 166         clk[IMX5_CLK_PER_PRED2]         = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
 167         clk[IMX5_CLK_PER_PODF]          = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
 168         clk[IMX5_CLK_PER_ROOT]          = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
 169                                                 per_root_sel, ARRAY_SIZE(per_root_sel));
 170         clk[IMX5_CLK_AHB]               = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
 171         clk[IMX5_CLK_AHB_MAX]           = imx_clk_gate2_flags("ahb_max", "ahb", MXC_CCM_CCGR0, 28, CLK_IS_CRITICAL);
 172         clk[IMX5_CLK_AIPS_TZ1]          = imx_clk_gate2_flags("aips_tz1", "ahb", MXC_CCM_CCGR0, 24, CLK_IS_CRITICAL);
 173         clk[IMX5_CLK_AIPS_TZ2]          = imx_clk_gate2_flags("aips_tz2", "ahb", MXC_CCM_CCGR0, 26, CLK_IS_CRITICAL);
 174         clk[IMX5_CLK_TMAX1]             = imx_clk_gate2_flags("tmax1", "ahb", MXC_CCM_CCGR1, 0, CLK_IS_CRITICAL);
 175         clk[IMX5_CLK_TMAX2]             = imx_clk_gate2_flags("tmax2", "ahb", MXC_CCM_CCGR1, 2, CLK_IS_CRITICAL);
 176         clk[IMX5_CLK_TMAX3]             = imx_clk_gate2_flags("tmax3", "ahb", MXC_CCM_CCGR1, 4, CLK_IS_CRITICAL);
 177         clk[IMX5_CLK_SPBA]              = imx_clk_gate2_flags("spba", "ipg", MXC_CCM_CCGR5, 0, CLK_IS_CRITICAL);
 178         clk[IMX5_CLK_IPG]               = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
 179         clk[IMX5_CLK_AXI_A]             = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
 180         clk[IMX5_CLK_AXI_B]             = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
 181         clk[IMX5_CLK_UART_SEL]          = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
 182                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 183         clk[IMX5_CLK_UART_PRED]         = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
 184         clk[IMX5_CLK_UART_ROOT]         = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
 185
 186         clk[IMX5_CLK_ESDHC_A_PRED]      = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
 187         clk[IMX5_CLK_ESDHC_A_PODF]      = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
 188         clk[IMX5_CLK_ESDHC_B_PRED]      = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
 189         clk[IMX5_CLK_ESDHC_B_PODF]      = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
 190
 191         clk[IMX5_CLK_EMI_SEL]           = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
 192                                                 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
 193         clk[IMX5_CLK_EMI_SLOW_PODF]     = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
 194         clk[IMX5_CLK_NFC_PODF]          = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
 195         clk[IMX5_CLK_ECSPI_SEL]         = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
 196                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 197         clk[IMX5_CLK_ECSPI_PRED]        = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
 198         clk[IMX5_CLK_ECSPI_PODF]        = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
 199         clk[IMX5_CLK_USBOH3_SEL]        = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
 200                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 201         clk[IMX5_CLK_USBOH3_PRED]       = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
 202         clk[IMX5_CLK_USBOH3_PODF]       = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
 203         clk[IMX5_CLK_USB_PHY_PRED]      = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
 204         clk[IMX5_CLK_USB_PHY_PODF]      = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
 205         clk[IMX5_CLK_USB_PHY_SEL]       = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
 206                                                 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
 207         clk[IMX5_CLK_STEP_SEL]          = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
 208         clk[IMX5_CLK_CPU_PODF_SEL]      = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
 209         clk[IMX5_CLK_CPU_PODF]          = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
 210         clk[IMX5_CLK_DI_PRED]           = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
 211         clk[IMX5_CLK_IIM_GATE]          = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
 212         clk[IMX5_CLK_UART1_IPG_GATE]    = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
 213         clk[IMX5_CLK_UART1_PER_GATE]    = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
 214         clk[IMX5_CLK_UART2_IPG_GATE]    = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
 215         clk[IMX5_CLK_UART2_PER_GATE]    = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
 216         clk[IMX5_CLK_UART3_IPG_GATE]    = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
 217         clk[IMX5_CLK_UART3_PER_GATE]    = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
 218         clk[IMX5_CLK_I2C1_GATE]         = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
 219         clk[IMX5_CLK_I2C2_GATE]         = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
 220         clk[IMX5_CLK_PWM1_IPG_GATE]     = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
 221         clk[IMX5_CLK_PWM1_HF_GATE]      = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
 222         clk[IMX5_CLK_PWM2_IPG_GATE]     = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
 223         clk[IMX5_CLK_PWM2_HF_GATE]      = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
 224         clk[IMX5_CLK_GPT_IPG_GATE]      = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
 225         clk[IMX5_CLK_GPT_HF_GATE]       = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
 226         clk[IMX5_CLK_FEC_GATE]          = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
 227         clk[IMX5_CLK_USBOH3_GATE]       = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
 228         clk[IMX5_CLK_USBOH3_PER_GATE]   = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
 229         clk[IMX5_CLK_ESDHC1_IPG_GATE]   = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
 230         clk[IMX5_CLK_ESDHC2_IPG_GATE]   = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
 231         clk[IMX5_CLK_ESDHC3_IPG_GATE]   = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
 232         clk[IMX5_CLK_ESDHC4_IPG_GATE]   = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
 233         clk[IMX5_CLK_SSI1_IPG_GATE]     = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
 234         clk[IMX5_CLK_SSI2_IPG_GATE]     = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
 235         clk[IMX5_CLK_SSI3_IPG_GATE]     = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
 236         clk[IMX5_CLK_ECSPI1_IPG_GATE]   = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
 237         clk[IMX5_CLK_ECSPI1_PER_GATE]   = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
 238         clk[IMX5_CLK_ECSPI2_IPG_GATE]   = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
 239         clk[IMX5_CLK_ECSPI2_PER_GATE]   = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
 240         clk[IMX5_CLK_CSPI_IPG_GATE]     = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
 241         clk[IMX5_CLK_SDMA_GATE]         = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
 242         clk[IMX5_CLK_EMI_FAST_GATE]     = imx_clk_gate2_flags("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14, CLK_IS_CRITICAL);
 243         clk[IMX5_CLK_EMI_SLOW_GATE]     = imx_clk_gate2_flags("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16, CLK_IS_CRITICAL);
 244         clk[IMX5_CLK_IPU_SEL]           = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
 245         clk[IMX5_CLK_IPU_GATE]          = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
 246         clk[IMX5_CLK_NFC_GATE]          = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
 247         clk[IMX5_CLK_IPU_DI0_GATE]      = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
 248         clk[IMX5_CLK_IPU_DI1_GATE]      = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
 249         clk[IMX5_CLK_GPU3D_SEL]         = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
 250         clk[IMX5_CLK_GPU2D_SEL]         = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
 251         clk[IMX5_CLK_GPU3D_GATE]        = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
 252         clk[IMX5_CLK_GARB_GATE]         = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
 253         clk[IMX5_CLK_GPU2D_GATE]        = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
 254         clk[IMX5_CLK_VPU_SEL]           = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
 255         clk[IMX5_CLK_VPU_GATE]          = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
 256         clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
 257         clk[IMX5_CLK_GPC_DVFS]          = imx_clk_gate2_flags("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24, CLK_IS_CRITICAL);
 258
 259         clk[IMX5_CLK_SSI_APM]           = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
 260         clk[IMX5_CLK_SSI1_ROOT_SEL]     = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 261         clk[IMX5_CLK_SSI2_ROOT_SEL]     = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 262         clk[IMX5_CLK_SSI3_ROOT_SEL]     = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
 263         clk[IMX5_CLK_SSI_EXT1_SEL]      = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 264         clk[IMX5_CLK_SSI_EXT2_SEL]      = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
 265         clk[IMX5_CLK_SSI_EXT1_COM_SEL]  = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
 266         clk[IMX5_CLK_SSI_EXT2_COM_SEL]  = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
 267         clk[IMX5_CLK_SSI1_ROOT_PRED]    = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
 268         clk[IMX5_CLK_SSI1_ROOT_PODF]    = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
 269         clk[IMX5_CLK_SSI2_ROOT_PRED]    = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
 270         clk[IMX5_CLK_SSI2_ROOT_PODF]    = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
 271         clk[IMX5_CLK_SSI_EXT1_PRED]     = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
 272         clk[IMX5_CLK_SSI_EXT1_PODF]     = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
 273         clk[IMX5_CLK_SSI_EXT2_PRED]     = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
 274         clk[IMX5_CLK_SSI_EXT2_PODF]     = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
 275         clk[IMX5_CLK_SSI1_ROOT_GATE]    = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
 276         clk[IMX5_CLK_SSI2_ROOT_GATE]    = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
 277         clk[IMX5_CLK_SSI3_ROOT_GATE]    = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
 278         clk[IMX5_CLK_SSI_EXT1_GATE]     = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
 279         clk[IMX5_CLK_SSI_EXT2_GATE]     = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
 280         clk[IMX5_CLK_EPIT1_IPG_GATE]    = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
 281         clk[IMX5_CLK_EPIT1_HF_GATE]     = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
 282         clk[IMX5_CLK_EPIT2_IPG_GATE]    = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
 283         clk[IMX5_CLK_EPIT2_HF_GATE]     = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
 284         clk[IMX5_CLK_OWIRE_GATE]        = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
 285         clk[IMX5_CLK_SRTC_GATE]         = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
 286         clk[IMX5_CLK_PATA_GATE]         = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
 287         clk[IMX5_CLK_SPDIF0_SEL]        = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
 288         clk[IMX5_CLK_SPDIF0_PRED]       = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
 289         clk[IMX5_CLK_SPDIF0_PODF]       = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
 290         clk[IMX5_CLK_SPDIF0_COM_SEL]    = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
 291                                                 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
 292         clk[IMX5_CLK_SPDIF0_GATE]       = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
 293         clk[IMX5_CLK_SPDIF_IPG_GATE]    = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
 294         clk[IMX5_CLK_SAHARA_IPG_GATE]   = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
 295         clk[IMX5_CLK_SATA_REF]          = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
 296
 297         clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
 298         clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
 299
 300         /* move usb phy clk to 24MHz */
 301         clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
 302 }
 303
 304 static void __init mx50_clocks_init(struct device_node *np)
 305 {
 306         void __iomem *ccm_base;
 307         void __iomem *pll_base;
 308         unsigned long r;
 309
 310         pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
 311         WARN_ON(!pll_base);
 312         clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", pll_base);
 313
 314         pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
 315         WARN_ON(!pll_base);
 316         clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", pll_base);
 317
 318         pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
 319         WARN_ON(!pll_base);
 320         clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", pll_base);
 321
 322         ccm_base = of_iomap(np, 0);
 323         WARN_ON(!ccm_base);
 324
 325         mx5_clocks_common_init(ccm_base);
 326
 327         /*
 328          * This clock is called periph_clk in the i.MX50 Reference Manual, but
 329          * it comes closest in scope to the main_bus_clk of i.MX51 and i.MX53
 330          */
 331         clk[IMX5_CLK_MAIN_BUS]          = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 2,
 332                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 333
 334         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
 335                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
 336         clk[IMX5_CLK_ESDHC_A_SEL]       = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 21, 2,
 337                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 338         clk[IMX5_CLK_ESDHC_B_SEL]       = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
 339                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 340         clk[IMX5_CLK_ESDHC_C_SEL]       = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 20, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
 341         clk[IMX5_CLK_ESDHC_D_SEL]       = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
 342         clk[IMX5_CLK_ESDHC1_PER_GATE]   = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
 343         clk[IMX5_CLK_ESDHC2_PER_GATE]   = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
 344         clk[IMX5_CLK_ESDHC3_PER_GATE]   = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
 345         clk[IMX5_CLK_ESDHC4_PER_GATE]   = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
 346         clk[IMX5_CLK_USB_PHY1_GATE]     = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
 347         clk[IMX5_CLK_USB_PHY2_GATE]     = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
 348         clk[IMX5_CLK_I2C3_GATE]         = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
 349         clk[IMX5_CLK_UART4_IPG_GATE]    = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
 350         clk[IMX5_CLK_UART4_PER_GATE]    = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
 351         clk[IMX5_CLK_UART5_IPG_GATE]    = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
 352         clk[IMX5_CLK_UART5_PER_GATE]    = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
 353
 354         clk[IMX5_CLK_CKO1_SEL]          = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
 355                                                 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
 356         clk[IMX5_CLK_CKO1_PODF]         = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
 357         clk[IMX5_CLK_CKO1]              = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
 358
 359         clk[IMX5_CLK_CKO2_SEL]          = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
 360                                                 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
 361         clk[IMX5_CLK_CKO2_PODF]         = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
 362         clk[IMX5_CLK_CKO2]              = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
 363
 364         imx_check_clocks(clk, ARRAY_SIZE(clk));
 365
 366         clk_data.clks = clk;
 367         clk_data.clk_num = ARRAY_SIZE(clk);
 368         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 369
 370         /* Set SDHC parents to be PLL2 */
 371         clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
 372         clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
 373
 374         /* set SDHC root clock to 200MHZ*/
 375         clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
 376         clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
 377
 378         clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
 379         imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
 380         clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
 381
 382         r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
 383         clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
 384
 385         imx_register_uart_clocks(uart_clks_mx50_mx53);
 386 }
 387 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
 388
 389 static void __init mx51_clocks_init(struct device_node *np)
 390 {
 391         void __iomem *ccm_base;
 392         void __iomem *pll_base;
 393         u32 val;
 394
 395         pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
 396         WARN_ON(!pll_base);
 397         clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", pll_base);
 398
 399         pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
 400         WARN_ON(!pll_base);
 401         clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", pll_base);
 402
 403         pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
 404         WARN_ON(!pll_base);
 405         clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", pll_base);
 406
 407         ccm_base = of_iomap(np, 0);
 408         WARN_ON(!ccm_base);
 409
 410         mx5_clocks_common_init(ccm_base);
 411
 412         clk[IMX5_CLK_PERIPH_APM]        = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
 413                                                 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
 414         clk[IMX5_CLK_MAIN_BUS]          = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
 415                                                 main_bus_sel, ARRAY_SIZE(main_bus_sel));
 416         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
 417                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
 418         clk[IMX5_CLK_IPU_DI0_SEL]       = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
 419                                                 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel), CLK_SET_RATE_PARENT);
 420         clk[IMX5_CLK_IPU_DI1_SEL]       = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
 421                                                 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel), CLK_SET_RATE_PARENT);
 422         clk[IMX5_CLK_TVE_EXT_SEL]       = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
 423                                                 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
 424         clk[IMX5_CLK_TVE_SEL]           = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
 425                                                 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
 426         clk[IMX5_CLK_TVE_GATE]          = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
 427         clk[IMX5_CLK_TVE_PRED]          = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
 428         clk[IMX5_CLK_ESDHC_A_SEL]       = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
 429                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 430         clk[IMX5_CLK_ESDHC_B_SEL]       = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
 431                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 432         clk[IMX5_CLK_ESDHC_C_SEL]       = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
 433         clk[IMX5_CLK_ESDHC_D_SEL]       = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
 434         clk[IMX5_CLK_ESDHC1_PER_GATE]   = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
 435         clk[IMX5_CLK_ESDHC2_PER_GATE]   = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
 436         clk[IMX5_CLK_ESDHC3_PER_GATE]   = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
 437         clk[IMX5_CLK_ESDHC4_PER_GATE]   = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
 438         clk[IMX5_CLK_USB_PHY_GATE]      = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
 439         clk[IMX5_CLK_HSI2C_GATE]        = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
 440         clk[IMX5_CLK_SCC2_IPG_GATE]     = imx_clk_gate2("scc2_gate", "ipg", MXC_CCM_CCGR1, 30);
 441         clk[IMX5_CLK_MIPI_HSC1_GATE]    = imx_clk_gate2_flags("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6, CLK_IS_CRITICAL);
 442         clk[IMX5_CLK_MIPI_HSC2_GATE]    = imx_clk_gate2_flags("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8, CLK_IS_CRITICAL);
 443         clk[IMX5_CLK_MIPI_ESC_GATE]     = imx_clk_gate2_flags("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10, CLK_IS_CRITICAL);
 444         clk[IMX5_CLK_MIPI_HSP_GATE]     = imx_clk_gate2_flags("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12, CLK_IS_CRITICAL);
 445         clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
 446                                                 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
 447         clk[IMX5_CLK_SPDIF1_SEL]        = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
 448                                                 spdif_sel, ARRAY_SIZE(spdif_sel));
 449         clk[IMX5_CLK_SPDIF1_PRED]       = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
 450         clk[IMX5_CLK_SPDIF1_PODF]       = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
 451         clk[IMX5_CLK_SPDIF1_COM_SEL]    = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
 452                                                 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
 453         clk[IMX5_CLK_SPDIF1_GATE]       = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
 454
 455         imx_check_clocks(clk, ARRAY_SIZE(clk));
 456
 457         clk_data.clks = clk;
 458         clk_data.clk_num = ARRAY_SIZE(clk);
 459         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 460
 461         /* set the usboh3 parent to pll2_sw */
 462         clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
 463
 464         /* Set SDHC parents to be PLL2 */
 465         clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
 466         clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
 467
 468         /* set SDHC root clock to 166.25MHZ*/
 469         clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
 470         clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
 471
 472         clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
 473         imx_print_silicon_rev("i.MX51", mx51_revision());
 474         clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
 475
 476         /*
 477          * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
 478          * longer supported. Set to one for better power saving.
 479          *
 480          * The effect of not setting these bits is that MIPI clocks can't be
 481          * enabled without the IPU clock being enabled aswell.
 482          */
 483         val = readl(MXC_CCM_CCDR);
 484         val |= 1 << 18;
 485         writel(val, MXC_CCM_CCDR);
 486
 487         val = readl(MXC_CCM_CLPCR);
 488         val |= 1 << 23;
 489         writel(val, MXC_CCM_CLPCR);
 490
 491         imx_register_uart_clocks(uart_clks_mx51);
 492 }
 493 CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
 494
 495 static void __init mx53_clocks_init(struct device_node *np)
 496 {
 497         void __iomem *ccm_base;
 498         void __iomem *pll_base;
 499         unsigned long r;
 500
 501         pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
 502         WARN_ON(!pll_base);
 503         clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", pll_base);
 504
 505         pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
 506         WARN_ON(!pll_base);
 507         clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", pll_base);
 508
 509         pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
 510         WARN_ON(!pll_base);
 511         clk[IMX5_CLK_PLL3_SW]           = imx_clk_pllv2("pll3_sw", "osc", pll_base);
 512
 513         pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
 514         WARN_ON(!pll_base);
 515         clk[IMX5_CLK_PLL4_SW]           = imx_clk_pllv2("pll4_sw", "osc", pll_base);
 516
 517         ccm_base = of_iomap(np, 0);
 518         WARN_ON(!ccm_base);
 519
 520         mx5_clocks_common_init(ccm_base);
 521
 522         clk[IMX5_CLK_PERIPH_APM]        = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
 523                                                 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
 524         clk[IMX5_CLK_MAIN_BUS]          = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
 525                                                 main_bus_sel, ARRAY_SIZE(main_bus_sel));
 526         clk[IMX5_CLK_LP_APM]            = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
 527                                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
 528         clk[IMX5_CLK_LDB_DI1_DIV_3_5]   = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
 529         clk[IMX5_CLK_LDB_DI1_DIV]       = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
 530         clk[IMX5_CLK_LDB_DI1_SEL]       = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
 531                                                 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
 532         clk[IMX5_CLK_DI_PLL4_PODF]      = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
 533         clk[IMX5_CLK_LDB_DI0_DIV_3_5]   = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
 534         clk[IMX5_CLK_LDB_DI0_DIV]       = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
 535         clk[IMX5_CLK_LDB_DI0_SEL]       = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
 536                                                 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
 537         clk[IMX5_CLK_LDB_DI0_GATE]      = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
 538         clk[IMX5_CLK_LDB_DI1_GATE]      = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
 539         clk[IMX5_CLK_IPU_DI0_SEL]       = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
 540                                                 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);
 541         clk[IMX5_CLK_IPU_DI1_SEL]       = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
 542                                                 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);
 543         clk[IMX5_CLK_TVE_EXT_SEL]       = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
 544                                                 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
 545         clk[IMX5_CLK_TVE_GATE]          = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
 546         clk[IMX5_CLK_TVE_PRED]          = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
 547         clk[IMX5_CLK_ESDHC_A_SEL]       = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
 548                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 549         clk[IMX5_CLK_ESDHC_B_SEL]       = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
 550                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 551         clk[IMX5_CLK_ESDHC_C_SEL]       = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
 552         clk[IMX5_CLK_ESDHC_D_SEL]       = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
 553         clk[IMX5_CLK_ESDHC1_PER_GATE]   = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
 554         clk[IMX5_CLK_ESDHC2_PER_GATE]   = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
 555         clk[IMX5_CLK_ESDHC3_PER_GATE]   = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
 556         clk[IMX5_CLK_ESDHC4_PER_GATE]   = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
 557         clk[IMX5_CLK_USB_PHY1_GATE]     = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
 558         clk[IMX5_CLK_USB_PHY2_GATE]     = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
 559         clk[IMX5_CLK_CAN_SEL]           = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
 560                                                 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
 561         clk[IMX5_CLK_CAN1_SERIAL_GATE]  = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
 562         clk[IMX5_CLK_CAN1_IPG_GATE]     = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
 563         clk[IMX5_CLK_OCRAM]             = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
 564         clk[IMX5_CLK_CAN2_SERIAL_GATE]  = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
 565         clk[IMX5_CLK_CAN2_IPG_GATE]     = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
 566         clk[IMX5_CLK_I2C3_GATE]         = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
 567         clk[IMX5_CLK_SATA_GATE]         = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
 568
 569         clk[IMX5_CLK_FIRI_SEL]          = imx_clk_mux("firi_sel", MXC_CCM_CSCMR2, 12, 2,
 570                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 571         clk[IMX5_CLK_FIRI_PRED]         = imx_clk_divider("firi_pred", "firi_sel", MXC_CCM_CSCDR3, 6, 3);
 572         clk[IMX5_CLK_FIRI_PODF]         = imx_clk_divider("firi_podf", "firi_pred", MXC_CCM_CSCDR3, 0, 6);
 573         clk[IMX5_CLK_FIRI_SERIAL_GATE]  = imx_clk_gate2("firi_serial_gate", "firi_podf", MXC_CCM_CCGR1, 28);
 574         clk[IMX5_CLK_FIRI_IPG_GATE]     = imx_clk_gate2("firi_ipg_gate", "ipg", MXC_CCM_CCGR1, 26);
 575
 576         clk[IMX5_CLK_CSI0_MCLK1_SEL]    = imx_clk_mux("csi0_mclk1_sel", MXC_CCM_CSCMR2, 22, 2,
 577                                                 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
 578         clk[IMX5_CLK_CSI0_MCLK1_PRED]   = imx_clk_divider("csi0_mclk1_pred", "csi0_mclk1_sel", MXC_CCM_CSCDR4, 6, 3);
 579         clk[IMX5_CLK_CSI0_MCLK1_PODF]   = imx_clk_divider("csi0_mclk1_podf", "csi0_mclk1_pred", MXC_CCM_CSCDR4, 0, 6);
 580         clk[IMX5_CLK_CSI0_MCLK1_GATE]   = imx_clk_gate2("csi0_mclk1_serial_gate", "csi0_mclk1_podf", MXC_CCM_CCGR6, 4);
 581
 582         clk[IMX5_CLK_IEEE1588_SEL]      = imx_clk_mux("ieee1588_sel", MXC_CCM_CSCMR2, 14, 2,
 583                                                 ieee1588_sels, ARRAY_SIZE(ieee1588_sels));
 584         clk[IMX5_CLK_IEEE1588_PRED]     = imx_clk_divider("ieee1588_pred", "ieee1588_sel", MXC_CCM_CSCDR2, 6, 3);
 585         clk[IMX5_CLK_IEEE1588_PODF]     = imx_clk_divider("ieee1588_podf", "ieee1588_pred", MXC_CCM_CSCDR2, 0, 6);
 586         clk[IMX5_CLK_IEEE1588_GATE]     = imx_clk_gate2("ieee1588_serial_gate", "ieee1588_podf", MXC_CCM_CCGR7, 6);
 587         clk[IMX5_CLK_UART4_IPG_GATE]    = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
 588         clk[IMX5_CLK_UART4_PER_GATE]    = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
 589         clk[IMX5_CLK_UART5_IPG_GATE]    = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
 590         clk[IMX5_CLK_UART5_PER_GATE]    = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
 591
 592         clk[IMX5_CLK_CKO1_SEL]          = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
 593                                                 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
 594         clk[IMX5_CLK_CKO1_PODF]         = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
 595         clk[IMX5_CLK_CKO1]              = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
 596
 597         clk[IMX5_CLK_CKO2_SEL]          = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
 598                                                 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
 599         clk[IMX5_CLK_CKO2_PODF]         = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
 600         clk[IMX5_CLK_CKO2]              = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
 601         clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
 602                                                 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
 603         clk[IMX5_CLK_ARM]               = imx_clk_cpu("arm", "cpu_podf",
 604                                                 clk[IMX5_CLK_CPU_PODF],
 605                                                 clk[IMX5_CLK_CPU_PODF_SEL],
 606                                                 clk[IMX5_CLK_PLL1_SW],
 607                                                 clk[IMX5_CLK_STEP_SEL]);
 608
 609         imx_check_clocks(clk, ARRAY_SIZE(clk));
 610
 611         clk_data.clks = clk;
 612         clk_data.clk_num = ARRAY_SIZE(clk);
 613         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 614
 615         /* Set SDHC parents to be PLL2 */
 616         clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
 617         clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
 618
 619         /* set SDHC root clock to 200MHZ*/
 620         clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
 621         clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
 622
 623         /* move can bus clk to 24MHz */
 624         clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
 625
 626         /* make sure step clock is running from 24MHz */
 627         clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
 628
 629         clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
 630         imx_print_silicon_rev("i.MX53", mx53_revision());
 631         clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
 632
 633         r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
 634         clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
 635
 636         imx_register_uart_clocks(uart_clks_mx50_mx53);
 637 }
 638 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);