arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 #ifdef MODULE
  51 static const struct x86_cpu_id svm_cpu_id[] = {
  52         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  53         {}
  54 };
  55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  56 #endif
  57
  58 #define IOPM_ALLOC_ORDER 2
  59 #define MSRPM_ALLOC_ORDER 1
  60
  61 #define SEG_TYPE_LDT 2
  62 #define SEG_TYPE_BUSY_TSS16 3
  63
  64 #define SVM_FEATURE_LBRV           (1 <<  1)
  65 #define SVM_FEATURE_SVML           (1 <<  2)
  66 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  67 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  68 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  69 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  70 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  71
  72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  73
  74 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  75 #define TSC_RATIO_MIN           0x0000000000000001ULL
  76 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  77
  78 static bool erratum_383_found __read_mostly;
  79
  80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  81
  82 /*
  83  * Set osvw_len to higher value when updated Revision Guides
  84  * are published and we know what the new status bits are
  85  */
  86 static uint64_t osvw_len = 4, osvw_status;
  87
  88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  89 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  90
  91 static const struct svm_direct_access_msrs {
  92         u32 index;   /* Index of the MSR */
  93         bool always; /* True if intercept is initially cleared */
  94 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  95         { .index = MSR_STAR,                            .always = true  },
  96         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_EFER,                            .always = false },
 112         { .index = MSR_IA32_CR_PAT,                     .always = false },
 113         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
 114         { .index = MSR_INVALID,                         .always = false },
 115 };
 116
 117 /* enable NPT for AMD64 and X86 with PAE */
 118 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 119 bool npt_enabled = true;
 120 #else
 121 bool npt_enabled;
 122 #endif
 123
 124 /*
 125  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 126  * pause_filter_count: On processors that support Pause filtering(indicated
 127  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 128  *      count value. On VMRUN this value is loaded into an internal counter.
 129  *      Each time a pause instruction is executed, this counter is decremented
 130  *      until it reaches zero at which time a #VMEXIT is generated if pause
 131  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 132  *      Intercept Filtering for more details.
 133  *      This also indicate if ple logic enabled.
 134  *
 135  * pause_filter_thresh: In addition, some processor families support advanced
 136  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 137  *      the amount of time a guest is allowed to execute in a pause loop.
 138  *      In this mode, a 16-bit pause filter threshold field is added in the
 139  *      VMCB. The threshold value is a cycle count that is used to reset the
 140  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 141  *      count value from VMCB into an internal counter. Then, on each pause
 142  *      instruction the hardware checks the elapsed number of cycles since
 143  *      the most recent pause instruction against the pause filter threshold.
 144  *      If the elapsed cycle count is greater than the pause filter threshold,
 145  *      then the internal pause count is reloaded from the VMCB and execution
 146  *      continues. If the elapsed cycle count is less than the pause filter
 147  *      threshold, then the internal pause count is decremented. If the count
 148  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 149  *      triggered. If advanced pause filtering is supported and pause filter
 150  *      threshold field is set to zero, the filter will operate in the simpler,
 151  *      count only mode.
 152  */
 153
 154 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 155 module_param(pause_filter_thresh, ushort, 0444);
 156
 157 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 158 module_param(pause_filter_count, ushort, 0444);
 159
 160 /* Default doubles per-vcpu window every exit. */
 161 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 162 module_param(pause_filter_count_grow, ushort, 0444);
 163
 164 /* Default resets per-vcpu window every exit to pause_filter_count. */
 165 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 166 module_param(pause_filter_count_shrink, ushort, 0444);
 167
 168 /* Default is to compute the maximum so we can never overflow. */
 169 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 170 module_param(pause_filter_count_max, ushort, 0444);
 171
 172 /* allow nested paging (virtualized MMU) for all guests */
 173 static int npt = true;
 174 module_param(npt, int, S_IRUGO);
 175
 176 /* allow nested virtualization in KVM/SVM */
 177 static int nested = true;
 178 module_param(nested, int, S_IRUGO);
 179
 180 /* enable/disable Next RIP Save */
 181 static int nrips = true;
 182 module_param(nrips, int, 0444);
 183
 184 /* enable/disable Virtual VMLOAD VMSAVE */
 185 static int vls = true;
 186 module_param(vls, int, 0444);
 187
 188 /* enable/disable Virtual GIF */
 189 static int vgif = true;
 190 module_param(vgif, int, 0444);
 191
 192 /* enable/disable SEV support */
 193 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 194 module_param(sev, int, 0444);
 195
 196 /* enable/disable SEV-ES support */
 197 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 198 module_param(sev_es, int, 0444);
 199
 200 bool __read_mostly dump_invalid_vmcb;
 201 module_param(dump_invalid_vmcb, bool, 0644);
 202
 203 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 204
 205 static void svm_complete_interrupts(struct vcpu_svm *svm);
 206
 207 static unsigned long iopm_base;
 208
 209 struct kvm_ldttss_desc {
 210         u16 limit0;
 211         u16 base0;
 212         unsigned base1:8, type:5, dpl:2, p:1;
 213         unsigned limit1:4, zero0:3, g:1, base2:8;
 214         u32 base3;
 215         u32 zero1;
 216 } __attribute__((packed));
 217
 218 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 219
 220 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 221
 222 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 223 #define MSRS_RANGE_SIZE 2048
 224 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 225
 226 u32 svm_msrpm_offset(u32 msr)
 227 {
 228         u32 offset;
 229         int i;
 230
 231         for (i = 0; i < NUM_MSR_MAPS; i++) {
 232                 if (msr < msrpm_ranges[i] ||
 233                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 234                         continue;
 235
 236                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 237                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 238
 239                 /* Now we have the u8 offset - but need the u32 offset */
 240                 return offset / 4;
 241         }
 242
 243         /* MSR not in any range */
 244         return MSR_INVALID;
 245 }
 246
 247 #define MAX_INST_SIZE 15
 248
 249 static inline void clgi(void)
 250 {
 251         asm volatile (__ex("clgi"));
 252 }
 253
 254 static inline void stgi(void)
 255 {
 256         asm volatile (__ex("stgi"));
 257 }
 258
 259 static inline void invlpga(unsigned long addr, u32 asid)
 260 {
 261         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 262 }
 263
 264 static int get_max_npt_level(void)
 265 {
 266 #ifdef CONFIG_X86_64
 267         return PT64_ROOT_4LEVEL;
 268 #else
 269         return PT32E_ROOT_LEVEL;
 270 #endif
 271 }
 272
 273 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 274 {
 275         struct vcpu_svm *svm = to_svm(vcpu);
 276         u64 old_efer = vcpu->arch.efer;
 277         vcpu->arch.efer = efer;
 278
 279         if (!npt_enabled) {
 280                 /* Shadow paging assumes NX to be available.  */
 281                 efer |= EFER_NX;
 282
 283                 if (!(efer & EFER_LMA))
 284                         efer &= ~EFER_LME;
 285         }
 286
 287         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 288                 if (!(efer & EFER_SVME)) {
 289                         svm_leave_nested(svm);
 290                         svm_set_gif(svm, true);
 291
 292                         /*
 293                          * Free the nested guest state, unless we are in SMM.
 294                          * In this case we will return to the nested guest
 295                          * as soon as we leave SMM.
 296                          */
 297                         if (!is_smm(&svm->vcpu))
 298                                 svm_free_nested(svm);
 299
 300                 } else {
 301                         int ret = svm_allocate_nested(svm);
 302
 303                         if (ret) {
 304                                 vcpu->arch.efer = old_efer;
 305                                 return ret;
 306                         }
 307                 }
 308         }
 309
 310         svm->vmcb->save.efer = efer | EFER_SVME;
 311         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 312         return 0;
 313 }
 314
 315 static int is_external_interrupt(u32 info)
 316 {
 317         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 318         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 319 }
 320
 321 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 322 {
 323         struct vcpu_svm *svm = to_svm(vcpu);
 324         u32 ret = 0;
 325
 326         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 327                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 328         return ret;
 329 }
 330
 331 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 332 {
 333         struct vcpu_svm *svm = to_svm(vcpu);
 334
 335         if (mask == 0)
 336                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 337         else
 338                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 339
 340 }
 341
 342 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 343 {
 344         struct vcpu_svm *svm = to_svm(vcpu);
 345
 346         /*
 347          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 348          * the type of exit and the #VC handler in the guest.
 349          */
 350         if (sev_es_guest(vcpu->kvm))
 351                 goto done;
 352
 353         if (nrips && svm->vmcb->control.next_rip != 0) {
 354                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 355                 svm->next_rip = svm->vmcb->control.next_rip;
 356         }
 357
 358         if (!svm->next_rip) {
 359                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 360                         return 0;
 361         } else {
 362                 kvm_rip_write(vcpu, svm->next_rip);
 363         }
 364
 365 done:
 366         svm_set_interrupt_shadow(vcpu, 0);
 367
 368         return 1;
 369 }
 370
 371 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 372 {
 373         struct vcpu_svm *svm = to_svm(vcpu);
 374         unsigned nr = vcpu->arch.exception.nr;
 375         bool has_error_code = vcpu->arch.exception.has_error_code;
 376         u32 error_code = vcpu->arch.exception.error_code;
 377
 378         kvm_deliver_exception_payload(&svm->vcpu);
 379
 380         if (nr == BP_VECTOR && !nrips) {
 381                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 382
 383                 /*
 384                  * For guest debugging where we have to reinject #BP if some
 385                  * INT3 is guest-owned:
 386                  * Emulate nRIP by moving RIP forward. Will fail if injection
 387                  * raises a fault that is not intercepted. Still better than
 388                  * failing in all cases.
 389                  */
 390                 (void)skip_emulated_instruction(&svm->vcpu);
 391                 rip = kvm_rip_read(&svm->vcpu);
 392                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 393                 svm->int3_injected = rip - old_rip;
 394         }
 395
 396         svm->vmcb->control.event_inj = nr
 397                 | SVM_EVTINJ_VALID
 398                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 399                 | SVM_EVTINJ_TYPE_EXEPT;
 400         svm->vmcb->control.event_inj_err = error_code;
 401 }
 402
 403 static void svm_init_erratum_383(void)
 404 {
 405         u32 low, high;
 406         int err;
 407         u64 val;
 408
 409         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 410                 return;
 411
 412         /* Use _safe variants to not break nested virtualization */
 413         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 414         if (err)
 415                 return;
 416
 417         val |= (1ULL << 47);
 418
 419         low  = lower_32_bits(val);
 420         high = upper_32_bits(val);
 421
 422         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 423
 424         erratum_383_found = true;
 425 }
 426
 427 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 428 {
 429         /*
 430          * Guests should see errata 400 and 415 as fixed (assuming that
 431          * HLT and IO instructions are intercepted).
 432          */
 433         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 434         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 435
 436         /*
 437          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 438          * all osvw.status bits inside that length, including bit 0 (which is
 439          * reserved for erratum 298), are valid. However, if host processor's
 440          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 441          * be conservative here and therefore we tell the guest that erratum 298
 442          * is present (because we really don't know).
 443          */
 444         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 445                 vcpu->arch.osvw.status |= 1;
 446 }
 447
 448 static int has_svm(void)
 449 {
 450         const char *msg;
 451
 452         if (!cpu_has_svm(&msg)) {
 453                 printk(KERN_INFO "has_svm: %s\n", msg);
 454                 return 0;
 455         }
 456
 457         return 1;
 458 }
 459
 460 static void svm_hardware_disable(void)
 461 {
 462         /* Make sure we clean up behind us */
 463         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 464                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 465
 466         cpu_svm_disable();
 467
 468         amd_pmu_disable_virt();
 469 }
 470
 471 static int svm_hardware_enable(void)
 472 {
 473
 474         struct svm_cpu_data *sd;
 475         uint64_t efer;
 476         struct desc_struct *gdt;
 477         int me = raw_smp_processor_id();
 478
 479         rdmsrl(MSR_EFER, efer);
 480         if (efer & EFER_SVME)
 481                 return -EBUSY;
 482
 483         if (!has_svm()) {
 484                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 485                 return -EINVAL;
 486         }
 487         sd = per_cpu(svm_data, me);
 488         if (!sd) {
 489                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 490                 return -EINVAL;
 491         }
 492
 493         sd->asid_generation = 1;
 494         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 495         sd->next_asid = sd->max_asid + 1;
 496         sd->min_asid = max_sev_asid + 1;
 497
 498         gdt = get_current_gdt_rw();
 499         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 500
 501         wrmsrl(MSR_EFER, efer | EFER_SVME);
 502
 503         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 504
 505         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 506                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 507                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 508         }
 509
 510
 511         /*
 512          * Get OSVW bits.
 513          *
 514          * Note that it is possible to have a system with mixed processor
 515          * revisions and therefore different OSVW bits. If bits are not the same
 516          * on different processors then choose the worst case (i.e. if erratum
 517          * is present on one processor and not on another then assume that the
 518          * erratum is present everywhere).
 519          */
 520         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 521                 uint64_t len, status = 0;
 522                 int err;
 523
 524                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 525                 if (!err)
 526                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 527                                                       &err);
 528
 529                 if (err)
 530                         osvw_status = osvw_len = 0;
 531                 else {
 532                         if (len < osvw_len)
 533                                 osvw_len = len;
 534                         osvw_status |= status;
 535                         osvw_status &= (1ULL << osvw_len) - 1;
 536                 }
 537         } else
 538                 osvw_status = osvw_len = 0;
 539
 540         svm_init_erratum_383();
 541
 542         amd_pmu_enable_virt();
 543
 544         return 0;
 545 }
 546
 547 static void svm_cpu_uninit(int cpu)
 548 {
 549         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 550
 551         if (!sd)
 552                 return;
 553
 554         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 555         kfree(sd->sev_vmcbs);
 556         __free_page(sd->save_area);
 557         kfree(sd);
 558 }
 559
 560 static int svm_cpu_init(int cpu)
 561 {
 562         struct svm_cpu_data *sd;
 563
 564         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 565         if (!sd)
 566                 return -ENOMEM;
 567         sd->cpu = cpu;
 568         sd->save_area = alloc_page(GFP_KERNEL);
 569         if (!sd->save_area)
 570                 goto free_cpu_data;
 571         clear_page(page_address(sd->save_area));
 572
 573         if (svm_sev_enabled()) {
 574                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 575                                               sizeof(void *),
 576                                               GFP_KERNEL);
 577                 if (!sd->sev_vmcbs)
 578                         goto free_save_area;
 579         }
 580
 581         per_cpu(svm_data, cpu) = sd;
 582
 583         return 0;
 584
 585 free_save_area:
 586         __free_page(sd->save_area);
 587 free_cpu_data:
 588         kfree(sd);
 589         return -ENOMEM;
 590
 591 }
 592
 593 static int direct_access_msr_slot(u32 msr)
 594 {
 595         u32 i;
 596
 597         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 598                 if (direct_access_msrs[i].index == msr)
 599                         return i;
 600
 601         return -ENOENT;
 602 }
 603
 604 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 605                                      int write)
 606 {
 607         struct vcpu_svm *svm = to_svm(vcpu);
 608         int slot = direct_access_msr_slot(msr);
 609
 610         if (slot == -ENOENT)
 611                 return;
 612
 613         /* Set the shadow bitmaps to the desired intercept states */
 614         if (read)
 615                 set_bit(slot, svm->shadow_msr_intercept.read);
 616         else
 617                 clear_bit(slot, svm->shadow_msr_intercept.read);
 618
 619         if (write)
 620                 set_bit(slot, svm->shadow_msr_intercept.write);
 621         else
 622                 clear_bit(slot, svm->shadow_msr_intercept.write);
 623 }
 624
 625 static bool valid_msr_intercept(u32 index)
 626 {
 627         return direct_access_msr_slot(index) != -ENOENT;
 628 }
 629
 630 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 631 {
 632         u8 bit_write;
 633         unsigned long tmp;
 634         u32 offset;
 635         u32 *msrpm;
 636
 637         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 638                                       to_svm(vcpu)->msrpm;
 639
 640         offset    = svm_msrpm_offset(msr);
 641         bit_write = 2 * (msr & 0x0f) + 1;
 642         tmp       = msrpm[offset];
 643
 644         BUG_ON(offset == MSR_INVALID);
 645
 646         return !!test_bit(bit_write,  &tmp);
 647 }
 648
 649 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 650                                         u32 msr, int read, int write)
 651 {
 652         u8 bit_read, bit_write;
 653         unsigned long tmp;
 654         u32 offset;
 655
 656         /*
 657          * If this warning triggers extend the direct_access_msrs list at the
 658          * beginning of the file
 659          */
 660         WARN_ON(!valid_msr_intercept(msr));
 661
 662         /* Enforce non allowed MSRs to trap */
 663         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 664                 read = 0;
 665
 666         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 667                 write = 0;
 668
 669         offset    = svm_msrpm_offset(msr);
 670         bit_read  = 2 * (msr & 0x0f);
 671         bit_write = 2 * (msr & 0x0f) + 1;
 672         tmp       = msrpm[offset];
 673
 674         BUG_ON(offset == MSR_INVALID);
 675
 676         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 677         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 678
 679         msrpm[offset] = tmp;
 680 }
 681
 682 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 683                           int read, int write)
 684 {
 685         set_shadow_msr_intercept(vcpu, msr, read, write);
 686         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 687 }
 688
 689 u32 *svm_vcpu_alloc_msrpm(void)
 690 {
 691         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
 692         u32 *msrpm;
 693
 694         if (!pages)
 695                 return NULL;
 696
 697         msrpm = page_address(pages);
 698         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 699
 700         return msrpm;
 701 }
 702
 703 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 704 {
 705         int i;
 706
 707         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 708                 if (!direct_access_msrs[i].always)
 709                         continue;
 710                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 711         }
 712 }
 713
 714
 715 void svm_vcpu_free_msrpm(u32 *msrpm)
 716 {
 717         __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
 718 }
 719
 720 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 721 {
 722         struct vcpu_svm *svm = to_svm(vcpu);
 723         u32 i;
 724
 725         /*
 726          * Set intercept permissions for all direct access MSRs again. They
 727          * will automatically get filtered through the MSR filter, so we are
 728          * back in sync after this.
 729          */
 730         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 731                 u32 msr = direct_access_msrs[i].index;
 732                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 733                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 734
 735                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 736         }
 737 }
 738
 739 static void add_msr_offset(u32 offset)
 740 {
 741         int i;
 742
 743         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 744
 745                 /* Offset already in list? */
 746                 if (msrpm_offsets[i] == offset)
 747                         return;
 748
 749                 /* Slot used by another offset? */
 750                 if (msrpm_offsets[i] != MSR_INVALID)
 751                         continue;
 752
 753                 /* Add offset to list */
 754                 msrpm_offsets[i] = offset;
 755
 756                 return;
 757         }
 758
 759         /*
 760          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 761          * increase MSRPM_OFFSETS in this case.
 762          */
 763         BUG();
 764 }
 765
 766 static void init_msrpm_offsets(void)
 767 {
 768         int i;
 769
 770         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 771
 772         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 773                 u32 offset;
 774
 775                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 776                 BUG_ON(offset == MSR_INVALID);
 777
 778                 add_msr_offset(offset);
 779         }
 780 }
 781
 782 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 783 {
 784         struct vcpu_svm *svm = to_svm(vcpu);
 785
 786         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 787         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 788         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 789         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 790         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 791 }
 792
 793 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 794 {
 795         struct vcpu_svm *svm = to_svm(vcpu);
 796
 797         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 798         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 799         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 800         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 801         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 802 }
 803
 804 void disable_nmi_singlestep(struct vcpu_svm *svm)
 805 {
 806         svm->nmi_singlestep = false;
 807
 808         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 809                 /* Clear our flags if they were not set by the guest */
 810                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 811                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 812                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 813                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 814         }
 815 }
 816
 817 static void grow_ple_window(struct kvm_vcpu *vcpu)
 818 {
 819         struct vcpu_svm *svm = to_svm(vcpu);
 820         struct vmcb_control_area *control = &svm->vmcb->control;
 821         int old = control->pause_filter_count;
 822
 823         control->pause_filter_count = __grow_ple_window(old,
 824                                                         pause_filter_count,
 825                                                         pause_filter_count_grow,
 826                                                         pause_filter_count_max);
 827
 828         if (control->pause_filter_count != old) {
 829                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 830                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 831                                             control->pause_filter_count, old);
 832         }
 833 }
 834
 835 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 836 {
 837         struct vcpu_svm *svm = to_svm(vcpu);
 838         struct vmcb_control_area *control = &svm->vmcb->control;
 839         int old = control->pause_filter_count;
 840
 841         control->pause_filter_count =
 842                                 __shrink_ple_window(old,
 843                                                     pause_filter_count,
 844                                                     pause_filter_count_shrink,
 845                                                     pause_filter_count);
 846         if (control->pause_filter_count != old) {
 847                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 848                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 849                                             control->pause_filter_count, old);
 850         }
 851 }
 852
 853 /*
 854  * The default MMIO mask is a single bit (excluding the present bit),
 855  * which could conflict with the memory encryption bit. Check for
 856  * memory encryption support and override the default MMIO mask if
 857  * memory encryption is enabled.
 858  */
 859 static __init void svm_adjust_mmio_mask(void)
 860 {
 861         unsigned int enc_bit, mask_bit;
 862         u64 msr, mask;
 863
 864         /* If there is no memory encryption support, use existing mask */
 865         if (cpuid_eax(0x80000000) < 0x8000001f)
 866                 return;
 867
 868         /* If memory encryption is not enabled, use existing mask */
 869         rdmsrl(MSR_K8_SYSCFG, msr);
 870         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 871                 return;
 872
 873         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 874         mask_bit = boot_cpu_data.x86_phys_bits;
 875
 876         /* Increment the mask bit if it is the same as the encryption bit */
 877         if (enc_bit == mask_bit)
 878                 mask_bit++;
 879
 880         /*
 881          * If the mask bit location is below 52, then some bits above the
 882          * physical addressing limit will always be reserved, so use the
 883          * rsvd_bits() function to generate the mask. This mask, along with
 884          * the present bit, will be used to generate a page fault with
 885          * PFER.RSV = 1.
 886          *
 887          * If the mask bit location is 52 (or above), then clear the mask.
 888          */
 889         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 890
 891         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
 892 }
 893
 894 static void svm_hardware_teardown(void)
 895 {
 896         int cpu;
 897
 898         if (svm_sev_enabled())
 899                 sev_hardware_teardown();
 900
 901         for_each_possible_cpu(cpu)
 902                 svm_cpu_uninit(cpu);
 903
 904         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 905         iopm_base = 0;
 906 }
 907
 908 static __init void svm_set_cpu_caps(void)
 909 {
 910         kvm_set_cpu_caps();
 911
 912         supported_xss = 0;
 913
 914         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 915         if (nested) {
 916                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 917
 918                 if (nrips)
 919                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 920
 921                 if (npt_enabled)
 922                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 923         }
 924
 925         /* CPUID 0x80000008 */
 926         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 927             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 928                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 929
 930         /* Enable INVPCID feature */
 931         kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
 932 }
 933
 934 static __init int svm_hardware_setup(void)
 935 {
 936         int cpu;
 937         struct page *iopm_pages;
 938         void *iopm_va;
 939         int r;
 940
 941         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 942
 943         if (!iopm_pages)
 944                 return -ENOMEM;
 945
 946         iopm_va = page_address(iopm_pages);
 947         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 948         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 949
 950         init_msrpm_offsets();
 951
 952         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 953
 954         if (boot_cpu_has(X86_FEATURE_NX))
 955                 kvm_enable_efer_bits(EFER_NX);
 956
 957         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 958                 kvm_enable_efer_bits(EFER_FFXSR);
 959
 960         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 961                 kvm_has_tsc_control = true;
 962                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 963                 kvm_tsc_scaling_ratio_frac_bits = 32;
 964         }
 965
 966         /* Check for pause filtering support */
 967         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 968                 pause_filter_count = 0;
 969                 pause_filter_thresh = 0;
 970         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 971                 pause_filter_thresh = 0;
 972         }
 973
 974         if (nested) {
 975                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 976                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 977         }
 978
 979         if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
 980                 sev_hardware_setup();
 981         } else {
 982                 sev = false;
 983                 sev_es = false;
 984         }
 985
 986         svm_adjust_mmio_mask();
 987
 988         for_each_possible_cpu(cpu) {
 989                 r = svm_cpu_init(cpu);
 990                 if (r)
 991                         goto err;
 992         }
 993
 994         if (!boot_cpu_has(X86_FEATURE_NPT))
 995                 npt_enabled = false;
 996
 997         if (npt_enabled && !npt)
 998                 npt_enabled = false;
 999
1000         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
1001         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1002
1003         if (nrips) {
1004                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1005                         nrips = false;
1006         }
1007
1008         if (avic) {
1009                 if (!npt_enabled ||
1010                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1011                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1012                         avic = false;
1013                 } else {
1014                         pr_info("AVIC enabled\n");
1015
1016                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1017                 }
1018         }
1019
1020         if (vls) {
1021                 if (!npt_enabled ||
1022                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1023                     !IS_ENABLED(CONFIG_X86_64)) {
1024                         vls = false;
1025                 } else {
1026                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1027                 }
1028         }
1029
1030         if (vgif) {
1031                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1032                         vgif = false;
1033                 else
1034                         pr_info("Virtual GIF supported\n");
1035         }
1036
1037         svm_set_cpu_caps();
1038
1039         /*
1040          * It seems that on AMD processors PTE's accessed bit is
1041          * being set by the CPU hardware before the NPF vmexit.
1042          * This is not expected behaviour and our tests fail because
1043          * of it.
1044          * A workaround here is to disable support for
1045          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1046          * In this case userspace can know if there is support using
1047          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1048          * it
1049          * If future AMD CPU models change the behaviour described above,
1050          * this variable can be changed accordingly
1051          */
1052         allow_smaller_maxphyaddr = !npt_enabled;
1053
1054         return 0;
1055
1056 err:
1057         svm_hardware_teardown();
1058         return r;
1059 }
1060
1061 static void init_seg(struct vmcb_seg *seg)
1062 {
1063         seg->selector = 0;
1064         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1065                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1066         seg->limit = 0xffff;
1067         seg->base = 0;
1068 }
1069
1070 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1071 {
1072         seg->selector = 0;
1073         seg->attrib = SVM_SELECTOR_P_MASK | type;
1074         seg->limit = 0xffff;
1075         seg->base = 0;
1076 }
1077
1078 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1079 {
1080         struct vcpu_svm *svm = to_svm(vcpu);
1081         u64 g_tsc_offset = 0;
1082
1083         if (is_guest_mode(vcpu)) {
1084                 /* Write L1's TSC offset.  */
1085                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1086                                svm->nested.hsave->control.tsc_offset;
1087                 svm->nested.hsave->control.tsc_offset = offset;
1088         }
1089
1090         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1091                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1092                                    offset);
1093
1094         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1095
1096         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1097         return svm->vmcb->control.tsc_offset;
1098 }
1099
1100 static void svm_check_invpcid(struct vcpu_svm *svm)
1101 {
1102         /*
1103          * Intercept INVPCID instruction only if shadow page table is
1104          * enabled. Interception is not required with nested page table
1105          * enabled.
1106          */
1107         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1108                 if (!npt_enabled)
1109                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1110                 else
1111                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1112         }
1113 }
1114
1115 static void init_vmcb(struct vcpu_svm *svm)
1116 {
1117         struct vmcb_control_area *control = &svm->vmcb->control;
1118         struct vmcb_save_area *save = &svm->vmcb->save;
1119
1120         svm->vcpu.arch.hflags = 0;
1121
1122         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1123         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1124         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1125         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1126         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1127         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1128         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1129                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1130
1131         set_dr_intercepts(svm);
1132
1133         set_exception_intercept(svm, PF_VECTOR);
1134         set_exception_intercept(svm, UD_VECTOR);
1135         set_exception_intercept(svm, MC_VECTOR);
1136         set_exception_intercept(svm, AC_VECTOR);
1137         set_exception_intercept(svm, DB_VECTOR);
1138         /*
1139          * Guest access to VMware backdoor ports could legitimately
1140          * trigger #GP because of TSS I/O permission bitmap.
1141          * We intercept those #GP and allow access to them anyway
1142          * as VMware does.
1143          */
1144         if (enable_vmware_backdoor)
1145                 set_exception_intercept(svm, GP_VECTOR);
1146
1147         svm_set_intercept(svm, INTERCEPT_INTR);
1148         svm_set_intercept(svm, INTERCEPT_NMI);
1149         svm_set_intercept(svm, INTERCEPT_SMI);
1150         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1151         svm_set_intercept(svm, INTERCEPT_RDPMC);
1152         svm_set_intercept(svm, INTERCEPT_CPUID);
1153         svm_set_intercept(svm, INTERCEPT_INVD);
1154         svm_set_intercept(svm, INTERCEPT_INVLPG);
1155         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1156         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1157         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1158         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1159         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1160         svm_set_intercept(svm, INTERCEPT_VMRUN);
1161         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1162         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1163         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1164         svm_set_intercept(svm, INTERCEPT_STGI);
1165         svm_set_intercept(svm, INTERCEPT_CLGI);
1166         svm_set_intercept(svm, INTERCEPT_SKINIT);
1167         svm_set_intercept(svm, INTERCEPT_WBINVD);
1168         svm_set_intercept(svm, INTERCEPT_XSETBV);
1169         svm_set_intercept(svm, INTERCEPT_RDPRU);
1170         svm_set_intercept(svm, INTERCEPT_RSM);
1171
1172         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1173                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1174                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1175         }
1176
1177         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1178                 svm_set_intercept(svm, INTERCEPT_HLT);
1179
1180         control->iopm_base_pa = __sme_set(iopm_base);
1181         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1182         control->int_ctl = V_INTR_MASKING_MASK;
1183
1184         init_seg(&save->es);
1185         init_seg(&save->ss);
1186         init_seg(&save->ds);
1187         init_seg(&save->fs);
1188         init_seg(&save->gs);
1189
1190         save->cs.selector = 0xf000;
1191         save->cs.base = 0xffff0000;
1192         /* Executable/Readable Code Segment */
1193         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1194                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1195         save->cs.limit = 0xffff;
1196
1197         save->gdtr.limit = 0xffff;
1198         save->idtr.limit = 0xffff;
1199
1200         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1201         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1202
1203         svm_set_efer(&svm->vcpu, 0);
1204         save->dr6 = 0xffff0ff0;
1205         kvm_set_rflags(&svm->vcpu, 2);
1206         save->rip = 0x0000fff0;
1207         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1208
1209         /*
1210          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1211          * It also updates the guest-visible cr0 value.
1212          */
1213         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1214         kvm_mmu_reset_context(&svm->vcpu);
1215
1216         save->cr4 = X86_CR4_PAE;
1217         /* rdx = ?? */
1218
1219         if (npt_enabled) {
1220                 /* Setup VMCB for Nested Paging */
1221                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1222                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1223                 clr_exception_intercept(svm, PF_VECTOR);
1224                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1225                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1226                 save->g_pat = svm->vcpu.arch.pat;
1227                 save->cr3 = 0;
1228                 save->cr4 = 0;
1229         }
1230         svm->asid_generation = 0;
1231         svm->asid = 0;
1232
1233         svm->nested.vmcb12_gpa = 0;
1234         svm->vcpu.arch.hflags = 0;
1235
1236         if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1237                 control->pause_filter_count = pause_filter_count;
1238                 if (pause_filter_thresh)
1239                         control->pause_filter_thresh = pause_filter_thresh;
1240                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1241         } else {
1242                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1243         }
1244
1245         svm_check_invpcid(svm);
1246
1247         if (kvm_vcpu_apicv_active(&svm->vcpu))
1248                 avic_init_vmcb(svm);
1249
1250         /*
1251          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1252          * in VMCB and clear intercepts to avoid #VMEXIT.
1253          */
1254         if (vls) {
1255                 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1256                 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1257                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1258         }
1259
1260         if (vgif) {
1261                 svm_clr_intercept(svm, INTERCEPT_STGI);
1262                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1263                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1264         }
1265
1266         if (sev_guest(svm->vcpu.kvm)) {
1267                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1268                 clr_exception_intercept(svm, UD_VECTOR);
1269
1270                 if (sev_es_guest(svm->vcpu.kvm)) {
1271                         /* Perform SEV-ES specific VMCB updates */
1272                         sev_es_init_vmcb(svm);
1273                 }
1274         }
1275
1276         vmcb_mark_all_dirty(svm->vmcb);
1277
1278         enable_gif(svm);
1279
1280 }
1281
1282 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1283 {
1284         struct vcpu_svm *svm = to_svm(vcpu);
1285         u32 dummy;
1286         u32 eax = 1;
1287
1288         svm->spec_ctrl = 0;
1289         svm->virt_spec_ctrl = 0;
1290
1291         if (!init_event) {
1292                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1293                                            MSR_IA32_APICBASE_ENABLE;
1294                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1295                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1296         }
1297         init_vmcb(svm);
1298
1299         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1300         kvm_rdx_write(vcpu, eax);
1301
1302         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1303                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1304 }
1305
1306 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1307 {
1308         struct vcpu_svm *svm;
1309         struct page *vmcb_page;
1310         struct page *vmsa_page = NULL;
1311         int err;
1312
1313         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1314         svm = to_svm(vcpu);
1315
1316         err = -ENOMEM;
1317         vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1318         if (!vmcb_page)
1319                 goto out;
1320
1321         if (sev_es_guest(svm->vcpu.kvm)) {
1322                 /*
1323                  * SEV-ES guests require a separate VMSA page used to contain
1324                  * the encrypted register state of the guest.
1325                  */
1326                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1327                 if (!vmsa_page)
1328                         goto error_free_vmcb_page;
1329
1330                 /*
1331                  * SEV-ES guests maintain an encrypted version of their FPU
1332                  * state which is restored and saved on VMRUN and VMEXIT.
1333                  * Free the fpu structure to prevent KVM from attempting to
1334                  * access the FPU state.
1335                  */
1336                 kvm_free_guest_fpu(vcpu);
1337         }
1338
1339         err = avic_init_vcpu(svm);
1340         if (err)
1341                 goto error_free_vmsa_page;
1342
1343         /* We initialize this flag to true to make sure that the is_running
1344          * bit would be set the first time the vcpu is loaded.
1345          */
1346         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1347                 svm->avic_is_running = true;
1348
1349         svm->msrpm = svm_vcpu_alloc_msrpm();
1350         if (!svm->msrpm)
1351                 goto error_free_vmsa_page;
1352
1353         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1354
1355         svm->vmcb = page_address(vmcb_page);
1356         svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1357
1358         if (vmsa_page)
1359                 svm->vmsa = page_address(vmsa_page);
1360
1361         svm->asid_generation = 0;
1362         init_vmcb(svm);
1363
1364         svm_init_osvw(vcpu);
1365         vcpu->arch.microcode_version = 0x01000065;
1366
1367         if (sev_es_guest(svm->vcpu.kvm))
1368                 /* Perform SEV-ES specific VMCB creation updates */
1369                 sev_es_create_vcpu(svm);
1370
1371         return 0;
1372
1373 error_free_vmsa_page:
1374         if (vmsa_page)
1375                 __free_page(vmsa_page);
1376 error_free_vmcb_page:
1377         __free_page(vmcb_page);
1378 out:
1379         return err;
1380 }
1381
1382 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1383 {
1384         int i;
1385
1386         for_each_online_cpu(i)
1387                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1388 }
1389
1390 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1391 {
1392         struct vcpu_svm *svm = to_svm(vcpu);
1393
1394         /*
1395          * The vmcb page can be recycled, causing a false negative in
1396          * svm_vcpu_load(). So, ensure that no logical CPU has this
1397          * vmcb page recorded as its current vmcb.
1398          */
1399         svm_clear_current_vmcb(svm->vmcb);
1400
1401         svm_free_nested(svm);
1402
1403         sev_free_vcpu(vcpu);
1404
1405         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1406         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1407 }
1408
1409 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1410 {
1411         struct vcpu_svm *svm = to_svm(vcpu);
1412         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1413         int i;
1414
1415         if (unlikely(cpu != vcpu->cpu)) {
1416                 svm->asid_generation = 0;
1417                 vmcb_mark_all_dirty(svm->vmcb);
1418         }
1419
1420         if (sev_es_guest(svm->vcpu.kvm)) {
1421                 sev_es_vcpu_load(svm, cpu);
1422         } else {
1423 #ifdef CONFIG_X86_64
1424                 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1425 #endif
1426                 savesegment(fs, svm->host.fs);
1427                 savesegment(gs, svm->host.gs);
1428                 svm->host.ldt = kvm_read_ldt();
1429
1430                 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1431                         rdmsrl(host_save_user_msrs[i].index,
1432                                svm->host_user_msrs[i]);
1433         }
1434
1435         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1436                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1437                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1438                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1439                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1440                 }
1441         }
1442         /* This assumes that the kernel never uses MSR_TSC_AUX */
1443         if (static_cpu_has(X86_FEATURE_RDTSCP))
1444                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1445
1446         if (sd->current_vmcb != svm->vmcb) {
1447                 sd->current_vmcb = svm->vmcb;
1448                 indirect_branch_prediction_barrier();
1449         }
1450         avic_vcpu_load(vcpu, cpu);
1451 }
1452
1453 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1454 {
1455         struct vcpu_svm *svm = to_svm(vcpu);
1456         int i;
1457
1458         avic_vcpu_put(vcpu);
1459
1460         ++vcpu->stat.host_state_reload;
1461         if (sev_es_guest(svm->vcpu.kvm)) {
1462                 sev_es_vcpu_put(svm);
1463         } else {
1464                 kvm_load_ldt(svm->host.ldt);
1465 #ifdef CONFIG_X86_64
1466                 loadsegment(fs, svm->host.fs);
1467                 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1468                 load_gs_index(svm->host.gs);
1469 #else
1470 #ifdef CONFIG_X86_32_LAZY_GS
1471                 loadsegment(gs, svm->host.gs);
1472 #endif
1473 #endif
1474
1475                 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1476                         wrmsrl(host_save_user_msrs[i].index,
1477                                svm->host_user_msrs[i]);
1478         }
1479 }
1480
1481 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1482 {
1483         struct vcpu_svm *svm = to_svm(vcpu);
1484         unsigned long rflags = svm->vmcb->save.rflags;
1485
1486         if (svm->nmi_singlestep) {
1487                 /* Hide our flags if they were not set by the guest */
1488                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1489                         rflags &= ~X86_EFLAGS_TF;
1490                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1491                         rflags &= ~X86_EFLAGS_RF;
1492         }
1493         return rflags;
1494 }
1495
1496 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1497 {
1498         if (to_svm(vcpu)->nmi_singlestep)
1499                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1500
1501        /*
1502         * Any change of EFLAGS.VM is accompanied by a reload of SS
1503         * (caused by either a task switch or an inter-privilege IRET),
1504         * so we do not need to update the CPL here.
1505         */
1506         to_svm(vcpu)->vmcb->save.rflags = rflags;
1507 }
1508
1509 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1510 {
1511         switch (reg) {
1512         case VCPU_EXREG_PDPTR:
1513                 BUG_ON(!npt_enabled);
1514                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1515                 break;
1516         default:
1517                 WARN_ON_ONCE(1);
1518         }
1519 }
1520
1521 static void svm_set_vintr(struct vcpu_svm *svm)
1522 {
1523         struct vmcb_control_area *control;
1524
1525         /* The following fields are ignored when AVIC is enabled */
1526         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1527         svm_set_intercept(svm, INTERCEPT_VINTR);
1528
1529         /*
1530          * This is just a dummy VINTR to actually cause a vmexit to happen.
1531          * Actual injection of virtual interrupts happens through EVENTINJ.
1532          */
1533         control = &svm->vmcb->control;
1534         control->int_vector = 0x0;
1535         control->int_ctl &= ~V_INTR_PRIO_MASK;
1536         control->int_ctl |= V_IRQ_MASK |
1537                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1538         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1539 }
1540
1541 static void svm_clear_vintr(struct vcpu_svm *svm)
1542 {
1543         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1544         svm_clr_intercept(svm, INTERCEPT_VINTR);
1545
1546         /* Drop int_ctl fields related to VINTR injection.  */
1547         svm->vmcb->control.int_ctl &= mask;
1548         if (is_guest_mode(&svm->vcpu)) {
1549                 svm->nested.hsave->control.int_ctl &= mask;
1550
1551                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1552                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1553                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1554         }
1555
1556         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1557 }
1558
1559 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1560 {
1561         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1562
1563         switch (seg) {
1564         case VCPU_SREG_CS: return &save->cs;
1565         case VCPU_SREG_DS: return &save->ds;
1566         case VCPU_SREG_ES: return &save->es;
1567         case VCPU_SREG_FS: return &save->fs;
1568         case VCPU_SREG_GS: return &save->gs;
1569         case VCPU_SREG_SS: return &save->ss;
1570         case VCPU_SREG_TR: return &save->tr;
1571         case VCPU_SREG_LDTR: return &save->ldtr;
1572         }
1573         BUG();
1574         return NULL;
1575 }
1576
1577 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1578 {
1579         struct vmcb_seg *s = svm_seg(vcpu, seg);
1580
1581         return s->base;
1582 }
1583
1584 static void svm_get_segment(struct kvm_vcpu *vcpu,
1585                             struct kvm_segment *var, int seg)
1586 {
1587         struct vmcb_seg *s = svm_seg(vcpu, seg);
1588
1589         var->base = s->base;
1590         var->limit = s->limit;
1591         var->selector = s->selector;
1592         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1593         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1594         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1595         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1596         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1597         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1598         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1599
1600         /*
1601          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1602          * However, the SVM spec states that the G bit is not observed by the
1603          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1604          * So let's synthesize a legal G bit for all segments, this helps
1605          * running KVM nested. It also helps cross-vendor migration, because
1606          * Intel's vmentry has a check on the 'G' bit.
1607          */
1608         var->g = s->limit > 0xfffff;
1609
1610         /*
1611          * AMD's VMCB does not have an explicit unusable field, so emulate it
1612          * for cross vendor migration purposes by "not present"
1613          */
1614         var->unusable = !var->present;
1615
1616         switch (seg) {
1617         case VCPU_SREG_TR:
1618                 /*
1619                  * Work around a bug where the busy flag in the tr selector
1620                  * isn't exposed
1621                  */
1622                 var->type |= 0x2;
1623                 break;
1624         case VCPU_SREG_DS:
1625         case VCPU_SREG_ES:
1626         case VCPU_SREG_FS:
1627         case VCPU_SREG_GS:
1628                 /*
1629                  * The accessed bit must always be set in the segment
1630                  * descriptor cache, although it can be cleared in the
1631                  * descriptor, the cached bit always remains at 1. Since
1632                  * Intel has a check on this, set it here to support
1633                  * cross-vendor migration.
1634                  */
1635                 if (!var->unusable)
1636                         var->type |= 0x1;
1637                 break;
1638         case VCPU_SREG_SS:
1639                 /*
1640                  * On AMD CPUs sometimes the DB bit in the segment
1641                  * descriptor is left as 1, although the whole segment has
1642                  * been made unusable. Clear it here to pass an Intel VMX
1643                  * entry check when cross vendor migrating.
1644                  */
1645                 if (var->unusable)
1646                         var->db = 0;
1647                 /* This is symmetric with svm_set_segment() */
1648                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1649                 break;
1650         }
1651 }
1652
1653 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1654 {
1655         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1656
1657         return save->cpl;
1658 }
1659
1660 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1661 {
1662         struct vcpu_svm *svm = to_svm(vcpu);
1663
1664         dt->size = svm->vmcb->save.idtr.limit;
1665         dt->address = svm->vmcb->save.idtr.base;
1666 }
1667
1668 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1669 {
1670         struct vcpu_svm *svm = to_svm(vcpu);
1671
1672         svm->vmcb->save.idtr.limit = dt->size;
1673         svm->vmcb->save.idtr.base = dt->address ;
1674         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1675 }
1676
1677 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1678 {
1679         struct vcpu_svm *svm = to_svm(vcpu);
1680
1681         dt->size = svm->vmcb->save.gdtr.limit;
1682         dt->address = svm->vmcb->save.gdtr.base;
1683 }
1684
1685 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1686 {
1687         struct vcpu_svm *svm = to_svm(vcpu);
1688
1689         svm->vmcb->save.gdtr.limit = dt->size;
1690         svm->vmcb->save.gdtr.base = dt->address ;
1691         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1692 }
1693
1694 static void update_cr0_intercept(struct vcpu_svm *svm)
1695 {
1696         ulong gcr0;
1697         u64 *hcr0;
1698
1699         /*
1700          * SEV-ES guests must always keep the CR intercepts cleared. CR
1701          * tracking is done using the CR write traps.
1702          */
1703         if (sev_es_guest(svm->vcpu.kvm))
1704                 return;
1705
1706         gcr0 = svm->vcpu.arch.cr0;
1707         hcr0 = &svm->vmcb->save.cr0;
1708         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1709                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1710
1711         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1712
1713         if (gcr0 == *hcr0) {
1714                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1715                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1716         } else {
1717                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1718                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1719         }
1720 }
1721
1722 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1723 {
1724         struct vcpu_svm *svm = to_svm(vcpu);
1725
1726 #ifdef CONFIG_X86_64
1727         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1728                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1729                         vcpu->arch.efer |= EFER_LMA;
1730                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1731                 }
1732
1733                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1734                         vcpu->arch.efer &= ~EFER_LMA;
1735                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1736                 }
1737         }
1738 #endif
1739         vcpu->arch.cr0 = cr0;
1740
1741         if (!npt_enabled)
1742                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1743
1744         /*
1745          * re-enable caching here because the QEMU bios
1746          * does not do it - this results in some delay at
1747          * reboot
1748          */
1749         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1750                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1751         svm->vmcb->save.cr0 = cr0;
1752         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1753         update_cr0_intercept(svm);
1754 }
1755
1756 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1757 {
1758         return true;
1759 }
1760
1761 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1762 {
1763         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1764         unsigned long old_cr4 = vcpu->arch.cr4;
1765
1766         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1767                 svm_flush_tlb(vcpu);
1768
1769         vcpu->arch.cr4 = cr4;
1770         if (!npt_enabled)
1771                 cr4 |= X86_CR4_PAE;
1772         cr4 |= host_cr4_mce;
1773         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1774         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1775
1776         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1777                 kvm_update_cpuid_runtime(vcpu);
1778 }
1779
1780 static void svm_set_segment(struct kvm_vcpu *vcpu,
1781                             struct kvm_segment *var, int seg)
1782 {
1783         struct vcpu_svm *svm = to_svm(vcpu);
1784         struct vmcb_seg *s = svm_seg(vcpu, seg);
1785
1786         s->base = var->base;
1787         s->limit = var->limit;
1788         s->selector = var->selector;
1789         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1790         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1791         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1792         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1793         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1794         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1795         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1796         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1797
1798         /*
1799          * This is always accurate, except if SYSRET returned to a segment
1800          * with SS.DPL != 3.  Intel does not have this quirk, and always
1801          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1802          * would entail passing the CPL to userspace and back.
1803          */
1804         if (seg == VCPU_SREG_SS)
1805                 /* This is symmetric with svm_get_segment() */
1806                 svm->vmcb->save.cpl = (var->dpl & 3);
1807
1808         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1809 }
1810
1811 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1812 {
1813         struct vcpu_svm *svm = to_svm(vcpu);
1814
1815         clr_exception_intercept(svm, BP_VECTOR);
1816
1817         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1818                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1819                         set_exception_intercept(svm, BP_VECTOR);
1820         }
1821 }
1822
1823 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1824 {
1825         if (sd->next_asid > sd->max_asid) {
1826                 ++sd->asid_generation;
1827                 sd->next_asid = sd->min_asid;
1828                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1829                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1830         }
1831
1832         svm->asid_generation = sd->asid_generation;
1833         svm->asid = sd->next_asid++;
1834 }
1835
1836 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1837 {
1838         struct vmcb *vmcb = svm->vmcb;
1839
1840         if (svm->vcpu.arch.guest_state_protected)
1841                 return;
1842
1843         if (unlikely(value != vmcb->save.dr6)) {
1844                 vmcb->save.dr6 = value;
1845                 vmcb_mark_dirty(vmcb, VMCB_DR);
1846         }
1847 }
1848
1849 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1850 {
1851         struct vcpu_svm *svm = to_svm(vcpu);
1852
1853         if (vcpu->arch.guest_state_protected)
1854                 return;
1855
1856         get_debugreg(vcpu->arch.db[0], 0);
1857         get_debugreg(vcpu->arch.db[1], 1);
1858         get_debugreg(vcpu->arch.db[2], 2);
1859         get_debugreg(vcpu->arch.db[3], 3);
1860         /*
1861          * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1862          * because db_interception might need it.  We can do it before vmentry.
1863          */
1864         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1865         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1866         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1867         set_dr_intercepts(svm);
1868 }
1869
1870 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1871 {
1872         struct vcpu_svm *svm = to_svm(vcpu);
1873
1874         if (vcpu->arch.guest_state_protected)
1875                 return;
1876
1877         svm->vmcb->save.dr7 = value;
1878         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1879 }
1880
1881 static int pf_interception(struct vcpu_svm *svm)
1882 {
1883         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1884         u64 error_code = svm->vmcb->control.exit_info_1;
1885
1886         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1887                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1888                         svm->vmcb->control.insn_bytes : NULL,
1889                         svm->vmcb->control.insn_len);
1890 }
1891
1892 static int npf_interception(struct vcpu_svm *svm)
1893 {
1894         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1895         u64 error_code = svm->vmcb->control.exit_info_1;
1896
1897         trace_kvm_page_fault(fault_address, error_code);
1898         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1899                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1900                         svm->vmcb->control.insn_bytes : NULL,
1901                         svm->vmcb->control.insn_len);
1902 }
1903
1904 static int db_interception(struct vcpu_svm *svm)
1905 {
1906         struct kvm_run *kvm_run = svm->vcpu.run;
1907         struct kvm_vcpu *vcpu = &svm->vcpu;
1908
1909         if (!(svm->vcpu.guest_debug &
1910               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1911                 !svm->nmi_singlestep) {
1912                 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1913                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1914                 return 1;
1915         }
1916
1917         if (svm->nmi_singlestep) {
1918                 disable_nmi_singlestep(svm);
1919                 /* Make sure we check for pending NMIs upon entry */
1920                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1921         }
1922
1923         if (svm->vcpu.guest_debug &
1924             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1925                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1926                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1927                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1928                 kvm_run->debug.arch.pc =
1929                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1930                 kvm_run->debug.arch.exception = DB_VECTOR;
1931                 return 0;
1932         }
1933
1934         return 1;
1935 }
1936
1937 static int bp_interception(struct vcpu_svm *svm)
1938 {
1939         struct kvm_run *kvm_run = svm->vcpu.run;
1940
1941         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1942         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1943         kvm_run->debug.arch.exception = BP_VECTOR;
1944         return 0;
1945 }
1946
1947 static int ud_interception(struct vcpu_svm *svm)
1948 {
1949         return handle_ud(&svm->vcpu);
1950 }
1951
1952 static int ac_interception(struct vcpu_svm *svm)
1953 {
1954         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1955         return 1;
1956 }
1957
1958 static int gp_interception(struct vcpu_svm *svm)
1959 {
1960         struct kvm_vcpu *vcpu = &svm->vcpu;
1961         u32 error_code = svm->vmcb->control.exit_info_1;
1962
1963         WARN_ON_ONCE(!enable_vmware_backdoor);
1964
1965         /*
1966          * VMware backdoor emulation on #GP interception only handles IN{S},
1967          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1968          */
1969         if (error_code) {
1970                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1971                 return 1;
1972         }
1973         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1974 }
1975
1976 static bool is_erratum_383(void)
1977 {
1978         int err, i;
1979         u64 value;
1980
1981         if (!erratum_383_found)
1982                 return false;
1983
1984         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1985         if (err)
1986                 return false;
1987
1988         /* Bit 62 may or may not be set for this mce */
1989         value &= ~(1ULL << 62);
1990
1991         if (value != 0xb600000000010015ULL)
1992                 return false;
1993
1994         /* Clear MCi_STATUS registers */
1995         for (i = 0; i < 6; ++i)
1996                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1997
1998         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1999         if (!err) {
2000                 u32 low, high;
2001
2002                 value &= ~(1ULL << 2);
2003                 low    = lower_32_bits(value);
2004                 high   = upper_32_bits(value);
2005
2006                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2007         }
2008
2009         /* Flush tlb to evict multi-match entries */
2010         __flush_tlb_all();
2011
2012         return true;
2013 }
2014
2015 static void svm_handle_mce(struct vcpu_svm *svm)
2016 {
2017         if (is_erratum_383()) {
2018                 /*
2019                  * Erratum 383 triggered. Guest state is corrupt so kill the
2020                  * guest.
2021                  */
2022                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2023
2024                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2025
2026                 return;
2027         }
2028
2029         /*
2030          * On an #MC intercept the MCE handler is not called automatically in
2031          * the host. So do it by hand here.
2032          */
2033         kvm_machine_check();
2034 }
2035
2036 static int mc_interception(struct vcpu_svm *svm)
2037 {
2038         return 1;
2039 }
2040
2041 static int shutdown_interception(struct vcpu_svm *svm)
2042 {
2043         struct kvm_run *kvm_run = svm->vcpu.run;
2044
2045         /*
2046          * The VM save area has already been encrypted so it
2047          * cannot be reinitialized - just terminate.
2048          */
2049         if (sev_es_guest(svm->vcpu.kvm))
2050                 return -EINVAL;
2051
2052         /*
2053          * VMCB is undefined after a SHUTDOWN intercept
2054          * so reinitialize it.
2055          */
2056         clear_page(svm->vmcb);
2057         init_vmcb(svm);
2058
2059         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2060         return 0;
2061 }
2062
2063 static int io_interception(struct vcpu_svm *svm)
2064 {
2065         struct kvm_vcpu *vcpu = &svm->vcpu;
2066         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2067         int size, in, string;
2068         unsigned port;
2069
2070         ++svm->vcpu.stat.io_exits;
2071         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2072         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2073         port = io_info >> 16;
2074         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2075
2076         if (string) {
2077                 if (sev_es_guest(vcpu->kvm))
2078                         return sev_es_string_io(svm, size, port, in);
2079                 else
2080                         return kvm_emulate_instruction(vcpu, 0);
2081         }
2082
2083         svm->next_rip = svm->vmcb->control.exit_info_2;
2084
2085         return kvm_fast_pio(&svm->vcpu, size, port, in);
2086 }
2087
2088 static int nmi_interception(struct vcpu_svm *svm)
2089 {
2090         return 1;
2091 }
2092
2093 static int intr_interception(struct vcpu_svm *svm)
2094 {
2095         ++svm->vcpu.stat.irq_exits;
2096         return 1;
2097 }
2098
2099 static int nop_on_interception(struct vcpu_svm *svm)
2100 {
2101         return 1;
2102 }
2103
2104 static int halt_interception(struct vcpu_svm *svm)
2105 {
2106         return kvm_emulate_halt(&svm->vcpu);
2107 }
2108
2109 static int vmmcall_interception(struct vcpu_svm *svm)
2110 {
2111         return kvm_emulate_hypercall(&svm->vcpu);
2112 }
2113
2114 static int vmload_interception(struct vcpu_svm *svm)
2115 {
2116         struct vmcb *nested_vmcb;
2117         struct kvm_host_map map;
2118         int ret;
2119
2120         if (nested_svm_check_permissions(svm))
2121                 return 1;
2122
2123         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2124         if (ret) {
2125                 if (ret == -EINVAL)
2126                         kvm_inject_gp(&svm->vcpu, 0);
2127                 return 1;
2128         }
2129
2130         nested_vmcb = map.hva;
2131
2132         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2133
2134         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2135         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2136
2137         return ret;
2138 }
2139
2140 static int vmsave_interception(struct vcpu_svm *svm)
2141 {
2142         struct vmcb *nested_vmcb;
2143         struct kvm_host_map map;
2144         int ret;
2145
2146         if (nested_svm_check_permissions(svm))
2147                 return 1;
2148
2149         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2150         if (ret) {
2151                 if (ret == -EINVAL)
2152                         kvm_inject_gp(&svm->vcpu, 0);
2153                 return 1;
2154         }
2155
2156         nested_vmcb = map.hva;
2157
2158         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2159
2160         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2161         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2162
2163         return ret;
2164 }
2165
2166 static int vmrun_interception(struct vcpu_svm *svm)
2167 {
2168         if (nested_svm_check_permissions(svm))
2169                 return 1;
2170
2171         return nested_svm_vmrun(svm);
2172 }
2173
2174 void svm_set_gif(struct vcpu_svm *svm, bool value)
2175 {
2176         if (value) {
2177                 /*
2178                  * If VGIF is enabled, the STGI intercept is only added to
2179                  * detect the opening of the SMI/NMI window; remove it now.
2180                  * Likewise, clear the VINTR intercept, we will set it
2181                  * again while processing KVM_REQ_EVENT if needed.
2182                  */
2183                 if (vgif_enabled(svm))
2184                         svm_clr_intercept(svm, INTERCEPT_STGI);
2185                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2186                         svm_clear_vintr(svm);
2187
2188                 enable_gif(svm);
2189                 if (svm->vcpu.arch.smi_pending ||
2190                     svm->vcpu.arch.nmi_pending ||
2191                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2192                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2193         } else {
2194                 disable_gif(svm);
2195
2196                 /*
2197                  * After a CLGI no interrupts should come.  But if vGIF is
2198                  * in use, we still rely on the VINTR intercept (rather than
2199                  * STGI) to detect an open interrupt window.
2200                 */
2201                 if (!vgif_enabled(svm))
2202                         svm_clear_vintr(svm);
2203         }
2204 }
2205
2206 static int stgi_interception(struct vcpu_svm *svm)
2207 {
2208         int ret;
2209
2210         if (nested_svm_check_permissions(svm))
2211                 return 1;
2212
2213         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2214         svm_set_gif(svm, true);
2215         return ret;
2216 }
2217
2218 static int clgi_interception(struct vcpu_svm *svm)
2219 {
2220         int ret;
2221
2222         if (nested_svm_check_permissions(svm))
2223                 return 1;
2224
2225         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2226         svm_set_gif(svm, false);
2227         return ret;
2228 }
2229
2230 static int invlpga_interception(struct vcpu_svm *svm)
2231 {
2232         struct kvm_vcpu *vcpu = &svm->vcpu;
2233
2234         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2235                           kvm_rax_read(&svm->vcpu));
2236
2237         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2238         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2239
2240         return kvm_skip_emulated_instruction(&svm->vcpu);
2241 }
2242
2243 static int skinit_interception(struct vcpu_svm *svm)
2244 {
2245         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2246
2247         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2248         return 1;
2249 }
2250
2251 static int wbinvd_interception(struct vcpu_svm *svm)
2252 {
2253         return kvm_emulate_wbinvd(&svm->vcpu);
2254 }
2255
2256 static int xsetbv_interception(struct vcpu_svm *svm)
2257 {
2258         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2259         u32 index = kvm_rcx_read(&svm->vcpu);
2260
2261         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2262                 return kvm_skip_emulated_instruction(&svm->vcpu);
2263         }
2264
2265         return 1;
2266 }
2267
2268 static int rdpru_interception(struct vcpu_svm *svm)
2269 {
2270         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2271         return 1;
2272 }
2273
2274 static int task_switch_interception(struct vcpu_svm *svm)
2275 {
2276         u16 tss_selector;
2277         int reason;
2278         int int_type = svm->vmcb->control.exit_int_info &
2279                 SVM_EXITINTINFO_TYPE_MASK;
2280         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2281         uint32_t type =
2282                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2283         uint32_t idt_v =
2284                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2285         bool has_error_code = false;
2286         u32 error_code = 0;
2287
2288         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2289
2290         if (svm->vmcb->control.exit_info_2 &
2291             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2292                 reason = TASK_SWITCH_IRET;
2293         else if (svm->vmcb->control.exit_info_2 &
2294                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2295                 reason = TASK_SWITCH_JMP;
2296         else if (idt_v)
2297                 reason = TASK_SWITCH_GATE;
2298         else
2299                 reason = TASK_SWITCH_CALL;
2300
2301         if (reason == TASK_SWITCH_GATE) {
2302                 switch (type) {
2303                 case SVM_EXITINTINFO_TYPE_NMI:
2304                         svm->vcpu.arch.nmi_injected = false;
2305                         break;
2306                 case SVM_EXITINTINFO_TYPE_EXEPT:
2307                         if (svm->vmcb->control.exit_info_2 &
2308                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2309                                 has_error_code = true;
2310                                 error_code =
2311                                         (u32)svm->vmcb->control.exit_info_2;
2312                         }
2313                         kvm_clear_exception_queue(&svm->vcpu);
2314                         break;
2315                 case SVM_EXITINTINFO_TYPE_INTR:
2316                         kvm_clear_interrupt_queue(&svm->vcpu);
2317                         break;
2318                 default:
2319                         break;
2320                 }
2321         }
2322
2323         if (reason != TASK_SWITCH_GATE ||
2324             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2325             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2326              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2327                 if (!skip_emulated_instruction(&svm->vcpu))
2328                         return 0;
2329         }
2330
2331         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2332                 int_vec = -1;
2333
2334         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2335                                has_error_code, error_code);
2336 }
2337
2338 static int cpuid_interception(struct vcpu_svm *svm)
2339 {
2340         return kvm_emulate_cpuid(&svm->vcpu);
2341 }
2342
2343 static int iret_interception(struct vcpu_svm *svm)
2344 {
2345         ++svm->vcpu.stat.nmi_window_exits;
2346         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2347         if (!sev_es_guest(svm->vcpu.kvm)) {
2348                 svm_clr_intercept(svm, INTERCEPT_IRET);
2349                 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2350         }
2351         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2352         return 1;
2353 }
2354
2355 static int invd_interception(struct vcpu_svm *svm)
2356 {
2357         /* Treat an INVD instruction as a NOP and just skip it. */
2358         return kvm_skip_emulated_instruction(&svm->vcpu);
2359 }
2360
2361 static int invlpg_interception(struct vcpu_svm *svm)
2362 {
2363         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2364                 return kvm_emulate_instruction(&svm->vcpu, 0);
2365
2366         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2367         return kvm_skip_emulated_instruction(&svm->vcpu);
2368 }
2369
2370 static int emulate_on_interception(struct vcpu_svm *svm)
2371 {
2372         return kvm_emulate_instruction(&svm->vcpu, 0);
2373 }
2374
2375 static int rsm_interception(struct vcpu_svm *svm)
2376 {
2377         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2378 }
2379
2380 static int rdpmc_interception(struct vcpu_svm *svm)
2381 {
2382         int err;
2383
2384         if (!nrips)
2385                 return emulate_on_interception(svm);
2386
2387         err = kvm_rdpmc(&svm->vcpu);
2388         return kvm_complete_insn_gp(&svm->vcpu, err);
2389 }
2390
2391 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2392                                             unsigned long val)
2393 {
2394         unsigned long cr0 = svm->vcpu.arch.cr0;
2395         bool ret = false;
2396
2397         if (!is_guest_mode(&svm->vcpu) ||
2398             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2399                 return false;
2400
2401         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2402         val &= ~SVM_CR0_SELECTIVE_MASK;
2403
2404         if (cr0 ^ val) {
2405                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2406                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2407         }
2408
2409         return ret;
2410 }
2411
2412 #define CR_VALID (1ULL << 63)
2413
2414 static int cr_interception(struct vcpu_svm *svm)
2415 {
2416         int reg, cr;
2417         unsigned long val;
2418         int err;
2419
2420         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2421                 return emulate_on_interception(svm);
2422
2423         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2424                 return emulate_on_interception(svm);
2425
2426         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2427         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2428                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2429         else
2430                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2431
2432         err = 0;
2433         if (cr >= 16) { /* mov to cr */
2434                 cr -= 16;
2435                 val = kvm_register_read(&svm->vcpu, reg);
2436                 trace_kvm_cr_write(cr, val);
2437                 switch (cr) {
2438                 case 0:
2439                         if (!check_selective_cr0_intercepted(svm, val))
2440                                 err = kvm_set_cr0(&svm->vcpu, val);
2441                         else
2442                                 return 1;
2443
2444                         break;
2445                 case 3:
2446                         err = kvm_set_cr3(&svm->vcpu, val);
2447                         break;
2448                 case 4:
2449                         err = kvm_set_cr4(&svm->vcpu, val);
2450                         break;
2451                 case 8:
2452                         err = kvm_set_cr8(&svm->vcpu, val);
2453                         break;
2454                 default:
2455                         WARN(1, "unhandled write to CR%d", cr);
2456                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2457                         return 1;
2458                 }
2459         } else { /* mov from cr */
2460                 switch (cr) {
2461                 case 0:
2462                         val = kvm_read_cr0(&svm->vcpu);
2463                         break;
2464                 case 2:
2465                         val = svm->vcpu.arch.cr2;
2466                         break;
2467                 case 3:
2468                         val = kvm_read_cr3(&svm->vcpu);
2469                         break;
2470                 case 4:
2471                         val = kvm_read_cr4(&svm->vcpu);
2472                         break;
2473                 case 8:
2474                         val = kvm_get_cr8(&svm->vcpu);
2475                         break;
2476                 default:
2477                         WARN(1, "unhandled read from CR%d", cr);
2478                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2479                         return 1;
2480                 }
2481                 kvm_register_write(&svm->vcpu, reg, val);
2482                 trace_kvm_cr_read(cr, val);
2483         }
2484         return kvm_complete_insn_gp(&svm->vcpu, err);
2485 }
2486
2487 static int cr_trap(struct vcpu_svm *svm)
2488 {
2489         struct kvm_vcpu *vcpu = &svm->vcpu;
2490         unsigned long old_value, new_value;
2491         unsigned int cr;
2492         int ret = 0;
2493
2494         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2495
2496         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2497         switch (cr) {
2498         case 0:
2499                 old_value = kvm_read_cr0(vcpu);
2500                 svm_set_cr0(vcpu, new_value);
2501
2502                 kvm_post_set_cr0(vcpu, old_value, new_value);
2503                 break;
2504         case 4:
2505                 old_value = kvm_read_cr4(vcpu);
2506                 svm_set_cr4(vcpu, new_value);
2507
2508                 kvm_post_set_cr4(vcpu, old_value, new_value);
2509                 break;
2510         case 8:
2511                 ret = kvm_set_cr8(&svm->vcpu, new_value);
2512                 break;
2513         default:
2514                 WARN(1, "unhandled CR%d write trap", cr);
2515                 kvm_queue_exception(vcpu, UD_VECTOR);
2516                 return 1;
2517         }
2518
2519         return kvm_complete_insn_gp(vcpu, ret);
2520 }
2521
2522 static int dr_interception(struct vcpu_svm *svm)
2523 {
2524         int reg, dr;
2525         unsigned long val;
2526
2527         if (svm->vcpu.guest_debug == 0) {
2528                 /*
2529                  * No more DR vmexits; force a reload of the debug registers
2530                  * and reenter on this instruction.  The next vmexit will
2531                  * retrieve the full state of the debug registers.
2532                  */
2533                 clr_dr_intercepts(svm);
2534                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2535                 return 1;
2536         }
2537
2538         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2539                 return emulate_on_interception(svm);
2540
2541         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2542         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2543
2544         if (dr >= 16) { /* mov to DRn */
2545                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2546                         return 1;
2547                 val = kvm_register_read(&svm->vcpu, reg);
2548                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2549         } else {
2550                 if (!kvm_require_dr(&svm->vcpu, dr))
2551                         return 1;
2552                 kvm_get_dr(&svm->vcpu, dr, &val);
2553                 kvm_register_write(&svm->vcpu, reg, val);
2554         }
2555
2556         return kvm_skip_emulated_instruction(&svm->vcpu);
2557 }
2558
2559 static int cr8_write_interception(struct vcpu_svm *svm)
2560 {
2561         struct kvm_run *kvm_run = svm->vcpu.run;
2562         int r;
2563
2564         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2565         /* instruction emulation calls kvm_set_cr8() */
2566         r = cr_interception(svm);
2567         if (lapic_in_kernel(&svm->vcpu))
2568                 return r;
2569         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2570                 return r;
2571         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2572         return 0;
2573 }
2574
2575 static int efer_trap(struct vcpu_svm *svm)
2576 {
2577         struct msr_data msr_info;
2578         int ret;
2579
2580         /*
2581          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2582          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2583          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2584          * the guest doesn't have X86_FEATURE_SVM.
2585          */
2586         msr_info.host_initiated = false;
2587         msr_info.index = MSR_EFER;
2588         msr_info.data = svm->vmcb->control.exit_info_1 & ~EFER_SVME;
2589         ret = kvm_set_msr_common(&svm->vcpu, &msr_info);
2590
2591         return kvm_complete_insn_gp(&svm->vcpu, ret);
2592 }
2593
2594 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2595 {
2596         msr->data = 0;
2597
2598         switch (msr->index) {
2599         case MSR_F10H_DECFG:
2600                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2601                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2602                 break;
2603         case MSR_IA32_PERF_CAPABILITIES:
2604                 return 0;
2605         default:
2606                 return KVM_MSR_RET_INVALID;
2607         }
2608
2609         return 0;
2610 }
2611
2612 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2613 {
2614         struct vcpu_svm *svm = to_svm(vcpu);
2615
2616         switch (msr_info->index) {
2617         case MSR_STAR:
2618                 msr_info->data = svm->vmcb->save.star;
2619                 break;
2620 #ifdef CONFIG_X86_64
2621         case MSR_LSTAR:
2622                 msr_info->data = svm->vmcb->save.lstar;
2623                 break;
2624         case MSR_CSTAR:
2625                 msr_info->data = svm->vmcb->save.cstar;
2626                 break;
2627         case MSR_KERNEL_GS_BASE:
2628                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2629                 break;
2630         case MSR_SYSCALL_MASK:
2631                 msr_info->data = svm->vmcb->save.sfmask;
2632                 break;
2633 #endif
2634         case MSR_IA32_SYSENTER_CS:
2635                 msr_info->data = svm->vmcb->save.sysenter_cs;
2636                 break;
2637         case MSR_IA32_SYSENTER_EIP:
2638                 msr_info->data = svm->sysenter_eip;
2639                 break;
2640         case MSR_IA32_SYSENTER_ESP:
2641                 msr_info->data = svm->sysenter_esp;
2642                 break;
2643         case MSR_TSC_AUX:
2644                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2645                         return 1;
2646                 msr_info->data = svm->tsc_aux;
2647                 break;
2648         /*
2649          * Nobody will change the following 5 values in the VMCB so we can
2650          * safely return them on rdmsr. They will always be 0 until LBRV is
2651          * implemented.
2652          */
2653         case MSR_IA32_DEBUGCTLMSR:
2654                 msr_info->data = svm->vmcb->save.dbgctl;
2655                 break;
2656         case MSR_IA32_LASTBRANCHFROMIP:
2657                 msr_info->data = svm->vmcb->save.br_from;
2658                 break;
2659         case MSR_IA32_LASTBRANCHTOIP:
2660                 msr_info->data = svm->vmcb->save.br_to;
2661                 break;
2662         case MSR_IA32_LASTINTFROMIP:
2663                 msr_info->data = svm->vmcb->save.last_excp_from;
2664                 break;
2665         case MSR_IA32_LASTINTTOIP:
2666                 msr_info->data = svm->vmcb->save.last_excp_to;
2667                 break;
2668         case MSR_VM_HSAVE_PA:
2669                 msr_info->data = svm->nested.hsave_msr;
2670                 break;
2671         case MSR_VM_CR:
2672                 msr_info->data = svm->nested.vm_cr_msr;
2673                 break;
2674         case MSR_IA32_SPEC_CTRL:
2675                 if (!msr_info->host_initiated &&
2676                     !guest_has_spec_ctrl_msr(vcpu))
2677                         return 1;
2678
2679                 msr_info->data = svm->spec_ctrl;
2680                 break;
2681         case MSR_AMD64_VIRT_SPEC_CTRL:
2682                 if (!msr_info->host_initiated &&
2683                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2684                         return 1;
2685
2686                 msr_info->data = svm->virt_spec_ctrl;
2687                 break;
2688         case MSR_F15H_IC_CFG: {
2689
2690                 int family, model;
2691
2692                 family = guest_cpuid_family(vcpu);
2693                 model  = guest_cpuid_model(vcpu);
2694
2695                 if (family < 0 || model < 0)
2696                         return kvm_get_msr_common(vcpu, msr_info);
2697
2698                 msr_info->data = 0;
2699
2700                 if (family == 0x15 &&
2701                     (model >= 0x2 && model < 0x20))
2702                         msr_info->data = 0x1E;
2703                 }
2704                 break;
2705         case MSR_F10H_DECFG:
2706                 msr_info->data = svm->msr_decfg;
2707                 break;
2708         default:
2709                 return kvm_get_msr_common(vcpu, msr_info);
2710         }
2711         return 0;
2712 }
2713
2714 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2715 {
2716         struct vcpu_svm *svm = to_svm(vcpu);
2717         if (!sev_es_guest(svm->vcpu.kvm) || !err)
2718                 return kvm_complete_insn_gp(&svm->vcpu, err);
2719
2720         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2721         ghcb_set_sw_exit_info_2(svm->ghcb,
2722                                 X86_TRAP_GP |
2723                                 SVM_EVTINJ_TYPE_EXEPT |
2724                                 SVM_EVTINJ_VALID);
2725         return 1;
2726 }
2727
2728 static int rdmsr_interception(struct vcpu_svm *svm)
2729 {
2730         return kvm_emulate_rdmsr(&svm->vcpu);
2731 }
2732
2733 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2734 {
2735         struct vcpu_svm *svm = to_svm(vcpu);
2736         int svm_dis, chg_mask;
2737
2738         if (data & ~SVM_VM_CR_VALID_MASK)
2739                 return 1;
2740
2741         chg_mask = SVM_VM_CR_VALID_MASK;
2742
2743         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2744                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2745
2746         svm->nested.vm_cr_msr &= ~chg_mask;
2747         svm->nested.vm_cr_msr |= (data & chg_mask);
2748
2749         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2750
2751         /* check for svm_disable while efer.svme is set */
2752         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2753                 return 1;
2754
2755         return 0;
2756 }
2757
2758 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2759 {
2760         struct vcpu_svm *svm = to_svm(vcpu);
2761
2762         u32 ecx = msr->index;
2763         u64 data = msr->data;
2764         switch (ecx) {
2765         case MSR_IA32_CR_PAT:
2766                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2767                         return 1;
2768                 vcpu->arch.pat = data;
2769                 svm->vmcb->save.g_pat = data;
2770                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2771                 break;
2772         case MSR_IA32_SPEC_CTRL:
2773                 if (!msr->host_initiated &&
2774                     !guest_has_spec_ctrl_msr(vcpu))
2775                         return 1;
2776
2777                 if (kvm_spec_ctrl_test_value(data))
2778                         return 1;
2779
2780                 svm->spec_ctrl = data;
2781                 if (!data)
2782                         break;
2783
2784                 /*
2785                  * For non-nested:
2786                  * When it's written (to non-zero) for the first time, pass
2787                  * it through.
2788                  *
2789                  * For nested:
2790                  * The handling of the MSR bitmap for L2 guests is done in
2791                  * nested_svm_vmrun_msrpm.
2792                  * We update the L1 MSR bit as well since it will end up
2793                  * touching the MSR anyway now.
2794                  */
2795                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2796                 break;
2797         case MSR_IA32_PRED_CMD:
2798                 if (!msr->host_initiated &&
2799                     !guest_has_pred_cmd_msr(vcpu))
2800                         return 1;
2801
2802                 if (data & ~PRED_CMD_IBPB)
2803                         return 1;
2804                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2805                         return 1;
2806                 if (!data)
2807                         break;
2808
2809                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2810                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2811                 break;
2812         case MSR_AMD64_VIRT_SPEC_CTRL:
2813                 if (!msr->host_initiated &&
2814                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2815                         return 1;
2816
2817                 if (data & ~SPEC_CTRL_SSBD)
2818                         return 1;
2819
2820                 svm->virt_spec_ctrl = data;
2821                 break;
2822         case MSR_STAR:
2823                 svm->vmcb->save.star = data;
2824                 break;
2825 #ifdef CONFIG_X86_64
2826         case MSR_LSTAR:
2827                 svm->vmcb->save.lstar = data;
2828                 break;
2829         case MSR_CSTAR:
2830                 svm->vmcb->save.cstar = data;
2831                 break;
2832         case MSR_KERNEL_GS_BASE:
2833                 svm->vmcb->save.kernel_gs_base = data;
2834                 break;
2835         case MSR_SYSCALL_MASK:
2836                 svm->vmcb->save.sfmask = data;
2837                 break;
2838 #endif
2839         case MSR_IA32_SYSENTER_CS:
2840                 svm->vmcb->save.sysenter_cs = data;
2841                 break;
2842         case MSR_IA32_SYSENTER_EIP:
2843                 svm->sysenter_eip = data;
2844                 svm->vmcb->save.sysenter_eip = data;
2845                 break;
2846         case MSR_IA32_SYSENTER_ESP:
2847                 svm->sysenter_esp = data;
2848                 svm->vmcb->save.sysenter_esp = data;
2849                 break;
2850         case MSR_TSC_AUX:
2851                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2852                         return 1;
2853
2854                 /*
2855                  * This is rare, so we update the MSR here instead of using
2856                  * direct_access_msrs.  Doing that would require a rdmsr in
2857                  * svm_vcpu_put.
2858                  */
2859                 svm->tsc_aux = data;
2860                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2861                 break;
2862         case MSR_IA32_DEBUGCTLMSR:
2863                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2864                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2865                                     __func__, data);
2866                         break;
2867                 }
2868                 if (data & DEBUGCTL_RESERVED_BITS)
2869                         return 1;
2870
2871                 svm->vmcb->save.dbgctl = data;
2872                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2873                 if (data & (1ULL<<0))
2874                         svm_enable_lbrv(vcpu);
2875                 else
2876                         svm_disable_lbrv(vcpu);
2877                 break;
2878         case MSR_VM_HSAVE_PA:
2879                 svm->nested.hsave_msr = data;
2880                 break;
2881         case MSR_VM_CR:
2882                 return svm_set_vm_cr(vcpu, data);
2883         case MSR_VM_IGNNE:
2884                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2885                 break;
2886         case MSR_F10H_DECFG: {
2887                 struct kvm_msr_entry msr_entry;
2888
2889                 msr_entry.index = msr->index;
2890                 if (svm_get_msr_feature(&msr_entry))
2891                         return 1;
2892
2893                 /* Check the supported bits */
2894                 if (data & ~msr_entry.data)
2895                         return 1;
2896
2897                 /* Don't allow the guest to change a bit, #GP */
2898                 if (!msr->host_initiated && (data ^ msr_entry.data))
2899                         return 1;
2900
2901                 svm->msr_decfg = data;
2902                 break;
2903         }
2904         case MSR_IA32_APICBASE:
2905                 if (kvm_vcpu_apicv_active(vcpu))
2906                         avic_update_vapic_bar(to_svm(vcpu), data);
2907                 fallthrough;
2908         default:
2909                 return kvm_set_msr_common(vcpu, msr);
2910         }
2911         return 0;
2912 }
2913
2914 static int wrmsr_interception(struct vcpu_svm *svm)
2915 {
2916         return kvm_emulate_wrmsr(&svm->vcpu);
2917 }
2918
2919 static int msr_interception(struct vcpu_svm *svm)
2920 {
2921         if (svm->vmcb->control.exit_info_1)
2922                 return wrmsr_interception(svm);
2923         else
2924                 return rdmsr_interception(svm);
2925 }
2926
2927 static int interrupt_window_interception(struct vcpu_svm *svm)
2928 {
2929         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2930         svm_clear_vintr(svm);
2931
2932         /*
2933          * For AVIC, the only reason to end up here is ExtINTs.
2934          * In this case AVIC was temporarily disabled for
2935          * requesting the IRQ window and we have to re-enable it.
2936          */
2937         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2938
2939         ++svm->vcpu.stat.irq_window_exits;
2940         return 1;
2941 }
2942
2943 static int pause_interception(struct vcpu_svm *svm)
2944 {
2945         struct kvm_vcpu *vcpu = &svm->vcpu;
2946         bool in_kernel;
2947
2948         /*
2949          * CPL is not made available for an SEV-ES guest, therefore
2950          * vcpu->arch.preempted_in_kernel can never be true.  Just
2951          * set in_kernel to false as well.
2952          */
2953         in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
2954
2955         if (!kvm_pause_in_guest(vcpu->kvm))
2956                 grow_ple_window(vcpu);
2957
2958         kvm_vcpu_on_spin(vcpu, in_kernel);
2959         return 1;
2960 }
2961
2962 static int nop_interception(struct vcpu_svm *svm)
2963 {
2964         return kvm_skip_emulated_instruction(&(svm->vcpu));
2965 }
2966
2967 static int monitor_interception(struct vcpu_svm *svm)
2968 {
2969         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2970         return nop_interception(svm);
2971 }
2972
2973 static int mwait_interception(struct vcpu_svm *svm)
2974 {
2975         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2976         return nop_interception(svm);
2977 }
2978
2979 static int invpcid_interception(struct vcpu_svm *svm)
2980 {
2981         struct kvm_vcpu *vcpu = &svm->vcpu;
2982         unsigned long type;
2983         gva_t gva;
2984
2985         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2986                 kvm_queue_exception(vcpu, UD_VECTOR);
2987                 return 1;
2988         }
2989
2990         /*
2991          * For an INVPCID intercept:
2992          * EXITINFO1 provides the linear address of the memory operand.
2993          * EXITINFO2 provides the contents of the register operand.
2994          */
2995         type = svm->vmcb->control.exit_info_2;
2996         gva = svm->vmcb->control.exit_info_1;
2997
2998         if (type > 3) {
2999                 kvm_inject_gp(vcpu, 0);
3000                 return 1;
3001         }
3002
3003         return kvm_handle_invpcid(vcpu, type, gva);
3004 }
3005
3006 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3007         [SVM_EXIT_READ_CR0]                     = cr_interception,
3008         [SVM_EXIT_READ_CR3]                     = cr_interception,
3009         [SVM_EXIT_READ_CR4]                     = cr_interception,
3010         [SVM_EXIT_READ_CR8]                     = cr_interception,
3011         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3012         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3013         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3014         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3015         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3016         [SVM_EXIT_READ_DR0]                     = dr_interception,
3017         [SVM_EXIT_READ_DR1]                     = dr_interception,
3018         [SVM_EXIT_READ_DR2]                     = dr_interception,
3019         [SVM_EXIT_READ_DR3]                     = dr_interception,
3020         [SVM_EXIT_READ_DR4]                     = dr_interception,
3021         [SVM_EXIT_READ_DR5]                     = dr_interception,
3022         [SVM_EXIT_READ_DR6]                     = dr_interception,
3023         [SVM_EXIT_READ_DR7]                     = dr_interception,
3024         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3025         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3026         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3027         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3028         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3029         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3030         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3031         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3032         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3033         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3034         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3035         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3036         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3037         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3038         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3039         [SVM_EXIT_INTR]                         = intr_interception,
3040         [SVM_EXIT_NMI]                          = nmi_interception,
3041         [SVM_EXIT_SMI]                          = nop_on_interception,
3042         [SVM_EXIT_INIT]                         = nop_on_interception,
3043         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3044         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3045         [SVM_EXIT_CPUID]                        = cpuid_interception,
3046         [SVM_EXIT_IRET]                         = iret_interception,
3047         [SVM_EXIT_INVD]                         = invd_interception,
3048         [SVM_EXIT_PAUSE]                        = pause_interception,
3049         [SVM_EXIT_HLT]                          = halt_interception,
3050         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3051         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3052         [SVM_EXIT_IOIO]                         = io_interception,
3053         [SVM_EXIT_MSR]                          = msr_interception,
3054         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3055         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3056         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3057         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3058         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3059         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3060         [SVM_EXIT_STGI]                         = stgi_interception,
3061         [SVM_EXIT_CLGI]                         = clgi_interception,
3062         [SVM_EXIT_SKINIT]                       = skinit_interception,
3063         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
3064         [SVM_EXIT_MONITOR]                      = monitor_interception,
3065         [SVM_EXIT_MWAIT]                        = mwait_interception,
3066         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3067         [SVM_EXIT_RDPRU]                        = rdpru_interception,
3068         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3069         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3070         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3071         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3072         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3073         [SVM_EXIT_NPF]                          = npf_interception,
3074         [SVM_EXIT_RSM]                          = rsm_interception,
3075         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3076         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3077         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3078 };
3079
3080 static void dump_vmcb(struct kvm_vcpu *vcpu)
3081 {
3082         struct vcpu_svm *svm = to_svm(vcpu);
3083         struct vmcb_control_area *control = &svm->vmcb->control;
3084         struct vmcb_save_area *save = &svm->vmcb->save;
3085
3086         if (!dump_invalid_vmcb) {
3087                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3088                 return;
3089         }
3090
3091         pr_err("VMCB Control Area:\n");
3092         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3093         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3094         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3095         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3096         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3097         pr_err("%-20s%08x %08x\n", "intercepts:",
3098               control->intercepts[INTERCEPT_WORD3],
3099                control->intercepts[INTERCEPT_WORD4]);
3100         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3101         pr_err("%-20s%d\n", "pause filter threshold:",
3102                control->pause_filter_thresh);
3103         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3104         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3105         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3106         pr_err("%-20s%d\n", "asid:", control->asid);
3107         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3108         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3109         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3110         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3111         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3112         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3113         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3114         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3115         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3116         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3117         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3118         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3119         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3120         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3121         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3122         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3123         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3124         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3125         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3126         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3127         pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3128         pr_err("VMCB State Save Area:\n");
3129         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3130                "es:",
3131                save->es.selector, save->es.attrib,
3132                save->es.limit, save->es.base);
3133         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3134                "cs:",
3135                save->cs.selector, save->cs.attrib,
3136                save->cs.limit, save->cs.base);
3137         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3138                "ss:",
3139                save->ss.selector, save->ss.attrib,
3140                save->ss.limit, save->ss.base);
3141         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3142                "ds:",
3143                save->ds.selector, save->ds.attrib,
3144                save->ds.limit, save->ds.base);
3145         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3146                "fs:",
3147                save->fs.selector, save->fs.attrib,
3148                save->fs.limit, save->fs.base);
3149         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3150                "gs:",
3151                save->gs.selector, save->gs.attrib,
3152                save->gs.limit, save->gs.base);
3153         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3154                "gdtr:",
3155                save->gdtr.selector, save->gdtr.attrib,
3156                save->gdtr.limit, save->gdtr.base);
3157         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3158                "ldtr:",
3159                save->ldtr.selector, save->ldtr.attrib,
3160                save->ldtr.limit, save->ldtr.base);
3161         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3162                "idtr:",
3163                save->idtr.selector, save->idtr.attrib,
3164                save->idtr.limit, save->idtr.base);
3165         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3166                "tr:",
3167                save->tr.selector, save->tr.attrib,
3168                save->tr.limit, save->tr.base);
3169         pr_err("cpl:            %d                efer:         %016llx\n",
3170                 save->cpl, save->efer);
3171         pr_err("%-15s %016llx %-13s %016llx\n",
3172                "cr0:", save->cr0, "cr2:", save->cr2);
3173         pr_err("%-15s %016llx %-13s %016llx\n",
3174                "cr3:", save->cr3, "cr4:", save->cr4);
3175         pr_err("%-15s %016llx %-13s %016llx\n",
3176                "dr6:", save->dr6, "dr7:", save->dr7);
3177         pr_err("%-15s %016llx %-13s %016llx\n",
3178                "rip:", save->rip, "rflags:", save->rflags);
3179         pr_err("%-15s %016llx %-13s %016llx\n",
3180                "rsp:", save->rsp, "rax:", save->rax);
3181         pr_err("%-15s %016llx %-13s %016llx\n",
3182                "star:", save->star, "lstar:", save->lstar);
3183         pr_err("%-15s %016llx %-13s %016llx\n",
3184                "cstar:", save->cstar, "sfmask:", save->sfmask);
3185         pr_err("%-15s %016llx %-13s %016llx\n",
3186                "kernel_gs_base:", save->kernel_gs_base,
3187                "sysenter_cs:", save->sysenter_cs);
3188         pr_err("%-15s %016llx %-13s %016llx\n",
3189                "sysenter_esp:", save->sysenter_esp,
3190                "sysenter_eip:", save->sysenter_eip);
3191         pr_err("%-15s %016llx %-13s %016llx\n",
3192                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3193         pr_err("%-15s %016llx %-13s %016llx\n",
3194                "br_from:", save->br_from, "br_to:", save->br_to);
3195         pr_err("%-15s %016llx %-13s %016llx\n",
3196                "excp_from:", save->last_excp_from,
3197                "excp_to:", save->last_excp_to);
3198 }
3199
3200 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3201 {
3202         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3203             svm_exit_handlers[exit_code])
3204                 return 0;
3205
3206         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3207         dump_vmcb(vcpu);
3208         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3209         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3210         vcpu->run->internal.ndata = 2;
3211         vcpu->run->internal.data[0] = exit_code;
3212         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3213
3214         return -EINVAL;
3215 }
3216
3217 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code)
3218 {
3219         if (svm_handle_invalid_exit(&svm->vcpu, exit_code))
3220                 return 0;
3221
3222 #ifdef CONFIG_RETPOLINE
3223         if (exit_code == SVM_EXIT_MSR)
3224                 return msr_interception(svm);
3225         else if (exit_code == SVM_EXIT_VINTR)
3226                 return interrupt_window_interception(svm);
3227         else if (exit_code == SVM_EXIT_INTR)
3228                 return intr_interception(svm);
3229         else if (exit_code == SVM_EXIT_HLT)
3230                 return halt_interception(svm);
3231         else if (exit_code == SVM_EXIT_NPF)
3232                 return npf_interception(svm);
3233 #endif
3234         return svm_exit_handlers[exit_code](svm);
3235 }
3236
3237 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3238                               u32 *intr_info, u32 *error_code)
3239 {
3240         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3241
3242         *info1 = control->exit_info_1;
3243         *info2 = control->exit_info_2;
3244         *intr_info = control->exit_int_info;
3245         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3246             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3247                 *error_code = control->exit_int_info_err;
3248         else
3249                 *error_code = 0;
3250 }
3251
3252 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3253 {
3254         struct vcpu_svm *svm = to_svm(vcpu);
3255         struct kvm_run *kvm_run = vcpu->run;
3256         u32 exit_code = svm->vmcb->control.exit_code;
3257
3258         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3259
3260         /* SEV-ES guests must use the CR write traps to track CR registers. */
3261         if (!sev_es_guest(vcpu->kvm)) {
3262                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3263                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3264                 if (npt_enabled)
3265                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3266         }
3267
3268         if (is_guest_mode(vcpu)) {
3269                 int vmexit;
3270
3271                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3272
3273                 vmexit = nested_svm_exit_special(svm);
3274
3275                 if (vmexit == NESTED_EXIT_CONTINUE)
3276                         vmexit = nested_svm_exit_handled(svm);
3277
3278                 if (vmexit == NESTED_EXIT_DONE)
3279                         return 1;
3280         }
3281
3282         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3283                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3284                 kvm_run->fail_entry.hardware_entry_failure_reason
3285                         = svm->vmcb->control.exit_code;
3286                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3287                 dump_vmcb(vcpu);
3288                 return 0;
3289         }
3290
3291         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3292             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3293             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3294             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3295                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3296                        "exit_code 0x%x\n",
3297                        __func__, svm->vmcb->control.exit_int_info,
3298                        exit_code);
3299
3300         if (exit_fastpath != EXIT_FASTPATH_NONE)
3301                 return 1;
3302
3303         return svm_invoke_exit_handler(svm, exit_code);
3304 }
3305
3306 static void reload_tss(struct kvm_vcpu *vcpu)
3307 {
3308         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3309
3310         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3311         load_TR_desc();
3312 }
3313
3314 static void pre_svm_run(struct vcpu_svm *svm)
3315 {
3316         struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3317
3318         if (sev_guest(svm->vcpu.kvm))
3319                 return pre_sev_run(svm, svm->vcpu.cpu);
3320
3321         /* FIXME: handle wraparound of asid_generation */
3322         if (svm->asid_generation != sd->asid_generation)
3323                 new_asid(svm, sd);
3324 }
3325
3326 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3327 {
3328         struct vcpu_svm *svm = to_svm(vcpu);
3329
3330         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3331         vcpu->arch.hflags |= HF_NMI_MASK;
3332         if (!sev_es_guest(svm->vcpu.kvm))
3333                 svm_set_intercept(svm, INTERCEPT_IRET);
3334         ++vcpu->stat.nmi_injections;
3335 }
3336
3337 static void svm_set_irq(struct kvm_vcpu *vcpu)
3338 {
3339         struct vcpu_svm *svm = to_svm(vcpu);
3340
3341         BUG_ON(!(gif_set(svm)));
3342
3343         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3344         ++vcpu->stat.irq_injections;
3345
3346         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3347                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3348 }
3349
3350 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3351 {
3352         struct vcpu_svm *svm = to_svm(vcpu);
3353
3354         /*
3355          * SEV-ES guests must always keep the CR intercepts cleared. CR
3356          * tracking is done using the CR write traps.
3357          */
3358         if (sev_es_guest(vcpu->kvm))
3359                 return;
3360
3361         if (nested_svm_virtualize_tpr(vcpu))
3362                 return;
3363
3364         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3365
3366         if (irr == -1)
3367                 return;
3368
3369         if (tpr >= irr)
3370                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3371 }
3372
3373 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3374 {
3375         struct vcpu_svm *svm = to_svm(vcpu);
3376         struct vmcb *vmcb = svm->vmcb;
3377         bool ret;
3378
3379         if (!gif_set(svm))
3380                 return true;
3381
3382         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3383                 return false;
3384
3385         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3386               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3387
3388         return ret;
3389 }
3390
3391 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3392 {
3393         struct vcpu_svm *svm = to_svm(vcpu);
3394         if (svm->nested.nested_run_pending)
3395                 return -EBUSY;
3396
3397         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3398         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3399                 return -EBUSY;
3400
3401         return !svm_nmi_blocked(vcpu);
3402 }
3403
3404 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3405 {
3406         struct vcpu_svm *svm = to_svm(vcpu);
3407
3408         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3409 }
3410
3411 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3412 {
3413         struct vcpu_svm *svm = to_svm(vcpu);
3414
3415         if (masked) {
3416                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3417                 if (!sev_es_guest(svm->vcpu.kvm))
3418                         svm_set_intercept(svm, INTERCEPT_IRET);
3419         } else {
3420                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3421                 if (!sev_es_guest(svm->vcpu.kvm))
3422                         svm_clr_intercept(svm, INTERCEPT_IRET);
3423         }
3424 }
3425
3426 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3427 {
3428         struct vcpu_svm *svm = to_svm(vcpu);
3429         struct vmcb *vmcb = svm->vmcb;
3430
3431         if (!gif_set(svm))
3432                 return true;
3433
3434         if (sev_es_guest(svm->vcpu.kvm)) {
3435                 /*
3436                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3437                  * bit to determine the state of the IF flag.
3438                  */
3439                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3440                         return true;
3441         } else if (is_guest_mode(vcpu)) {
3442                 /* As long as interrupts are being delivered...  */
3443                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3444                     ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3445                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3446                         return true;
3447
3448                 /* ... vmexits aren't blocked by the interrupt shadow  */
3449                 if (nested_exit_on_intr(svm))
3450                         return false;
3451         } else {
3452                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3453                         return true;
3454         }
3455
3456         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3457 }
3458
3459 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3460 {
3461         struct vcpu_svm *svm = to_svm(vcpu);
3462         if (svm->nested.nested_run_pending)
3463                 return -EBUSY;
3464
3465         /*
3466          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3467          * e.g. if the IRQ arrived asynchronously after checking nested events.
3468          */
3469         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3470                 return -EBUSY;
3471
3472         return !svm_interrupt_blocked(vcpu);
3473 }
3474
3475 static void enable_irq_window(struct kvm_vcpu *vcpu)
3476 {
3477         struct vcpu_svm *svm = to_svm(vcpu);
3478
3479         /*
3480          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3481          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3482          * get that intercept, this function will be called again though and
3483          * we'll get the vintr intercept. However, if the vGIF feature is
3484          * enabled, the STGI interception will not occur. Enable the irq
3485          * window under the assumption that the hardware will set the GIF.
3486          */
3487         if (vgif_enabled(svm) || gif_set(svm)) {
3488                 /*
3489                  * IRQ window is not needed when AVIC is enabled,
3490                  * unless we have pending ExtINT since it cannot be injected
3491                  * via AVIC. In such case, we need to temporarily disable AVIC,
3492                  * and fallback to injecting IRQ via V_IRQ.
3493                  */
3494                 svm_toggle_avic_for_irq_window(vcpu, false);
3495                 svm_set_vintr(svm);
3496         }
3497 }
3498
3499 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3500 {
3501         struct vcpu_svm *svm = to_svm(vcpu);
3502
3503         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3504             == HF_NMI_MASK)
3505                 return; /* IRET will cause a vm exit */
3506
3507         if (!gif_set(svm)) {
3508                 if (vgif_enabled(svm))
3509                         svm_set_intercept(svm, INTERCEPT_STGI);
3510                 return; /* STGI will cause a vm exit */
3511         }
3512
3513         /*
3514          * Something prevents NMI from been injected. Single step over possible
3515          * problem (IRET or exception injection or interrupt shadow)
3516          */
3517         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3518         svm->nmi_singlestep = true;
3519         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3520 }
3521
3522 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3523 {
3524         return 0;
3525 }
3526
3527 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3528 {
3529         return 0;
3530 }
3531
3532 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3533 {
3534         struct vcpu_svm *svm = to_svm(vcpu);
3535
3536         /*
3537          * Flush only the current ASID even if the TLB flush was invoked via
3538          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3539          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3540          * unconditionally does a TLB flush on both nested VM-Enter and nested
3541          * VM-Exit (via kvm_mmu_reset_context()).
3542          */
3543         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3544                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3545         else
3546                 svm->asid_generation--;
3547 }
3548
3549 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3550 {
3551         struct vcpu_svm *svm = to_svm(vcpu);
3552
3553         invlpga(gva, svm->vmcb->control.asid);
3554 }
3555
3556 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3557 {
3558 }
3559
3560 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3561 {
3562         struct vcpu_svm *svm = to_svm(vcpu);
3563
3564         if (nested_svm_virtualize_tpr(vcpu))
3565                 return;
3566
3567         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3568                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3569                 kvm_set_cr8(vcpu, cr8);
3570         }
3571 }
3572
3573 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3574 {
3575         struct vcpu_svm *svm = to_svm(vcpu);
3576         u64 cr8;
3577
3578         if (nested_svm_virtualize_tpr(vcpu) ||
3579             kvm_vcpu_apicv_active(vcpu))
3580                 return;
3581
3582         cr8 = kvm_get_cr8(vcpu);
3583         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3584         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3585 }
3586
3587 static void svm_complete_interrupts(struct vcpu_svm *svm)
3588 {
3589         u8 vector;
3590         int type;
3591         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3592         unsigned int3_injected = svm->int3_injected;
3593
3594         svm->int3_injected = 0;
3595
3596         /*
3597          * If we've made progress since setting HF_IRET_MASK, we've
3598          * executed an IRET and can allow NMI injection.
3599          */
3600         if ((svm->vcpu.arch.hflags & HF_IRET_MASK) &&
3601             (sev_es_guest(svm->vcpu.kvm) ||
3602              kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip)) {
3603                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3604                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3605         }
3606
3607         svm->vcpu.arch.nmi_injected = false;
3608         kvm_clear_exception_queue(&svm->vcpu);
3609         kvm_clear_interrupt_queue(&svm->vcpu);
3610
3611         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3612                 return;
3613
3614         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3615
3616         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3617         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3618
3619         switch (type) {
3620         case SVM_EXITINTINFO_TYPE_NMI:
3621                 svm->vcpu.arch.nmi_injected = true;
3622                 break;
3623         case SVM_EXITINTINFO_TYPE_EXEPT:
3624                 /*
3625                  * Never re-inject a #VC exception.
3626                  */
3627                 if (vector == X86_TRAP_VC)
3628                         break;
3629
3630                 /*
3631                  * In case of software exceptions, do not reinject the vector,
3632                  * but re-execute the instruction instead. Rewind RIP first
3633                  * if we emulated INT3 before.
3634                  */
3635                 if (kvm_exception_is_soft(vector)) {
3636                         if (vector == BP_VECTOR && int3_injected &&
3637                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3638                                 kvm_rip_write(&svm->vcpu,
3639                                               kvm_rip_read(&svm->vcpu) -
3640                                               int3_injected);
3641                         break;
3642                 }
3643                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3644                         u32 err = svm->vmcb->control.exit_int_info_err;
3645                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3646
3647                 } else
3648                         kvm_requeue_exception(&svm->vcpu, vector);
3649                 break;
3650         case SVM_EXITINTINFO_TYPE_INTR:
3651                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3652                 break;
3653         default:
3654                 break;
3655         }
3656 }
3657
3658 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3659 {
3660         struct vcpu_svm *svm = to_svm(vcpu);
3661         struct vmcb_control_area *control = &svm->vmcb->control;
3662
3663         control->exit_int_info = control->event_inj;
3664         control->exit_int_info_err = control->event_inj_err;
3665         control->event_inj = 0;
3666         svm_complete_interrupts(svm);
3667 }
3668
3669 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3670 {
3671         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3672             to_svm(vcpu)->vmcb->control.exit_info_1)
3673                 return handle_fastpath_set_msr_irqoff(vcpu);
3674
3675         return EXIT_FASTPATH_NONE;
3676 }
3677
3678 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3679
3680 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3681                                         struct vcpu_svm *svm)
3682 {
3683         /*
3684          * VMENTER enables interrupts (host state), but the kernel state is
3685          * interrupts disabled when this is invoked. Also tell RCU about
3686          * it. This is the same logic as for exit_to_user_mode().
3687          *
3688          * This ensures that e.g. latency analysis on the host observes
3689          * guest mode as interrupt enabled.
3690          *
3691          * guest_enter_irqoff() informs context tracking about the
3692          * transition to guest mode and if enabled adjusts RCU state
3693          * accordingly.
3694          */
3695         instrumentation_begin();
3696         trace_hardirqs_on_prepare();
3697         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3698         instrumentation_end();
3699
3700         guest_enter_irqoff();
3701         lockdep_hardirqs_on(CALLER_ADDR0);
3702
3703         if (sev_es_guest(svm->vcpu.kvm)) {
3704                 __svm_sev_es_vcpu_run(svm->vmcb_pa);
3705         } else {
3706                 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3707
3708 #ifdef CONFIG_X86_64
3709                 native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3710 #else
3711                 loadsegment(fs, svm->host.fs);
3712 #ifndef CONFIG_X86_32_LAZY_GS
3713                 loadsegment(gs, svm->host.gs);
3714 #endif
3715 #endif
3716         }
3717
3718         /*
3719          * VMEXIT disables interrupts (host state), but tracing and lockdep
3720          * have them in state 'on' as recorded before entering guest mode.
3721          * Same as enter_from_user_mode().
3722          *
3723          * guest_exit_irqoff() restores host context and reinstates RCU if
3724          * enabled and required.
3725          *
3726          * This needs to be done before the below as native_read_msr()
3727          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3728          * into world and some more.
3729          */
3730         lockdep_hardirqs_off(CALLER_ADDR0);
3731         guest_exit_irqoff();
3732
3733         instrumentation_begin();
3734         trace_hardirqs_off_finish();
3735         instrumentation_end();
3736 }
3737
3738 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3739 {
3740         struct vcpu_svm *svm = to_svm(vcpu);
3741
3742         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3743         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3744         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3745
3746         /*
3747          * Disable singlestep if we're injecting an interrupt/exception.
3748          * We don't want our modified rflags to be pushed on the stack where
3749          * we might not be able to easily reset them if we disabled NMI
3750          * singlestep later.
3751          */
3752         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3753                 /*
3754                  * Event injection happens before external interrupts cause a
3755                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3756                  * is enough to force an immediate vmexit.
3757                  */
3758                 disable_nmi_singlestep(svm);
3759                 smp_send_reschedule(vcpu->cpu);
3760         }
3761
3762         pre_svm_run(svm);
3763
3764         sync_lapic_to_cr8(vcpu);
3765
3766         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3767                 svm->vmcb->control.asid = svm->asid;
3768                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3769         }
3770         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3771
3772         /*
3773          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3774          * of a #DB.
3775          */
3776         if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3777                 svm_set_dr6(svm, vcpu->arch.dr6);
3778         else
3779                 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3780
3781         clgi();
3782         kvm_load_guest_xsave_state(vcpu);
3783
3784         kvm_wait_lapic_expire(vcpu);
3785
3786         /*
3787          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3788          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3789          * is no need to worry about the conditional branch over the wrmsr
3790          * being speculatively taken.
3791          */
3792         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3793
3794         svm_vcpu_enter_exit(vcpu, svm);
3795
3796         /*
3797          * We do not use IBRS in the kernel. If this vCPU has used the
3798          * SPEC_CTRL MSR it may have left it on; save the value and
3799          * turn it off. This is much more efficient than blindly adding
3800          * it to the atomic save/restore list. Especially as the former
3801          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3802          *
3803          * For non-nested case:
3804          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3805          * save it.
3806          *
3807          * For nested case:
3808          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3809          * save it.
3810          */
3811         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3812                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3813
3814         if (!sev_es_guest(svm->vcpu.kvm))
3815                 reload_tss(vcpu);
3816
3817         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3818
3819         if (!sev_es_guest(svm->vcpu.kvm)) {
3820                 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3821                 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3822                 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3823                 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3824         }
3825
3826         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3827                 kvm_before_interrupt(&svm->vcpu);
3828
3829         kvm_load_host_xsave_state(vcpu);
3830         stgi();
3831
3832         /* Any pending NMI will happen here */
3833
3834         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3835                 kvm_after_interrupt(&svm->vcpu);
3836
3837         sync_cr8_to_lapic(vcpu);
3838
3839         svm->next_rip = 0;
3840         if (is_guest_mode(&svm->vcpu)) {
3841                 sync_nested_vmcb_control(svm);
3842                 svm->nested.nested_run_pending = 0;
3843         }
3844
3845         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3846         vmcb_mark_all_clean(svm->vmcb);
3847
3848         /* if exit due to PF check for async PF */
3849         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3850                 svm->vcpu.arch.apf.host_apf_flags =
3851                         kvm_read_and_reset_apf_flags();
3852
3853         if (npt_enabled) {
3854                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3855                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3856         }
3857
3858         /*
3859          * We need to handle MC intercepts here before the vcpu has a chance to
3860          * change the physical cpu
3861          */
3862         if (unlikely(svm->vmcb->control.exit_code ==
3863                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3864                 svm_handle_mce(svm);
3865
3866         svm_complete_interrupts(svm);
3867
3868         if (is_guest_mode(vcpu))
3869                 return EXIT_FASTPATH_NONE;
3870
3871         return svm_exit_handlers_fastpath(vcpu);
3872 }
3873
3874 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3875                              int root_level)
3876 {
3877         struct vcpu_svm *svm = to_svm(vcpu);
3878         unsigned long cr3;
3879
3880         cr3 = __sme_set(root);
3881         if (npt_enabled) {
3882                 svm->vmcb->control.nested_cr3 = cr3;
3883                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3884
3885                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3886                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3887                         return;
3888                 cr3 = vcpu->arch.cr3;
3889         }
3890
3891         svm->vmcb->save.cr3 = cr3;
3892         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3893 }
3894
3895 static int is_disabled(void)
3896 {
3897         u64 vm_cr;
3898
3899         rdmsrl(MSR_VM_CR, vm_cr);
3900         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3901                 return 1;
3902
3903         return 0;
3904 }
3905
3906 static void
3907 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3908 {
3909         /*
3910          * Patch in the VMMCALL instruction:
3911          */
3912         hypercall[0] = 0x0f;
3913         hypercall[1] = 0x01;
3914         hypercall[2] = 0xd9;
3915 }
3916
3917 static int __init svm_check_processor_compat(void)
3918 {
3919         return 0;
3920 }
3921
3922 static bool svm_cpu_has_accelerated_tpr(void)
3923 {
3924         return false;
3925 }
3926
3927 /*
3928  * The kvm parameter can be NULL (module initialization, or invocation before
3929  * VM creation). Be sure to check the kvm parameter before using it.
3930  */
3931 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3932 {
3933         switch (index) {
3934         case MSR_IA32_MCG_EXT_CTL:
3935         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3936                 return false;
3937         case MSR_IA32_SMBASE:
3938                 /* SEV-ES guests do not support SMM, so report false */
3939                 if (kvm && sev_es_guest(kvm))
3940                         return false;
3941                 break;
3942         default:
3943                 break;
3944         }
3945
3946         return true;
3947 }
3948
3949 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3950 {
3951         return 0;
3952 }
3953
3954 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3955 {
3956         struct vcpu_svm *svm = to_svm(vcpu);
3957         struct kvm_cpuid_entry2 *best;
3958
3959         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3960                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3961                                     boot_cpu_has(X86_FEATURE_XSAVES);
3962
3963         /* Update nrips enabled cache */
3964         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3965                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3966
3967         /* Check again if INVPCID interception if required */
3968         svm_check_invpcid(svm);
3969
3970         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
3971         if (sev_guest(vcpu->kvm)) {
3972                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
3973                 if (best)
3974                         vcpu->arch.cr3_lm_rsvd_bits &= ~(1UL << (best->ebx & 0x3f));
3975         }
3976
3977         if (!kvm_vcpu_apicv_active(vcpu))
3978                 return;
3979
3980         /*
3981          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3982          * is exposed to the guest, disable AVIC.
3983          */
3984         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3985                 kvm_request_apicv_update(vcpu->kvm, false,
3986                                          APICV_INHIBIT_REASON_X2APIC);
3987
3988         /*
3989          * Currently, AVIC does not work with nested virtualization.
3990          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3991          */
3992         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3993                 kvm_request_apicv_update(vcpu->kvm, false,
3994                                          APICV_INHIBIT_REASON_NESTED);
3995 }
3996
3997 static bool svm_has_wbinvd_exit(void)
3998 {
3999         return true;
4000 }
4001
4002 #define PRE_EX(exit)  { .exit_code = (exit), \
4003                         .stage = X86_ICPT_PRE_EXCEPT, }
4004 #define POST_EX(exit) { .exit_code = (exit), \
4005                         .stage = X86_ICPT_POST_EXCEPT, }
4006 #define POST_MEM(exit) { .exit_code = (exit), \
4007                         .stage = X86_ICPT_POST_MEMACCESS, }
4008
4009 static const struct __x86_intercept {
4010         u32 exit_code;
4011         enum x86_intercept_stage stage;
4012 } x86_intercept_map[] = {
4013         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4014         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4015         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4016         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4017         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4018         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4019         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4020         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4021         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4022         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4023         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4024         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4025         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4026         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4027         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4028         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4029         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4030         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4031         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4032         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4033         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4034         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4035         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4036         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4037         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4038         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4039         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4040         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4041         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4042         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4043         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4044         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4045         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4046         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4047         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4048         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4049         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4050         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4051         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4052         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4053         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4054         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4055         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4056         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4057         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4058         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4059         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4060 };
4061
4062 #undef PRE_EX
4063 #undef POST_EX
4064 #undef POST_MEM
4065
4066 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4067                                struct x86_instruction_info *info,
4068                                enum x86_intercept_stage stage,
4069                                struct x86_exception *exception)
4070 {
4071         struct vcpu_svm *svm = to_svm(vcpu);
4072         int vmexit, ret = X86EMUL_CONTINUE;
4073         struct __x86_intercept icpt_info;
4074         struct vmcb *vmcb = svm->vmcb;
4075
4076         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4077                 goto out;
4078
4079         icpt_info = x86_intercept_map[info->intercept];
4080
4081         if (stage != icpt_info.stage)
4082                 goto out;
4083
4084         switch (icpt_info.exit_code) {
4085         case SVM_EXIT_READ_CR0:
4086                 if (info->intercept == x86_intercept_cr_read)
4087                         icpt_info.exit_code += info->modrm_reg;
4088                 break;
4089         case SVM_EXIT_WRITE_CR0: {
4090                 unsigned long cr0, val;
4091
4092                 if (info->intercept == x86_intercept_cr_write)
4093                         icpt_info.exit_code += info->modrm_reg;
4094
4095                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4096                     info->intercept == x86_intercept_clts)
4097                         break;
4098
4099                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4100                                         INTERCEPT_SELECTIVE_CR0)))
4101                         break;
4102
4103                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4104                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4105
4106                 if (info->intercept == x86_intercept_lmsw) {
4107                         cr0 &= 0xfUL;
4108                         val &= 0xfUL;
4109                         /* lmsw can't clear PE - catch this here */
4110                         if (cr0 & X86_CR0_PE)
4111                                 val |= X86_CR0_PE;
4112                 }
4113
4114                 if (cr0 ^ val)
4115                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4116
4117                 break;
4118         }
4119         case SVM_EXIT_READ_DR0:
4120         case SVM_EXIT_WRITE_DR0:
4121                 icpt_info.exit_code += info->modrm_reg;
4122                 break;
4123         case SVM_EXIT_MSR:
4124                 if (info->intercept == x86_intercept_wrmsr)
4125                         vmcb->control.exit_info_1 = 1;
4126                 else
4127                         vmcb->control.exit_info_1 = 0;
4128                 break;
4129         case SVM_EXIT_PAUSE:
4130                 /*
4131                  * We get this for NOP only, but pause
4132                  * is rep not, check this here
4133                  */
4134                 if (info->rep_prefix != REPE_PREFIX)
4135                         goto out;
4136                 break;
4137         case SVM_EXIT_IOIO: {
4138                 u64 exit_info;
4139                 u32 bytes;
4140
4141                 if (info->intercept == x86_intercept_in ||
4142                     info->intercept == x86_intercept_ins) {
4143                         exit_info = ((info->src_val & 0xffff) << 16) |
4144                                 SVM_IOIO_TYPE_MASK;
4145                         bytes = info->dst_bytes;
4146                 } else {
4147                         exit_info = (info->dst_val & 0xffff) << 16;
4148                         bytes = info->src_bytes;
4149                 }
4150
4151                 if (info->intercept == x86_intercept_outs ||
4152                     info->intercept == x86_intercept_ins)
4153                         exit_info |= SVM_IOIO_STR_MASK;
4154
4155                 if (info->rep_prefix)
4156                         exit_info |= SVM_IOIO_REP_MASK;
4157
4158                 bytes = min(bytes, 4u);
4159
4160                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4161
4162                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4163
4164                 vmcb->control.exit_info_1 = exit_info;
4165                 vmcb->control.exit_info_2 = info->next_rip;
4166
4167                 break;
4168         }
4169         default:
4170                 break;
4171         }
4172
4173         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4174         if (static_cpu_has(X86_FEATURE_NRIPS))
4175                 vmcb->control.next_rip  = info->next_rip;
4176         vmcb->control.exit_code = icpt_info.exit_code;
4177         vmexit = nested_svm_exit_handled(svm);
4178
4179         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4180                                            : X86EMUL_CONTINUE;
4181
4182 out:
4183         return ret;
4184 }
4185
4186 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4187 {
4188 }
4189
4190 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4191 {
4192         if (!kvm_pause_in_guest(vcpu->kvm))
4193                 shrink_ple_window(vcpu);
4194 }
4195
4196 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4197 {
4198         /* [63:9] are reserved. */
4199         vcpu->arch.mcg_cap &= 0x1ff;
4200 }
4201
4202 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4203 {
4204         struct vcpu_svm *svm = to_svm(vcpu);
4205
4206         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4207         if (!gif_set(svm))
4208                 return true;
4209
4210         return is_smm(vcpu);
4211 }
4212
4213 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4214 {
4215         struct vcpu_svm *svm = to_svm(vcpu);
4216         if (svm->nested.nested_run_pending)
4217                 return -EBUSY;
4218
4219         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4220         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4221                 return -EBUSY;
4222
4223         return !svm_smi_blocked(vcpu);
4224 }
4225
4226 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4227 {
4228         struct vcpu_svm *svm = to_svm(vcpu);
4229         int ret;
4230
4231         if (is_guest_mode(vcpu)) {
4232                 /* FED8h - SVM Guest */
4233                 put_smstate(u64, smstate, 0x7ed8, 1);
4234                 /* FEE0h - SVM Guest VMCB Physical Address */
4235                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4236
4237                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4238                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4239                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4240
4241                 ret = nested_svm_vmexit(svm);
4242                 if (ret)
4243                         return ret;
4244         }
4245         return 0;
4246 }
4247
4248 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4249 {
4250         struct vcpu_svm *svm = to_svm(vcpu);
4251         struct kvm_host_map map;
4252         int ret = 0;
4253
4254         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4255                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4256                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4257                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4258
4259                 if (guest) {
4260                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4261                                 return 1;
4262
4263                         if (!(saved_efer & EFER_SVME))
4264                                 return 1;
4265
4266                         if (kvm_vcpu_map(&svm->vcpu,
4267                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4268                                 return 1;
4269
4270                         if (svm_allocate_nested(svm))
4271                                 return 1;
4272
4273                         ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4274                         kvm_vcpu_unmap(&svm->vcpu, &map, true);
4275                 }
4276         }
4277
4278         return ret;
4279 }
4280
4281 static void enable_smi_window(struct kvm_vcpu *vcpu)
4282 {
4283         struct vcpu_svm *svm = to_svm(vcpu);
4284
4285         if (!gif_set(svm)) {
4286                 if (vgif_enabled(svm))
4287                         svm_set_intercept(svm, INTERCEPT_STGI);
4288                 /* STGI will cause a vm exit */
4289         } else {
4290                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4291         }
4292 }
4293
4294 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4295 {
4296         bool smep, smap, is_user;
4297         unsigned long cr4;
4298
4299         /*
4300          * When the guest is an SEV-ES guest, emulation is not possible.
4301          */
4302         if (sev_es_guest(vcpu->kvm))
4303                 return false;
4304
4305         /*
4306          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4307          *
4308          * Errata:
4309          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4310          * possible that CPU microcode implementing DecodeAssist will fail
4311          * to read bytes of instruction which caused #NPF. In this case,
4312          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4313          * return 0 instead of the correct guest instruction bytes.
4314          *
4315          * This happens because CPU microcode reading instruction bytes
4316          * uses a special opcode which attempts to read data using CPL=0
4317          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4318          * fault, it gives up and returns no instruction bytes.
4319          *
4320          * Detection:
4321          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4322          * returned 0 in GuestIntrBytes field of the VMCB.
4323          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4324          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4325          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4326          * a SMEP fault instead of #NPF).
4327          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4328          * As most guests enable SMAP if they have also enabled SMEP, use above
4329          * logic in order to attempt minimize false-positive of detecting errata
4330          * while still preserving all cases semantic correctness.
4331          *
4332          * Workaround:
4333          * To determine what instruction the guest was executing, the hypervisor
4334          * will have to decode the instruction at the instruction pointer.
4335          *
4336          * In non SEV guest, hypervisor will be able to read the guest
4337          * memory to decode the instruction pointer when insn_len is zero
4338          * so we return true to indicate that decoding is possible.
4339          *
4340          * But in the SEV guest, the guest memory is encrypted with the
4341          * guest specific key and hypervisor will not be able to decode the
4342          * instruction pointer so we will not able to workaround it. Lets
4343          * print the error and request to kill the guest.
4344          */
4345         if (likely(!insn || insn_len))
4346                 return true;
4347
4348         /*
4349          * If RIP is invalid, go ahead with emulation which will cause an
4350          * internal error exit.
4351          */
4352         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4353                 return true;
4354
4355         cr4 = kvm_read_cr4(vcpu);
4356         smep = cr4 & X86_CR4_SMEP;
4357         smap = cr4 & X86_CR4_SMAP;
4358         is_user = svm_get_cpl(vcpu) == 3;
4359         if (smap && (!smep || is_user)) {
4360                 if (!sev_guest(vcpu->kvm))
4361                         return true;
4362
4363                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4364                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4365         }
4366
4367         return false;
4368 }
4369
4370 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4371 {
4372         struct vcpu_svm *svm = to_svm(vcpu);
4373
4374         /*
4375          * TODO: Last condition latch INIT signals on vCPU when
4376          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4377          * To properly emulate the INIT intercept,
4378          * svm_check_nested_events() should call nested_svm_vmexit()
4379          * if an INIT signal is pending.
4380          */
4381         return !gif_set(svm) ||
4382                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4383 }
4384
4385 static void svm_vm_destroy(struct kvm *kvm)
4386 {
4387         avic_vm_destroy(kvm);
4388         sev_vm_destroy(kvm);
4389 }
4390
4391 static int svm_vm_init(struct kvm *kvm)
4392 {
4393         if (!pause_filter_count || !pause_filter_thresh)
4394                 kvm->arch.pause_in_guest = true;
4395
4396         if (avic) {
4397                 int ret = avic_vm_init(kvm);
4398                 if (ret)
4399                         return ret;
4400         }
4401
4402         kvm_apicv_init(kvm, avic);
4403         return 0;
4404 }
4405
4406 static struct kvm_x86_ops svm_x86_ops __initdata = {
4407         .hardware_unsetup = svm_hardware_teardown,
4408         .hardware_enable = svm_hardware_enable,
4409         .hardware_disable = svm_hardware_disable,
4410         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4411         .has_emulated_msr = svm_has_emulated_msr,
4412
4413         .vcpu_create = svm_create_vcpu,
4414         .vcpu_free = svm_free_vcpu,
4415         .vcpu_reset = svm_vcpu_reset,
4416
4417         .vm_size = sizeof(struct kvm_svm),
4418         .vm_init = svm_vm_init,
4419         .vm_destroy = svm_vm_destroy,
4420
4421         .prepare_guest_switch = svm_prepare_guest_switch,
4422         .vcpu_load = svm_vcpu_load,
4423         .vcpu_put = svm_vcpu_put,
4424         .vcpu_blocking = svm_vcpu_blocking,
4425         .vcpu_unblocking = svm_vcpu_unblocking,
4426
4427         .update_exception_bitmap = update_exception_bitmap,
4428         .get_msr_feature = svm_get_msr_feature,
4429         .get_msr = svm_get_msr,
4430         .set_msr = svm_set_msr,
4431         .get_segment_base = svm_get_segment_base,
4432         .get_segment = svm_get_segment,
4433         .set_segment = svm_set_segment,
4434         .get_cpl = svm_get_cpl,
4435         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4436         .set_cr0 = svm_set_cr0,
4437         .is_valid_cr4 = svm_is_valid_cr4,
4438         .set_cr4 = svm_set_cr4,
4439         .set_efer = svm_set_efer,
4440         .get_idt = svm_get_idt,
4441         .set_idt = svm_set_idt,
4442         .get_gdt = svm_get_gdt,
4443         .set_gdt = svm_set_gdt,
4444         .set_dr7 = svm_set_dr7,
4445         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4446         .cache_reg = svm_cache_reg,
4447         .get_rflags = svm_get_rflags,
4448         .set_rflags = svm_set_rflags,
4449
4450         .tlb_flush_all = svm_flush_tlb,
4451         .tlb_flush_current = svm_flush_tlb,
4452         .tlb_flush_gva = svm_flush_tlb_gva,
4453         .tlb_flush_guest = svm_flush_tlb,
4454
4455         .run = svm_vcpu_run,
4456         .handle_exit = handle_exit,
4457         .skip_emulated_instruction = skip_emulated_instruction,
4458         .update_emulated_instruction = NULL,
4459         .set_interrupt_shadow = svm_set_interrupt_shadow,
4460         .get_interrupt_shadow = svm_get_interrupt_shadow,
4461         .patch_hypercall = svm_patch_hypercall,
4462         .set_irq = svm_set_irq,
4463         .set_nmi = svm_inject_nmi,
4464         .queue_exception = svm_queue_exception,
4465         .cancel_injection = svm_cancel_injection,
4466         .interrupt_allowed = svm_interrupt_allowed,
4467         .nmi_allowed = svm_nmi_allowed,
4468         .get_nmi_mask = svm_get_nmi_mask,
4469         .set_nmi_mask = svm_set_nmi_mask,
4470         .enable_nmi_window = enable_nmi_window,
4471         .enable_irq_window = enable_irq_window,
4472         .update_cr8_intercept = update_cr8_intercept,
4473         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4474         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4475         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4476         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4477         .load_eoi_exitmap = svm_load_eoi_exitmap,
4478         .hwapic_irr_update = svm_hwapic_irr_update,
4479         .hwapic_isr_update = svm_hwapic_isr_update,
4480         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4481         .apicv_post_state_restore = avic_post_state_restore,
4482
4483         .set_tss_addr = svm_set_tss_addr,
4484         .set_identity_map_addr = svm_set_identity_map_addr,
4485         .get_mt_mask = svm_get_mt_mask,
4486
4487         .get_exit_info = svm_get_exit_info,
4488
4489         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4490
4491         .has_wbinvd_exit = svm_has_wbinvd_exit,
4492
4493         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4494
4495         .load_mmu_pgd = svm_load_mmu_pgd,
4496
4497         .check_intercept = svm_check_intercept,
4498         .handle_exit_irqoff = svm_handle_exit_irqoff,
4499
4500         .request_immediate_exit = __kvm_request_immediate_exit,
4501
4502         .sched_in = svm_sched_in,
4503
4504         .pmu_ops = &amd_pmu_ops,
4505         .nested_ops = &svm_nested_ops,
4506
4507         .deliver_posted_interrupt = svm_deliver_avic_intr,
4508         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4509         .update_pi_irte = svm_update_pi_irte,
4510         .setup_mce = svm_setup_mce,
4511
4512         .smi_allowed = svm_smi_allowed,
4513         .pre_enter_smm = svm_pre_enter_smm,
4514         .pre_leave_smm = svm_pre_leave_smm,
4515         .enable_smi_window = enable_smi_window,
4516
4517         .mem_enc_op = svm_mem_enc_op,
4518         .mem_enc_reg_region = svm_register_enc_region,
4519         .mem_enc_unreg_region = svm_unregister_enc_region,
4520
4521         .can_emulate_instruction = svm_can_emulate_instruction,
4522
4523         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4524
4525         .msr_filter_changed = svm_msr_filter_changed,
4526         .complete_emulated_msr = svm_complete_emulated_msr,
4527 };
4528
4529 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4530         .cpu_has_kvm_support = has_svm,
4531         .disabled_by_bios = is_disabled,
4532         .hardware_setup = svm_hardware_setup,
4533         .check_processor_compatibility = svm_check_processor_compat,
4534
4535         .runtime_ops = &svm_x86_ops,
4536 };
4537
4538 static int __init svm_init(void)
4539 {
4540         __unused_size_checks();
4541
4542         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4543                         __alignof__(struct vcpu_svm), THIS_MODULE);
4544 }
4545
4546 static void __exit svm_exit(void)
4547 {
4548         kvm_exit();
4549 }
4550
4551 module_init(svm_init)
4552 module_exit(svm_exit)