1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/smp.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/pgtable.h>
26 #include <asm/cmdline.h>
27 #include <asm/stackprotector.h>
28 #include <asm/perf_event.h>
29 #include <asm/mmu_context.h>
30 #include <asm/doublefault.h>
31 #include <asm/archrandom.h>
32 #include <asm/hypervisor.h>
33 #include <asm/processor.h>
34 #include <asm/tlbflush.h>
35 #include <asm/debugreg.h>
36 #include <asm/sections.h>
37 #include <asm/vsyscall.h>
38 #include <linux/topology.h>
39 #include <linux/cpumask.h>
40 #include <linux/atomic.h>
41 #include <asm/proto.h>
42 #include <asm/setup.h>
45 #include <asm/fpu/api.h>
47 #include <asm/hwcap2.h>
48 #include <linux/numa.h>
55 #include <asm/memtype.h>
56 #include <asm/microcode.h>
57 #include <asm/microcode_intel.h>
58 #include <asm/intel-family.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/uv/uv.h>
61 #include <asm/sigframe.h>
62 #include <asm/traps.h>
67 u32 elf_hwcap2 __read_mostly;
69 /* all of these masks are initialized in setup_cpu_local_masks() */
70 cpumask_var_t cpu_initialized_mask;
71 cpumask_var_t cpu_callout_mask;
72 cpumask_var_t cpu_callin_mask;
74 /* representing cpus for which sibling maps can be computed */
75 cpumask_var_t cpu_sibling_setup_mask;
77 /* Number of siblings per CPU package */
78 int smp_num_siblings = 1;
79 EXPORT_SYMBOL(smp_num_siblings);
81 /* Last level cache ID of each logical CPU */
82 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
84 u16 get_llc_id(unsigned int cpu)
86 return per_cpu(cpu_llc_id, cpu);
88 EXPORT_SYMBOL_GPL(get_llc_id);
90 /* L2 cache ID of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID;
93 static struct ppin_info {
98 [X86_VENDOR_INTEL] = {
99 .feature = X86_FEATURE_INTEL_PPIN,
100 .msr_ppin_ctl = MSR_PPIN_CTL,
104 .feature = X86_FEATURE_AMD_PPIN,
105 .msr_ppin_ctl = MSR_AMD_PPIN_CTL,
106 .msr_ppin = MSR_AMD_PPIN
110 static const struct x86_cpu_id ppin_cpuids[] = {
111 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
112 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
114 /* Legacy models without CPUID enumeration */
115 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
116 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
117 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
118 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
119 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
120 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
121 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
122 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
123 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
124 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
129 static void ppin_init(struct cpuinfo_x86 *c)
131 const struct x86_cpu_id *id;
132 unsigned long long val;
133 struct ppin_info *info;
135 id = x86_match_cpu(ppin_cpuids);
140 * Testing the presence of the MSR is not enough. Need to check
141 * that the PPIN_CTL allows reading of the PPIN.
143 info = (struct ppin_info *)id->driver_data;
145 if (rdmsrl_safe(info->msr_ppin_ctl, &val))
148 if ((val & 3UL) == 1UL) {
149 /* PPIN locked in disabled mode */
153 /* If PPIN is disabled, try to enable */
155 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL);
156 rdmsrl_safe(info->msr_ppin_ctl, &val);
159 /* Is the enable bit set? */
161 c->ppin = __rdmsr(info->msr_ppin);
162 set_cpu_cap(c, info->feature);
167 clear_cpu_cap(c, info->feature);
170 /* correctly size the local cpu masks */
171 void __init setup_cpu_local_masks(void)
173 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
174 alloc_bootmem_cpumask_var(&cpu_callin_mask);
175 alloc_bootmem_cpumask_var(&cpu_callout_mask);
176 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
179 static void default_init(struct cpuinfo_x86 *c)
182 cpu_detect_cache_sizes(c);
184 /* Not much we can do here... */
185 /* Check if at least it has cpuid */
186 if (c->cpuid_level == -1) {
187 /* No cpuid. It must be an ancient CPU */
189 strcpy(c->x86_model_id, "486");
190 else if (c->x86 == 3)
191 strcpy(c->x86_model_id, "386");
196 static const struct cpu_dev default_cpu = {
197 .c_init = default_init,
198 .c_vendor = "Unknown",
199 .c_x86_vendor = X86_VENDOR_UNKNOWN,
202 static const struct cpu_dev *this_cpu = &default_cpu;
204 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
207 * We need valid kernel segments for data and code in long mode too
208 * IRET will check the segment types kkeil 2000/10/28
209 * Also sysret mandates a special GDT layout
211 * TLS descriptors are currently at a different place compared to i386.
212 * Hopefully nobody expects them at a fixed place (Wine?)
214 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
215 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
216 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
217 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
218 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
219 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
221 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
222 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
223 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
224 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
226 * Segments used for calling PnP BIOS have byte granularity.
227 * They code segments and data segments have fixed 64k limits,
228 * the transfer segment sizes are set at run time.
231 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
233 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
235 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
237 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
239 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
241 * The APM segments have byte granularity and their bases
242 * are set at run time. All have 64k limits.
245 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
247 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
249 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
251 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
252 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
255 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
258 static int __init x86_nopcid_setup(char *s)
260 /* nopcid doesn't accept parameters */
264 /* do not emit a message if the feature is not present */
265 if (!boot_cpu_has(X86_FEATURE_PCID))
268 setup_clear_cpu_cap(X86_FEATURE_PCID);
269 pr_info("nopcid: PCID feature disabled\n");
272 early_param("nopcid", x86_nopcid_setup);
275 static int __init x86_noinvpcid_setup(char *s)
277 /* noinvpcid doesn't accept parameters */
281 /* do not emit a message if the feature is not present */
282 if (!boot_cpu_has(X86_FEATURE_INVPCID))
285 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
286 pr_info("noinvpcid: INVPCID feature disabled\n");
289 early_param("noinvpcid", x86_noinvpcid_setup);
292 static int cachesize_override = -1;
293 static int disable_x86_serial_nr = 1;
295 static int __init cachesize_setup(char *str)
297 get_option(&str, &cachesize_override);
300 __setup("cachesize=", cachesize_setup);
302 /* Standard macro to see if a specific flag is changeable */
303 static inline int flag_is_changeable_p(u32 flag)
308 * Cyrix and IDT cpus allow disabling of CPUID
309 * so the code below may return different results
310 * when it is executed before and after enabling
311 * the CPUID. Add "volatile" to not allow gcc to
312 * optimize the subsequent calls to this function.
314 asm volatile ("pushfl \n\t"
325 : "=&r" (f1), "=&r" (f2)
328 return ((f1^f2) & flag) != 0;
331 /* Probe for the CPUID instruction */
332 int have_cpuid_p(void)
334 return flag_is_changeable_p(X86_EFLAGS_ID);
337 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
339 unsigned long lo, hi;
341 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
344 /* Disable processor serial number: */
346 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
348 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
350 pr_notice("CPU serial number disabled.\n");
351 clear_cpu_cap(c, X86_FEATURE_PN);
353 /* Disabling the serial number may affect the cpuid level */
354 c->cpuid_level = cpuid_eax(0);
357 static int __init x86_serial_nr_setup(char *s)
359 disable_x86_serial_nr = 0;
362 __setup("serialnumber", x86_serial_nr_setup);
364 static inline int flag_is_changeable_p(u32 flag)
368 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
373 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
375 if (cpu_has(c, X86_FEATURE_SMEP))
376 cr4_set_bits(X86_CR4_SMEP);
379 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
381 unsigned long eflags = native_save_fl();
383 /* This should have been cleared long ago */
384 BUG_ON(eflags & X86_EFLAGS_AC);
386 if (cpu_has(c, X86_FEATURE_SMAP))
387 cr4_set_bits(X86_CR4_SMAP);
390 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
392 /* Check the boot processor, plus build option for UMIP. */
393 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
396 /* Check the current processor's cpuid bits. */
397 if (!cpu_has(c, X86_FEATURE_UMIP))
400 cr4_set_bits(X86_CR4_UMIP);
402 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
408 * Make sure UMIP is disabled in case it was enabled in a
409 * previous boot (e.g., via kexec).
411 cr4_clear_bits(X86_CR4_UMIP);
414 /* These bits should not change their value after CPU init is finished. */
415 static const unsigned long cr4_pinned_mask =
416 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
417 X86_CR4_FSGSBASE | X86_CR4_CET;
418 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
419 static unsigned long cr4_pinned_bits __ro_after_init;
421 void native_write_cr0(unsigned long val)
423 unsigned long bits_missing = 0;
426 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
428 if (static_branch_likely(&cr_pinning)) {
429 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
430 bits_missing = X86_CR0_WP;
434 /* Warn after we've set the missing bits. */
435 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
438 EXPORT_SYMBOL(native_write_cr0);
440 void __no_profile native_write_cr4(unsigned long val)
442 unsigned long bits_changed = 0;
445 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
447 if (static_branch_likely(&cr_pinning)) {
448 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
449 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
450 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
453 /* Warn after we've corrected the changed bits. */
454 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
458 #if IS_MODULE(CONFIG_LKDTM)
459 EXPORT_SYMBOL_GPL(native_write_cr4);
462 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
464 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
466 lockdep_assert_irqs_disabled();
468 newval = (cr4 & ~clear) | set;
470 this_cpu_write(cpu_tlbstate.cr4, newval);
474 EXPORT_SYMBOL(cr4_update_irqsoff);
476 /* Read the CR4 shadow. */
477 unsigned long cr4_read_shadow(void)
479 return this_cpu_read(cpu_tlbstate.cr4);
481 EXPORT_SYMBOL_GPL(cr4_read_shadow);
485 unsigned long cr4 = __read_cr4();
487 if (boot_cpu_has(X86_FEATURE_PCID))
488 cr4 |= X86_CR4_PCIDE;
489 if (static_branch_likely(&cr_pinning))
490 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
494 /* Initialize cr4 shadow for this CPU. */
495 this_cpu_write(cpu_tlbstate.cr4, cr4);
499 * Once CPU feature detection is finished (and boot params have been
500 * parsed), record any of the sensitive CR bits that are set, and
503 static void __init setup_cr_pinning(void)
505 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
506 static_key_enable(&cr_pinning.key);
509 static __init int x86_nofsgsbase_setup(char *arg)
511 /* Require an exact match without trailing characters. */
515 /* Do not emit a message if the feature is not present. */
516 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
519 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
520 pr_info("FSGSBASE disabled via kernel command line\n");
523 __setup("nofsgsbase", x86_nofsgsbase_setup);
526 * Protection Keys are not available in 32-bit mode.
528 static bool pku_disabled;
530 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
532 if (c == &boot_cpu_data) {
533 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
536 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
537 * bit to be set. Enforce it.
539 setup_force_cpu_cap(X86_FEATURE_OSPKE);
541 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
545 cr4_set_bits(X86_CR4_PKE);
546 /* Load the default PKRU value */
547 pkru_write_default();
550 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
551 static __init int setup_disable_pku(char *arg)
554 * Do not clear the X86_FEATURE_PKU bit. All of the
555 * runtime checks are against OSPKE so clearing the
558 * This way, we will see "pku" in cpuinfo, but not
559 * "ospke", which is exactly what we want. It shows
560 * that the CPU has PKU, but the OS has not enabled it.
561 * This happens to be exactly how a system would look
562 * if we disabled the config option.
564 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
568 __setup("nopku", setup_disable_pku);
569 #endif /* CONFIG_X86_64 */
571 #ifdef CONFIG_X86_KERNEL_IBT
573 __noendbr u64 ibt_save(void)
577 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
578 rdmsrl(MSR_IA32_S_CET, msr);
579 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
585 __noendbr void ibt_restore(u64 save)
589 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
590 rdmsrl(MSR_IA32_S_CET, msr);
591 msr &= ~CET_ENDBR_EN;
592 msr |= (save & CET_ENDBR_EN);
593 wrmsrl(MSR_IA32_S_CET, msr);
599 static __always_inline void setup_cet(struct cpuinfo_x86 *c)
601 u64 msr = CET_ENDBR_EN;
603 if (!HAS_KERNEL_IBT ||
604 !cpu_feature_enabled(X86_FEATURE_IBT))
607 wrmsrl(MSR_IA32_S_CET, msr);
608 cr4_set_bits(X86_CR4_CET);
610 if (!ibt_selftest()) {
611 pr_err("IBT selftest: Failed!\n");
612 setup_clear_cpu_cap(X86_FEATURE_IBT);
617 __noendbr void cet_disable(void)
619 if (cpu_feature_enabled(X86_FEATURE_IBT))
620 wrmsrl(MSR_IA32_S_CET, 0);
624 * Some CPU features depend on higher CPUID levels, which may not always
625 * be available due to CPUID level capping or broken virtualization
626 * software. Add those features to this table to auto-disable them.
628 struct cpuid_dependent_feature {
633 static const struct cpuid_dependent_feature
634 cpuid_dependent_features[] = {
635 { X86_FEATURE_MWAIT, 0x00000005 },
636 { X86_FEATURE_DCA, 0x00000009 },
637 { X86_FEATURE_XSAVE, 0x0000000d },
641 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
643 const struct cpuid_dependent_feature *df;
645 for (df = cpuid_dependent_features; df->feature; df++) {
647 if (!cpu_has(c, df->feature))
650 * Note: cpuid_level is set to -1 if unavailable, but
651 * extended_extended_level is set to 0 if unavailable
652 * and the legitimate extended levels are all negative
653 * when signed; hence the weird messing around with
656 if (!((s32)df->level < 0 ?
657 (u32)df->level > (u32)c->extended_cpuid_level :
658 (s32)df->level > (s32)c->cpuid_level))
661 clear_cpu_cap(c, df->feature);
665 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
666 x86_cap_flag(df->feature), df->level);
671 * Naming convention should be: <Name> [(<Codename>)]
672 * This table only is used unless init_<vendor>() below doesn't set it;
673 * in particular, if CPUID levels 0x80000002..4 are supported, this
677 /* Look up CPU names by table lookup. */
678 static const char *table_lookup_model(struct cpuinfo_x86 *c)
681 const struct legacy_cpu_model_info *info;
683 if (c->x86_model >= 16)
684 return NULL; /* Range check */
689 info = this_cpu->legacy_models;
691 while (info->family) {
692 if (info->family == c->x86)
693 return info->model_names[c->x86_model];
697 return NULL; /* Not found */
700 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
701 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
702 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
704 void load_percpu_segment(int cpu)
707 loadsegment(fs, __KERNEL_PERCPU);
709 __loadsegment_simple(gs, 0);
710 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
715 /* The 32-bit entry code needs to find cpu_entry_area. */
716 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
719 /* Load the original GDT from the per-cpu structure */
720 void load_direct_gdt(int cpu)
722 struct desc_ptr gdt_descr;
724 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
725 gdt_descr.size = GDT_SIZE - 1;
726 load_gdt(&gdt_descr);
728 EXPORT_SYMBOL_GPL(load_direct_gdt);
730 /* Load a fixmap remapping of the per-cpu GDT */
731 void load_fixmap_gdt(int cpu)
733 struct desc_ptr gdt_descr;
735 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
736 gdt_descr.size = GDT_SIZE - 1;
737 load_gdt(&gdt_descr);
739 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
742 * Current gdt points %fs at the "master" per-cpu area: after this,
743 * it's on the real one.
745 void switch_to_new_gdt(int cpu)
747 /* Load the original GDT */
748 load_direct_gdt(cpu);
749 /* Reload the per-cpu base */
750 load_percpu_segment(cpu);
753 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
755 static void get_model_name(struct cpuinfo_x86 *c)
760 if (c->extended_cpuid_level < 0x80000004)
763 v = (unsigned int *)c->x86_model_id;
764 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
765 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
766 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
767 c->x86_model_id[48] = 0;
769 /* Trim whitespace */
770 p = q = s = &c->x86_model_id[0];
776 /* Note the last non-whitespace index */
786 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
788 unsigned int eax, ebx, ecx, edx;
790 c->x86_max_cores = 1;
791 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
794 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
796 c->x86_max_cores = (eax >> 26) + 1;
799 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
801 unsigned int n, dummy, ebx, ecx, edx, l2size;
803 n = c->extended_cpuid_level;
805 if (n >= 0x80000005) {
806 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
807 c->x86_cache_size = (ecx>>24) + (edx>>24);
809 /* On K8 L1 TLB is inclusive, so don't count it */
814 if (n < 0x80000006) /* Some chips just has a large L1. */
817 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
821 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
823 /* do processor-specific cache resizing */
824 if (this_cpu->legacy_cache_size)
825 l2size = this_cpu->legacy_cache_size(c, l2size);
827 /* Allow user to override all this if necessary. */
828 if (cachesize_override != -1)
829 l2size = cachesize_override;
832 return; /* Again, no L2 cache is possible */
835 c->x86_cache_size = l2size;
838 u16 __read_mostly tlb_lli_4k[NR_INFO];
839 u16 __read_mostly tlb_lli_2m[NR_INFO];
840 u16 __read_mostly tlb_lli_4m[NR_INFO];
841 u16 __read_mostly tlb_lld_4k[NR_INFO];
842 u16 __read_mostly tlb_lld_2m[NR_INFO];
843 u16 __read_mostly tlb_lld_4m[NR_INFO];
844 u16 __read_mostly tlb_lld_1g[NR_INFO];
846 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
848 if (this_cpu->c_detect_tlb)
849 this_cpu->c_detect_tlb(c);
851 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
852 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
853 tlb_lli_4m[ENTRIES]);
855 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
856 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
857 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
860 int detect_ht_early(struct cpuinfo_x86 *c)
863 u32 eax, ebx, ecx, edx;
865 if (!cpu_has(c, X86_FEATURE_HT))
868 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
871 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
874 cpuid(1, &eax, &ebx, &ecx, &edx);
876 smp_num_siblings = (ebx & 0xff0000) >> 16;
877 if (smp_num_siblings == 1)
878 pr_info_once("CPU0: Hyper-Threading is disabled\n");
883 void detect_ht(struct cpuinfo_x86 *c)
886 int index_msb, core_bits;
888 if (detect_ht_early(c) < 0)
891 index_msb = get_count_order(smp_num_siblings);
892 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
894 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
896 index_msb = get_count_order(smp_num_siblings);
898 core_bits = get_count_order(c->x86_max_cores);
900 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
901 ((1 << core_bits) - 1);
905 static void get_cpu_vendor(struct cpuinfo_x86 *c)
907 char *v = c->x86_vendor_id;
910 for (i = 0; i < X86_VENDOR_NUM; i++) {
914 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
915 (cpu_devs[i]->c_ident[1] &&
916 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
918 this_cpu = cpu_devs[i];
919 c->x86_vendor = this_cpu->c_x86_vendor;
924 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
925 "CPU: Your system may be unstable.\n", v);
927 c->x86_vendor = X86_VENDOR_UNKNOWN;
928 this_cpu = &default_cpu;
931 void cpu_detect(struct cpuinfo_x86 *c)
933 /* Get vendor name */
934 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
935 (unsigned int *)&c->x86_vendor_id[0],
936 (unsigned int *)&c->x86_vendor_id[8],
937 (unsigned int *)&c->x86_vendor_id[4]);
940 /* Intel-defined flags: level 0x00000001 */
941 if (c->cpuid_level >= 0x00000001) {
942 u32 junk, tfms, cap0, misc;
944 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
945 c->x86 = x86_family(tfms);
946 c->x86_model = x86_model(tfms);
947 c->x86_stepping = x86_stepping(tfms);
949 if (cap0 & (1<<19)) {
950 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
951 c->x86_cache_alignment = c->x86_clflush_size;
956 static void apply_forced_caps(struct cpuinfo_x86 *c)
960 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
961 c->x86_capability[i] &= ~cpu_caps_cleared[i];
962 c->x86_capability[i] |= cpu_caps_set[i];
966 static void init_speculation_control(struct cpuinfo_x86 *c)
969 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
970 * and they also have a different bit for STIBP support. Also,
971 * a hypervisor might have set the individual AMD bits even on
972 * Intel CPUs, for finer-grained selection of what's available.
974 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
975 set_cpu_cap(c, X86_FEATURE_IBRS);
976 set_cpu_cap(c, X86_FEATURE_IBPB);
977 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
980 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
981 set_cpu_cap(c, X86_FEATURE_STIBP);
983 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
984 cpu_has(c, X86_FEATURE_VIRT_SSBD))
985 set_cpu_cap(c, X86_FEATURE_SSBD);
987 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
988 set_cpu_cap(c, X86_FEATURE_IBRS);
989 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
992 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
993 set_cpu_cap(c, X86_FEATURE_IBPB);
995 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
996 set_cpu_cap(c, X86_FEATURE_STIBP);
997 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1000 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
1001 set_cpu_cap(c, X86_FEATURE_SSBD);
1002 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1003 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
1007 void get_cpu_cap(struct cpuinfo_x86 *c)
1009 u32 eax, ebx, ecx, edx;
1011 /* Intel-defined flags: level 0x00000001 */
1012 if (c->cpuid_level >= 0x00000001) {
1013 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
1015 c->x86_capability[CPUID_1_ECX] = ecx;
1016 c->x86_capability[CPUID_1_EDX] = edx;
1019 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
1020 if (c->cpuid_level >= 0x00000006)
1021 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
1023 /* Additional Intel-defined flags: level 0x00000007 */
1024 if (c->cpuid_level >= 0x00000007) {
1025 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
1026 c->x86_capability[CPUID_7_0_EBX] = ebx;
1027 c->x86_capability[CPUID_7_ECX] = ecx;
1028 c->x86_capability[CPUID_7_EDX] = edx;
1030 /* Check valid sub-leaf index before accessing it */
1032 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
1033 c->x86_capability[CPUID_7_1_EAX] = eax;
1037 /* Extended state features: level 0x0000000d */
1038 if (c->cpuid_level >= 0x0000000d) {
1039 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
1041 c->x86_capability[CPUID_D_1_EAX] = eax;
1044 /* AMD-defined flags: level 0x80000001 */
1045 eax = cpuid_eax(0x80000000);
1046 c->extended_cpuid_level = eax;
1048 if ((eax & 0xffff0000) == 0x80000000) {
1049 if (eax >= 0x80000001) {
1050 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
1052 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1053 c->x86_capability[CPUID_8000_0001_EDX] = edx;
1057 if (c->extended_cpuid_level >= 0x80000007) {
1058 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
1060 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1064 if (c->extended_cpuid_level >= 0x80000008) {
1065 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1066 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1069 if (c->extended_cpuid_level >= 0x8000000a)
1070 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
1072 if (c->extended_cpuid_level >= 0x8000001f)
1073 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
1075 init_scattered_cpuid_features(c);
1076 init_speculation_control(c);
1079 * Clear/Set all flags overridden by options, after probe.
1080 * This needs to happen each time we re-probe, which may happen
1081 * several times during CPU initialization.
1083 apply_forced_caps(c);
1086 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1088 u32 eax, ebx, ecx, edx;
1090 if (c->extended_cpuid_level >= 0x80000008) {
1091 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1093 c->x86_virt_bits = (eax >> 8) & 0xff;
1094 c->x86_phys_bits = eax & 0xff;
1096 #ifdef CONFIG_X86_32
1097 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
1098 c->x86_phys_bits = 36;
1100 c->x86_cache_bits = c->x86_phys_bits;
1103 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1105 #ifdef CONFIG_X86_32
1109 * First of all, decide if this is a 486 or higher
1110 * It's a 486 if we can modify the AC flag
1112 if (flag_is_changeable_p(X86_EFLAGS_AC))
1117 for (i = 0; i < X86_VENDOR_NUM; i++)
1118 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1119 c->x86_vendor_id[0] = 0;
1120 cpu_devs[i]->c_identify(c);
1121 if (c->x86_vendor_id[0]) {
1129 #define NO_SPECULATION BIT(0)
1130 #define NO_MELTDOWN BIT(1)
1131 #define NO_SSB BIT(2)
1132 #define NO_L1TF BIT(3)
1133 #define NO_MDS BIT(4)
1134 #define MSBDS_ONLY BIT(5)
1135 #define NO_SWAPGS BIT(6)
1136 #define NO_ITLB_MULTIHIT BIT(7)
1137 #define NO_SPECTRE_V2 BIT(8)
1139 #define VULNWL(vendor, family, model, whitelist) \
1140 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1142 #define VULNWL_INTEL(model, whitelist) \
1143 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1145 #define VULNWL_AMD(family, whitelist) \
1146 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1148 #define VULNWL_HYGON(family, whitelist) \
1149 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1151 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1152 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1153 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1154 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1155 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1156 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION),
1157 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION),
1159 /* Intel Family 6 */
1160 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1161 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1162 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1163 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1164 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1166 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1167 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1168 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1169 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1170 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1171 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1173 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1175 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1176 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1178 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1179 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1180 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1183 * Technically, swapgs isn't serializing on AMD (despite it previously
1184 * being documented as such in the APM). But according to AMD, %gs is
1185 * updated non-speculatively, and the issuing of %gs-relative memory
1186 * operands will be blocked until the %gs update completes, which is
1187 * good enough for our purposes.
1190 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT),
1192 /* AMD Family 0xf - 0x12 */
1193 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1194 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1195 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1196 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1198 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1199 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1200 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1202 /* Zhaoxin Family 7 */
1203 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1204 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1208 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1209 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1210 INTEL_FAM6_##model, steppings, \
1211 X86_FEATURE_ANY, issues)
1213 #define SRBDS BIT(0)
1214 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1216 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1217 #define MMIO_SBDS BIT(2)
1219 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1220 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1221 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1222 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1223 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1224 VULNBL_INTEL_STEPPINGS(HASWELL_X, BIT(2) | BIT(4), MMIO),
1225 VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x5), MMIO),
1226 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1227 VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO),
1228 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1229 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPINGS(0x3, 0x3), SRBDS | MMIO),
1230 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS),
1231 VULNBL_INTEL_STEPPINGS(SKYLAKE_X, BIT(3) | BIT(4) | BIT(6) |
1232 BIT(7) | BIT(0xB), MMIO),
1233 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPINGS(0x3, 0x3), SRBDS | MMIO),
1234 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS),
1235 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x9, 0xC), SRBDS | MMIO),
1236 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0x8), SRBDS),
1237 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x9, 0xD), SRBDS | MMIO),
1238 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0x8), SRBDS),
1239 VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPINGS(0x5, 0x5), MMIO | MMIO_SBDS),
1240 VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x1, 0x1), MMIO),
1241 VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0x6), MMIO),
1242 VULNBL_INTEL_STEPPINGS(COMETLAKE, BIT(2) | BIT(3) | BIT(5), MMIO | MMIO_SBDS),
1243 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x1, 0x1), MMIO | MMIO_SBDS),
1244 VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO),
1245 VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPINGS(0x1, 0x1), MMIO | MMIO_SBDS),
1246 VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPINGS(0x1, 0x1), MMIO),
1247 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPINGS(0x1, 0x1), MMIO | MMIO_SBDS),
1248 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO),
1249 VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPINGS(0x0, 0x0), MMIO | MMIO_SBDS),
1253 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1255 const struct x86_cpu_id *m = x86_match_cpu(table);
1257 return m && !!(m->driver_data & which);
1260 u64 x86_read_arch_cap_msr(void)
1264 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1265 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1270 static bool arch_cap_mmio_immune(u64 ia32_cap)
1272 return (ia32_cap & ARCH_CAP_FBSDP_NO &&
1273 ia32_cap & ARCH_CAP_PSDP_NO &&
1274 ia32_cap & ARCH_CAP_SBDR_SSDP_NO);
1277 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1279 u64 ia32_cap = x86_read_arch_cap_msr();
1281 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1282 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1283 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1284 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1286 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1289 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1291 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1292 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1294 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1295 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1296 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1297 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1299 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1300 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1302 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1303 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1304 setup_force_cpu_bug(X86_BUG_MDS);
1305 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1306 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1309 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1310 setup_force_cpu_bug(X86_BUG_SWAPGS);
1313 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1314 * - TSX is supported or
1315 * - TSX_CTRL is present
1317 * TSX_CTRL check is needed for cases when TSX could be disabled before
1318 * the kernel boot e.g. kexec.
1319 * TSX_CTRL check alone is not sufficient for cases when the microcode
1320 * update is not present or running as guest that don't get TSX_CTRL.
1322 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1323 (cpu_has(c, X86_FEATURE_RTM) ||
1324 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1325 setup_force_cpu_bug(X86_BUG_TAA);
1328 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1329 * in the vulnerability blacklist.
1331 * Some of the implications and mitigation of Shared Buffers Data
1332 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1335 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1336 cpu_has(c, X86_FEATURE_RDSEED)) &&
1337 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1338 setup_force_cpu_bug(X86_BUG_SRBDS);
1341 * Processor MMIO Stale Data bug enumeration
1343 * Affected CPU list is generally enough to enumerate the vulnerability,
1344 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1345 * not want the guest to enumerate the bug.
1347 if (cpu_matches(cpu_vuln_blacklist, MMIO) &&
1348 !arch_cap_mmio_immune(ia32_cap))
1349 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1351 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1354 /* Rogue Data Cache Load? No! */
1355 if (ia32_cap & ARCH_CAP_RDCL_NO)
1358 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1360 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1363 setup_force_cpu_bug(X86_BUG_L1TF);
1367 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1368 * unfortunately, that's not true in practice because of early VIA
1369 * chips and (more importantly) broken virtualizers that are not easy
1370 * to detect. In the latter case it doesn't even *fail* reliably, so
1371 * probing for it doesn't even work. Disable it completely on 32-bit
1372 * unless we can find a reliable way to detect all the broken cases.
1373 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1375 static void detect_nopl(void)
1377 #ifdef CONFIG_X86_32
1378 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1380 setup_force_cpu_cap(X86_FEATURE_NOPL);
1385 * We parse cpu parameters early because fpu__init_system() is executed
1386 * before parse_early_param().
1388 static void __init cpu_parse_early_param(void)
1391 char *argptr = arg, *opt;
1392 int arglen, taint = 0;
1394 #ifdef CONFIG_X86_32
1395 if (cmdline_find_option_bool(boot_command_line, "no387"))
1396 #ifdef CONFIG_MATH_EMULATION
1397 setup_clear_cpu_cap(X86_FEATURE_FPU);
1399 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1402 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1403 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1406 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1407 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1409 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1410 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1412 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1413 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1415 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1419 pr_info("Clearing CPUID bits:");
1422 bool found __maybe_unused = false;
1425 opt = strsep(&argptr, ",");
1428 * Handle naked numbers first for feature flags which don't
1431 if (!kstrtouint(opt, 10, &bit)) {
1432 if (bit < NCAPINTS * 32) {
1434 #ifdef CONFIG_X86_FEATURE_NAMES
1435 /* empty-string, i.e., ""-defined feature flags */
1436 if (!x86_cap_flags[bit])
1437 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit));
1440 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1442 setup_clear_cpu_cap(bit);
1446 * The assumption is that there are no feature names with only
1447 * numbers in the name thus go to the next argument.
1452 #ifdef CONFIG_X86_FEATURE_NAMES
1453 for (bit = 0; bit < 32 * NCAPINTS; bit++) {
1454 if (!x86_cap_flag(bit))
1457 if (strcmp(x86_cap_flag(bit), opt))
1460 pr_cont(" %s", opt);
1461 setup_clear_cpu_cap(bit);
1468 pr_cont(" (unknown: %s)", opt);
1474 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1478 * Do minimum CPU detection early.
1479 * Fields really needed: vendor, cpuid_level, family, model, mask,
1481 * The others are not touched to avoid unwanted side effects.
1483 * WARNING: this function is only called on the boot CPU. Don't add code
1484 * here that is supposed to run on all CPUs.
1486 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1488 #ifdef CONFIG_X86_64
1489 c->x86_clflush_size = 64;
1490 c->x86_phys_bits = 36;
1491 c->x86_virt_bits = 48;
1493 c->x86_clflush_size = 32;
1494 c->x86_phys_bits = 32;
1495 c->x86_virt_bits = 32;
1497 c->x86_cache_alignment = c->x86_clflush_size;
1499 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1500 c->extended_cpuid_level = 0;
1502 if (!have_cpuid_p())
1503 identify_cpu_without_cpuid(c);
1505 /* cyrix could have cpuid enabled via c_identify()*/
1506 if (have_cpuid_p()) {
1510 get_cpu_address_sizes(c);
1511 setup_force_cpu_cap(X86_FEATURE_CPUID);
1512 cpu_parse_early_param();
1514 if (this_cpu->c_early_init)
1515 this_cpu->c_early_init(c);
1518 filter_cpuid_features(c, false);
1520 if (this_cpu->c_bsp_init)
1521 this_cpu->c_bsp_init(c);
1523 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1526 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1528 cpu_set_bug_bits(c);
1532 fpu__init_system(c);
1534 init_sigframe_size();
1536 #ifdef CONFIG_X86_32
1538 * Regardless of whether PCID is enumerated, the SDM says
1539 * that it can't be enabled in 32-bit mode.
1541 setup_clear_cpu_cap(X86_FEATURE_PCID);
1545 * Later in the boot process pgtable_l5_enabled() relies on
1546 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1547 * enabled by this point we need to clear the feature bit to avoid
1548 * false-positives at the later stage.
1550 * pgtable_l5_enabled() can be false here for several reasons:
1551 * - 5-level paging is disabled compile-time;
1552 * - it's 32-bit kernel;
1553 * - machine doesn't support 5-level paging;
1554 * - user specified 'no5lvl' in kernel command line.
1556 if (!pgtable_l5_enabled())
1557 setup_clear_cpu_cap(X86_FEATURE_LA57);
1562 void __init early_cpu_init(void)
1564 const struct cpu_dev *const *cdev;
1567 #ifdef CONFIG_PROCESSOR_SELECT
1568 pr_info("KERNEL supported cpus:\n");
1571 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1572 const struct cpu_dev *cpudev = *cdev;
1574 if (count >= X86_VENDOR_NUM)
1576 cpu_devs[count] = cpudev;
1579 #ifdef CONFIG_PROCESSOR_SELECT
1583 for (j = 0; j < 2; j++) {
1584 if (!cpudev->c_ident[j])
1586 pr_info(" %s %s\n", cpudev->c_vendor,
1587 cpudev->c_ident[j]);
1592 early_identify_cpu(&boot_cpu_data);
1595 static bool detect_null_seg_behavior(void)
1598 * Empirically, writing zero to a segment selector on AMD does
1599 * not clear the base, whereas writing zero to a segment
1600 * selector on Intel does clear the base. Intel's behavior
1601 * allows slightly faster context switches in the common case
1602 * where GS is unused by the prev and next threads.
1604 * Since neither vendor documents this anywhere that I can see,
1605 * detect it directly instead of hard-coding the choice by
1608 * I've designated AMD's behavior as the "bug" because it's
1609 * counterintuitive and less friendly.
1612 unsigned long old_base, tmp;
1613 rdmsrl(MSR_FS_BASE, old_base);
1614 wrmsrl(MSR_FS_BASE, 1);
1616 rdmsrl(MSR_FS_BASE, tmp);
1617 wrmsrl(MSR_FS_BASE, old_base);
1621 void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1623 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1624 if (!IS_ENABLED(CONFIG_X86_64))
1627 /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */
1628 if (c->extended_cpuid_level >= 0x80000021 &&
1629 cpuid_eax(0x80000021) & BIT(6))
1633 * CPUID bit above wasn't set. If this kernel is still running
1634 * as a HV guest, then the HV has decided not to advertize
1635 * that CPUID bit for whatever reason. For example, one
1636 * member of the migration pool might be vulnerable. Which
1637 * means, the bug is present: set the BUG flag and return.
1639 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1640 set_cpu_bug(c, X86_BUG_NULL_SEG);
1645 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1646 * 0x18 is the respective family for Hygon.
1648 if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1649 detect_null_seg_behavior())
1652 /* All the remaining ones are affected */
1653 set_cpu_bug(c, X86_BUG_NULL_SEG);
1656 static void generic_identify(struct cpuinfo_x86 *c)
1658 c->extended_cpuid_level = 0;
1660 if (!have_cpuid_p())
1661 identify_cpu_without_cpuid(c);
1663 /* cyrix could have cpuid enabled via c_identify()*/
1664 if (!have_cpuid_p())
1673 get_cpu_address_sizes(c);
1675 if (c->cpuid_level >= 0x00000001) {
1676 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1677 #ifdef CONFIG_X86_32
1679 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1681 c->apicid = c->initial_apicid;
1684 c->phys_proc_id = c->initial_apicid;
1687 get_model_name(c); /* Default name */
1690 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1691 * systems that run Linux at CPL > 0 may or may not have the
1692 * issue, but, even if they have the issue, there's absolutely
1693 * nothing we can do about it because we can't use the real IRET
1696 * NB: For the time being, only 32-bit kernels support
1697 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1698 * whether to apply espfix using paravirt hooks. If any
1699 * non-paravirt system ever shows up that does *not* have the
1700 * ESPFIX issue, we can change this.
1702 #ifdef CONFIG_X86_32
1703 set_cpu_bug(c, X86_BUG_ESPFIX);
1708 * Validate that ACPI/mptables have the same information about the
1709 * effective APIC id and update the package map.
1711 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1714 unsigned int apicid, cpu = smp_processor_id();
1716 apicid = apic->cpu_present_to_apicid(cpu);
1718 if (apicid != c->apicid) {
1719 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1720 cpu, apicid, c->initial_apicid);
1722 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1723 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1725 c->logical_proc_id = 0;
1730 * This does the hard work of actually picking apart the CPU stuff...
1732 static void identify_cpu(struct cpuinfo_x86 *c)
1736 c->loops_per_jiffy = loops_per_jiffy;
1737 c->x86_cache_size = 0;
1738 c->x86_vendor = X86_VENDOR_UNKNOWN;
1739 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1740 c->x86_vendor_id[0] = '\0'; /* Unset */
1741 c->x86_model_id[0] = '\0'; /* Unset */
1742 c->x86_max_cores = 1;
1743 c->x86_coreid_bits = 0;
1745 #ifdef CONFIG_X86_64
1746 c->x86_clflush_size = 64;
1747 c->x86_phys_bits = 36;
1748 c->x86_virt_bits = 48;
1750 c->cpuid_level = -1; /* CPUID not detected */
1751 c->x86_clflush_size = 32;
1752 c->x86_phys_bits = 32;
1753 c->x86_virt_bits = 32;
1755 c->x86_cache_alignment = c->x86_clflush_size;
1756 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1757 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1758 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1761 generic_identify(c);
1763 if (this_cpu->c_identify)
1764 this_cpu->c_identify(c);
1766 /* Clear/Set all flags overridden by options, after probe */
1767 apply_forced_caps(c);
1769 #ifdef CONFIG_X86_64
1770 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1774 * Vendor-specific initialization. In this section we
1775 * canonicalize the feature flags, meaning if there are
1776 * features a certain CPU supports which CPUID doesn't
1777 * tell us, CPUID claiming incorrect flags, or other bugs,
1778 * we handle them here.
1780 * At the end of this section, c->x86_capability better
1781 * indicate the features this CPU genuinely supports!
1783 if (this_cpu->c_init)
1784 this_cpu->c_init(c);
1786 /* Disable the PN if appropriate */
1787 squash_the_stupid_serial_number(c);
1789 /* Set up SMEP/SMAP/UMIP */
1794 /* Enable FSGSBASE instructions if available. */
1795 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1796 cr4_set_bits(X86_CR4_FSGSBASE);
1797 elf_hwcap2 |= HWCAP2_FSGSBASE;
1801 * The vendor-specific functions might have changed features.
1802 * Now we do "generic changes."
1805 /* Filter out anything that depends on CPUID levels we don't have */
1806 filter_cpuid_features(c, true);
1808 /* If the model name is still unset, do table lookup. */
1809 if (!c->x86_model_id[0]) {
1811 p = table_lookup_model(c);
1813 strcpy(c->x86_model_id, p);
1815 /* Last resort... */
1816 sprintf(c->x86_model_id, "%02x/%02x",
1817 c->x86, c->x86_model);
1820 #ifdef CONFIG_X86_64
1829 * Clear/Set all flags overridden by options, need do it
1830 * before following smp all cpus cap AND.
1832 apply_forced_caps(c);
1835 * On SMP, boot_cpu_data holds the common feature set between
1836 * all CPUs; so make sure that we indicate which features are
1837 * common between the CPUs. The first time this routine gets
1838 * executed, c == &boot_cpu_data.
1840 if (c != &boot_cpu_data) {
1841 /* AND the already accumulated flags with these */
1842 for (i = 0; i < NCAPINTS; i++)
1843 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1845 /* OR, i.e. replicate the bug flags */
1846 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1847 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1852 /* Init Machine Check Exception if available. */
1855 select_idle_routine(c);
1858 numa_add_cpu(smp_processor_id());
1863 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1864 * on 32-bit kernels:
1866 #ifdef CONFIG_X86_32
1867 void enable_sep_cpu(void)
1869 struct tss_struct *tss;
1872 if (!boot_cpu_has(X86_FEATURE_SEP))
1876 tss = &per_cpu(cpu_tss_rw, cpu);
1879 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1880 * see the big comment in struct x86_hw_tss's definition.
1883 tss->x86_tss.ss1 = __KERNEL_CS;
1884 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1885 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1886 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1892 void __init identify_boot_cpu(void)
1894 identify_cpu(&boot_cpu_data);
1895 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1896 pr_info("CET detected: Indirect Branch Tracking enabled\n");
1897 #ifdef CONFIG_X86_32
1901 cpu_detect_tlb(&boot_cpu_data);
1907 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1909 BUG_ON(c == &boot_cpu_data);
1911 #ifdef CONFIG_X86_32
1915 validate_apic_and_package_id(c);
1916 x86_spec_ctrl_setup_ap();
1922 void print_cpu_info(struct cpuinfo_x86 *c)
1924 const char *vendor = NULL;
1926 if (c->x86_vendor < X86_VENDOR_NUM) {
1927 vendor = this_cpu->c_vendor;
1929 if (c->cpuid_level >= 0)
1930 vendor = c->x86_vendor_id;
1933 if (vendor && !strstr(c->x86_model_id, vendor))
1934 pr_cont("%s ", vendor);
1936 if (c->x86_model_id[0])
1937 pr_cont("%s", c->x86_model_id);
1939 pr_cont("%d86", c->x86);
1941 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1943 if (c->x86_stepping || c->cpuid_level >= 0)
1944 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1950 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
1951 * function prevents it from becoming an environment variable for init.
1953 static __init int setup_clearcpuid(char *arg)
1957 __setup("clearcpuid=", setup_clearcpuid);
1959 #ifdef CONFIG_X86_64
1960 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1961 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1962 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1965 * The following percpu variables are hot. Align current_task to
1966 * cacheline size such that they fall in the same cacheline.
1968 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1970 EXPORT_PER_CPU_SYMBOL(current_task);
1972 DEFINE_PER_CPU(void *, hardirq_stack_ptr);
1973 DEFINE_PER_CPU(bool, hardirq_stack_inuse);
1975 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1976 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1978 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK;
1980 static void wrmsrl_cstar(unsigned long val)
1983 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
1984 * is so far ignored by the CPU, but raises a #VE trap in a TDX
1985 * guest. Avoid the pointless write on all Intel CPUs.
1987 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1988 wrmsrl(MSR_CSTAR, val);
1991 /* May not be marked __init: used by software suspend */
1992 void syscall_init(void)
1994 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1995 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1997 #ifdef CONFIG_IA32_EMULATION
1998 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
2000 * This only works on Intel CPUs.
2001 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
2002 * This does not cause SYSENTER to jump to the wrong location, because
2003 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
2005 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
2006 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
2007 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
2008 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
2010 wrmsrl_cstar((unsigned long)ignore_sysret);
2011 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
2012 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
2013 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
2017 * Flags to clear on syscall; clear as much as possible
2018 * to minimize user space-kernel interference.
2020 wrmsrl(MSR_SYSCALL_MASK,
2021 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
2022 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
2023 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
2024 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
2025 X86_EFLAGS_AC|X86_EFLAGS_ID);
2028 #else /* CONFIG_X86_64 */
2030 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
2031 EXPORT_PER_CPU_SYMBOL(current_task);
2032 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
2033 EXPORT_PER_CPU_SYMBOL(__preempt_count);
2036 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
2037 * the top of the kernel stack. Use an extra percpu variable to track the
2038 * top of the kernel stack directly.
2040 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
2041 (unsigned long)&init_thread_union + THREAD_SIZE;
2042 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
2044 #ifdef CONFIG_STACKPROTECTOR
2045 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
2046 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
2049 #endif /* CONFIG_X86_64 */
2052 * Clear all 6 debug registers:
2054 static void clear_all_debug_regs(void)
2058 for (i = 0; i < 8; i++) {
2059 /* Ignore db4, db5 */
2060 if ((i == 4) || (i == 5))
2069 * Restore debug regs if using kgdbwait and you have a kernel debugger
2070 * connection established.
2072 static void dbg_restore_debug_regs(void)
2074 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2075 arch_kgdb_ops.correct_hw_break();
2077 #else /* ! CONFIG_KGDB */
2078 #define dbg_restore_debug_regs()
2079 #endif /* ! CONFIG_KGDB */
2081 static void wait_for_master_cpu(int cpu)
2085 * wait for ACK from master CPU before continuing
2086 * with AP initialization
2088 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
2089 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
2094 #ifdef CONFIG_X86_64
2095 static inline void setup_getcpu(int cpu)
2097 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2098 struct desc_struct d = { };
2100 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2101 wrmsr(MSR_TSC_AUX, cpudata, 0);
2103 /* Store CPU and node number in limit. */
2105 d.limit1 = cpudata >> 16;
2107 d.type = 5; /* RO data, expand down, accessed */
2108 d.dpl = 3; /* Visible to user code */
2109 d.s = 1; /* Not a system segment */
2110 d.p = 1; /* Present */
2111 d.d = 1; /* 32-bit */
2113 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2116 static inline void ucode_cpu_init(int cpu)
2122 static inline void tss_setup_ist(struct tss_struct *tss)
2124 /* Set up the per-CPU TSS IST stacks */
2125 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2126 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2127 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2128 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2129 /* Only mapped when SEV-ES is active */
2130 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2133 #else /* CONFIG_X86_64 */
2135 static inline void setup_getcpu(int cpu) { }
2137 static inline void ucode_cpu_init(int cpu)
2139 show_ucode_info_early();
2142 static inline void tss_setup_ist(struct tss_struct *tss) { }
2144 #endif /* !CONFIG_X86_64 */
2146 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2148 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2150 #ifdef CONFIG_X86_IOPL_IOPERM
2151 tss->io_bitmap.prev_max = 0;
2152 tss->io_bitmap.prev_sequence = 0;
2153 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2155 * Invalidate the extra array entry past the end of the all
2156 * permission bitmap as required by the hardware.
2158 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2163 * Setup everything needed to handle exceptions from the IDT, including the IST
2164 * exceptions which use paranoid_entry().
2166 void cpu_init_exception_handling(void)
2168 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2169 int cpu = raw_smp_processor_id();
2171 /* paranoid_entry() gets the CPU number from the GDT */
2174 /* IST vectors need TSS to be set up. */
2176 tss_setup_io_bitmap(tss);
2177 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2181 /* GHCB needs to be setup to handle #VC. */
2184 /* Finally load the IDT */
2189 * cpu_init() initializes state that is per-CPU. Some data is already
2190 * initialized (naturally) in the bootstrap process, such as the GDT. We
2191 * reload it nevertheless, this function acts as a 'CPU state barrier',
2192 * nothing should get across.
2196 struct task_struct *cur = current;
2197 int cpu = raw_smp_processor_id();
2199 wait_for_master_cpu(cpu);
2201 ucode_cpu_init(cpu);
2204 if (this_cpu_read(numa_node) == 0 &&
2205 early_cpu_to_node(cpu) != NUMA_NO_NODE)
2206 set_numa_node(early_cpu_to_node(cpu));
2208 pr_debug("Initializing CPU#%d\n", cpu);
2210 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2211 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2212 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2215 * Initialize the per-CPU GDT with the boot GDT,
2216 * and set up the GDT descriptor:
2218 switch_to_new_gdt(cpu);
2220 if (IS_ENABLED(CONFIG_X86_64)) {
2222 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2225 wrmsrl(MSR_FS_BASE, 0);
2226 wrmsrl(MSR_KERNEL_GS_BASE, 0);
2233 cur->active_mm = &init_mm;
2235 initialize_tlbstate_and_flush();
2236 enter_lazy_tlb(&init_mm, cur);
2239 * sp0 points to the entry trampoline stack regardless of what task
2242 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2244 load_mm_ldt(&init_mm);
2246 clear_all_debug_regs();
2247 dbg_restore_debug_regs();
2249 doublefault_init_cpu_tss();
2256 load_fixmap_gdt(cpu);
2260 void cpu_init_secondary(void)
2263 * Relies on the BP having set-up the IDT tables, which are loaded
2264 * on this CPU in cpu_init_exception_handling().
2266 cpu_init_exception_handling();
2271 #ifdef CONFIG_MICROCODE_LATE_LOADING
2273 * The microcode loader calls this upon late microcode load to recheck features,
2274 * only when microcode has been updated. Caller holds microcode_mutex and CPU
2277 void microcode_check(void)
2279 struct cpuinfo_x86 info;
2281 perf_check_microcode();
2283 /* Reload CPUID max function as it might've changed. */
2284 info.cpuid_level = cpuid_eax(0);
2287 * Copy all capability leafs to pick up the synthetic ones so that
2288 * memcmp() below doesn't fail on that. The ones coming from CPUID will
2289 * get overwritten in get_cpu_cap().
2291 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
2295 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
2298 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2299 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2304 * Invoked from core CPU hotplug code after hotplug operations
2306 void arch_smt_update(void)
2308 /* Handle the speculative execution misfeatures */
2309 cpu_bugs_smt_update();
2310 /* Check whether IPI broadcasting can be enabled */