1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
4 #include <linux/iommu.h>
6 #include <asm/msi_bitmap.h>
10 /* Maximum possible number of ATSD MMIO registers per NPU */
11 #define NV_NMMU_ATSD_REGS 8
19 /* Precise PHB model for error management */
21 PNV_PHB_MODEL_UNKNOWN,
28 #define PNV_PCI_DIAG_BUF_SIZE 8192
29 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
30 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
31 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
32 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
33 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
34 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
36 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
37 #define PNV_IODA_STOPPED_STATE 0x8000000000000000
39 /* Data associated with a PE, including IOMMU tracking etc.. */
46 /* A PE can be associated with a single device or an
47 * entire bus (& children). In the former case, pdev
48 * is populated, in the later case, pbus is.
51 struct pci_dev *parent_dev;
56 /* Effective RID (device RID for a device PE and base bus
57 * RID with devfn 0 for a bus PE)
62 unsigned int pe_number;
64 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
65 struct iommu_table_group table_group;
67 /* 64-bit TCE bypass region */
68 bool tce_bypass_enabled;
69 uint64_t tce_bypass_base;
71 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
72 * and -1 if not supported. (It's actually identical to the
77 /* PEs in compound case */
78 struct pnv_ioda_pe *master;
79 struct list_head slaves;
82 int p2p_initiator_count;
84 /* Link in list of PE#s */
85 struct list_head list;
88 #define PNV_PHB_FLAG_EEH (1 << 0)
89 #define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */
92 struct pci_controller *hose;
93 enum pnv_phb_type type;
94 enum pnv_phb_model model;
103 #ifdef CONFIG_DEBUG_FS
105 struct dentry *dbgfs;
108 #ifdef CONFIG_PCI_MSI
109 unsigned int msi_base;
110 unsigned int msi32_support;
111 struct msi_bitmap msi_bmp;
113 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
114 unsigned int hwirq, unsigned int virq,
115 unsigned int is_64, struct msi_msg *msg);
116 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
117 void (*fixup_phb)(struct pci_controller *hose);
118 int (*init_m64)(struct pnv_phb *phb);
119 void (*reserve_m64_pe)(struct pci_bus *bus,
120 unsigned long *pe_bitmap, bool all);
121 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
122 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
123 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
124 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
127 /* Global bridge info */
128 unsigned int total_pe_num;
129 unsigned int reserved_pe_idx;
130 unsigned int root_pe_idx;
131 bool root_pe_populated;
133 /* 32-bit MMIO window */
134 unsigned int m32_size;
135 unsigned int m32_segsize;
136 unsigned int m32_pci_base;
138 /* 64-bit MMIO window */
139 unsigned int m64_bar_idx;
140 unsigned long m64_size;
141 unsigned long m64_segsize;
142 unsigned long m64_base;
143 unsigned long m64_bar_alloc;
146 unsigned int io_size;
147 unsigned int io_segsize;
148 unsigned int io_pci_base;
151 struct mutex pe_alloc_mutex;
152 unsigned long *pe_alloc;
153 struct pnv_ioda_pe *pe_array;
155 /* M32 & IO segment maps */
156 unsigned int *m64_segmap;
157 unsigned int *m32_segmap;
158 unsigned int *io_segmap;
160 /* DMA32 segment maps - IODA1 only */
161 unsigned int dma32_count;
162 unsigned int *dma32_segmap;
166 struct irq_chip irq_chip;
168 /* Sorted list of used PE's based
169 * on the sequence of creation
171 struct list_head pe_list;
172 struct mutex pe_list_mutex;
174 /* Reverse map of PEs, indexed by {bus, devfn} */
175 unsigned int pe_rmap[0x10000];
178 /* PHB and hub diagnostics */
179 unsigned int diag_data_size;
185 __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
186 unsigned int mmio_atsd_count;
188 /* Bitmask for MMIO register usage */
189 unsigned long mmio_atsd_usage;
192 #ifdef CONFIG_CXL_BASE
193 struct cxl_afu *cxl_afu;
195 int p2p_target_count;
198 extern struct pci_ops pnv_pci_ops;
199 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
200 unsigned long uaddr, enum dma_data_direction direction,
201 unsigned long attrs);
202 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
203 extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
204 unsigned long *hpa, enum dma_data_direction *direction);
205 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
207 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
208 unsigned char *log_buff);
209 int pnv_pci_cfg_read(struct pci_dn *pdn,
210 int where, int size, u32 *val);
211 int pnv_pci_cfg_write(struct pci_dn *pdn,
212 int where, int size, u32 val);
213 extern struct iommu_table *pnv_pci_table_alloc(int nid);
215 extern long pnv_pci_link_table_and_group(int node, int num,
216 struct iommu_table *tbl,
217 struct iommu_table_group *table_group);
218 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
219 struct iommu_table_group *table_group);
220 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
221 void *tce_mem, u64 tce_size,
222 u64 dma_offset, unsigned page_shift);
223 extern void pnv_pci_init_ioda_hub(struct device_node *np);
224 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
225 extern void pnv_pci_init_npu_phb(struct device_node *np);
226 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
227 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
229 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
230 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
231 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
232 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
233 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
234 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
235 extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
236 extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
238 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
239 const char *fmt, ...);
240 #define pe_err(pe, fmt, ...) \
241 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
242 #define pe_warn(pe, fmt, ...) \
243 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
244 #define pe_info(pe, fmt, ...) \
245 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
247 /* Nvlink functions */
248 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
249 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
250 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
251 extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
252 struct iommu_table *tbl);
253 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
254 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
255 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
256 extern int pnv_npu2_init(struct pnv_phb *phb);
259 extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
260 extern void pnv_cxl_disable_device(struct pci_dev *dev);
261 extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
262 extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
265 /* phb ops (cxl switches these when enabling the kernel api on the phb) */
266 extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;
268 #endif /* __POWERNV_PCI_H */