arch/powerpc/include/asm/dcr-native.h

   1 /*
   2  * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
   3  *                    <benh@kernel.crashing.org>
   4  *
   5  *   This program is free software;  you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation; either version 2 of the License, or
   8  *   (at your option) any later version.
   9  *
  10  *   This program is distributed in the hope that it will be useful,
  11  *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  13  *   the GNU General Public License for more details.
  14  *
  15  *   You should have received a copy of the GNU General Public License
  16  *   along with this program;  if not, write to the Free Software
  17  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18  */
  19
  20 #ifndef _ASM_POWERPC_DCR_NATIVE_H
  21 #define _ASM_POWERPC_DCR_NATIVE_H
  22 #ifdef __KERNEL__
  23 #ifndef __ASSEMBLY__
  24
  25 #include <linux/spinlock.h>
  26 #include <asm/cputable.h>
  27 #include <asm/cpu_has_feature.h>
  28 #include <linux/stringify.h>
  29
  30 typedef struct {
  31         unsigned int base;
  32 } dcr_host_native_t;
  33
  34 static inline bool dcr_map_ok_native(dcr_host_native_t host)
  35 {
  36         return true;
  37 }
  38
  39 #define dcr_map_native(dev, dcr_n, dcr_c) \
  40         ((dcr_host_native_t){ .base = (dcr_n) })
  41 #define dcr_unmap_native(host, dcr_c)           do {} while (0)
  42 #define dcr_read_native(host, dcr_n)            mfdcr(dcr_n + host.base)
  43 #define dcr_write_native(host, dcr_n, value)    mtdcr(dcr_n + host.base, value)
  44
  45 /* Table based DCR accessors */
  46 extern void __mtdcr(unsigned int reg, unsigned int val);
  47 extern unsigned int __mfdcr(unsigned int reg);
  48
  49 /* mfdcrx/mtdcrx instruction based accessors. We hand code
  50  * the opcodes in order not to depend on newer binutils
  51  */
  52 static inline unsigned int mfdcrx(unsigned int reg)
  53 {
  54         unsigned int ret;
  55         asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)"
  56                      : "=r" (ret) : "r" (reg));
  57         return ret;
  58 }
  59
  60 static inline void mtdcrx(unsigned int reg, unsigned int val)
  61 {
  62         asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)"
  63                      : : "r" (val), "r" (reg));
  64 }
  65
  66 #define mfdcr(rn)                                               \
  67         ({unsigned int rval;                                    \
  68         if (__builtin_constant_p(rn) && rn < 1024)              \
  69                 asm volatile("mfdcr %0," __stringify(rn)        \
  70                               : "=r" (rval));                   \
  71         else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))  \
  72                 rval = mfdcrx(rn);                              \
  73         else                                                    \
  74                 rval = __mfdcr(rn);                             \
  75         rval;})
  76
  77 #define mtdcr(rn, v)                                            \
  78 do {                                                            \
  79         if (__builtin_constant_p(rn) && rn < 1024)              \
  80                 asm volatile("mtdcr " __stringify(rn) ",%0"     \
  81                               : : "r" (v));                     \
  82         else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))  \
  83                 mtdcrx(rn, v);                                  \
  84         else                                                    \
  85                 __mtdcr(rn, v);                                 \
  86 } while (0)
  87
  88 /* R/W of indirect DCRs make use of standard naming conventions for DCRs */
  89 extern spinlock_t dcr_ind_lock;
  90
  91 static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
  92 {
  93         unsigned long flags;
  94         unsigned int val;
  95
  96         spin_lock_irqsave(&dcr_ind_lock, flags);
  97         if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
  98                 mtdcrx(base_addr, reg);
  99                 val = mfdcrx(base_data);
 100         } else {
 101                 __mtdcr(base_addr, reg);
 102                 val = __mfdcr(base_data);
 103         }
 104         spin_unlock_irqrestore(&dcr_ind_lock, flags);
 105         return val;
 106 }
 107
 108 static inline void __mtdcri(int base_addr, int base_data, int reg,
 109                             unsigned val)
 110 {
 111         unsigned long flags;
 112
 113         spin_lock_irqsave(&dcr_ind_lock, flags);
 114         if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
 115                 mtdcrx(base_addr, reg);
 116                 mtdcrx(base_data, val);
 117         } else {
 118                 __mtdcr(base_addr, reg);
 119                 __mtdcr(base_data, val);
 120         }
 121         spin_unlock_irqrestore(&dcr_ind_lock, flags);
 122 }
 123
 124 static inline void __dcri_clrset(int base_addr, int base_data, int reg,
 125                                  unsigned clr, unsigned set)
 126 {
 127         unsigned long flags;
 128         unsigned int val;
 129
 130         spin_lock_irqsave(&dcr_ind_lock, flags);
 131         if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
 132                 mtdcrx(base_addr, reg);
 133                 val = (mfdcrx(base_data) & ~clr) | set;
 134                 mtdcrx(base_data, val);
 135         } else {
 136                 __mtdcr(base_addr, reg);
 137                 val = (__mfdcr(base_data) & ~clr) | set;
 138                 __mtdcr(base_data, val);
 139         }
 140         spin_unlock_irqrestore(&dcr_ind_lock, flags);
 141 }
 142
 143 #define mfdcri(base, reg)       __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
 144                                          DCRN_ ## base ## _CONFIG_DATA, \
 145                                          reg)
 146
 147 #define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
 148                                          DCRN_ ## base ## _CONFIG_DATA, \
 149                                          reg, data)
 150
 151 #define dcri_clrset(base, reg, clr, set)        __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR,    \
 152                                                               DCRN_ ## base ## _CONFIG_DATA,    \
 153                                                               reg, clr, set)
 154
 155 #endif /* __ASSEMBLY__ */
 156 #endif /* __KERNEL__ */
 157 #endif /* _ASM_POWERPC_DCR_NATIVE_H */