102d86a6ae5636effea0288b436300fbc8fe1a1e
[sfrench/cifs-2.6.git] / arch / mn10300 / proc-mn103e010 / proc-init.c
1 /* MN103E010 Processor initialisation
2  *
3  * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4  * Written by David Howells (dhowells@redhat.com)
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public Licence
8  * as published by the Free Software Foundation; either version
9  * 2 of the Licence, or (at your option) any later version.
10  */
11 #include <linux/kernel.h>
12 #include <linux/irq.h>
13 #include <asm/cacheflush.h>
14 #include <asm/fpu.h>
15 #include <asm/irq.h>
16 #include <asm/rtc.h>
17 #include <asm/busctl-regs.h>
18
19 /*
20  * initialise the on-silicon processor peripherals
21  */
22 asmlinkage void __init processor_init(void)
23 {
24         int loop;
25
26         /* set up the exception table first */
27         for (loop = 0x000; loop < 0x400; loop += 8)
28                 __set_intr_stub(loop, __common_exception);
29
30         __set_intr_stub(EXCEP_ITLBMISS,         itlb_miss);
31         __set_intr_stub(EXCEP_DTLBMISS,         dtlb_miss);
32         __set_intr_stub(EXCEP_IAERROR,          itlb_aerror);
33         __set_intr_stub(EXCEP_DAERROR,          dtlb_aerror);
34         __set_intr_stub(EXCEP_BUSERROR,         raw_bus_error);
35         __set_intr_stub(EXCEP_DOUBLE_FAULT,     double_fault);
36         __set_intr_stub(EXCEP_FPU_DISABLED,     fpu_disabled);
37         __set_intr_stub(EXCEP_SYSCALL0,         system_call);
38
39         __set_intr_stub(EXCEP_NMI,              nmi_handler);
40         __set_intr_stub(EXCEP_WDT,              nmi_handler);
41         __set_intr_stub(EXCEP_IRQ_LEVEL0,       irq_handler);
42         __set_intr_stub(EXCEP_IRQ_LEVEL1,       irq_handler);
43         __set_intr_stub(EXCEP_IRQ_LEVEL2,       irq_handler);
44         __set_intr_stub(EXCEP_IRQ_LEVEL3,       irq_handler);
45         __set_intr_stub(EXCEP_IRQ_LEVEL4,       irq_handler);
46         __set_intr_stub(EXCEP_IRQ_LEVEL5,       irq_handler);
47         __set_intr_stub(EXCEP_IRQ_LEVEL6,       irq_handler);
48
49         IVAR0 = EXCEP_IRQ_LEVEL0;
50         IVAR1 = EXCEP_IRQ_LEVEL1;
51         IVAR2 = EXCEP_IRQ_LEVEL2;
52         IVAR3 = EXCEP_IRQ_LEVEL3;
53         IVAR4 = EXCEP_IRQ_LEVEL4;
54         IVAR5 = EXCEP_IRQ_LEVEL5;
55         IVAR6 = EXCEP_IRQ_LEVEL6;
56
57         mn10300_dcache_flush_inv();
58         mn10300_icache_inv();
59
60         /* disable all interrupts and set to priority 6 (lowest) */
61         for (loop = 0; loop < NR_IRQS; loop++)
62                 GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
63
64         /* clear the timers */
65         TM0MD   = 0;
66         TM1MD   = 0;
67         TM2MD   = 0;
68         TM3MD   = 0;
69         TM4MD   = 0;
70         TM5MD   = 0;
71         TM6MD   = 0;
72         TM6MDA  = 0;
73         TM6MDB  = 0;
74         TM7MD   = 0;
75         TM8MD   = 0;
76         TM9MD   = 0;
77         TM10MD  = 0;
78         TM11MD  = 0;
79
80         calibrate_clock();
81 }
82
83 /*
84  * determine the memory size and base from the memory controller regs
85  */
86 void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size)
87 {
88         unsigned long base, size;
89
90         *mem_base = 0;
91         *mem_size = 0;
92
93         base = SDBASE(0);
94         if (base & SDBASE_CE) {
95                 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
96                 size = ~size + 1;
97                 base &= SDBASE_CBA;
98
99                 printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base);
100                 *mem_size += size;
101                 *mem_base = base;
102         }
103
104         base = SDBASE(1);
105         if (base & SDBASE_CE) {
106                 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
107                 size = ~size + 1;
108                 base &= SDBASE_CBA;
109
110                 printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base);
111                 *mem_size += size;
112                 if (*mem_base == 0)
113                         *mem_base = base;
114         }
115 }