arch/mips/kernel/cpu-probe.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Processor capabilities determination functions.
   4  *
   5  * Copyright (C) xxxx  the Anonymous
   6  * Copyright (C) 1994 - 2006 Ralf Baechle
   7  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   8  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/ptrace.h>
  13 #include <linux/smp.h>
  14 #include <linux/stddef.h>
  15 #include <linux/export.h>
  16
  17 #include <asm/bugs.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpu-features.h>
  20 #include <asm/cpu-type.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/mipsmtregs.h>
  24 #include <asm/msa.h>
  25 #include <asm/watch.h>
  26 #include <asm/elf.h>
  27 #include <asm/pgtable-bits.h>
  28 #include <asm/spram.h>
  29 #include <asm/traps.h>
  30 #include <linux/uaccess.h>
  31
  32 #include "fpu-probe.h"
  33
  34 #include <asm/mach-loongson64/cpucfg-emul.h>
  35
  36 /* Hardware capabilities */
  37 unsigned int elf_hwcap __read_mostly;
  38 EXPORT_SYMBOL_GPL(elf_hwcap);
  39
  40 static inline unsigned long cpu_get_msa_id(void)
  41 {
  42         unsigned long status, msa_id;
  43
  44         status = read_c0_status();
  45         __enable_fpu(FPU_64BIT);
  46         enable_msa();
  47         msa_id = read_msa_ir();
  48         disable_msa();
  49         write_c0_status(status);
  50         return msa_id;
  51 }
  52
  53 static int mips_dsp_disabled;
  54
  55 static int __init dsp_disable(char *s)
  56 {
  57         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
  58         mips_dsp_disabled = 1;
  59
  60         return 1;
  61 }
  62
  63 __setup("nodsp", dsp_disable);
  64
  65 static int mips_htw_disabled;
  66
  67 static int __init htw_disable(char *s)
  68 {
  69         mips_htw_disabled = 1;
  70         cpu_data[0].options &= ~MIPS_CPU_HTW;
  71         write_c0_pwctl(read_c0_pwctl() &
  72                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
  73
  74         return 1;
  75 }
  76
  77 __setup("nohtw", htw_disable);
  78
  79 static int mips_ftlb_disabled;
  80 static int mips_has_ftlb_configured;
  81
  82 enum ftlb_flags {
  83         FTLB_EN         = 1 << 0,
  84         FTLB_SET_PROB   = 1 << 1,
  85 };
  86
  87 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
  88
  89 static int __init ftlb_disable(char *s)
  90 {
  91         unsigned int config4, mmuextdef;
  92
  93         /*
  94          * If the core hasn't done any FTLB configuration, there is nothing
  95          * for us to do here.
  96          */
  97         if (!mips_has_ftlb_configured)
  98                 return 1;
  99
 100         /* Disable it in the boot cpu */
 101         if (set_ftlb_enable(&cpu_data[0], 0)) {
 102                 pr_warn("Can't turn FTLB off\n");
 103                 return 1;
 104         }
 105
 106         config4 = read_c0_config4();
 107
 108         /* Check that FTLB has been disabled */
 109         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 110         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 111         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 112                 /* This should never happen */
 113                 pr_warn("FTLB could not be disabled!\n");
 114                 return 1;
 115         }
 116
 117         mips_ftlb_disabled = 1;
 118         mips_has_ftlb_configured = 0;
 119
 120         /*
 121          * noftlb is mainly used for debug purposes so print
 122          * an informative message instead of using pr_debug()
 123          */
 124         pr_info("FTLB has been disabled\n");
 125
 126         /*
 127          * Some of these bits are duplicated in the decode_config4.
 128          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 129          * once FTLB has been disabled so undo what decode_config4 did.
 130          */
 131         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 132                                cpu_data[0].tlbsizeftlbsets;
 133         cpu_data[0].tlbsizeftlbsets = 0;
 134         cpu_data[0].tlbsizeftlbways = 0;
 135
 136         return 1;
 137 }
 138
 139 __setup("noftlb", ftlb_disable);
 140
 141 /*
 142  * Check if the CPU has per tc perf counters
 143  */
 144 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
 145 {
 146         if (read_c0_config7() & MTI_CONF7_PTC)
 147                 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
 148 }
 149
 150 static inline void check_errata(void)
 151 {
 152         struct cpuinfo_mips *c = &current_cpu_data;
 153
 154         switch (current_cpu_type()) {
 155         case CPU_34K:
 156                 /*
 157                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 158                  * This code only handles VPE0, any SMP/RTOS code
 159                  * making use of VPE1 will be responsable for that VPE.
 160                  */
 161                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 162                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 163                 break;
 164         default:
 165                 break;
 166         }
 167 }
 168
 169 void __init check_bugs32(void)
 170 {
 171         check_errata();
 172 }
 173
 174 /*
 175  * Probe whether cpu has config register by trying to play with
 176  * alternate cache bit and see whether it matters.
 177  * It's used by cpu_probe to distinguish between R3000A and R3081.
 178  */
 179 static inline int cpu_has_confreg(void)
 180 {
 181 #ifdef CONFIG_CPU_R3000
 182         extern unsigned long r3k_cache_size(unsigned long);
 183         unsigned long size1, size2;
 184         unsigned long cfg = read_c0_conf();
 185
 186         size1 = r3k_cache_size(ST0_ISC);
 187         write_c0_conf(cfg ^ R30XX_CONF_AC);
 188         size2 = r3k_cache_size(ST0_ISC);
 189         write_c0_conf(cfg);
 190         return size1 != size2;
 191 #else
 192         return 0;
 193 #endif
 194 }
 195
 196 static inline void set_elf_platform(int cpu, const char *plat)
 197 {
 198         if (cpu == 0)
 199                 __elf_platform = plat;
 200 }
 201
 202 static inline void set_elf_base_platform(const char *plat)
 203 {
 204         if (__elf_base_platform == NULL) {
 205                 __elf_base_platform = plat;
 206         }
 207 }
 208
 209 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 210 {
 211 #ifdef __NEED_VMBITS_PROBE
 212         write_c0_entryhi(0x3fffffffffffe000ULL);
 213         back_to_back_c0_hazard();
 214         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 215 #endif
 216 }
 217
 218 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 219 {
 220         switch (isa) {
 221         case MIPS_CPU_ISA_M64R5:
 222                 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5;
 223                 set_elf_base_platform("mips64r5");
 224                 fallthrough;
 225         case MIPS_CPU_ISA_M64R2:
 226                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 227                 set_elf_base_platform("mips64r2");
 228                 fallthrough;
 229         case MIPS_CPU_ISA_M64R1:
 230                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 231                 set_elf_base_platform("mips64");
 232                 fallthrough;
 233         case MIPS_CPU_ISA_V:
 234                 c->isa_level |= MIPS_CPU_ISA_V;
 235                 set_elf_base_platform("mips5");
 236                 fallthrough;
 237         case MIPS_CPU_ISA_IV:
 238                 c->isa_level |= MIPS_CPU_ISA_IV;
 239                 set_elf_base_platform("mips4");
 240                 fallthrough;
 241         case MIPS_CPU_ISA_III:
 242                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 243                 set_elf_base_platform("mips3");
 244                 break;
 245
 246         /* R6 incompatible with everything else */
 247         case MIPS_CPU_ISA_M64R6:
 248                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 249                 set_elf_base_platform("mips64r6");
 250                 fallthrough;
 251         case MIPS_CPU_ISA_M32R6:
 252                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 253                 set_elf_base_platform("mips32r6");
 254                 /* Break here so we don't add incompatible ISAs */
 255                 break;
 256         case MIPS_CPU_ISA_M32R5:
 257                 c->isa_level |= MIPS_CPU_ISA_M32R5;
 258                 set_elf_base_platform("mips32r5");
 259                 fallthrough;
 260         case MIPS_CPU_ISA_M32R2:
 261                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 262                 set_elf_base_platform("mips32r2");
 263                 fallthrough;
 264         case MIPS_CPU_ISA_M32R1:
 265                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 266                 set_elf_base_platform("mips32");
 267                 fallthrough;
 268         case MIPS_CPU_ISA_II:
 269                 c->isa_level |= MIPS_CPU_ISA_II;
 270                 set_elf_base_platform("mips2");
 271                 break;
 272         }
 273 }
 274
 275 static char unknown_isa[] = KERN_ERR \
 276         "Unsupported ISA type, c0.config0: %d.";
 277
 278 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 279 {
 280
 281         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 282
 283         /*
 284          * 0 = All TLBWR instructions go to FTLB
 285          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 286          * FTLB and 1 goes to the VTLB.
 287          * 2 = 7:1: As above with 7:1 ratio.
 288          * 3 = 3:1: As above with 3:1 ratio.
 289          *
 290          * Use the linear midpoint as the probability threshold.
 291          */
 292         if (probability >= 12)
 293                 return 1;
 294         else if (probability >= 6)
 295                 return 2;
 296         else
 297                 /*
 298                  * So FTLB is less than 4 times bigger than VTLB.
 299                  * A 3:1 ratio can still be useful though.
 300                  */
 301                 return 3;
 302 }
 303
 304 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
 305 {
 306         unsigned int config;
 307
 308         /* It's implementation dependent how the FTLB can be enabled */
 309         switch (c->cputype) {
 310         case CPU_PROAPTIV:
 311         case CPU_P5600:
 312         case CPU_P6600:
 313                 /* proAptiv & related cores use Config6 to enable the FTLB */
 314                 config = read_c0_config6();
 315
 316                 if (flags & FTLB_EN)
 317                         config |= MTI_CONF6_FTLBEN;
 318                 else
 319                         config &= ~MTI_CONF6_FTLBEN;
 320
 321                 if (flags & FTLB_SET_PROB) {
 322                         config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
 323                         config |= calculate_ftlb_probability(c)
 324                                   << MTI_CONF6_FTLBP_SHIFT;
 325                 }
 326
 327                 write_c0_config6(config);
 328                 back_to_back_c0_hazard();
 329                 break;
 330         case CPU_I6400:
 331         case CPU_I6500:
 332                 /* There's no way to disable the FTLB */
 333                 if (!(flags & FTLB_EN))
 334                         return 1;
 335                 return 0;
 336         case CPU_LOONGSON64:
 337                 /* Flush ITLB, DTLB, VTLB and FTLB */
 338                 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
 339                               LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
 340                 /* Loongson-3 cores use Config6 to enable the FTLB */
 341                 config = read_c0_config6();
 342                 if (flags & FTLB_EN)
 343                         /* Enable FTLB */
 344                         write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
 345                 else
 346                         /* Disable FTLB */
 347                         write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
 348                 break;
 349         default:
 350                 return 1;
 351         }
 352
 353         return 0;
 354 }
 355
 356 static int mm_config(struct cpuinfo_mips *c)
 357 {
 358         unsigned int config0, update, mm;
 359
 360         config0 = read_c0_config();
 361         mm = config0 & MIPS_CONF_MM;
 362
 363         /*
 364          * It's implementation dependent what type of write-merge is supported
 365          * and whether it can be enabled/disabled. If it is settable lets make
 366          * the merging allowed by default. Some platforms might have
 367          * write-through caching unsupported. In this case just ignore the
 368          * CP0.Config.MM bit field value.
 369          */
 370         switch (c->cputype) {
 371         case CPU_24K:
 372         case CPU_34K:
 373         case CPU_74K:
 374         case CPU_P5600:
 375         case CPU_P6600:
 376                 c->options |= MIPS_CPU_MM_FULL;
 377                 update = MIPS_CONF_MM_FULL;
 378                 break;
 379         case CPU_1004K:
 380         case CPU_1074K:
 381         case CPU_INTERAPTIV:
 382         case CPU_PROAPTIV:
 383                 mm = 0;
 384                 fallthrough;
 385         default:
 386                 update = 0;
 387                 break;
 388         }
 389
 390         if (update) {
 391                 config0 = (config0 & ~MIPS_CONF_MM) | update;
 392                 write_c0_config(config0);
 393         } else if (mm == MIPS_CONF_MM_SYSAD) {
 394                 c->options |= MIPS_CPU_MM_SYSAD;
 395         } else if (mm == MIPS_CONF_MM_FULL) {
 396                 c->options |= MIPS_CPU_MM_FULL;
 397         }
 398
 399         return 0;
 400 }
 401
 402 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 403 {
 404         unsigned int config0;
 405         int isa, mt;
 406
 407         config0 = read_c0_config();
 408
 409         /*
 410          * Look for Standard TLB or Dual VTLB and FTLB
 411          */
 412         mt = config0 & MIPS_CONF_MT;
 413         if (mt == MIPS_CONF_MT_TLB)
 414                 c->options |= MIPS_CPU_TLB;
 415         else if (mt == MIPS_CONF_MT_FTLB)
 416                 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
 417
 418         isa = (config0 & MIPS_CONF_AT) >> 13;
 419         switch (isa) {
 420         case 0:
 421                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 422                 case 0:
 423                         set_isa(c, MIPS_CPU_ISA_M32R1);
 424                         break;
 425                 case 1:
 426                         set_isa(c, MIPS_CPU_ISA_M32R2);
 427                         break;
 428                 case 2:
 429                         set_isa(c, MIPS_CPU_ISA_M32R6);
 430                         break;
 431                 default:
 432                         goto unknown;
 433                 }
 434                 break;
 435         case 2:
 436                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 437                 case 0:
 438                         set_isa(c, MIPS_CPU_ISA_M64R1);
 439                         break;
 440                 case 1:
 441                         set_isa(c, MIPS_CPU_ISA_M64R2);
 442                         break;
 443                 case 2:
 444                         set_isa(c, MIPS_CPU_ISA_M64R6);
 445                         break;
 446                 default:
 447                         goto unknown;
 448                 }
 449                 break;
 450         default:
 451                 goto unknown;
 452         }
 453
 454         return config0 & MIPS_CONF_M;
 455
 456 unknown:
 457         panic(unknown_isa, config0);
 458 }
 459
 460 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 461 {
 462         unsigned int config1;
 463
 464         config1 = read_c0_config1();
 465
 466         if (config1 & MIPS_CONF1_MD)
 467                 c->ases |= MIPS_ASE_MDMX;
 468         if (config1 & MIPS_CONF1_PC)
 469                 c->options |= MIPS_CPU_PERF;
 470         if (config1 & MIPS_CONF1_WR)
 471                 c->options |= MIPS_CPU_WATCH;
 472         if (config1 & MIPS_CONF1_CA)
 473                 c->ases |= MIPS_ASE_MIPS16;
 474         if (config1 & MIPS_CONF1_EP)
 475                 c->options |= MIPS_CPU_EJTAG;
 476         if (config1 & MIPS_CONF1_FP) {
 477                 c->options |= MIPS_CPU_FPU;
 478                 c->options |= MIPS_CPU_32FPR;
 479         }
 480         if (cpu_has_tlb) {
 481                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 482                 c->tlbsizevtlb = c->tlbsize;
 483                 c->tlbsizeftlbsets = 0;
 484         }
 485
 486         return config1 & MIPS_CONF_M;
 487 }
 488
 489 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 490 {
 491         unsigned int config2;
 492
 493         config2 = read_c0_config2();
 494
 495         if (config2 & MIPS_CONF2_SL)
 496                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 497
 498         return config2 & MIPS_CONF_M;
 499 }
 500
 501 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 502 {
 503         unsigned int config3;
 504
 505         config3 = read_c0_config3();
 506
 507         if (config3 & MIPS_CONF3_SM) {
 508                 c->ases |= MIPS_ASE_SMARTMIPS;
 509                 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
 510         }
 511         if (config3 & MIPS_CONF3_RXI)
 512                 c->options |= MIPS_CPU_RIXI;
 513         if (config3 & MIPS_CONF3_CTXTC)
 514                 c->options |= MIPS_CPU_CTXTC;
 515         if (config3 & MIPS_CONF3_DSP)
 516                 c->ases |= MIPS_ASE_DSP;
 517         if (config3 & MIPS_CONF3_DSP2P) {
 518                 c->ases |= MIPS_ASE_DSP2P;
 519                 if (cpu_has_mips_r6)
 520                         c->ases |= MIPS_ASE_DSP3;
 521         }
 522         if (config3 & MIPS_CONF3_VINT)
 523                 c->options |= MIPS_CPU_VINT;
 524         if (config3 & MIPS_CONF3_VEIC)
 525                 c->options |= MIPS_CPU_VEIC;
 526         if (config3 & MIPS_CONF3_LPA)
 527                 c->options |= MIPS_CPU_LPA;
 528         if (config3 & MIPS_CONF3_MT)
 529                 c->ases |= MIPS_ASE_MIPSMT;
 530         if (config3 & MIPS_CONF3_ULRI)
 531                 c->options |= MIPS_CPU_ULRI;
 532         if (config3 & MIPS_CONF3_ISA)
 533                 c->options |= MIPS_CPU_MICROMIPS;
 534         if (config3 & MIPS_CONF3_VZ)
 535                 c->ases |= MIPS_ASE_VZ;
 536         if (config3 & MIPS_CONF3_SC)
 537                 c->options |= MIPS_CPU_SEGMENTS;
 538         if (config3 & MIPS_CONF3_BI)
 539                 c->options |= MIPS_CPU_BADINSTR;
 540         if (config3 & MIPS_CONF3_BP)
 541                 c->options |= MIPS_CPU_BADINSTRP;
 542         if (config3 & MIPS_CONF3_MSA)
 543                 c->ases |= MIPS_ASE_MSA;
 544         if (config3 & MIPS_CONF3_PW) {
 545                 c->htw_seq = 0;
 546                 c->options |= MIPS_CPU_HTW;
 547         }
 548         if (config3 & MIPS_CONF3_CDMM)
 549                 c->options |= MIPS_CPU_CDMM;
 550         if (config3 & MIPS_CONF3_SP)
 551                 c->options |= MIPS_CPU_SP;
 552
 553         return config3 & MIPS_CONF_M;
 554 }
 555
 556 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 557 {
 558         unsigned int config4;
 559         unsigned int newcf4;
 560         unsigned int mmuextdef;
 561         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 562         unsigned long asid_mask;
 563
 564         config4 = read_c0_config4();
 565
 566         if (cpu_has_tlb) {
 567                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 568                         c->options |= MIPS_CPU_TLBINV;
 569
 570                 /*
 571                  * R6 has dropped the MMUExtDef field from config4.
 572                  * On R6 the fields always describe the FTLB, and only if it is
 573                  * present according to Config.MT.
 574                  */
 575                 if (!cpu_has_mips_r6)
 576                         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 577                 else if (cpu_has_ftlb)
 578                         mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
 579                 else
 580                         mmuextdef = 0;
 581
 582                 switch (mmuextdef) {
 583                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 584                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 585                         c->tlbsizevtlb = c->tlbsize;
 586                         break;
 587                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 588                         c->tlbsizevtlb +=
 589                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 590                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 591                         c->tlbsize = c->tlbsizevtlb;
 592                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 593                         fallthrough;
 594                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 595                         if (mips_ftlb_disabled)
 596                                 break;
 597                         newcf4 = (config4 & ~ftlb_page) |
 598                                 (page_size_ftlb(mmuextdef) <<
 599                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 600                         write_c0_config4(newcf4);
 601                         back_to_back_c0_hazard();
 602                         config4 = read_c0_config4();
 603                         if (config4 != newcf4) {
 604                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 605                                        PAGE_SIZE, config4);
 606                                 /* Switch FTLB off */
 607                                 set_ftlb_enable(c, 0);
 608                                 mips_ftlb_disabled = 1;
 609                                 break;
 610                         }
 611                         c->tlbsizeftlbsets = 1 <<
 612                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 613                                  MIPS_CONF4_FTLBSETS_SHIFT);
 614                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 615                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 616                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 617                         mips_has_ftlb_configured = 1;
 618                         break;
 619                 }
 620         }
 621
 622         c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
 623                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
 624
 625         asid_mask = MIPS_ENTRYHI_ASID;
 626         if (config4 & MIPS_CONF4_AE)
 627                 asid_mask |= MIPS_ENTRYHI_ASIDX;
 628         set_cpu_asid_mask(c, asid_mask);
 629
 630         /*
 631          * Warn if the computed ASID mask doesn't match the mask the kernel
 632          * is built for. This may indicate either a serious problem or an
 633          * easy optimisation opportunity, but either way should be addressed.
 634          */
 635         WARN_ON(asid_mask != cpu_asid_mask(c));
 636
 637         return config4 & MIPS_CONF_M;
 638 }
 639
 640 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 641 {
 642         unsigned int config5, max_mmid_width;
 643         unsigned long asid_mask;
 644
 645         config5 = read_c0_config5();
 646         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 647
 648         if (cpu_has_mips_r6) {
 649                 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
 650                         config5 |= MIPS_CONF5_MI;
 651                 else
 652                         config5 &= ~MIPS_CONF5_MI;
 653         }
 654
 655         write_c0_config5(config5);
 656
 657         if (config5 & MIPS_CONF5_EVA)
 658                 c->options |= MIPS_CPU_EVA;
 659         if (config5 & MIPS_CONF5_MRP)
 660                 c->options |= MIPS_CPU_MAAR;
 661         if (config5 & MIPS_CONF5_LLB)
 662                 c->options |= MIPS_CPU_RW_LLB;
 663         if (config5 & MIPS_CONF5_MVH)
 664                 c->options |= MIPS_CPU_MVH;
 665         if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
 666                 c->options |= MIPS_CPU_VP;
 667         if (config5 & MIPS_CONF5_CA2)
 668                 c->ases |= MIPS_ASE_MIPS16E2;
 669
 670         if (config5 & MIPS_CONF5_CRCP)
 671                 elf_hwcap |= HWCAP_MIPS_CRC32;
 672
 673         if (cpu_has_mips_r6) {
 674                 /* Ensure the write to config5 above takes effect */
 675                 back_to_back_c0_hazard();
 676
 677                 /* Check whether we successfully enabled MMID support */
 678                 config5 = read_c0_config5();
 679                 if (config5 & MIPS_CONF5_MI)
 680                         c->options |= MIPS_CPU_MMID;
 681
 682                 /*
 683                  * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
 684                  * for the CPU we're running on, or if CPUs in an SMP system
 685                  * have inconsistent MMID support.
 686                  */
 687                 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
 688
 689                 if (cpu_has_mmid) {
 690                         write_c0_memorymapid(~0ul);
 691                         back_to_back_c0_hazard();
 692                         asid_mask = read_c0_memorymapid();
 693
 694                         /*
 695                          * We maintain a bitmap to track MMID allocation, and
 696                          * need a sensible upper bound on the size of that
 697                          * bitmap. The initial CPU with MMID support (I6500)
 698                          * supports 16 bit MMIDs, which gives us an 8KiB
 699                          * bitmap. The architecture recommends that hardware
 700                          * support 32 bit MMIDs, which would give us a 512MiB
 701                          * bitmap - that's too big in most cases.
 702                          *
 703                          * Cap MMID width at 16 bits for now & we can revisit
 704                          * this if & when hardware supports anything wider.
 705                          */
 706                         max_mmid_width = 16;
 707                         if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
 708                                 pr_info("Capping MMID width at %d bits",
 709                                         max_mmid_width);
 710                                 asid_mask = GENMASK(max_mmid_width - 1, 0);
 711                         }
 712
 713                         set_cpu_asid_mask(c, asid_mask);
 714                 }
 715         }
 716
 717         return config5 & MIPS_CONF_M;
 718 }
 719
 720 static void decode_configs(struct cpuinfo_mips *c)
 721 {
 722         int ok;
 723
 724         /* MIPS32 or MIPS64 compliant CPU.  */
 725         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 726                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 727
 728         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 729
 730         /* Enable FTLB if present and not disabled */
 731         set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
 732
 733         ok = decode_config0(c);                 /* Read Config registers.  */
 734         BUG_ON(!ok);                            /* Arch spec violation!  */
 735         if (ok)
 736                 ok = decode_config1(c);
 737         if (ok)
 738                 ok = decode_config2(c);
 739         if (ok)
 740                 ok = decode_config3(c);
 741         if (ok)
 742                 ok = decode_config4(c);
 743         if (ok)
 744                 ok = decode_config5(c);
 745
 746         /* Probe the EBase.WG bit */
 747         if (cpu_has_mips_r2_r6) {
 748                 u64 ebase;
 749                 unsigned int status;
 750
 751                 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
 752                 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
 753                                          : (s32)read_c0_ebase();
 754                 if (ebase & MIPS_EBASE_WG) {
 755                         /* WG bit already set, we can avoid the clumsy probe */
 756                         c->options |= MIPS_CPU_EBASE_WG;
 757                 } else {
 758                         /* Its UNDEFINED to change EBase while BEV=0 */
 759                         status = read_c0_status();
 760                         write_c0_status(status | ST0_BEV);
 761                         irq_enable_hazard();
 762                         /*
 763                          * On pre-r6 cores, this may well clobber the upper bits
 764                          * of EBase. This is hard to avoid without potentially
 765                          * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
 766                          */
 767                         if (cpu_has_mips64r6)
 768                                 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
 769                         else
 770                                 write_c0_ebase(ebase | MIPS_EBASE_WG);
 771                         back_to_back_c0_hazard();
 772                         /* Restore BEV */
 773                         write_c0_status(status);
 774                         if (read_c0_ebase() & MIPS_EBASE_WG) {
 775                                 c->options |= MIPS_CPU_EBASE_WG;
 776                                 write_c0_ebase(ebase);
 777                         }
 778                 }
 779         }
 780
 781         /* configure the FTLB write probability */
 782         set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
 783
 784         mips_probe_watch_registers(c);
 785
 786 #ifndef CONFIG_MIPS_CPS
 787         if (cpu_has_mips_r2_r6) {
 788                 unsigned int core;
 789
 790                 core = get_ebase_cpunum();
 791                 if (cpu_has_mipsmt)
 792                         core >>= fls(core_nvpes()) - 1;
 793                 cpu_set_core(c, core);
 794         }
 795 #endif
 796 }
 797
 798 /*
 799  * Probe for certain guest capabilities by writing config bits and reading back.
 800  * Finally write back the original value.
 801  */
 802 #define probe_gc0_config(name, maxconf, bits)                           \
 803 do {                                                                    \
 804         unsigned int tmp;                                               \
 805         tmp = read_gc0_##name();                                        \
 806         write_gc0_##name(tmp | (bits));                                 \
 807         back_to_back_c0_hazard();                                       \
 808         maxconf = read_gc0_##name();                                    \
 809         write_gc0_##name(tmp);                                          \
 810 } while (0)
 811
 812 /*
 813  * Probe for dynamic guest capabilities by changing certain config bits and
 814  * reading back to see if they change. Finally write back the original value.
 815  */
 816 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits)              \
 817 do {                                                                    \
 818         maxconf = read_gc0_##name();                                    \
 819         write_gc0_##name(maxconf ^ (bits));                             \
 820         back_to_back_c0_hazard();                                       \
 821         dynconf = maxconf ^ read_gc0_##name();                          \
 822         write_gc0_##name(maxconf);                                      \
 823         maxconf |= dynconf;                                             \
 824 } while (0)
 825
 826 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
 827 {
 828         unsigned int config0;
 829
 830         probe_gc0_config(config, config0, MIPS_CONF_M);
 831
 832         if (config0 & MIPS_CONF_M)
 833                 c->guest.conf |= BIT(1);
 834         return config0 & MIPS_CONF_M;
 835 }
 836
 837 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
 838 {
 839         unsigned int config1, config1_dyn;
 840
 841         probe_gc0_config_dyn(config1, config1, config1_dyn,
 842                              MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
 843                              MIPS_CONF1_FP);
 844
 845         if (config1 & MIPS_CONF1_FP)
 846                 c->guest.options |= MIPS_CPU_FPU;
 847         if (config1_dyn & MIPS_CONF1_FP)
 848                 c->guest.options_dyn |= MIPS_CPU_FPU;
 849
 850         if (config1 & MIPS_CONF1_WR)
 851                 c->guest.options |= MIPS_CPU_WATCH;
 852         if (config1_dyn & MIPS_CONF1_WR)
 853                 c->guest.options_dyn |= MIPS_CPU_WATCH;
 854
 855         if (config1 & MIPS_CONF1_PC)
 856                 c->guest.options |= MIPS_CPU_PERF;
 857         if (config1_dyn & MIPS_CONF1_PC)
 858                 c->guest.options_dyn |= MIPS_CPU_PERF;
 859
 860         if (config1 & MIPS_CONF_M)
 861                 c->guest.conf |= BIT(2);
 862         return config1 & MIPS_CONF_M;
 863 }
 864
 865 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
 866 {
 867         unsigned int config2;
 868
 869         probe_gc0_config(config2, config2, MIPS_CONF_M);
 870
 871         if (config2 & MIPS_CONF_M)
 872                 c->guest.conf |= BIT(3);
 873         return config2 & MIPS_CONF_M;
 874 }
 875
 876 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
 877 {
 878         unsigned int config3, config3_dyn;
 879
 880         probe_gc0_config_dyn(config3, config3, config3_dyn,
 881                              MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
 882                              MIPS_CONF3_CTXTC);
 883
 884         if (config3 & MIPS_CONF3_CTXTC)
 885                 c->guest.options |= MIPS_CPU_CTXTC;
 886         if (config3_dyn & MIPS_CONF3_CTXTC)
 887                 c->guest.options_dyn |= MIPS_CPU_CTXTC;
 888
 889         if (config3 & MIPS_CONF3_PW)
 890                 c->guest.options |= MIPS_CPU_HTW;
 891
 892         if (config3 & MIPS_CONF3_ULRI)
 893                 c->guest.options |= MIPS_CPU_ULRI;
 894
 895         if (config3 & MIPS_CONF3_SC)
 896                 c->guest.options |= MIPS_CPU_SEGMENTS;
 897
 898         if (config3 & MIPS_CONF3_BI)
 899                 c->guest.options |= MIPS_CPU_BADINSTR;
 900         if (config3 & MIPS_CONF3_BP)
 901                 c->guest.options |= MIPS_CPU_BADINSTRP;
 902
 903         if (config3 & MIPS_CONF3_MSA)
 904                 c->guest.ases |= MIPS_ASE_MSA;
 905         if (config3_dyn & MIPS_CONF3_MSA)
 906                 c->guest.ases_dyn |= MIPS_ASE_MSA;
 907
 908         if (config3 & MIPS_CONF_M)
 909                 c->guest.conf |= BIT(4);
 910         return config3 & MIPS_CONF_M;
 911 }
 912
 913 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
 914 {
 915         unsigned int config4;
 916
 917         probe_gc0_config(config4, config4,
 918                          MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
 919
 920         c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
 921                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
 922
 923         if (config4 & MIPS_CONF_M)
 924                 c->guest.conf |= BIT(5);
 925         return config4 & MIPS_CONF_M;
 926 }
 927
 928 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
 929 {
 930         unsigned int config5, config5_dyn;
 931
 932         probe_gc0_config_dyn(config5, config5, config5_dyn,
 933                          MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
 934
 935         if (config5 & MIPS_CONF5_MRP)
 936                 c->guest.options |= MIPS_CPU_MAAR;
 937         if (config5_dyn & MIPS_CONF5_MRP)
 938                 c->guest.options_dyn |= MIPS_CPU_MAAR;
 939
 940         if (config5 & MIPS_CONF5_LLB)
 941                 c->guest.options |= MIPS_CPU_RW_LLB;
 942
 943         if (config5 & MIPS_CONF5_MVH)
 944                 c->guest.options |= MIPS_CPU_MVH;
 945
 946         if (config5 & MIPS_CONF_M)
 947                 c->guest.conf |= BIT(6);
 948         return config5 & MIPS_CONF_M;
 949 }
 950
 951 static inline void decode_guest_configs(struct cpuinfo_mips *c)
 952 {
 953         unsigned int ok;
 954
 955         ok = decode_guest_config0(c);
 956         if (ok)
 957                 ok = decode_guest_config1(c);
 958         if (ok)
 959                 ok = decode_guest_config2(c);
 960         if (ok)
 961                 ok = decode_guest_config3(c);
 962         if (ok)
 963                 ok = decode_guest_config4(c);
 964         if (ok)
 965                 decode_guest_config5(c);
 966 }
 967
 968 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
 969 {
 970         unsigned int guestctl0, temp;
 971
 972         guestctl0 = read_c0_guestctl0();
 973
 974         if (guestctl0 & MIPS_GCTL0_G0E)
 975                 c->options |= MIPS_CPU_GUESTCTL0EXT;
 976         if (guestctl0 & MIPS_GCTL0_G1)
 977                 c->options |= MIPS_CPU_GUESTCTL1;
 978         if (guestctl0 & MIPS_GCTL0_G2)
 979                 c->options |= MIPS_CPU_GUESTCTL2;
 980         if (!(guestctl0 & MIPS_GCTL0_RAD)) {
 981                 c->options |= MIPS_CPU_GUESTID;
 982
 983                 /*
 984                  * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
 985                  * first, otherwise all data accesses will be fully virtualised
 986                  * as if they were performed by guest mode.
 987                  */
 988                 write_c0_guestctl1(0);
 989                 tlbw_use_hazard();
 990
 991                 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
 992                 back_to_back_c0_hazard();
 993                 temp = read_c0_guestctl0();
 994
 995                 if (temp & MIPS_GCTL0_DRG) {
 996                         write_c0_guestctl0(guestctl0);
 997                         c->options |= MIPS_CPU_DRG;
 998                 }
 999         }
1000 }
1001
1002 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1003 {
1004         if (cpu_has_guestid) {
1005                 /* determine the number of bits of GuestID available */
1006                 write_c0_guestctl1(MIPS_GCTL1_ID);
1007                 back_to_back_c0_hazard();
1008                 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1009                                                 >> MIPS_GCTL1_ID_SHIFT;
1010                 write_c0_guestctl1(0);
1011         }
1012 }
1013
1014 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1015 {
1016         /* determine the number of bits of GTOffset available */
1017         write_c0_gtoffset(0xffffffff);
1018         back_to_back_c0_hazard();
1019         c->gtoffset_mask = read_c0_gtoffset();
1020         write_c0_gtoffset(0);
1021 }
1022
1023 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1024 {
1025         cpu_probe_guestctl0(c);
1026         if (cpu_has_guestctl1)
1027                 cpu_probe_guestctl1(c);
1028
1029         cpu_probe_gtoffset(c);
1030
1031         decode_guest_configs(c);
1032 }
1033
1034 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1035                 | MIPS_CPU_COUNTER)
1036
1037 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1038 {
1039         switch (c->processor_id & PRID_IMP_MASK) {
1040         case PRID_IMP_R2000:
1041                 c->cputype = CPU_R2000;
1042                 __cpu_name[cpu] = "R2000";
1043                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1044                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1045                              MIPS_CPU_NOFPUEX;
1046                 if (__cpu_has_fpu())
1047                         c->options |= MIPS_CPU_FPU;
1048                 c->tlbsize = 64;
1049                 break;
1050         case PRID_IMP_R3000:
1051                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1052                         if (cpu_has_confreg()) {
1053                                 c->cputype = CPU_R3081E;
1054                                 __cpu_name[cpu] = "R3081";
1055                         } else {
1056                                 c->cputype = CPU_R3000A;
1057                                 __cpu_name[cpu] = "R3000A";
1058                         }
1059                 } else {
1060                         c->cputype = CPU_R3000;
1061                         __cpu_name[cpu] = "R3000";
1062                 }
1063                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1064                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1065                              MIPS_CPU_NOFPUEX;
1066                 if (__cpu_has_fpu())
1067                         c->options |= MIPS_CPU_FPU;
1068                 c->tlbsize = 64;
1069                 break;
1070         case PRID_IMP_R4000:
1071                 if (read_c0_config() & CONF_SC) {
1072                         if ((c->processor_id & PRID_REV_MASK) >=
1073                             PRID_REV_R4400) {
1074                                 c->cputype = CPU_R4400PC;
1075                                 __cpu_name[cpu] = "R4400PC";
1076                         } else {
1077                                 c->cputype = CPU_R4000PC;
1078                                 __cpu_name[cpu] = "R4000PC";
1079                         }
1080                 } else {
1081                         int cca = read_c0_config() & CONF_CM_CMASK;
1082                         int mc;
1083
1084                         /*
1085                          * SC and MC versions can't be reliably told apart,
1086                          * but only the latter support coherent caching
1087                          * modes so assume the firmware has set the KSEG0
1088                          * coherency attribute reasonably (if uncached, we
1089                          * assume SC).
1090                          */
1091                         switch (cca) {
1092                         case CONF_CM_CACHABLE_CE:
1093                         case CONF_CM_CACHABLE_COW:
1094                         case CONF_CM_CACHABLE_CUW:
1095                                 mc = 1;
1096                                 break;
1097                         default:
1098                                 mc = 0;
1099                                 break;
1100                         }
1101                         if ((c->processor_id & PRID_REV_MASK) >=
1102                             PRID_REV_R4400) {
1103                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1104                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1105                         } else {
1106                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1107                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1108                         }
1109                 }
1110
1111                 set_isa(c, MIPS_CPU_ISA_III);
1112                 c->fpu_msk31 |= FPU_CSR_CONDX;
1113                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1114                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
1115                              MIPS_CPU_LLSC;
1116                 c->tlbsize = 48;
1117                 break;
1118         case PRID_IMP_VR41XX:
1119                 set_isa(c, MIPS_CPU_ISA_III);
1120                 c->fpu_msk31 |= FPU_CSR_CONDX;
1121                 c->options = R4K_OPTS;
1122                 c->tlbsize = 32;
1123                 switch (c->processor_id & 0xf0) {
1124                 case PRID_REV_VR4111:
1125                         c->cputype = CPU_VR4111;
1126                         __cpu_name[cpu] = "NEC VR4111";
1127                         break;
1128                 case PRID_REV_VR4121:
1129                         c->cputype = CPU_VR4121;
1130                         __cpu_name[cpu] = "NEC VR4121";
1131                         break;
1132                 case PRID_REV_VR4122:
1133                         if ((c->processor_id & 0xf) < 0x3) {
1134                                 c->cputype = CPU_VR4122;
1135                                 __cpu_name[cpu] = "NEC VR4122";
1136                         } else {
1137                                 c->cputype = CPU_VR4181A;
1138                                 __cpu_name[cpu] = "NEC VR4181A";
1139                         }
1140                         break;
1141                 case PRID_REV_VR4130:
1142                         if ((c->processor_id & 0xf) < 0x4) {
1143                                 c->cputype = CPU_VR4131;
1144                                 __cpu_name[cpu] = "NEC VR4131";
1145                         } else {
1146                                 c->cputype = CPU_VR4133;
1147                                 c->options |= MIPS_CPU_LLSC;
1148                                 __cpu_name[cpu] = "NEC VR4133";
1149                         }
1150                         break;
1151                 default:
1152                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1153                         c->cputype = CPU_VR41XX;
1154                         __cpu_name[cpu] = "NEC Vr41xx";
1155                         break;
1156                 }
1157                 break;
1158         case PRID_IMP_R4300:
1159                 c->cputype = CPU_R4300;
1160                 __cpu_name[cpu] = "R4300";
1161                 set_isa(c, MIPS_CPU_ISA_III);
1162                 c->fpu_msk31 |= FPU_CSR_CONDX;
1163                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1164                              MIPS_CPU_LLSC;
1165                 c->tlbsize = 32;
1166                 break;
1167         case PRID_IMP_R4600:
1168                 c->cputype = CPU_R4600;
1169                 __cpu_name[cpu] = "R4600";
1170                 set_isa(c, MIPS_CPU_ISA_III);
1171                 c->fpu_msk31 |= FPU_CSR_CONDX;
1172                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1173                              MIPS_CPU_LLSC;
1174                 c->tlbsize = 48;
1175                 break;
1176         #if 0
1177         case PRID_IMP_R4650:
1178                 /*
1179                  * This processor doesn't have an MMU, so it's not
1180                  * "real easy" to run Linux on it. It is left purely
1181                  * for documentation.  Commented out because it shares
1182                  * it's c0_prid id number with the TX3900.
1183                  */
1184                 c->cputype = CPU_R4650;
1185                 __cpu_name[cpu] = "R4650";
1186                 set_isa(c, MIPS_CPU_ISA_III);
1187                 c->fpu_msk31 |= FPU_CSR_CONDX;
1188                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1189                 c->tlbsize = 48;
1190                 break;
1191         #endif
1192         case PRID_IMP_TX39:
1193                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1194                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1195
1196                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1197                         c->cputype = CPU_TX3927;
1198                         __cpu_name[cpu] = "TX3927";
1199                         c->tlbsize = 64;
1200                 } else {
1201                         switch (c->processor_id & PRID_REV_MASK) {
1202                         case PRID_REV_TX3912:
1203                                 c->cputype = CPU_TX3912;
1204                                 __cpu_name[cpu] = "TX3912";
1205                                 c->tlbsize = 32;
1206                                 break;
1207                         case PRID_REV_TX3922:
1208                                 c->cputype = CPU_TX3922;
1209                                 __cpu_name[cpu] = "TX3922";
1210                                 c->tlbsize = 64;
1211                                 break;
1212                         }
1213                 }
1214                 break;
1215         case PRID_IMP_R4700:
1216                 c->cputype = CPU_R4700;
1217                 __cpu_name[cpu] = "R4700";
1218                 set_isa(c, MIPS_CPU_ISA_III);
1219                 c->fpu_msk31 |= FPU_CSR_CONDX;
1220                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1221                              MIPS_CPU_LLSC;
1222                 c->tlbsize = 48;
1223                 break;
1224         case PRID_IMP_TX49:
1225                 c->cputype = CPU_TX49XX;
1226                 __cpu_name[cpu] = "R49XX";
1227                 set_isa(c, MIPS_CPU_ISA_III);
1228                 c->fpu_msk31 |= FPU_CSR_CONDX;
1229                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1230                 if (!(c->processor_id & 0x08))
1231                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1232                 c->tlbsize = 48;
1233                 break;
1234         case PRID_IMP_R5000:
1235                 c->cputype = CPU_R5000;
1236                 __cpu_name[cpu] = "R5000";
1237                 set_isa(c, MIPS_CPU_ISA_IV);
1238                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1239                              MIPS_CPU_LLSC;
1240                 c->tlbsize = 48;
1241                 break;
1242         case PRID_IMP_R5500:
1243                 c->cputype = CPU_R5500;
1244                 __cpu_name[cpu] = "R5500";
1245                 set_isa(c, MIPS_CPU_ISA_IV);
1246                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1247                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1248                 c->tlbsize = 48;
1249                 break;
1250         case PRID_IMP_NEVADA:
1251                 c->cputype = CPU_NEVADA;
1252                 __cpu_name[cpu] = "Nevada";
1253                 set_isa(c, MIPS_CPU_ISA_IV);
1254                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1255                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1256                 c->tlbsize = 48;
1257                 break;
1258         case PRID_IMP_RM7000:
1259                 c->cputype = CPU_RM7000;
1260                 __cpu_name[cpu] = "RM7000";
1261                 set_isa(c, MIPS_CPU_ISA_IV);
1262                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1263                              MIPS_CPU_LLSC;
1264                 /*
1265                  * Undocumented RM7000:  Bit 29 in the info register of
1266                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
1267                  * entries.
1268                  *
1269                  * 29      1 =>    64 entry JTLB
1270                  *         0 =>    48 entry JTLB
1271                  */
1272                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1273                 break;
1274         case PRID_IMP_R10000:
1275                 c->cputype = CPU_R10000;
1276                 __cpu_name[cpu] = "R10000";
1277                 set_isa(c, MIPS_CPU_ISA_IV);
1278                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1279                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1280                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1281                              MIPS_CPU_LLSC;
1282                 c->tlbsize = 64;
1283                 break;
1284         case PRID_IMP_R12000:
1285                 c->cputype = CPU_R12000;
1286                 __cpu_name[cpu] = "R12000";
1287                 set_isa(c, MIPS_CPU_ISA_IV);
1288                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1289                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1290                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1291                              MIPS_CPU_LLSC;
1292                 c->tlbsize = 64;
1293                 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1294                 break;
1295         case PRID_IMP_R14000:
1296                 if (((c->processor_id >> 4) & 0x0f) > 2) {
1297                         c->cputype = CPU_R16000;
1298                         __cpu_name[cpu] = "R16000";
1299                 } else {
1300                         c->cputype = CPU_R14000;
1301                         __cpu_name[cpu] = "R14000";
1302                 }
1303                 set_isa(c, MIPS_CPU_ISA_IV);
1304                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1305                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1306                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1307                              MIPS_CPU_LLSC;
1308                 c->tlbsize = 64;
1309                 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1310                 break;
1311         case PRID_IMP_LOONGSON_64C:  /* Loongson-2/3 */
1312                 switch (c->processor_id & PRID_REV_MASK) {
1313                 case PRID_REV_LOONGSON2E:
1314                         c->cputype = CPU_LOONGSON2EF;
1315                         __cpu_name[cpu] = "ICT Loongson-2";
1316                         set_elf_platform(cpu, "loongson2e");
1317                         set_isa(c, MIPS_CPU_ISA_III);
1318                         c->fpu_msk31 |= FPU_CSR_CONDX;
1319                         break;
1320                 case PRID_REV_LOONGSON2F:
1321                         c->cputype = CPU_LOONGSON2EF;
1322                         __cpu_name[cpu] = "ICT Loongson-2";
1323                         set_elf_platform(cpu, "loongson2f");
1324                         set_isa(c, MIPS_CPU_ISA_III);
1325                         c->fpu_msk31 |= FPU_CSR_CONDX;
1326                         break;
1327                 case PRID_REV_LOONGSON3A_R1:
1328                         c->cputype = CPU_LOONGSON64;
1329                         __cpu_name[cpu] = "ICT Loongson-3";
1330                         set_elf_platform(cpu, "loongson3a");
1331                         set_isa(c, MIPS_CPU_ISA_M64R1);
1332                         c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1333                                 MIPS_ASE_LOONGSON_EXT);
1334                         break;
1335                 case PRID_REV_LOONGSON3B_R1:
1336                 case PRID_REV_LOONGSON3B_R2:
1337                         c->cputype = CPU_LOONGSON64;
1338                         __cpu_name[cpu] = "ICT Loongson-3";
1339                         set_elf_platform(cpu, "loongson3b");
1340                         set_isa(c, MIPS_CPU_ISA_M64R1);
1341                         c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1342                                 MIPS_ASE_LOONGSON_EXT);
1343                         break;
1344                 }
1345
1346                 c->options = R4K_OPTS |
1347                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
1348                              MIPS_CPU_32FPR;
1349                 c->tlbsize = 64;
1350                 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1351                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1352                 break;
1353         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1354                 decode_configs(c);
1355
1356                 c->cputype = CPU_LOONGSON32;
1357
1358                 switch (c->processor_id & PRID_REV_MASK) {
1359                 case PRID_REV_LOONGSON1B:
1360                         __cpu_name[cpu] = "Loongson 1B";
1361                         break;
1362                 }
1363
1364                 break;
1365         }
1366 }
1367
1368 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1369 {
1370         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1371         switch (c->processor_id & PRID_IMP_MASK) {
1372         case PRID_IMP_QEMU_GENERIC:
1373                 c->writecombine = _CACHE_UNCACHED;
1374                 c->cputype = CPU_QEMU_GENERIC;
1375                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1376                 break;
1377         case PRID_IMP_4KC:
1378                 c->cputype = CPU_4KC;
1379                 c->writecombine = _CACHE_UNCACHED;
1380                 __cpu_name[cpu] = "MIPS 4Kc";
1381                 break;
1382         case PRID_IMP_4KEC:
1383         case PRID_IMP_4KECR2:
1384                 c->cputype = CPU_4KEC;
1385                 c->writecombine = _CACHE_UNCACHED;
1386                 __cpu_name[cpu] = "MIPS 4KEc";
1387                 break;
1388         case PRID_IMP_4KSC:
1389         case PRID_IMP_4KSD:
1390                 c->cputype = CPU_4KSC;
1391                 c->writecombine = _CACHE_UNCACHED;
1392                 __cpu_name[cpu] = "MIPS 4KSc";
1393                 break;
1394         case PRID_IMP_5KC:
1395                 c->cputype = CPU_5KC;
1396                 c->writecombine = _CACHE_UNCACHED;
1397                 __cpu_name[cpu] = "MIPS 5Kc";
1398                 break;
1399         case PRID_IMP_5KE:
1400                 c->cputype = CPU_5KE;
1401                 c->writecombine = _CACHE_UNCACHED;
1402                 __cpu_name[cpu] = "MIPS 5KE";
1403                 break;
1404         case PRID_IMP_20KC:
1405                 c->cputype = CPU_20KC;
1406                 c->writecombine = _CACHE_UNCACHED;
1407                 __cpu_name[cpu] = "MIPS 20Kc";
1408                 break;
1409         case PRID_IMP_24K:
1410                 c->cputype = CPU_24K;
1411                 c->writecombine = _CACHE_UNCACHED;
1412                 __cpu_name[cpu] = "MIPS 24Kc";
1413                 break;
1414         case PRID_IMP_24KE:
1415                 c->cputype = CPU_24K;
1416                 c->writecombine = _CACHE_UNCACHED;
1417                 __cpu_name[cpu] = "MIPS 24KEc";
1418                 break;
1419         case PRID_IMP_25KF:
1420                 c->cputype = CPU_25KF;
1421                 c->writecombine = _CACHE_UNCACHED;
1422                 __cpu_name[cpu] = "MIPS 25Kc";
1423                 break;
1424         case PRID_IMP_34K:
1425                 c->cputype = CPU_34K;
1426                 c->writecombine = _CACHE_UNCACHED;
1427                 __cpu_name[cpu] = "MIPS 34Kc";
1428                 cpu_set_mt_per_tc_perf(c);
1429                 break;
1430         case PRID_IMP_74K:
1431                 c->cputype = CPU_74K;
1432                 c->writecombine = _CACHE_UNCACHED;
1433                 __cpu_name[cpu] = "MIPS 74Kc";
1434                 break;
1435         case PRID_IMP_M14KC:
1436                 c->cputype = CPU_M14KC;
1437                 c->writecombine = _CACHE_UNCACHED;
1438                 __cpu_name[cpu] = "MIPS M14Kc";
1439                 break;
1440         case PRID_IMP_M14KEC:
1441                 c->cputype = CPU_M14KEC;
1442                 c->writecombine = _CACHE_UNCACHED;
1443                 __cpu_name[cpu] = "MIPS M14KEc";
1444                 break;
1445         case PRID_IMP_1004K:
1446                 c->cputype = CPU_1004K;
1447                 c->writecombine = _CACHE_UNCACHED;
1448                 __cpu_name[cpu] = "MIPS 1004Kc";
1449                 cpu_set_mt_per_tc_perf(c);
1450                 break;
1451         case PRID_IMP_1074K:
1452                 c->cputype = CPU_1074K;
1453                 c->writecombine = _CACHE_UNCACHED;
1454                 __cpu_name[cpu] = "MIPS 1074Kc";
1455                 break;
1456         case PRID_IMP_INTERAPTIV_UP:
1457                 c->cputype = CPU_INTERAPTIV;
1458                 __cpu_name[cpu] = "MIPS interAptiv";
1459                 cpu_set_mt_per_tc_perf(c);
1460                 break;
1461         case PRID_IMP_INTERAPTIV_MP:
1462                 c->cputype = CPU_INTERAPTIV;
1463                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1464                 cpu_set_mt_per_tc_perf(c);
1465                 break;
1466         case PRID_IMP_PROAPTIV_UP:
1467                 c->cputype = CPU_PROAPTIV;
1468                 __cpu_name[cpu] = "MIPS proAptiv";
1469                 break;
1470         case PRID_IMP_PROAPTIV_MP:
1471                 c->cputype = CPU_PROAPTIV;
1472                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1473                 break;
1474         case PRID_IMP_P5600:
1475                 c->cputype = CPU_P5600;
1476                 __cpu_name[cpu] = "MIPS P5600";
1477                 break;
1478         case PRID_IMP_P6600:
1479                 c->cputype = CPU_P6600;
1480                 __cpu_name[cpu] = "MIPS P6600";
1481                 break;
1482         case PRID_IMP_I6400:
1483                 c->cputype = CPU_I6400;
1484                 __cpu_name[cpu] = "MIPS I6400";
1485                 break;
1486         case PRID_IMP_I6500:
1487                 c->cputype = CPU_I6500;
1488                 __cpu_name[cpu] = "MIPS I6500";
1489                 break;
1490         case PRID_IMP_M5150:
1491                 c->cputype = CPU_M5150;
1492                 __cpu_name[cpu] = "MIPS M5150";
1493                 break;
1494         case PRID_IMP_M6250:
1495                 c->cputype = CPU_M6250;
1496                 __cpu_name[cpu] = "MIPS M6250";
1497                 break;
1498         }
1499
1500         decode_configs(c);
1501
1502         spram_config();
1503
1504         mm_config(c);
1505
1506         switch (__get_cpu_type(c->cputype)) {
1507         case CPU_M5150:
1508         case CPU_P5600:
1509                 set_isa(c, MIPS_CPU_ISA_M32R5);
1510                 break;
1511         case CPU_I6500:
1512                 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1513                 fallthrough;
1514         case CPU_I6400:
1515                 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1516                 fallthrough;
1517         default:
1518                 break;
1519         }
1520
1521         /* Recent MIPS cores use the implementation-dependent ExcCode 16 for
1522          * cache/FTLB parity exceptions.
1523          */
1524         switch (__get_cpu_type(c->cputype)) {
1525         case CPU_PROAPTIV:
1526         case CPU_P5600:
1527         case CPU_P6600:
1528         case CPU_I6400:
1529         case CPU_I6500:
1530                 c->options |= MIPS_CPU_FTLBPAREX;
1531                 break;
1532         }
1533 }
1534
1535 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1536 {
1537         decode_configs(c);
1538         switch (c->processor_id & PRID_IMP_MASK) {
1539         case PRID_IMP_AU1_REV1:
1540         case PRID_IMP_AU1_REV2:
1541                 c->cputype = CPU_ALCHEMY;
1542                 switch ((c->processor_id >> 24) & 0xff) {
1543                 case 0:
1544                         __cpu_name[cpu] = "Au1000";
1545                         break;
1546                 case 1:
1547                         __cpu_name[cpu] = "Au1500";
1548                         break;
1549                 case 2:
1550                         __cpu_name[cpu] = "Au1100";
1551                         break;
1552                 case 3:
1553                         __cpu_name[cpu] = "Au1550";
1554                         break;
1555                 case 4:
1556                         __cpu_name[cpu] = "Au1200";
1557                         if ((c->processor_id & PRID_REV_MASK) == 2)
1558                                 __cpu_name[cpu] = "Au1250";
1559                         break;
1560                 case 5:
1561                         __cpu_name[cpu] = "Au1210";
1562                         break;
1563                 default:
1564                         __cpu_name[cpu] = "Au1xxx";
1565                         break;
1566                 }
1567                 break;
1568         }
1569 }
1570
1571 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1572 {
1573         decode_configs(c);
1574
1575         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1576         switch (c->processor_id & PRID_IMP_MASK) {
1577         case PRID_IMP_SB1:
1578                 c->cputype = CPU_SB1;
1579                 __cpu_name[cpu] = "SiByte SB1";
1580                 /* FPU in pass1 is known to have issues. */
1581                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1582                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1583                 break;
1584         case PRID_IMP_SB1A:
1585                 c->cputype = CPU_SB1A;
1586                 __cpu_name[cpu] = "SiByte SB1A";
1587                 break;
1588         }
1589 }
1590
1591 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1592 {
1593         decode_configs(c);
1594         switch (c->processor_id & PRID_IMP_MASK) {
1595         case PRID_IMP_SR71000:
1596                 c->cputype = CPU_SR71000;
1597                 __cpu_name[cpu] = "Sandcraft SR71000";
1598                 c->scache.ways = 8;
1599                 c->tlbsize = 64;
1600                 break;
1601         }
1602 }
1603
1604 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1605 {
1606         decode_configs(c);
1607         switch (c->processor_id & PRID_IMP_MASK) {
1608         case PRID_IMP_PR4450:
1609                 c->cputype = CPU_PR4450;
1610                 __cpu_name[cpu] = "Philips PR4450";
1611                 set_isa(c, MIPS_CPU_ISA_M32R1);
1612                 break;
1613         }
1614 }
1615
1616 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1617 {
1618         decode_configs(c);
1619         switch (c->processor_id & PRID_IMP_MASK) {
1620         case PRID_IMP_BMIPS32_REV4:
1621         case PRID_IMP_BMIPS32_REV8:
1622                 c->cputype = CPU_BMIPS32;
1623                 __cpu_name[cpu] = "Broadcom BMIPS32";
1624                 set_elf_platform(cpu, "bmips32");
1625                 break;
1626         case PRID_IMP_BMIPS3300:
1627         case PRID_IMP_BMIPS3300_ALT:
1628         case PRID_IMP_BMIPS3300_BUG:
1629                 c->cputype = CPU_BMIPS3300;
1630                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1631                 set_elf_platform(cpu, "bmips3300");
1632                 reserve_exception_space(0x400, VECTORSPACING * 64);
1633                 break;
1634         case PRID_IMP_BMIPS43XX: {
1635                 int rev = c->processor_id & PRID_REV_MASK;
1636
1637                 if (rev >= PRID_REV_BMIPS4380_LO &&
1638                                 rev <= PRID_REV_BMIPS4380_HI) {
1639                         c->cputype = CPU_BMIPS4380;
1640                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1641                         set_elf_platform(cpu, "bmips4380");
1642                         c->options |= MIPS_CPU_RIXI;
1643                         reserve_exception_space(0x400, VECTORSPACING * 64);
1644                 } else {
1645                         c->cputype = CPU_BMIPS4350;
1646                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1647                         set_elf_platform(cpu, "bmips4350");
1648                 }
1649                 break;
1650         }
1651         case PRID_IMP_BMIPS5000:
1652         case PRID_IMP_BMIPS5200:
1653                 c->cputype = CPU_BMIPS5000;
1654                 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1655                         __cpu_name[cpu] = "Broadcom BMIPS5200";
1656                 else
1657                         __cpu_name[cpu] = "Broadcom BMIPS5000";
1658                 set_elf_platform(cpu, "bmips5000");
1659                 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1660                 reserve_exception_space(0x1000, VECTORSPACING * 64);
1661                 break;
1662         }
1663 }
1664
1665 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1666 {
1667         decode_configs(c);
1668         switch (c->processor_id & PRID_IMP_MASK) {
1669         case PRID_IMP_CAVIUM_CN38XX:
1670         case PRID_IMP_CAVIUM_CN31XX:
1671         case PRID_IMP_CAVIUM_CN30XX:
1672                 c->cputype = CPU_CAVIUM_OCTEON;
1673                 __cpu_name[cpu] = "Cavium Octeon";
1674                 goto platform;
1675         case PRID_IMP_CAVIUM_CN58XX:
1676         case PRID_IMP_CAVIUM_CN56XX:
1677         case PRID_IMP_CAVIUM_CN50XX:
1678         case PRID_IMP_CAVIUM_CN52XX:
1679                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1680                 __cpu_name[cpu] = "Cavium Octeon+";
1681 platform:
1682                 set_elf_platform(cpu, "octeon");
1683                 break;
1684         case PRID_IMP_CAVIUM_CN61XX:
1685         case PRID_IMP_CAVIUM_CN63XX:
1686         case PRID_IMP_CAVIUM_CN66XX:
1687         case PRID_IMP_CAVIUM_CN68XX:
1688         case PRID_IMP_CAVIUM_CNF71XX:
1689                 c->cputype = CPU_CAVIUM_OCTEON2;
1690                 __cpu_name[cpu] = "Cavium Octeon II";
1691                 set_elf_platform(cpu, "octeon2");
1692                 break;
1693         case PRID_IMP_CAVIUM_CN70XX:
1694         case PRID_IMP_CAVIUM_CN73XX:
1695         case PRID_IMP_CAVIUM_CNF75XX:
1696         case PRID_IMP_CAVIUM_CN78XX:
1697                 c->cputype = CPU_CAVIUM_OCTEON3;
1698                 __cpu_name[cpu] = "Cavium Octeon III";
1699                 set_elf_platform(cpu, "octeon3");
1700                 break;
1701         default:
1702                 printk(KERN_INFO "Unknown Octeon chip!\n");
1703                 c->cputype = CPU_UNKNOWN;
1704                 break;
1705         }
1706 }
1707
1708 #ifdef CONFIG_CPU_LOONGSON64
1709 #include <loongson_regs.h>
1710
1711 static inline void decode_cpucfg(struct cpuinfo_mips *c)
1712 {
1713         u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
1714         u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
1715         u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
1716
1717         if (cfg1 & LOONGSON_CFG1_MMI)
1718                 c->ases |= MIPS_ASE_LOONGSON_MMI;
1719
1720         if (cfg2 & LOONGSON_CFG2_LEXT1)
1721                 c->ases |= MIPS_ASE_LOONGSON_EXT;
1722
1723         if (cfg2 & LOONGSON_CFG2_LEXT2)
1724                 c->ases |= MIPS_ASE_LOONGSON_EXT2;
1725
1726         if (cfg2 & LOONGSON_CFG2_LSPW) {
1727                 c->options |= MIPS_CPU_LDPTE;
1728                 c->guest.options |= MIPS_CPU_LDPTE;
1729         }
1730
1731         if (cfg3 & LOONGSON_CFG3_LCAMP)
1732                 c->ases |= MIPS_ASE_LOONGSON_CAM;
1733 }
1734
1735 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1736 {
1737         decode_configs(c);
1738
1739         /* All Loongson processors covered here define ExcCode 16 as GSExc. */
1740         c->options |= MIPS_CPU_GSEXCEX;
1741
1742         switch (c->processor_id & PRID_IMP_MASK) {
1743         case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
1744                 switch (c->processor_id & PRID_REV_MASK) {
1745                 case PRID_REV_LOONGSON2K_R1_0:
1746                 case PRID_REV_LOONGSON2K_R1_1:
1747                 case PRID_REV_LOONGSON2K_R1_2:
1748                 case PRID_REV_LOONGSON2K_R1_3:
1749                         c->cputype = CPU_LOONGSON64;
1750                         __cpu_name[cpu] = "Loongson-2K";
1751                         set_elf_platform(cpu, "gs264e");
1752                         set_isa(c, MIPS_CPU_ISA_M64R2);
1753                         break;
1754                 }
1755                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1756                 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
1757                                 MIPS_ASE_LOONGSON_EXT2);
1758                 break;
1759         case PRID_IMP_LOONGSON_64C:  /* Loongson-3 Classic */
1760                 switch (c->processor_id & PRID_REV_MASK) {
1761                 case PRID_REV_LOONGSON3A_R2_0:
1762                 case PRID_REV_LOONGSON3A_R2_1:
1763                         c->cputype = CPU_LOONGSON64;
1764                         __cpu_name[cpu] = "ICT Loongson-3";
1765                         set_elf_platform(cpu, "loongson3a");
1766                         set_isa(c, MIPS_CPU_ISA_M64R2);
1767                         break;
1768                 case PRID_REV_LOONGSON3A_R3_0:
1769                 case PRID_REV_LOONGSON3A_R3_1:
1770                         c->cputype = CPU_LOONGSON64;
1771                         __cpu_name[cpu] = "ICT Loongson-3";
1772                         set_elf_platform(cpu, "loongson3a");
1773                         set_isa(c, MIPS_CPU_ISA_M64R2);
1774                         break;
1775                 }
1776                 /*
1777                  * Loongson-3 Classic did not implement MIPS standard TLBINV
1778                  * but implemented TLBINVF and EHINV. As currently we're only
1779                  * using these two features, enable MIPS_CPU_TLBINV as well.
1780                  *
1781                  * Also some early Loongson-3A2000 had wrong TLB type in Config
1782                  * register, we correct it here.
1783                  */
1784                 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1785                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1786                 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1787                         MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1788                 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
1789                 break;
1790         case PRID_IMP_LOONGSON_64G:
1791                 c->cputype = CPU_LOONGSON64;
1792                 __cpu_name[cpu] = "ICT Loongson-3";
1793                 set_elf_platform(cpu, "loongson3a");
1794                 set_isa(c, MIPS_CPU_ISA_M64R2);
1795                 decode_cpucfg(c);
1796                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1797                 break;
1798         default:
1799                 panic("Unknown Loongson Processor ID!");
1800                 break;
1801         }
1802 }
1803 #else
1804 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
1805 #endif
1806
1807 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1808 {
1809         decode_configs(c);
1810
1811         /*
1812          * XBurst misses a config2 register, so config3 decode was skipped in
1813          * decode_configs().
1814          */
1815         decode_config3(c);
1816
1817         /* XBurst does not implement the CP0 counter. */
1818         c->options &= ~MIPS_CPU_COUNTER;
1819         BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);
1820
1821         /* XBurst has virtually tagged icache */
1822         c->icache.flags |= MIPS_CACHE_VTAG;
1823
1824         switch (c->processor_id & PRID_IMP_MASK) {
1825
1826         /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
1827         case PRID_IMP_XBURST_REV1:
1828
1829                 /*
1830                  * The XBurst core by default attempts to avoid branch target
1831                  * buffer lookups by detecting & special casing loops. This
1832                  * feature will cause BogoMIPS and lpj calculate in error.
1833                  * Set cp0 config7 bit 4 to disable this feature.
1834                  */
1835                 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
1836
1837                 switch (c->processor_id & PRID_COMP_MASK) {
1838
1839                 /*
1840                  * The config0 register in the XBurst CPUs with a processor ID of
1841                  * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
1842                  * but they don't actually support this ISA.
1843                  */
1844                 case PRID_COMP_INGENIC_D0:
1845                         c->isa_level &= ~MIPS_CPU_ISA_M32R2;
1846                         fallthrough;
1847
1848                 /*
1849                  * The config0 register in the XBurst CPUs with a processor ID of
1850                  * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned
1851                  * huge page tlb mode, this mode is not compatible with the MIPS
1852                  * standard, it will cause tlbmiss and into an infinite loop
1853                  * (line 21 in the tlb-funcs.S) when starting the init process.
1854                  * After chip reset, the default is HPTLB mode, Write 0xa9000000
1855                  * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent
1856                  * getting stuck.
1857                  */
1858                 case PRID_COMP_INGENIC_D1:
1859                         write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
1860                         break;
1861
1862                 default:
1863                         break;
1864                 }
1865                 fallthrough;
1866
1867         /* XBurst®1 with MXU2.0 SIMD ISA */
1868         case PRID_IMP_XBURST_REV2:
1869                 /* Ingenic uses the WA bit to achieve write-combine memory writes */
1870                 c->writecombine = _CACHE_CACHABLE_WA;
1871                 c->cputype = CPU_XBURST;
1872                 __cpu_name[cpu] = "Ingenic XBurst";
1873                 break;
1874
1875         /* XBurst®2 with MXU2.1 SIMD ISA */
1876         case PRID_IMP_XBURST2:
1877                 c->cputype = CPU_XBURST;
1878                 __cpu_name[cpu] = "Ingenic XBurst II";
1879                 break;
1880
1881         default:
1882                 panic("Unknown Ingenic Processor ID!");
1883                 break;
1884         }
1885 }
1886
1887 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1888 {
1889         decode_configs(c);
1890
1891         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1892                 c->cputype = CPU_ALCHEMY;
1893                 __cpu_name[cpu] = "Au1300";
1894                 /* following stuff is not for Alchemy */
1895                 return;
1896         }
1897
1898         c->options = (MIPS_CPU_TLB       |
1899                         MIPS_CPU_4KEX    |
1900                         MIPS_CPU_COUNTER |
1901                         MIPS_CPU_DIVEC   |
1902                         MIPS_CPU_WATCH   |
1903                         MIPS_CPU_EJTAG   |
1904                         MIPS_CPU_LLSC);
1905
1906         switch (c->processor_id & PRID_IMP_MASK) {
1907         case PRID_IMP_NETLOGIC_XLP2XX:
1908         case PRID_IMP_NETLOGIC_XLP9XX:
1909         case PRID_IMP_NETLOGIC_XLP5XX:
1910                 c->cputype = CPU_XLP;
1911                 __cpu_name[cpu] = "Broadcom XLPII";
1912                 break;
1913
1914         case PRID_IMP_NETLOGIC_XLP8XX:
1915         case PRID_IMP_NETLOGIC_XLP3XX:
1916                 c->cputype = CPU_XLP;
1917                 __cpu_name[cpu] = "Netlogic XLP";
1918                 break;
1919
1920         case PRID_IMP_NETLOGIC_XLR732:
1921         case PRID_IMP_NETLOGIC_XLR716:
1922         case PRID_IMP_NETLOGIC_XLR532:
1923         case PRID_IMP_NETLOGIC_XLR308:
1924         case PRID_IMP_NETLOGIC_XLR532C:
1925         case PRID_IMP_NETLOGIC_XLR516C:
1926         case PRID_IMP_NETLOGIC_XLR508C:
1927         case PRID_IMP_NETLOGIC_XLR308C:
1928                 c->cputype = CPU_XLR;
1929                 __cpu_name[cpu] = "Netlogic XLR";
1930                 break;
1931
1932         case PRID_IMP_NETLOGIC_XLS608:
1933         case PRID_IMP_NETLOGIC_XLS408:
1934         case PRID_IMP_NETLOGIC_XLS404:
1935         case PRID_IMP_NETLOGIC_XLS208:
1936         case PRID_IMP_NETLOGIC_XLS204:
1937         case PRID_IMP_NETLOGIC_XLS108:
1938         case PRID_IMP_NETLOGIC_XLS104:
1939         case PRID_IMP_NETLOGIC_XLS616B:
1940         case PRID_IMP_NETLOGIC_XLS608B:
1941         case PRID_IMP_NETLOGIC_XLS416B:
1942         case PRID_IMP_NETLOGIC_XLS412B:
1943         case PRID_IMP_NETLOGIC_XLS408B:
1944         case PRID_IMP_NETLOGIC_XLS404B:
1945                 c->cputype = CPU_XLR;
1946                 __cpu_name[cpu] = "Netlogic XLS";
1947                 break;
1948
1949         default:
1950                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1951                        c->processor_id);
1952                 c->cputype = CPU_XLR;
1953                 break;
1954         }
1955
1956         if (c->cputype == CPU_XLP) {
1957                 set_isa(c, MIPS_CPU_ISA_M64R2);
1958                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1959                 /* This will be updated again after all threads are woken up */
1960                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1961         } else {
1962                 set_isa(c, MIPS_CPU_ISA_M64R1);
1963                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1964         }
1965         c->kscratch_mask = 0xf;
1966 }
1967
1968 #ifdef CONFIG_64BIT
1969 /* For use by uaccess.h */
1970 u64 __ua_limit;
1971 EXPORT_SYMBOL(__ua_limit);
1972 #endif
1973
1974 const char *__cpu_name[NR_CPUS];
1975 const char *__elf_platform;
1976 const char *__elf_base_platform;
1977
1978 void cpu_probe(void)
1979 {
1980         struct cpuinfo_mips *c = &current_cpu_data;
1981         unsigned int cpu = smp_processor_id();
1982
1983         /*
1984          * Set a default elf platform, cpu probe may later
1985          * overwrite it with a more precise value
1986          */
1987         set_elf_platform(cpu, "mips");
1988
1989         c->processor_id = PRID_IMP_UNKNOWN;
1990         c->fpu_id       = FPIR_IMP_NONE;
1991         c->cputype      = CPU_UNKNOWN;
1992         c->writecombine = _CACHE_UNCACHED;
1993
1994         c->fpu_csr31    = FPU_CSR_RN;
1995         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1996
1997         c->processor_id = read_c0_prid();
1998         switch (c->processor_id & PRID_COMP_MASK) {
1999         case PRID_COMP_LEGACY:
2000                 cpu_probe_legacy(c, cpu);
2001                 break;
2002         case PRID_COMP_MIPS:
2003                 cpu_probe_mips(c, cpu);
2004                 break;
2005         case PRID_COMP_ALCHEMY:
2006                 cpu_probe_alchemy(c, cpu);
2007                 break;
2008         case PRID_COMP_SIBYTE:
2009                 cpu_probe_sibyte(c, cpu);
2010                 break;
2011         case PRID_COMP_BROADCOM:
2012                 cpu_probe_broadcom(c, cpu);
2013                 break;
2014         case PRID_COMP_SANDCRAFT:
2015                 cpu_probe_sandcraft(c, cpu);
2016                 break;
2017         case PRID_COMP_NXP:
2018                 cpu_probe_nxp(c, cpu);
2019                 break;
2020         case PRID_COMP_CAVIUM:
2021                 cpu_probe_cavium(c, cpu);
2022                 break;
2023         case PRID_COMP_LOONGSON:
2024                 cpu_probe_loongson(c, cpu);
2025                 break;
2026         case PRID_COMP_INGENIC_13:
2027         case PRID_COMP_INGENIC_D0:
2028         case PRID_COMP_INGENIC_D1:
2029         case PRID_COMP_INGENIC_E1:
2030                 cpu_probe_ingenic(c, cpu);
2031                 break;
2032         case PRID_COMP_NETLOGIC:
2033                 cpu_probe_netlogic(c, cpu);
2034                 break;
2035         }
2036
2037         BUG_ON(!__cpu_name[cpu]);
2038         BUG_ON(c->cputype == CPU_UNKNOWN);
2039
2040         /*
2041          * Platform code can force the cpu type to optimize code
2042          * generation. In that case be sure the cpu type is correctly
2043          * manually setup otherwise it could trigger some nasty bugs.
2044          */
2045         BUG_ON(current_cpu_type() != c->cputype);
2046
2047         if (cpu_has_rixi) {
2048                 /* Enable the RIXI exceptions */
2049                 set_c0_pagegrain(PG_IEC);
2050                 back_to_back_c0_hazard();
2051                 /* Verify the IEC bit is set */
2052                 if (read_c0_pagegrain() & PG_IEC)
2053                         c->options |= MIPS_CPU_RIXIEX;
2054         }
2055
2056         if (mips_fpu_disabled)
2057                 c->options &= ~MIPS_CPU_FPU;
2058
2059         if (mips_dsp_disabled)
2060                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2061
2062         if (mips_htw_disabled) {
2063                 c->options &= ~MIPS_CPU_HTW;
2064                 write_c0_pwctl(read_c0_pwctl() &
2065                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2066         }
2067
2068         if (c->options & MIPS_CPU_FPU)
2069                 cpu_set_fpu_opts(c);
2070         else
2071                 cpu_set_nofpu_opts(c);
2072
2073         if (cpu_has_mips_r2_r6) {
2074                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2075                 /* R2 has Performance Counter Interrupt indicator */
2076                 c->options |= MIPS_CPU_PCI;
2077         }
2078         else
2079                 c->srsets = 1;
2080
2081         if (cpu_has_mips_r6)
2082                 elf_hwcap |= HWCAP_MIPS_R6;
2083
2084         if (cpu_has_msa) {
2085                 c->msa_id = cpu_get_msa_id();
2086                 WARN(c->msa_id & MSA_IR_WRPF,
2087                      "Vector register partitioning unimplemented!");
2088                 elf_hwcap |= HWCAP_MIPS_MSA;
2089         }
2090
2091         if (cpu_has_mips16)
2092                 elf_hwcap |= HWCAP_MIPS_MIPS16;
2093
2094         if (cpu_has_mdmx)
2095                 elf_hwcap |= HWCAP_MIPS_MDMX;
2096
2097         if (cpu_has_mips3d)
2098                 elf_hwcap |= HWCAP_MIPS_MIPS3D;
2099
2100         if (cpu_has_smartmips)
2101                 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
2102
2103         if (cpu_has_dsp)
2104                 elf_hwcap |= HWCAP_MIPS_DSP;
2105
2106         if (cpu_has_dsp2)
2107                 elf_hwcap |= HWCAP_MIPS_DSP2;
2108
2109         if (cpu_has_dsp3)
2110                 elf_hwcap |= HWCAP_MIPS_DSP3;
2111
2112         if (cpu_has_mips16e2)
2113                 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
2114
2115         if (cpu_has_loongson_mmi)
2116                 elf_hwcap |= HWCAP_LOONGSON_MMI;
2117
2118         if (cpu_has_loongson_ext)
2119                 elf_hwcap |= HWCAP_LOONGSON_EXT;
2120
2121         if (cpu_has_loongson_ext2)
2122                 elf_hwcap |= HWCAP_LOONGSON_EXT2;
2123
2124         if (cpu_has_vz)
2125                 cpu_probe_vz(c);
2126
2127         cpu_probe_vmbits(c);
2128
2129         /* Synthesize CPUCFG data if running on Loongson processors;
2130          * no-op otherwise.
2131          *
2132          * This looks at previously probed features, so keep this at bottom.
2133          */
2134         loongson3_cpucfg_synthesize_data(c);
2135
2136 #ifdef CONFIG_64BIT
2137         if (cpu == 0)
2138                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2139 #endif
2140
2141         reserve_exception_space(0, 0x1000);
2142 }
2143
2144 void cpu_report(void)
2145 {
2146         struct cpuinfo_mips *c = &current_cpu_data;
2147
2148         pr_info("CPU%d revision is: %08x (%s)\n",
2149                 smp_processor_id(), c->processor_id, cpu_name_string());
2150         if (c->options & MIPS_CPU_FPU)
2151                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2152         if (cpu_has_msa)
2153                 pr_info("MSA revision is: %08x\n", c->msa_id);
2154 }
2155
2156 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2157 {
2158         /* Ensure the core number fits in the field */
2159         WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2160                            MIPS_GLOBALNUMBER_CLUSTER_SHF));
2161
2162         cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2163         cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2164 }
2165
2166 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2167 {
2168         /* Ensure the core number fits in the field */
2169         WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2170
2171         cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2172         cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2173 }
2174
2175 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2176 {
2177         /* Ensure the VP(E) ID fits in the field */
2178         WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2179
2180         /* Ensure we're not using VP(E)s without support */
2181         WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2182                 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2183
2184         cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2185         cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2186 }