1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "brcm,bcm7360";
11 mips-hpt-frequency = <375000000>;
14 compatible = "brcm,bmips3300";
24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
29 #interrupt-cells = <1>;
34 compatible = "fixed-clock";
36 clock-frequency = <81000000>;
40 compatible = "fixed-clock";
42 clock-frequency = <27000000>;
50 compatible = "simple-bus";
51 ranges = <0 0x10000000 0x01000000>;
53 periph_intc: interrupt-controller@411400 {
54 compatible = "brcm,bcm7038-l1-intc";
55 reg = <0x411400 0x30>;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
65 compatible = "brcm,l2-intc";
66 reg = <0x403000 0x30>;
68 #interrupt-cells = <1>;
69 interrupt-parent = <&periph_intc>;
74 compatible = "brcm,bcm7400-gisb-arb";
75 reg = <0x400000 0xdc>;
77 interrupt-parent = <&sun_l2_intc>;
78 interrupts = <0>, <2>;
79 brcm,gisb-arb-master-mask = <0x2f3>;
80 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
85 upg_irq0_intc: interrupt-controller@406600 {
86 compatible = "brcm,bcm7120-l2-intc";
89 brcm,int-map-mask = <0x44>, <0x7000000>;
90 brcm,int-fwd-mask = <0x70000>;
93 #interrupt-cells = <1>;
95 interrupt-parent = <&periph_intc>;
96 interrupts = <56>, <54>;
97 interrupt-names = "upg_main", "upg_bsc";
100 upg_aon_irq0_intc: interrupt-controller@408b80 {
101 compatible = "brcm,bcm7120-l2-intc";
102 reg = <0x408b80 0x8>;
104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
105 brcm,int-fwd-mask = <0>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
111 interrupt-parent = <&periph_intc>;
112 interrupts = <57>, <55>, <59>;
113 interrupt-names = "upg_main_aon", "upg_bsc_aon",
117 sun_top_ctrl: syscon@404000 {
118 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
119 reg = <0x404000 0x51c>;
124 compatible = "brcm,brcmstb-reboot";
125 syscon = <&sun_top_ctrl 0x304 0x308>;
128 uart0: serial@406800 {
129 compatible = "ns16550a";
130 reg = <0x406800 0x20>;
131 reg-io-width = <0x4>;
134 interrupt-parent = <&periph_intc>;
136 clocks = <&uart_clk>;
140 uart1: serial@406840 {
141 compatible = "ns16550a";
142 reg = <0x406840 0x20>;
143 reg-io-width = <0x4>;
146 interrupt-parent = <&periph_intc>;
148 clocks = <&uart_clk>;
152 uart2: serial@406880 {
153 compatible = "ns16550a";
154 reg = <0x406880 0x20>;
155 reg-io-width = <0x4>;
158 interrupt-parent = <&periph_intc>;
160 clocks = <&uart_clk>;
165 clock-frequency = <390000>;
166 compatible = "brcm,brcmstb-i2c";
167 interrupt-parent = <&upg_irq0_intc>;
168 reg = <0x406200 0x58>;
170 interrupt-names = "upg_bsca";
175 clock-frequency = <390000>;
176 compatible = "brcm,brcmstb-i2c";
177 interrupt-parent = <&upg_irq0_intc>;
178 reg = <0x406280 0x58>;
180 interrupt-names = "upg_bscb";
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
188 reg = <0x406300 0x58>;
190 interrupt-names = "upg_bscc";
195 clock-frequency = <390000>;
196 compatible = "brcm,brcmstb-i2c";
197 interrupt-parent = <&upg_aon_irq0_intc>;
198 reg = <0x408980 0x58>;
200 interrupt-names = "upg_bscd";
205 compatible = "brcm,bcm7038-pwm";
206 reg = <0x406400 0x28>;
212 aon_pm_l2_intc: interrupt-controller@408440 {
213 compatible = "brcm,l2-intc";
214 reg = <0x408440 0x30>;
215 interrupt-controller;
216 #interrupt-cells = <1>;
217 interrupt-parent = <&periph_intc>;
222 upg_gio: gpio@406500 {
223 compatible = "brcm,brcmstb-gpio";
224 reg = <0x406500 0xa0>;
226 #interrupt-cells = <2>;
228 interrupt-controller;
229 interrupt-parent = <&upg_irq0_intc>;
231 brcm,gpio-bank-widths = <32 32 32 29 4>;
234 upg_gio_aon: gpio@408c00 {
235 compatible = "brcm,brcmstb-gpio";
236 reg = <0x408c00 0x60>;
238 #interrupt-cells = <2>;
240 interrupt-controller;
241 interrupt-parent = <&upg_aon_irq0_intc>;
243 interrupts-extended = <&upg_aon_irq0_intc 6>,
246 brcm,gpio-bank-widths = <21 32 2>;
249 enet0: ethernet@430000 {
250 phy-mode = "internal";
251 phy-handle = <&phy1>;
252 mac-address = [ 00 10 18 36 23 1a ];
253 compatible = "brcm,genet-v2";
254 #address-cells = <0x1>;
256 reg = <0x430000 0x4c8c>;
257 interrupts = <24>, <25>;
258 interrupt-parent = <&periph_intc>;
262 compatible = "brcm,genet-mdio-v2";
263 #address-cells = <0x1>;
267 phy1: ethernet-phy@1 {
270 compatible = "brcm,40nm-ephy",
271 "ethernet-phy-ieee802.3-c22";
277 compatible = "brcm,bcm7360-ehci", "generic-ehci";
278 reg = <0x480300 0x100>;
280 interrupt-parent = <&periph_intc>;
286 compatible = "brcm,bcm7360-ohci", "generic-ohci";
287 reg = <0x480400 0x100>;
290 interrupt-parent = <&periph_intc>;
295 hif_l2_intc: interrupt-controller@411000 {
296 compatible = "brcm,l2-intc";
297 reg = <0x411000 0x30>;
298 interrupt-controller;
299 #interrupt-cells = <1>;
300 interrupt-parent = <&periph_intc>;
305 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
306 #address-cells = <1>;
309 reg = <0x412800 0x400>;
310 interrupt-parent = <&hif_l2_intc>;
316 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
317 reg-names = "ahci", "top-ctrl";
318 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
319 interrupt-parent = <&periph_intc>;
321 #address-cells = <1>;
336 sata_phy: sata-phy@180100 {
337 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
338 reg = <0x180100 0x0eff>;
340 #address-cells = <1>;
344 sata_phy0: sata-phy@0 {
349 sata_phy1: sata-phy@1 {
355 sdhci0: sdhci@410000 {
356 compatible = "brcm,bcm7425-sdhci";
357 reg = <0x410000 0x100>;
358 interrupt-parent = <&periph_intc>;
363 spi_l2_intc: interrupt-controller@411d00 {
364 compatible = "brcm,l2-intc";
365 reg = <0x411d00 0x30>;
366 interrupt-controller;
367 #interrupt-cells = <1>;
368 interrupt-parent = <&periph_intc>;
373 #address-cells = <0x1>;
375 compatible = "brcm,spi-bcm-qspi",
376 "brcm,spi-brcmstb-qspi";
378 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
379 reg-names = "cs_reg", "hif_mspi", "bspi";
380 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
381 interrupt-parent = <&spi_l2_intc>;
382 interrupt-names = "spi_lr_fullness_reached",
383 "spi_lr_session_aborted",
385 "spi_lr_session_done",
393 #address-cells = <1>;
395 compatible = "brcm,spi-bcm-qspi",
396 "brcm,spi-brcmstb-mspi";
398 reg = <0x408a00 0x180>;
401 interrupt-parent = <&upg_aon_irq0_intc>;
402 interrupt-names = "mspi_done";