arch/blackfin/mach-common/smp.c

   1 /*
   2  * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
   3  *
   4  * Copyright 2007-2009 Analog Devices Inc.
   5  *                         Philippe Gerum <rpm@xenomai.org>
   6  *
   7  * Licensed under the GPL-2.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/sched/mm.h>
  15 #include <linux/sched/task_stack.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/cache.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/profile.h>
  20 #include <linux/errno.h>
  21 #include <linux/mm.h>
  22 #include <linux/cpu.h>
  23 #include <linux/smp.h>
  24 #include <linux/cpumask.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/irq.h>
  27 #include <linux/slab.h>
  28 #include <linux/atomic.h>
  29 #include <asm/cacheflush.h>
  30 #include <asm/irq_handler.h>
  31 #include <asm/mmu_context.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/pgalloc.h>
  34 #include <asm/processor.h>
  35 #include <asm/ptrace.h>
  36 #include <asm/cpu.h>
  37 #include <asm/time.h>
  38 #include <linux/err.h>
  39
  40 /*
  41  * Anomaly notes:
  42  * 05000120 - we always define corelock as 32-bit integer in L2
  43  */
  44 struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
  45
  46 #ifdef CONFIG_ICACHE_FLUSH_L1
  47 unsigned long blackfin_iflush_l1_entry[NR_CPUS];
  48 #endif
  49
  50 struct blackfin_initial_pda initial_pda_coreb;
  51
  52 enum ipi_message_type {
  53         BFIN_IPI_NONE,
  54         BFIN_IPI_TIMER,
  55         BFIN_IPI_RESCHEDULE,
  56         BFIN_IPI_CALL_FUNC,
  57         BFIN_IPI_CPU_STOP,
  58 };
  59
  60 struct blackfin_flush_data {
  61         unsigned long start;
  62         unsigned long end;
  63 };
  64
  65 void *secondary_stack;
  66
  67 static struct blackfin_flush_data smp_flush_data;
  68
  69 static DEFINE_SPINLOCK(stop_lock);
  70
  71 /* A magic number - stress test shows this is safe for common cases */
  72 #define BFIN_IPI_MSGQ_LEN 5
  73
  74 /* Simple FIFO buffer, overflow leads to panic */
  75 struct ipi_data {
  76         atomic_t count;
  77         atomic_t bits;
  78 };
  79
  80 static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
  81
  82 static void ipi_cpu_stop(unsigned int cpu)
  83 {
  84         spin_lock(&stop_lock);
  85         printk(KERN_CRIT "CPU%u: stopping\n", cpu);
  86         dump_stack();
  87         spin_unlock(&stop_lock);
  88
  89         set_cpu_online(cpu, false);
  90
  91         local_irq_disable();
  92
  93         while (1)
  94                 SSYNC();
  95 }
  96
  97 static void ipi_flush_icache(void *info)
  98 {
  99         struct blackfin_flush_data *fdata = info;
 100
 101         /* Invalidate the memory holding the bounds of the flushed region. */
 102         blackfin_dcache_invalidate_range((unsigned long)fdata,
 103                                          (unsigned long)fdata + sizeof(*fdata));
 104
 105         /* Make sure all write buffers in the data side of the core
 106          * are flushed before trying to invalidate the icache.  This
 107          * needs to be after the data flush and before the icache
 108          * flush so that the SSYNC does the right thing in preventing
 109          * the instruction prefetcher from hitting things in cached
 110          * memory at the wrong time -- it runs much further ahead than
 111          * the pipeline.
 112          */
 113         SSYNC();
 114
 115         /* ipi_flaush_icache is invoked by generic flush_icache_range,
 116          * so call blackfin arch icache flush directly here.
 117          */
 118         blackfin_icache_flush_range(fdata->start, fdata->end);
 119 }
 120
 121 /* Use IRQ_SUPPLE_0 to request reschedule.
 122  * When returning from interrupt to user space,
 123  * there is chance to reschedule */
 124 static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
 125 {
 126         unsigned int cpu = smp_processor_id();
 127
 128         platform_clear_ipi(cpu, IRQ_SUPPLE_0);
 129         return IRQ_HANDLED;
 130 }
 131
 132 DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
 133 void ipi_timer(void)
 134 {
 135         int cpu = smp_processor_id();
 136         struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
 137         evt->event_handler(evt);
 138 }
 139
 140 static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
 141 {
 142         struct ipi_data *bfin_ipi_data;
 143         unsigned int cpu = smp_processor_id();
 144         unsigned long pending;
 145         unsigned long msg;
 146
 147         platform_clear_ipi(cpu, IRQ_SUPPLE_1);
 148
 149         smp_rmb();
 150         bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
 151         while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
 152                 msg = 0;
 153                 do {
 154                         msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
 155                         switch (msg) {
 156                         case BFIN_IPI_TIMER:
 157                                 ipi_timer();
 158                                 break;
 159                         case BFIN_IPI_RESCHEDULE:
 160                                 scheduler_ipi();
 161                                 break;
 162                         case BFIN_IPI_CALL_FUNC:
 163                                 generic_smp_call_function_interrupt();
 164                                 break;
 165                         case BFIN_IPI_CPU_STOP:
 166                                 ipi_cpu_stop(cpu);
 167                                 break;
 168                         default:
 169                                 goto out;
 170                         }
 171                         atomic_dec(&bfin_ipi_data->count);
 172                 } while (msg < BITS_PER_LONG);
 173
 174         }
 175 out:
 176         return IRQ_HANDLED;
 177 }
 178
 179 static void bfin_ipi_init(void)
 180 {
 181         unsigned int cpu;
 182         struct ipi_data *bfin_ipi_data;
 183         for_each_possible_cpu(cpu) {
 184                 bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
 185                 atomic_set(&bfin_ipi_data->bits, 0);
 186                 atomic_set(&bfin_ipi_data->count, 0);
 187         }
 188 }
 189
 190 void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
 191 {
 192         unsigned int cpu;
 193         struct ipi_data *bfin_ipi_data;
 194         unsigned long flags;
 195
 196         local_irq_save(flags);
 197         for_each_cpu(cpu, cpumask) {
 198                 bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
 199                 atomic_or((1 << msg), &bfin_ipi_data->bits);
 200                 atomic_inc(&bfin_ipi_data->count);
 201         }
 202         local_irq_restore(flags);
 203         smp_wmb();
 204         for_each_cpu(cpu, cpumask)
 205                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
 206 }
 207
 208 void arch_send_call_function_single_ipi(int cpu)
 209 {
 210         send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
 211 }
 212
 213 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 214 {
 215         send_ipi(mask, BFIN_IPI_CALL_FUNC);
 216 }
 217
 218 void smp_send_reschedule(int cpu)
 219 {
 220         send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);
 221
 222         return;
 223 }
 224
 225 void smp_send_msg(const struct cpumask *mask, unsigned long type)
 226 {
 227         send_ipi(mask, type);
 228 }
 229
 230 void smp_timer_broadcast(const struct cpumask *mask)
 231 {
 232         smp_send_msg(mask, BFIN_IPI_TIMER);
 233 }
 234
 235 void smp_send_stop(void)
 236 {
 237         cpumask_t callmap;
 238
 239         preempt_disable();
 240         cpumask_copy(&callmap, cpu_online_mask);
 241         cpumask_clear_cpu(smp_processor_id(), &callmap);
 242         if (!cpumask_empty(&callmap))
 243                 send_ipi(&callmap, BFIN_IPI_CPU_STOP);
 244
 245         preempt_enable();
 246
 247         return;
 248 }
 249
 250 int __cpu_up(unsigned int cpu, struct task_struct *idle)
 251 {
 252         int ret;
 253
 254         secondary_stack = task_stack_page(idle) + THREAD_SIZE;
 255
 256         ret = platform_boot_secondary(cpu, idle);
 257
 258         secondary_stack = NULL;
 259
 260         return ret;
 261 }
 262
 263 static void setup_secondary(unsigned int cpu)
 264 {
 265         unsigned long ilat;
 266
 267         bfin_write_IMASK(0);
 268         CSYNC();
 269         ilat = bfin_read_ILAT();
 270         CSYNC();
 271         bfin_write_ILAT(ilat);
 272         CSYNC();
 273
 274         /* Enable interrupt levels IVG7-15. IARs have been already
 275          * programmed by the boot CPU.  */
 276         bfin_irq_flags |= IMASK_IVG15 |
 277             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
 278             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 279 }
 280
 281 void secondary_start_kernel(void)
 282 {
 283         unsigned int cpu = smp_processor_id();
 284         struct mm_struct *mm = &init_mm;
 285
 286         if (_bfin_swrst & SWRST_DBL_FAULT_B) {
 287                 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
 288 #ifdef CONFIG_DEBUG_DOUBLEFAULT
 289                 printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
 290                         initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
 291                         initial_pda_coreb.retx_doublefault);
 292                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n",
 293                         initial_pda_coreb.dcplb_doublefault_addr);
 294                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n",
 295                         initial_pda_coreb.icplb_doublefault_addr);
 296 #endif
 297                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
 298                         initial_pda_coreb.retx);
 299         }
 300
 301         /*
 302          * We want the D-cache to be enabled early, in case the atomic
 303          * support code emulates cache coherence (see
 304          * __ARCH_SYNC_CORE_DCACHE).
 305          */
 306         init_exception_vectors();
 307
 308         local_irq_disable();
 309
 310         /* Attach the new idle task to the global mm. */
 311         mmget(mm);
 312         mmgrab(mm);
 313         current->active_mm = mm;
 314
 315         preempt_disable();
 316
 317         setup_secondary(cpu);
 318
 319         platform_secondary_init(cpu);
 320         /* setup local core timer */
 321         bfin_local_timer_setup();
 322
 323         local_irq_enable();
 324
 325         bfin_setup_caches(cpu);
 326
 327         notify_cpu_starting(cpu);
 328         /*
 329          * Calibrate loops per jiffy value.
 330          * IRQs need to be enabled here - D-cache can be invalidated
 331          * in timer irq handler, so core B can read correct jiffies.
 332          */
 333         calibrate_delay();
 334
 335         /* We are done with local CPU inits, unblock the boot CPU. */
 336         set_cpu_online(cpu, true);
 337         cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
 338 }
 339
 340 void __init smp_prepare_boot_cpu(void)
 341 {
 342 }
 343
 344 void __init smp_prepare_cpus(unsigned int max_cpus)
 345 {
 346         platform_prepare_cpus(max_cpus);
 347         bfin_ipi_init();
 348         platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
 349         platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
 350 }
 351
 352 void __init smp_cpus_done(unsigned int max_cpus)
 353 {
 354         unsigned long bogosum = 0;
 355         unsigned int cpu;
 356
 357         for_each_online_cpu(cpu)
 358                 bogosum += loops_per_jiffy;
 359
 360         printk(KERN_INFO "SMP: Total of %d processors activated "
 361                "(%lu.%02lu BogoMIPS).\n",
 362                num_online_cpus(),
 363                bogosum / (500000/HZ),
 364                (bogosum / (5000/HZ)) % 100);
 365 }
 366
 367 void smp_icache_flush_range_others(unsigned long start, unsigned long end)
 368 {
 369         smp_flush_data.start = start;
 370         smp_flush_data.end = end;
 371
 372         preempt_disable();
 373         if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
 374                 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
 375         preempt_enable();
 376 }
 377 EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
 378
 379 #ifdef __ARCH_SYNC_CORE_ICACHE
 380 unsigned long icache_invld_count[NR_CPUS];
 381 void resync_core_icache(void)
 382 {
 383         unsigned int cpu = get_cpu();
 384         blackfin_invalidate_entire_icache();
 385         icache_invld_count[cpu]++;
 386         put_cpu();
 387 }
 388 EXPORT_SYMBOL(resync_core_icache);
 389 #endif
 390
 391 #ifdef __ARCH_SYNC_CORE_DCACHE
 392 unsigned long dcache_invld_count[NR_CPUS];
 393 unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
 394
 395 void resync_core_dcache(void)
 396 {
 397         unsigned int cpu = get_cpu();
 398         blackfin_invalidate_entire_dcache();
 399         dcache_invld_count[cpu]++;
 400         put_cpu();
 401 }
 402 EXPORT_SYMBOL(resync_core_dcache);
 403 #endif
 404
 405 #ifdef CONFIG_HOTPLUG_CPU
 406 int __cpu_disable(void)
 407 {
 408         unsigned int cpu = smp_processor_id();
 409
 410         if (cpu == 0)
 411                 return -EPERM;
 412
 413         set_cpu_online(cpu, false);
 414         return 0;
 415 }
 416
 417 int __cpu_die(unsigned int cpu)
 418 {
 419         return cpu_wait_death(cpu, 5);
 420 }
 421
 422 void cpu_die(void)
 423 {
 424         (void)cpu_report_death();
 425
 426         atomic_dec(&init_mm.mm_users);
 427         atomic_dec(&init_mm.mm_count);
 428
 429         local_irq_disable();
 430         platform_cpu_die();
 431 }
 432 #endif