arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
  12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
  13 #include <dt-bindings/dma/qcom-gpi.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16 #include <dt-bindings/interconnect/qcom,sm8250.h>
  17 #include <dt-bindings/mailbox/qcom-ipcc.h>
  18 #include <dt-bindings/phy/phy-qcom-qmp.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/power/qcom,rpmhpd.h>
  21 #include <dt-bindings/soc/qcom,apr.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/sound/qcom,q6afe.h>
  24 #include <dt-bindings/thermal/thermal.h>
  25 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
  26 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
  27
  28 / {
  29         interrupt-parent = <&intc>;
  30
  31         #address-cells = <2>;
  32         #size-cells = <2>;
  33
  34         aliases {
  35                 i2c0 = &i2c0;
  36                 i2c1 = &i2c1;
  37                 i2c2 = &i2c2;
  38                 i2c3 = &i2c3;
  39                 i2c4 = &i2c4;
  40                 i2c5 = &i2c5;
  41                 i2c6 = &i2c6;
  42                 i2c7 = &i2c7;
  43                 i2c8 = &i2c8;
  44                 i2c9 = &i2c9;
  45                 i2c10 = &i2c10;
  46                 i2c11 = &i2c11;
  47                 i2c12 = &i2c12;
  48                 i2c13 = &i2c13;
  49                 i2c14 = &i2c14;
  50                 i2c15 = &i2c15;
  51                 i2c16 = &i2c16;
  52                 i2c17 = &i2c17;
  53                 i2c18 = &i2c18;
  54                 i2c19 = &i2c19;
  55                 spi0 = &spi0;
  56                 spi1 = &spi1;
  57                 spi2 = &spi2;
  58                 spi3 = &spi3;
  59                 spi4 = &spi4;
  60                 spi5 = &spi5;
  61                 spi6 = &spi6;
  62                 spi7 = &spi7;
  63                 spi8 = &spi8;
  64                 spi9 = &spi9;
  65                 spi10 = &spi10;
  66                 spi11 = &spi11;
  67                 spi12 = &spi12;
  68                 spi13 = &spi13;
  69                 spi14 = &spi14;
  70                 spi15 = &spi15;
  71                 spi16 = &spi16;
  72                 spi17 = &spi17;
  73                 spi18 = &spi18;
  74                 spi19 = &spi19;
  75         };
  76
  77         chosen { };
  78
  79         clocks {
  80                 xo_board: xo-board {
  81                         compatible = "fixed-clock";
  82                         #clock-cells = <0>;
  83                         clock-frequency = <38400000>;
  84                         clock-output-names = "xo_board";
  85                 };
  86
  87                 sleep_clk: sleep-clk {
  88                         compatible = "fixed-clock";
  89                         clock-frequency = <32768>;
  90                         #clock-cells = <0>;
  91                 };
  92         };
  93
  94         cpus {
  95                 #address-cells = <2>;
  96                 #size-cells = <0>;
  97
  98                 CPU0: cpu@0 {
  99                         device_type = "cpu";
 100                         compatible = "qcom,kryo485";
 101                         reg = <0x0 0x0>;
 102                         clocks = <&cpufreq_hw 0>;
 103                         enable-method = "psci";
 104                         capacity-dmips-mhz = <448>;
 105                         dynamic-power-coefficient = <105>;
 106                         next-level-cache = <&L2_0>;
 107                         power-domains = <&CPU_PD0>;
 108                         power-domain-names = "psci";
 109                         qcom,freq-domain = <&cpufreq_hw 0>;
 110                         operating-points-v2 = <&cpu0_opp_table>;
 111                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 112                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 113                         #cooling-cells = <2>;
 114                         L2_0: l2-cache {
 115                                 compatible = "cache";
 116                                 cache-level = <2>;
 117                                 cache-size = <0x20000>;
 118                                 cache-unified;
 119                                 next-level-cache = <&L3_0>;
 120                                 L3_0: l3-cache {
 121                                         compatible = "cache";
 122                                         cache-level = <3>;
 123                                         cache-size = <0x400000>;
 124                                         cache-unified;
 125                                 };
 126                         };
 127                 };
 128
 129                 CPU1: cpu@100 {
 130                         device_type = "cpu";
 131                         compatible = "qcom,kryo485";
 132                         reg = <0x0 0x100>;
 133                         clocks = <&cpufreq_hw 0>;
 134                         enable-method = "psci";
 135                         capacity-dmips-mhz = <448>;
 136                         dynamic-power-coefficient = <105>;
 137                         next-level-cache = <&L2_100>;
 138                         power-domains = <&CPU_PD1>;
 139                         power-domain-names = "psci";
 140                         qcom,freq-domain = <&cpufreq_hw 0>;
 141                         operating-points-v2 = <&cpu0_opp_table>;
 142                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 143                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 144                         #cooling-cells = <2>;
 145                         L2_100: l2-cache {
 146                                 compatible = "cache";
 147                                 cache-level = <2>;
 148                                 cache-size = <0x20000>;
 149                                 cache-unified;
 150                                 next-level-cache = <&L3_0>;
 151                         };
 152                 };
 153
 154                 CPU2: cpu@200 {
 155                         device_type = "cpu";
 156                         compatible = "qcom,kryo485";
 157                         reg = <0x0 0x200>;
 158                         clocks = <&cpufreq_hw 0>;
 159                         enable-method = "psci";
 160                         capacity-dmips-mhz = <448>;
 161                         dynamic-power-coefficient = <105>;
 162                         next-level-cache = <&L2_200>;
 163                         power-domains = <&CPU_PD2>;
 164                         power-domain-names = "psci";
 165                         qcom,freq-domain = <&cpufreq_hw 0>;
 166                         operating-points-v2 = <&cpu0_opp_table>;
 167                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 168                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 169                         #cooling-cells = <2>;
 170                         L2_200: l2-cache {
 171                                 compatible = "cache";
 172                                 cache-level = <2>;
 173                                 cache-size = <0x20000>;
 174                                 cache-unified;
 175                                 next-level-cache = <&L3_0>;
 176                         };
 177                 };
 178
 179                 CPU3: cpu@300 {
 180                         device_type = "cpu";
 181                         compatible = "qcom,kryo485";
 182                         reg = <0x0 0x300>;
 183                         clocks = <&cpufreq_hw 0>;
 184                         enable-method = "psci";
 185                         capacity-dmips-mhz = <448>;
 186                         dynamic-power-coefficient = <105>;
 187                         next-level-cache = <&L2_300>;
 188                         power-domains = <&CPU_PD3>;
 189                         power-domain-names = "psci";
 190                         qcom,freq-domain = <&cpufreq_hw 0>;
 191                         operating-points-v2 = <&cpu0_opp_table>;
 192                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 193                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 194                         #cooling-cells = <2>;
 195                         L2_300: l2-cache {
 196                                 compatible = "cache";
 197                                 cache-level = <2>;
 198                                 cache-size = <0x20000>;
 199                                 cache-unified;
 200                                 next-level-cache = <&L3_0>;
 201                         };
 202                 };
 203
 204                 CPU4: cpu@400 {
 205                         device_type = "cpu";
 206                         compatible = "qcom,kryo485";
 207                         reg = <0x0 0x400>;
 208                         clocks = <&cpufreq_hw 1>;
 209                         enable-method = "psci";
 210                         capacity-dmips-mhz = <1024>;
 211                         dynamic-power-coefficient = <379>;
 212                         next-level-cache = <&L2_400>;
 213                         power-domains = <&CPU_PD4>;
 214                         power-domain-names = "psci";
 215                         qcom,freq-domain = <&cpufreq_hw 1>;
 216                         operating-points-v2 = <&cpu4_opp_table>;
 217                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 218                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 219                         #cooling-cells = <2>;
 220                         L2_400: l2-cache {
 221                                 compatible = "cache";
 222                                 cache-level = <2>;
 223                                 cache-size = <0x40000>;
 224                                 cache-unified;
 225                                 next-level-cache = <&L3_0>;
 226                         };
 227                 };
 228
 229                 CPU5: cpu@500 {
 230                         device_type = "cpu";
 231                         compatible = "qcom,kryo485";
 232                         reg = <0x0 0x500>;
 233                         clocks = <&cpufreq_hw 1>;
 234                         enable-method = "psci";
 235                         capacity-dmips-mhz = <1024>;
 236                         dynamic-power-coefficient = <379>;
 237                         next-level-cache = <&L2_500>;
 238                         power-domains = <&CPU_PD5>;
 239                         power-domain-names = "psci";
 240                         qcom,freq-domain = <&cpufreq_hw 1>;
 241                         operating-points-v2 = <&cpu4_opp_table>;
 242                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 243                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 244                         #cooling-cells = <2>;
 245                         L2_500: l2-cache {
 246                                 compatible = "cache";
 247                                 cache-level = <2>;
 248                                 cache-size = <0x40000>;
 249                                 cache-unified;
 250                                 next-level-cache = <&L3_0>;
 251                         };
 252                 };
 253
 254                 CPU6: cpu@600 {
 255                         device_type = "cpu";
 256                         compatible = "qcom,kryo485";
 257                         reg = <0x0 0x600>;
 258                         clocks = <&cpufreq_hw 1>;
 259                         enable-method = "psci";
 260                         capacity-dmips-mhz = <1024>;
 261                         dynamic-power-coefficient = <379>;
 262                         next-level-cache = <&L2_600>;
 263                         power-domains = <&CPU_PD6>;
 264                         power-domain-names = "psci";
 265                         qcom,freq-domain = <&cpufreq_hw 1>;
 266                         operating-points-v2 = <&cpu4_opp_table>;
 267                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 268                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 269                         #cooling-cells = <2>;
 270                         L2_600: l2-cache {
 271                                 compatible = "cache";
 272                                 cache-level = <2>;
 273                                 cache-size = <0x40000>;
 274                                 cache-unified;
 275                                 next-level-cache = <&L3_0>;
 276                         };
 277                 };
 278
 279                 CPU7: cpu@700 {
 280                         device_type = "cpu";
 281                         compatible = "qcom,kryo485";
 282                         reg = <0x0 0x700>;
 283                         clocks = <&cpufreq_hw 2>;
 284                         enable-method = "psci";
 285                         capacity-dmips-mhz = <1024>;
 286                         dynamic-power-coefficient = <444>;
 287                         next-level-cache = <&L2_700>;
 288                         power-domains = <&CPU_PD7>;
 289                         power-domain-names = "psci";
 290                         qcom,freq-domain = <&cpufreq_hw 2>;
 291                         operating-points-v2 = <&cpu7_opp_table>;
 292                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 293                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 294                         #cooling-cells = <2>;
 295                         L2_700: l2-cache {
 296                                 compatible = "cache";
 297                                 cache-level = <2>;
 298                                 cache-size = <0x80000>;
 299                                 cache-unified;
 300                                 next-level-cache = <&L3_0>;
 301                         };
 302                 };
 303
 304                 cpu-map {
 305                         cluster0 {
 306                                 core0 {
 307                                         cpu = <&CPU0>;
 308                                 };
 309
 310                                 core1 {
 311                                         cpu = <&CPU1>;
 312                                 };
 313
 314                                 core2 {
 315                                         cpu = <&CPU2>;
 316                                 };
 317
 318                                 core3 {
 319                                         cpu = <&CPU3>;
 320                                 };
 321
 322                                 core4 {
 323                                         cpu = <&CPU4>;
 324                                 };
 325
 326                                 core5 {
 327                                         cpu = <&CPU5>;
 328                                 };
 329
 330                                 core6 {
 331                                         cpu = <&CPU6>;
 332                                 };
 333
 334                                 core7 {
 335                                         cpu = <&CPU7>;
 336                                 };
 337                         };
 338                 };
 339
 340                 idle-states {
 341                         entry-method = "psci";
 342
 343                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 344                                 compatible = "arm,idle-state";
 345                                 idle-state-name = "silver-rail-power-collapse";
 346                                 arm,psci-suspend-param = <0x40000004>;
 347                                 entry-latency-us = <360>;
 348                                 exit-latency-us = <531>;
 349                                 min-residency-us = <3934>;
 350                                 local-timer-stop;
 351                         };
 352
 353                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 354                                 compatible = "arm,idle-state";
 355                                 idle-state-name = "gold-rail-power-collapse";
 356                                 arm,psci-suspend-param = <0x40000004>;
 357                                 entry-latency-us = <702>;
 358                                 exit-latency-us = <1061>;
 359                                 min-residency-us = <4488>;
 360                                 local-timer-stop;
 361                         };
 362                 };
 363
 364                 domain-idle-states {
 365                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 366                                 compatible = "domain-idle-state";
 367                                 arm,psci-suspend-param = <0x4100c244>;
 368                                 entry-latency-us = <3264>;
 369                                 exit-latency-us = <6562>;
 370                                 min-residency-us = <9987>;
 371                         };
 372                 };
 373         };
 374
 375         qup_virt: interconnect-qup-virt {
 376                 compatible = "qcom,sm8250-qup-virt";
 377                 #interconnect-cells = <2>;
 378                 qcom,bcm-voters = <&apps_bcm_voter>;
 379         };
 380
 381         cpu0_opp_table: opp-table-cpu0 {
 382                 compatible = "operating-points-v2";
 383                 opp-shared;
 384
 385                 cpu0_opp1: opp-300000000 {
 386                         opp-hz = /bits/ 64 <300000000>;
 387                         opp-peak-kBps = <800000 9600000>;
 388                 };
 389
 390                 cpu0_opp2: opp-403200000 {
 391                         opp-hz = /bits/ 64 <403200000>;
 392                         opp-peak-kBps = <800000 9600000>;
 393                 };
 394
 395                 cpu0_opp3: opp-518400000 {
 396                         opp-hz = /bits/ 64 <518400000>;
 397                         opp-peak-kBps = <800000 16588800>;
 398                 };
 399
 400                 cpu0_opp4: opp-614400000 {
 401                         opp-hz = /bits/ 64 <614400000>;
 402                         opp-peak-kBps = <800000 16588800>;
 403                 };
 404
 405                 cpu0_opp5: opp-691200000 {
 406                         opp-hz = /bits/ 64 <691200000>;
 407                         opp-peak-kBps = <800000 19660800>;
 408                 };
 409
 410                 cpu0_opp6: opp-787200000 {
 411                         opp-hz = /bits/ 64 <787200000>;
 412                         opp-peak-kBps = <1804000 19660800>;
 413                 };
 414
 415                 cpu0_opp7: opp-883200000 {
 416                         opp-hz = /bits/ 64 <883200000>;
 417                         opp-peak-kBps = <1804000 23347200>;
 418                 };
 419
 420                 cpu0_opp8: opp-979200000 {
 421                         opp-hz = /bits/ 64 <979200000>;
 422                         opp-peak-kBps = <1804000 26419200>;
 423                 };
 424
 425                 cpu0_opp9: opp-1075200000 {
 426                         opp-hz = /bits/ 64 <1075200000>;
 427                         opp-peak-kBps = <1804000 29491200>;
 428                 };
 429
 430                 cpu0_opp10: opp-1171200000 {
 431                         opp-hz = /bits/ 64 <1171200000>;
 432                         opp-peak-kBps = <1804000 32563200>;
 433                 };
 434
 435                 cpu0_opp11: opp-1248000000 {
 436                         opp-hz = /bits/ 64 <1248000000>;
 437                         opp-peak-kBps = <1804000 36249600>;
 438                 };
 439
 440                 cpu0_opp12: opp-1344000000 {
 441                         opp-hz = /bits/ 64 <1344000000>;
 442                         opp-peak-kBps = <2188000 36249600>;
 443                 };
 444
 445                 cpu0_opp13: opp-1420800000 {
 446                         opp-hz = /bits/ 64 <1420800000>;
 447                         opp-peak-kBps = <2188000 39321600>;
 448                 };
 449
 450                 cpu0_opp14: opp-1516800000 {
 451                         opp-hz = /bits/ 64 <1516800000>;
 452                         opp-peak-kBps = <3072000 42393600>;
 453                 };
 454
 455                 cpu0_opp15: opp-1612800000 {
 456                         opp-hz = /bits/ 64 <1612800000>;
 457                         opp-peak-kBps = <3072000 42393600>;
 458                 };
 459
 460                 cpu0_opp16: opp-1708800000 {
 461                         opp-hz = /bits/ 64 <1708800000>;
 462                         opp-peak-kBps = <4068000 42393600>;
 463                 };
 464
 465                 cpu0_opp17: opp-1804800000 {
 466                         opp-hz = /bits/ 64 <1804800000>;
 467                         opp-peak-kBps = <4068000 42393600>;
 468                 };
 469         };
 470
 471         cpu4_opp_table: opp-table-cpu4 {
 472                 compatible = "operating-points-v2";
 473                 opp-shared;
 474
 475                 cpu4_opp1: opp-710400000 {
 476                         opp-hz = /bits/ 64 <710400000>;
 477                         opp-peak-kBps = <1804000 19660800>;
 478                 };
 479
 480                 cpu4_opp2: opp-825600000 {
 481                         opp-hz = /bits/ 64 <825600000>;
 482                         opp-peak-kBps = <2188000 23347200>;
 483                 };
 484
 485                 cpu4_opp3: opp-940800000 {
 486                         opp-hz = /bits/ 64 <940800000>;
 487                         opp-peak-kBps = <2188000 26419200>;
 488                 };
 489
 490                 cpu4_opp4: opp-1056000000 {
 491                         opp-hz = /bits/ 64 <1056000000>;
 492                         opp-peak-kBps = <3072000 26419200>;
 493                 };
 494
 495                 cpu4_opp5: opp-1171200000 {
 496                         opp-hz = /bits/ 64 <1171200000>;
 497                         opp-peak-kBps = <3072000 29491200>;
 498                 };
 499
 500                 cpu4_opp6: opp-1286400000 {
 501                         opp-hz = /bits/ 64 <1286400000>;
 502                         opp-peak-kBps = <4068000 29491200>;
 503                 };
 504
 505                 cpu4_opp7: opp-1382400000 {
 506                         opp-hz = /bits/ 64 <1382400000>;
 507                         opp-peak-kBps = <4068000 32563200>;
 508                 };
 509
 510                 cpu4_opp8: opp-1478400000 {
 511                         opp-hz = /bits/ 64 <1478400000>;
 512                         opp-peak-kBps = <4068000 32563200>;
 513                 };
 514
 515                 cpu4_opp9: opp-1574400000 {
 516                         opp-hz = /bits/ 64 <1574400000>;
 517                         opp-peak-kBps = <5412000 39321600>;
 518                 };
 519
 520                 cpu4_opp10: opp-1670400000 {
 521                         opp-hz = /bits/ 64 <1670400000>;
 522                         opp-peak-kBps = <5412000 42393600>;
 523                 };
 524
 525                 cpu4_opp11: opp-1766400000 {
 526                         opp-hz = /bits/ 64 <1766400000>;
 527                         opp-peak-kBps = <5412000 45465600>;
 528                 };
 529
 530                 cpu4_opp12: opp-1862400000 {
 531                         opp-hz = /bits/ 64 <1862400000>;
 532                         opp-peak-kBps = <6220000 45465600>;
 533                 };
 534
 535                 cpu4_opp13: opp-1958400000 {
 536                         opp-hz = /bits/ 64 <1958400000>;
 537                         opp-peak-kBps = <6220000 48537600>;
 538                 };
 539
 540                 cpu4_opp14: opp-2054400000 {
 541                         opp-hz = /bits/ 64 <2054400000>;
 542                         opp-peak-kBps = <7216000 48537600>;
 543                 };
 544
 545                 cpu4_opp15: opp-2150400000 {
 546                         opp-hz = /bits/ 64 <2150400000>;
 547                         opp-peak-kBps = <7216000 51609600>;
 548                 };
 549
 550                 cpu4_opp16: opp-2246400000 {
 551                         opp-hz = /bits/ 64 <2246400000>;
 552                         opp-peak-kBps = <7216000 51609600>;
 553                 };
 554
 555                 cpu4_opp17: opp-2342400000 {
 556                         opp-hz = /bits/ 64 <2342400000>;
 557                         opp-peak-kBps = <8368000 51609600>;
 558                 };
 559
 560                 cpu4_opp18: opp-2419200000 {
 561                         opp-hz = /bits/ 64 <2419200000>;
 562                         opp-peak-kBps = <8368000 51609600>;
 563                 };
 564         };
 565
 566         cpu7_opp_table: opp-table-cpu7 {
 567                 compatible = "operating-points-v2";
 568                 opp-shared;
 569
 570                 cpu7_opp1: opp-844800000 {
 571                         opp-hz = /bits/ 64 <844800000>;
 572                         opp-peak-kBps = <2188000 19660800>;
 573                 };
 574
 575                 cpu7_opp2: opp-960000000 {
 576                         opp-hz = /bits/ 64 <960000000>;
 577                         opp-peak-kBps = <2188000 26419200>;
 578                 };
 579
 580                 cpu7_opp3: opp-1075200000 {
 581                         opp-hz = /bits/ 64 <1075200000>;
 582                         opp-peak-kBps = <3072000 26419200>;
 583                 };
 584
 585                 cpu7_opp4: opp-1190400000 {
 586                         opp-hz = /bits/ 64 <1190400000>;
 587                         opp-peak-kBps = <3072000 29491200>;
 588                 };
 589
 590                 cpu7_opp5: opp-1305600000 {
 591                         opp-hz = /bits/ 64 <1305600000>;
 592                         opp-peak-kBps = <4068000 32563200>;
 593                 };
 594
 595                 cpu7_opp6: opp-1401600000 {
 596                         opp-hz = /bits/ 64 <1401600000>;
 597                         opp-peak-kBps = <4068000 32563200>;
 598                 };
 599
 600                 cpu7_opp7: opp-1516800000 {
 601                         opp-hz = /bits/ 64 <1516800000>;
 602                         opp-peak-kBps = <4068000 36249600>;
 603                 };
 604
 605                 cpu7_opp8: opp-1632000000 {
 606                         opp-hz = /bits/ 64 <1632000000>;
 607                         opp-peak-kBps = <5412000 39321600>;
 608                 };
 609
 610                 cpu7_opp9: opp-1747200000 {
 611                         opp-hz = /bits/ 64 <1708800000>;
 612                         opp-peak-kBps = <5412000 42393600>;
 613                 };
 614
 615                 cpu7_opp10: opp-1862400000 {
 616                         opp-hz = /bits/ 64 <1862400000>;
 617                         opp-peak-kBps = <6220000 45465600>;
 618                 };
 619
 620                 cpu7_opp11: opp-1977600000 {
 621                         opp-hz = /bits/ 64 <1977600000>;
 622                         opp-peak-kBps = <6220000 48537600>;
 623                 };
 624
 625                 cpu7_opp12: opp-2073600000 {
 626                         opp-hz = /bits/ 64 <2073600000>;
 627                         opp-peak-kBps = <7216000 48537600>;
 628                 };
 629
 630                 cpu7_opp13: opp-2169600000 {
 631                         opp-hz = /bits/ 64 <2169600000>;
 632                         opp-peak-kBps = <7216000 51609600>;
 633                 };
 634
 635                 cpu7_opp14: opp-2265600000 {
 636                         opp-hz = /bits/ 64 <2265600000>;
 637                         opp-peak-kBps = <7216000 51609600>;
 638                 };
 639
 640                 cpu7_opp15: opp-2361600000 {
 641                         opp-hz = /bits/ 64 <2361600000>;
 642                         opp-peak-kBps = <8368000 51609600>;
 643                 };
 644
 645                 cpu7_opp16: opp-2457600000 {
 646                         opp-hz = /bits/ 64 <2457600000>;
 647                         opp-peak-kBps = <8368000 51609600>;
 648                 };
 649
 650                 cpu7_opp17: opp-2553600000 {
 651                         opp-hz = /bits/ 64 <2553600000>;
 652                         opp-peak-kBps = <8368000 51609600>;
 653                 };
 654
 655                 cpu7_opp18: opp-2649600000 {
 656                         opp-hz = /bits/ 64 <2649600000>;
 657                         opp-peak-kBps = <8368000 51609600>;
 658                 };
 659
 660                 cpu7_opp19: opp-2745600000 {
 661                         opp-hz = /bits/ 64 <2745600000>;
 662                         opp-peak-kBps = <8368000 51609600>;
 663                 };
 664
 665                 cpu7_opp20: opp-2841600000 {
 666                         opp-hz = /bits/ 64 <2841600000>;
 667                         opp-peak-kBps = <8368000 51609600>;
 668                 };
 669         };
 670
 671         firmware {
 672                 scm: scm {
 673                         compatible = "qcom,scm-sm8250", "qcom,scm";
 674                         qcom,dload-mode = <&tcsr 0x13000>;
 675                         #reset-cells = <1>;
 676                 };
 677         };
 678
 679         memory@80000000 {
 680                 device_type = "memory";
 681                 /* We expect the bootloader to fill in the size */
 682                 reg = <0x0 0x80000000 0x0 0x0>;
 683         };
 684
 685         pmu {
 686                 compatible = "arm,armv8-pmuv3";
 687                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 688         };
 689
 690         psci {
 691                 compatible = "arm,psci-1.0";
 692                 method = "smc";
 693
 694                 CPU_PD0: power-domain-cpu0 {
 695                         #power-domain-cells = <0>;
 696                         power-domains = <&CLUSTER_PD>;
 697                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 698                 };
 699
 700                 CPU_PD1: power-domain-cpu1 {
 701                         #power-domain-cells = <0>;
 702                         power-domains = <&CLUSTER_PD>;
 703                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 704                 };
 705
 706                 CPU_PD2: power-domain-cpu2 {
 707                         #power-domain-cells = <0>;
 708                         power-domains = <&CLUSTER_PD>;
 709                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 710                 };
 711
 712                 CPU_PD3: power-domain-cpu3 {
 713                         #power-domain-cells = <0>;
 714                         power-domains = <&CLUSTER_PD>;
 715                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 716                 };
 717
 718                 CPU_PD4: power-domain-cpu4 {
 719                         #power-domain-cells = <0>;
 720                         power-domains = <&CLUSTER_PD>;
 721                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 722                 };
 723
 724                 CPU_PD5: power-domain-cpu5 {
 725                         #power-domain-cells = <0>;
 726                         power-domains = <&CLUSTER_PD>;
 727                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 728                 };
 729
 730                 CPU_PD6: power-domain-cpu6 {
 731                         #power-domain-cells = <0>;
 732                         power-domains = <&CLUSTER_PD>;
 733                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 734                 };
 735
 736                 CPU_PD7: power-domain-cpu7 {
 737                         #power-domain-cells = <0>;
 738                         power-domains = <&CLUSTER_PD>;
 739                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 740                 };
 741
 742                 CLUSTER_PD: power-domain-cpu-cluster0 {
 743                         #power-domain-cells = <0>;
 744                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 745                 };
 746         };
 747
 748         qup_opp_table: opp-table-qup {
 749                 compatible = "operating-points-v2";
 750
 751                 opp-50000000 {
 752                         opp-hz = /bits/ 64 <50000000>;
 753                         required-opps = <&rpmhpd_opp_min_svs>;
 754                 };
 755
 756                 opp-75000000 {
 757                         opp-hz = /bits/ 64 <75000000>;
 758                         required-opps = <&rpmhpd_opp_low_svs>;
 759                 };
 760
 761                 opp-120000000 {
 762                         opp-hz = /bits/ 64 <120000000>;
 763                         required-opps = <&rpmhpd_opp_svs>;
 764                 };
 765         };
 766
 767         reserved-memory {
 768                 #address-cells = <2>;
 769                 #size-cells = <2>;
 770                 ranges;
 771
 772                 hyp_mem: memory@80000000 {
 773                         reg = <0x0 0x80000000 0x0 0x600000>;
 774                         no-map;
 775                 };
 776
 777                 xbl_aop_mem: memory@80700000 {
 778                         reg = <0x0 0x80700000 0x0 0x160000>;
 779                         no-map;
 780                 };
 781
 782                 cmd_db: memory@80860000 {
 783                         compatible = "qcom,cmd-db";
 784                         reg = <0x0 0x80860000 0x0 0x20000>;
 785                         no-map;
 786                 };
 787
 788                 smem_mem: memory@80900000 {
 789                         reg = <0x0 0x80900000 0x0 0x200000>;
 790                         no-map;
 791                 };
 792
 793                 removed_mem: memory@80b00000 {
 794                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 795                         no-map;
 796                 };
 797
 798                 camera_mem: memory@86200000 {
 799                         reg = <0x0 0x86200000 0x0 0x500000>;
 800                         no-map;
 801                 };
 802
 803                 wlan_mem: memory@86700000 {
 804                         reg = <0x0 0x86700000 0x0 0x100000>;
 805                         no-map;
 806                 };
 807
 808                 ipa_fw_mem: memory@86800000 {
 809                         reg = <0x0 0x86800000 0x0 0x10000>;
 810                         no-map;
 811                 };
 812
 813                 ipa_gsi_mem: memory@86810000 {
 814                         reg = <0x0 0x86810000 0x0 0xa000>;
 815                         no-map;
 816                 };
 817
 818                 gpu_mem: memory@8681a000 {
 819                         reg = <0x0 0x8681a000 0x0 0x2000>;
 820                         no-map;
 821                 };
 822
 823                 npu_mem: memory@86900000 {
 824                         reg = <0x0 0x86900000 0x0 0x500000>;
 825                         no-map;
 826                 };
 827
 828                 video_mem: memory@86e00000 {
 829                         reg = <0x0 0x86e00000 0x0 0x500000>;
 830                         no-map;
 831                 };
 832
 833                 cvp_mem: memory@87300000 {
 834                         reg = <0x0 0x87300000 0x0 0x500000>;
 835                         no-map;
 836                 };
 837
 838                 cdsp_mem: memory@87800000 {
 839                         reg = <0x0 0x87800000 0x0 0x1400000>;
 840                         no-map;
 841                 };
 842
 843                 slpi_mem: memory@88c00000 {
 844                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 845                         no-map;
 846                 };
 847
 848                 adsp_mem: memory@8a100000 {
 849                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 850                         no-map;
 851                 };
 852
 853                 spss_mem: memory@8be00000 {
 854                         reg = <0x0 0x8be00000 0x0 0x100000>;
 855                         no-map;
 856                 };
 857
 858                 cdsp_secure_heap: memory@8bf00000 {
 859                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 860                         no-map;
 861                 };
 862         };
 863
 864         smem {
 865                 compatible = "qcom,smem";
 866                 memory-region = <&smem_mem>;
 867                 hwlocks = <&tcsr_mutex 3>;
 868         };
 869
 870         smp2p-adsp {
 871                 compatible = "qcom,smp2p";
 872                 qcom,smem = <443>, <429>;
 873                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 874                                              IPCC_MPROC_SIGNAL_SMP2P
 875                                              IRQ_TYPE_EDGE_RISING>;
 876                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 877                                 IPCC_MPROC_SIGNAL_SMP2P>;
 878
 879                 qcom,local-pid = <0>;
 880                 qcom,remote-pid = <2>;
 881
 882                 smp2p_adsp_out: master-kernel {
 883                         qcom,entry-name = "master-kernel";
 884                         #qcom,smem-state-cells = <1>;
 885                 };
 886
 887                 smp2p_adsp_in: slave-kernel {
 888                         qcom,entry-name = "slave-kernel";
 889                         interrupt-controller;
 890                         #interrupt-cells = <2>;
 891                 };
 892         };
 893
 894         smp2p-cdsp {
 895                 compatible = "qcom,smp2p";
 896                 qcom,smem = <94>, <432>;
 897                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 898                                              IPCC_MPROC_SIGNAL_SMP2P
 899                                              IRQ_TYPE_EDGE_RISING>;
 900                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 901                                 IPCC_MPROC_SIGNAL_SMP2P>;
 902
 903                 qcom,local-pid = <0>;
 904                 qcom,remote-pid = <5>;
 905
 906                 smp2p_cdsp_out: master-kernel {
 907                         qcom,entry-name = "master-kernel";
 908                         #qcom,smem-state-cells = <1>;
 909                 };
 910
 911                 smp2p_cdsp_in: slave-kernel {
 912                         qcom,entry-name = "slave-kernel";
 913                         interrupt-controller;
 914                         #interrupt-cells = <2>;
 915                 };
 916         };
 917
 918         smp2p-slpi {
 919                 compatible = "qcom,smp2p";
 920                 qcom,smem = <481>, <430>;
 921                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 922                                              IPCC_MPROC_SIGNAL_SMP2P
 923                                              IRQ_TYPE_EDGE_RISING>;
 924                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 925                                 IPCC_MPROC_SIGNAL_SMP2P>;
 926
 927                 qcom,local-pid = <0>;
 928                 qcom,remote-pid = <3>;
 929
 930                 smp2p_slpi_out: master-kernel {
 931                         qcom,entry-name = "master-kernel";
 932                         #qcom,smem-state-cells = <1>;
 933                 };
 934
 935                 smp2p_slpi_in: slave-kernel {
 936                         qcom,entry-name = "slave-kernel";
 937                         interrupt-controller;
 938                         #interrupt-cells = <2>;
 939                 };
 940         };
 941
 942         soc: soc@0 {
 943                 #address-cells = <2>;
 944                 #size-cells = <2>;
 945                 ranges = <0 0 0 0 0x10 0>;
 946                 dma-ranges = <0 0 0 0 0x10 0>;
 947                 compatible = "simple-bus";
 948
 949                 gcc: clock-controller@100000 {
 950                         compatible = "qcom,gcc-sm8250";
 951                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 952                         #clock-cells = <1>;
 953                         #reset-cells = <1>;
 954                         #power-domain-cells = <1>;
 955                         clock-names = "bi_tcxo",
 956                                       "bi_tcxo_ao",
 957                                       "sleep_clk";
 958                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 959                                  <&rpmhcc RPMH_CXO_CLK_A>,
 960                                  <&sleep_clk>;
 961                 };
 962
 963                 ipcc: mailbox@408000 {
 964                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 965                         reg = <0 0x00408000 0 0x1000>;
 966                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 967                         interrupt-controller;
 968                         #interrupt-cells = <3>;
 969                         #mbox-cells = <2>;
 970                 };
 971
 972                 qfprom: efuse@784000 {
 973                         compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
 974                         reg = <0 0x00784000 0 0x8ff>;
 975                         #address-cells = <1>;
 976                         #size-cells = <1>;
 977
 978                         gpu_speed_bin: gpu-speed-bin@19b {
 979                                 reg = <0x19b 0x1>;
 980                                 bits = <5 3>;
 981                         };
 982                 };
 983
 984                 rng: rng@793000 {
 985                         compatible = "qcom,prng-ee";
 986                         reg = <0 0x00793000 0 0x1000>;
 987                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 988                         clock-names = "core";
 989                 };
 990
 991                 gpi_dma2: dma-controller@800000 {
 992                         compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
 993                         reg = <0 0x00800000 0 0x70000>;
 994                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 995                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 996                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 997                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 998                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 999                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1000                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1001                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1002                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1003                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1004                         dma-channels = <10>;
1005                         dma-channel-mask = <0x3f>;
1006                         iommus = <&apps_smmu 0x76 0x0>;
1007                         #dma-cells = <3>;
1008                         status = "disabled";
1009                 };
1010
1011                 qupv3_id_2: geniqup@8c0000 {
1012                         compatible = "qcom,geni-se-qup";
1013                         reg = <0x0 0x008c0000 0x0 0x6000>;
1014                         clock-names = "m-ahb", "s-ahb";
1015                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1016                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1017                         #address-cells = <2>;
1018                         #size-cells = <2>;
1019                         iommus = <&apps_smmu 0x63 0x0>;
1020                         ranges;
1021                         status = "disabled";
1022
1023                         i2c14: i2c@880000 {
1024                                 compatible = "qcom,geni-i2c";
1025                                 reg = <0 0x00880000 0 0x4000>;
1026                                 clock-names = "se";
1027                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1028                                 pinctrl-names = "default";
1029                                 pinctrl-0 = <&qup_i2c14_default>;
1030                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1031                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1032                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1033                                 dma-names = "tx", "rx";
1034                                 power-domains = <&rpmhpd SM8250_CX>;
1035                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1036                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1037                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1038                                 interconnect-names = "qup-core",
1039                                                      "qup-config",
1040                                                      "qup-memory";
1041                                 #address-cells = <1>;
1042                                 #size-cells = <0>;
1043                                 status = "disabled";
1044                         };
1045
1046                         spi14: spi@880000 {
1047                                 compatible = "qcom,geni-spi";
1048                                 reg = <0 0x00880000 0 0x4000>;
1049                                 clock-names = "se";
1050                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1051                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1052                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1053                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1054                                 dma-names = "tx", "rx";
1055                                 power-domains = <&rpmhpd RPMHPD_CX>;
1056                                 operating-points-v2 = <&qup_opp_table>;
1057                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1058                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1059                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1060                                 interconnect-names = "qup-core",
1061                                                      "qup-config",
1062                                                      "qup-memory";
1063                                 #address-cells = <1>;
1064                                 #size-cells = <0>;
1065                                 status = "disabled";
1066                         };
1067
1068                         i2c15: i2c@884000 {
1069                                 compatible = "qcom,geni-i2c";
1070                                 reg = <0 0x00884000 0 0x4000>;
1071                                 clock-names = "se";
1072                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1073                                 pinctrl-names = "default";
1074                                 pinctrl-0 = <&qup_i2c15_default>;
1075                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1076                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1077                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1078                                 dma-names = "tx", "rx";
1079                                 power-domains = <&rpmhpd SM8250_CX>;
1080                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1081                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1082                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1083                                 interconnect-names = "qup-core",
1084                                                      "qup-config",
1085                                                      "qup-memory";
1086                                 #address-cells = <1>;
1087                                 #size-cells = <0>;
1088                                 status = "disabled";
1089                         };
1090
1091                         spi15: spi@884000 {
1092                                 compatible = "qcom,geni-spi";
1093                                 reg = <0 0x00884000 0 0x4000>;
1094                                 clock-names = "se";
1095                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1096                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1097                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1098                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1099                                 dma-names = "tx", "rx";
1100                                 power-domains = <&rpmhpd RPMHPD_CX>;
1101                                 operating-points-v2 = <&qup_opp_table>;
1102                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1103                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1104                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1105                                 interconnect-names = "qup-core",
1106                                                      "qup-config",
1107                                                      "qup-memory";
1108                                 #address-cells = <1>;
1109                                 #size-cells = <0>;
1110                                 status = "disabled";
1111                         };
1112
1113                         i2c16: i2c@888000 {
1114                                 compatible = "qcom,geni-i2c";
1115                                 reg = <0 0x00888000 0 0x4000>;
1116                                 clock-names = "se";
1117                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1118                                 pinctrl-names = "default";
1119                                 pinctrl-0 = <&qup_i2c16_default>;
1120                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1121                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1122                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1123                                 dma-names = "tx", "rx";
1124                                 power-domains = <&rpmhpd SM8250_CX>;
1125                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1126                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1127                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1128                                 interconnect-names = "qup-core",
1129                                                      "qup-config",
1130                                                      "qup-memory";
1131                                 #address-cells = <1>;
1132                                 #size-cells = <0>;
1133                                 status = "disabled";
1134                         };
1135
1136                         spi16: spi@888000 {
1137                                 compatible = "qcom,geni-spi";
1138                                 reg = <0 0x00888000 0 0x4000>;
1139                                 clock-names = "se";
1140                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1141                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1142                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1143                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1144                                 dma-names = "tx", "rx";
1145                                 power-domains = <&rpmhpd RPMHPD_CX>;
1146                                 operating-points-v2 = <&qup_opp_table>;
1147                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1148                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1149                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1150                                 interconnect-names = "qup-core",
1151                                                      "qup-config",
1152                                                      "qup-memory";
1153                                 #address-cells = <1>;
1154                                 #size-cells = <0>;
1155                                 status = "disabled";
1156                         };
1157
1158                         i2c17: i2c@88c000 {
1159                                 compatible = "qcom,geni-i2c";
1160                                 reg = <0 0x0088c000 0 0x4000>;
1161                                 clock-names = "se";
1162                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1163                                 pinctrl-names = "default";
1164                                 pinctrl-0 = <&qup_i2c17_default>;
1165                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1166                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1167                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1168                                 dma-names = "tx", "rx";
1169                                 power-domains = <&rpmhpd SM8250_CX>;
1170                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1171                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1172                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1173                                 interconnect-names = "qup-core",
1174                                                      "qup-config",
1175                                                      "qup-memory";
1176                                 #address-cells = <1>;
1177                                 #size-cells = <0>;
1178                                 status = "disabled";
1179                         };
1180
1181                         spi17: spi@88c000 {
1182                                 compatible = "qcom,geni-spi";
1183                                 reg = <0 0x0088c000 0 0x4000>;
1184                                 clock-names = "se";
1185                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1186                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1187                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1188                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1189                                 dma-names = "tx", "rx";
1190                                 power-domains = <&rpmhpd RPMHPD_CX>;
1191                                 operating-points-v2 = <&qup_opp_table>;
1192                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1193                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1194                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1195                                 interconnect-names = "qup-core",
1196                                                      "qup-config",
1197                                                      "qup-memory";
1198                                 #address-cells = <1>;
1199                                 #size-cells = <0>;
1200                                 status = "disabled";
1201                         };
1202
1203                         uart17: serial@88c000 {
1204                                 compatible = "qcom,geni-uart";
1205                                 reg = <0 0x0088c000 0 0x4000>;
1206                                 clock-names = "se";
1207                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1208                                 pinctrl-names = "default";
1209                                 pinctrl-0 = <&qup_uart17_default>;
1210                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1211                                 power-domains = <&rpmhpd RPMHPD_CX>;
1212                                 operating-points-v2 = <&qup_opp_table>;
1213                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1214                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1215                                 interconnect-names = "qup-core",
1216                                                      "qup-config";
1217                                 status = "disabled";
1218                         };
1219
1220                         i2c18: i2c@890000 {
1221                                 compatible = "qcom,geni-i2c";
1222                                 reg = <0 0x00890000 0 0x4000>;
1223                                 clock-names = "se";
1224                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1225                                 pinctrl-names = "default";
1226                                 pinctrl-0 = <&qup_i2c18_default>;
1227                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1228                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1229                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1230                                 dma-names = "tx", "rx";
1231                                 power-domains = <&rpmhpd SM8250_CX>;
1232                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1233                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1234                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1235                                 interconnect-names = "qup-core",
1236                                                      "qup-config",
1237                                                      "qup-memory";
1238                                 #address-cells = <1>;
1239                                 #size-cells = <0>;
1240                                 status = "disabled";
1241                         };
1242
1243                         spi18: spi@890000 {
1244                                 compatible = "qcom,geni-spi";
1245                                 reg = <0 0x00890000 0 0x4000>;
1246                                 clock-names = "se";
1247                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1248                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1249                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1250                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1251                                 dma-names = "tx", "rx";
1252                                 power-domains = <&rpmhpd RPMHPD_CX>;
1253                                 operating-points-v2 = <&qup_opp_table>;
1254                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1255                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1256                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1257                                 interconnect-names = "qup-core",
1258                                                      "qup-config",
1259                                                      "qup-memory";
1260                                 #address-cells = <1>;
1261                                 #size-cells = <0>;
1262                                 status = "disabled";
1263                         };
1264
1265                         uart18: serial@890000 {
1266                                 compatible = "qcom,geni-uart";
1267                                 reg = <0 0x00890000 0 0x4000>;
1268                                 clock-names = "se";
1269                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1270                                 pinctrl-names = "default";
1271                                 pinctrl-0 = <&qup_uart18_default>;
1272                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1273                                 power-domains = <&rpmhpd RPMHPD_CX>;
1274                                 operating-points-v2 = <&qup_opp_table>;
1275                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1276                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1277                                 interconnect-names = "qup-core",
1278                                                      "qup-config";
1279                                 status = "disabled";
1280                         };
1281
1282                         i2c19: i2c@894000 {
1283                                 compatible = "qcom,geni-i2c";
1284                                 reg = <0 0x00894000 0 0x4000>;
1285                                 clock-names = "se";
1286                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1287                                 pinctrl-names = "default";
1288                                 pinctrl-0 = <&qup_i2c19_default>;
1289                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1290                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1291                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1292                                 dma-names = "tx", "rx";
1293                                 power-domains = <&rpmhpd SM8250_CX>;
1294                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1295                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1296                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1297                                 interconnect-names = "qup-core",
1298                                                      "qup-config",
1299                                                      "qup-memory";
1300                                 #address-cells = <1>;
1301                                 #size-cells = <0>;
1302                                 status = "disabled";
1303                         };
1304
1305                         spi19: spi@894000 {
1306                                 compatible = "qcom,geni-spi";
1307                                 reg = <0 0x00894000 0 0x4000>;
1308                                 clock-names = "se";
1309                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1310                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1311                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1312                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1313                                 dma-names = "tx", "rx";
1314                                 power-domains = <&rpmhpd RPMHPD_CX>;
1315                                 operating-points-v2 = <&qup_opp_table>;
1316                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1317                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1318                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1319                                 interconnect-names = "qup-core",
1320                                                      "qup-config",
1321                                                      "qup-memory";
1322                                 #address-cells = <1>;
1323                                 #size-cells = <0>;
1324                                 status = "disabled";
1325                         };
1326                 };
1327
1328                 gpi_dma0: dma-controller@900000 {
1329                         compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1330                         reg = <0 0x00900000 0 0x70000>;
1331                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1332                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1333                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1334                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1335                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1336                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1337                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1338                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1339                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1340                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1341                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1342                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1343                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1344                         dma-channels = <15>;
1345                         dma-channel-mask = <0x7ff>;
1346                         iommus = <&apps_smmu 0x5b6 0x0>;
1347                         #dma-cells = <3>;
1348                         status = "disabled";
1349                 };
1350
1351                 qupv3_id_0: geniqup@9c0000 {
1352                         compatible = "qcom,geni-se-qup";
1353                         reg = <0x0 0x009c0000 0x0 0x6000>;
1354                         clock-names = "m-ahb", "s-ahb";
1355                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1356                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1357                         #address-cells = <2>;
1358                         #size-cells = <2>;
1359                         iommus = <&apps_smmu 0x5a3 0x0>;
1360                         ranges;
1361                         status = "disabled";
1362
1363                         i2c0: i2c@980000 {
1364                                 compatible = "qcom,geni-i2c";
1365                                 reg = <0 0x00980000 0 0x4000>;
1366                                 clock-names = "se";
1367                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1368                                 pinctrl-names = "default";
1369                                 pinctrl-0 = <&qup_i2c0_default>;
1370                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1371                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1372                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1373                                 dma-names = "tx", "rx";
1374                                 power-domains = <&rpmhpd SM8250_CX>;
1375                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1376                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1377                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1378                                 interconnect-names = "qup-core",
1379                                                      "qup-config",
1380                                                      "qup-memory";
1381                                 #address-cells = <1>;
1382                                 #size-cells = <0>;
1383                                 status = "disabled";
1384                         };
1385
1386                         spi0: spi@980000 {
1387                                 compatible = "qcom,geni-spi";
1388                                 reg = <0 0x00980000 0 0x4000>;
1389                                 clock-names = "se";
1390                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1391                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1392                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1393                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1394                                 dma-names = "tx", "rx";
1395                                 power-domains = <&rpmhpd RPMHPD_CX>;
1396                                 operating-points-v2 = <&qup_opp_table>;
1397                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1398                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1399                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1400                                 interconnect-names = "qup-core",
1401                                                      "qup-config",
1402                                                      "qup-memory";
1403                                 #address-cells = <1>;
1404                                 #size-cells = <0>;
1405                                 status = "disabled";
1406                         };
1407
1408                         i2c1: i2c@984000 {
1409                                 compatible = "qcom,geni-i2c";
1410                                 reg = <0 0x00984000 0 0x4000>;
1411                                 clock-names = "se";
1412                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1413                                 pinctrl-names = "default";
1414                                 pinctrl-0 = <&qup_i2c1_default>;
1415                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1416                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1417                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1418                                 dma-names = "tx", "rx";
1419                                 power-domains = <&rpmhpd SM8250_CX>;
1420                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1421                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1422                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1423                                 interconnect-names = "qup-core",
1424                                                      "qup-config",
1425                                                      "qup-memory";
1426                                 #address-cells = <1>;
1427                                 #size-cells = <0>;
1428                                 status = "disabled";
1429                         };
1430
1431                         spi1: spi@984000 {
1432                                 compatible = "qcom,geni-spi";
1433                                 reg = <0 0x00984000 0 0x4000>;
1434                                 clock-names = "se";
1435                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1436                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1437                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1438                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1439                                 dma-names = "tx", "rx";
1440                                 power-domains = <&rpmhpd RPMHPD_CX>;
1441                                 operating-points-v2 = <&qup_opp_table>;
1442                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1443                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1444                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1445                                 interconnect-names = "qup-core",
1446                                                      "qup-config",
1447                                                      "qup-memory";
1448                                 #address-cells = <1>;
1449                                 #size-cells = <0>;
1450                                 status = "disabled";
1451                         };
1452
1453                         i2c2: i2c@988000 {
1454                                 compatible = "qcom,geni-i2c";
1455                                 reg = <0 0x00988000 0 0x4000>;
1456                                 clock-names = "se";
1457                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1458                                 pinctrl-names = "default";
1459                                 pinctrl-0 = <&qup_i2c2_default>;
1460                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1461                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1462                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1463                                 dma-names = "tx", "rx";
1464                                 power-domains = <&rpmhpd SM8250_CX>;
1465                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1466                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1467                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1468                                 interconnect-names = "qup-core",
1469                                                      "qup-config",
1470                                                      "qup-memory";
1471                                 #address-cells = <1>;
1472                                 #size-cells = <0>;
1473                                 status = "disabled";
1474                         };
1475
1476                         spi2: spi@988000 {
1477                                 compatible = "qcom,geni-spi";
1478                                 reg = <0 0x00988000 0 0x4000>;
1479                                 clock-names = "se";
1480                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1481                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1482                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1483                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1484                                 dma-names = "tx", "rx";
1485                                 power-domains = <&rpmhpd RPMHPD_CX>;
1486                                 operating-points-v2 = <&qup_opp_table>;
1487                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1488                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1489                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1490                                 interconnect-names = "qup-core",
1491                                                      "qup-config",
1492                                                      "qup-memory";
1493                                 #address-cells = <1>;
1494                                 #size-cells = <0>;
1495                                 status = "disabled";
1496                         };
1497
1498                         uart2: serial@988000 {
1499                                 compatible = "qcom,geni-debug-uart";
1500                                 reg = <0 0x00988000 0 0x4000>;
1501                                 clock-names = "se";
1502                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1503                                 pinctrl-names = "default";
1504                                 pinctrl-0 = <&qup_uart2_default>;
1505                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1506                                 power-domains = <&rpmhpd RPMHPD_CX>;
1507                                 operating-points-v2 = <&qup_opp_table>;
1508                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1509                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1510                                 interconnect-names = "qup-core",
1511                                                      "qup-config";
1512                                 status = "disabled";
1513                         };
1514
1515                         i2c3: i2c@98c000 {
1516                                 compatible = "qcom,geni-i2c";
1517                                 reg = <0 0x0098c000 0 0x4000>;
1518                                 clock-names = "se";
1519                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1520                                 pinctrl-names = "default";
1521                                 pinctrl-0 = <&qup_i2c3_default>;
1522                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1523                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1524                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1525                                 dma-names = "tx", "rx";
1526                                 power-domains = <&rpmhpd SM8250_CX>;
1527                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1528                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1529                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1530                                 interconnect-names = "qup-core",
1531                                                      "qup-config",
1532                                                      "qup-memory";
1533                                 #address-cells = <1>;
1534                                 #size-cells = <0>;
1535                                 status = "disabled";
1536                         };
1537
1538                         spi3: spi@98c000 {
1539                                 compatible = "qcom,geni-spi";
1540                                 reg = <0 0x0098c000 0 0x4000>;
1541                                 clock-names = "se";
1542                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1543                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1544                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1545                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1546                                 dma-names = "tx", "rx";
1547                                 power-domains = <&rpmhpd RPMHPD_CX>;
1548                                 operating-points-v2 = <&qup_opp_table>;
1549                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1550                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1551                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1552                                 interconnect-names = "qup-core",
1553                                                      "qup-config",
1554                                                      "qup-memory";
1555                                 #address-cells = <1>;
1556                                 #size-cells = <0>;
1557                                 status = "disabled";
1558                         };
1559
1560                         i2c4: i2c@990000 {
1561                                 compatible = "qcom,geni-i2c";
1562                                 reg = <0 0x00990000 0 0x4000>;
1563                                 clock-names = "se";
1564                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1565                                 pinctrl-names = "default";
1566                                 pinctrl-0 = <&qup_i2c4_default>;
1567                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1568                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1569                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1570                                 dma-names = "tx", "rx";
1571                                 power-domains = <&rpmhpd SM8250_CX>;
1572                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1573                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1574                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1575                                 interconnect-names = "qup-core",
1576                                                      "qup-config",
1577                                                      "qup-memory";
1578                                 #address-cells = <1>;
1579                                 #size-cells = <0>;
1580                                 status = "disabled";
1581                         };
1582
1583                         spi4: spi@990000 {
1584                                 compatible = "qcom,geni-spi";
1585                                 reg = <0 0x00990000 0 0x4000>;
1586                                 clock-names = "se";
1587                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1588                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1589                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1590                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1591                                 dma-names = "tx", "rx";
1592                                 power-domains = <&rpmhpd RPMHPD_CX>;
1593                                 operating-points-v2 = <&qup_opp_table>;
1594                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1595                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1596                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1597                                 interconnect-names = "qup-core",
1598                                                      "qup-config",
1599                                                      "qup-memory";
1600                                 #address-cells = <1>;
1601                                 #size-cells = <0>;
1602                                 status = "disabled";
1603                         };
1604
1605                         i2c5: i2c@994000 {
1606                                 compatible = "qcom,geni-i2c";
1607                                 reg = <0 0x00994000 0 0x4000>;
1608                                 clock-names = "se";
1609                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1610                                 pinctrl-names = "default";
1611                                 pinctrl-0 = <&qup_i2c5_default>;
1612                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1613                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1614                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1615                                 dma-names = "tx", "rx";
1616                                 power-domains = <&rpmhpd SM8250_CX>;
1617                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1618                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1619                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1620                                 interconnect-names = "qup-core",
1621                                                      "qup-config",
1622                                                      "qup-memory";
1623                                 #address-cells = <1>;
1624                                 #size-cells = <0>;
1625                                 status = "disabled";
1626                         };
1627
1628                         spi5: spi@994000 {
1629                                 compatible = "qcom,geni-spi";
1630                                 reg = <0 0x00994000 0 0x4000>;
1631                                 clock-names = "se";
1632                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1633                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1634                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1635                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1636                                 dma-names = "tx", "rx";
1637                                 power-domains = <&rpmhpd RPMHPD_CX>;
1638                                 operating-points-v2 = <&qup_opp_table>;
1639                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1640                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1641                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1642                                 interconnect-names = "qup-core",
1643                                                      "qup-config",
1644                                                      "qup-memory";
1645                                 #address-cells = <1>;
1646                                 #size-cells = <0>;
1647                                 status = "disabled";
1648                         };
1649
1650                         i2c6: i2c@998000 {
1651                                 compatible = "qcom,geni-i2c";
1652                                 reg = <0 0x00998000 0 0x4000>;
1653                                 clock-names = "se";
1654                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1655                                 pinctrl-names = "default";
1656                                 pinctrl-0 = <&qup_i2c6_default>;
1657                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1658                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1659                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1660                                 dma-names = "tx", "rx";
1661                                 power-domains = <&rpmhpd SM8250_CX>;
1662                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1663                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1664                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1665                                 interconnect-names = "qup-core",
1666                                                      "qup-config",
1667                                                      "qup-memory";
1668                                 #address-cells = <1>;
1669                                 #size-cells = <0>;
1670                                 status = "disabled";
1671                         };
1672
1673                         spi6: spi@998000 {
1674                                 compatible = "qcom,geni-spi";
1675                                 reg = <0 0x00998000 0 0x4000>;
1676                                 clock-names = "se";
1677                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1678                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1679                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1680                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1681                                 dma-names = "tx", "rx";
1682                                 power-domains = <&rpmhpd RPMHPD_CX>;
1683                                 operating-points-v2 = <&qup_opp_table>;
1684                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1685                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1686                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1687                                 interconnect-names = "qup-core",
1688                                                      "qup-config",
1689                                                      "qup-memory";
1690                                 #address-cells = <1>;
1691                                 #size-cells = <0>;
1692                                 status = "disabled";
1693                         };
1694
1695                         uart6: serial@998000 {
1696                                 compatible = "qcom,geni-uart";
1697                                 reg = <0 0x00998000 0 0x4000>;
1698                                 clock-names = "se";
1699                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1700                                 pinctrl-names = "default";
1701                                 pinctrl-0 = <&qup_uart6_default>;
1702                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1703                                 power-domains = <&rpmhpd RPMHPD_CX>;
1704                                 operating-points-v2 = <&qup_opp_table>;
1705                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1706                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1707                                 interconnect-names = "qup-core",
1708                                                      "qup-config";
1709                                 status = "disabled";
1710                         };
1711
1712                         i2c7: i2c@99c000 {
1713                                 compatible = "qcom,geni-i2c";
1714                                 reg = <0 0x0099c000 0 0x4000>;
1715                                 clock-names = "se";
1716                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1717                                 pinctrl-names = "default";
1718                                 pinctrl-0 = <&qup_i2c7_default>;
1719                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1720                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1721                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1722                                 dma-names = "tx", "rx";
1723                                 power-domains = <&rpmhpd SM8250_CX>;
1724                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1725                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1726                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1727                                 interconnect-names = "qup-core",
1728                                                      "qup-config",
1729                                                      "qup-memory";
1730                                 #address-cells = <1>;
1731                                 #size-cells = <0>;
1732                                 status = "disabled";
1733                         };
1734
1735                         spi7: spi@99c000 {
1736                                 compatible = "qcom,geni-spi";
1737                                 reg = <0 0x0099c000 0 0x4000>;
1738                                 clock-names = "se";
1739                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1740                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1741                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1742                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1743                                 dma-names = "tx", "rx";
1744                                 power-domains = <&rpmhpd RPMHPD_CX>;
1745                                 operating-points-v2 = <&qup_opp_table>;
1746                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1747                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1748                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1749                                 interconnect-names = "qup-core",
1750                                                      "qup-config",
1751                                                      "qup-memory";
1752                                 #address-cells = <1>;
1753                                 #size-cells = <0>;
1754                                 status = "disabled";
1755                         };
1756                 };
1757
1758                 gpi_dma1: dma-controller@a00000 {
1759                         compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1760                         reg = <0 0x00a00000 0 0x70000>;
1761                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1762                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1763                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1764                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1765                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1766                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1767                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1768                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1769                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1770                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1771                         dma-channels = <10>;
1772                         dma-channel-mask = <0x3f>;
1773                         iommus = <&apps_smmu 0x56 0x0>;
1774                         #dma-cells = <3>;
1775                         status = "disabled";
1776                 };
1777
1778                 qupv3_id_1: geniqup@ac0000 {
1779                         compatible = "qcom,geni-se-qup";
1780                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1781                         clock-names = "m-ahb", "s-ahb";
1782                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1783                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1784                         #address-cells = <2>;
1785                         #size-cells = <2>;
1786                         iommus = <&apps_smmu 0x43 0x0>;
1787                         ranges;
1788                         status = "disabled";
1789
1790                         i2c8: i2c@a80000 {
1791                                 compatible = "qcom,geni-i2c";
1792                                 reg = <0 0x00a80000 0 0x4000>;
1793                                 clock-names = "se";
1794                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1795                                 pinctrl-names = "default";
1796                                 pinctrl-0 = <&qup_i2c8_default>;
1797                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1798                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1799                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1800                                 dma-names = "tx", "rx";
1801                                 power-domains = <&rpmhpd SM8250_CX>;
1802                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1803                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1804                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1805                                 interconnect-names = "qup-core",
1806                                                      "qup-config",
1807                                                      "qup-memory";
1808                                 #address-cells = <1>;
1809                                 #size-cells = <0>;
1810                                 status = "disabled";
1811                         };
1812
1813                         spi8: spi@a80000 {
1814                                 compatible = "qcom,geni-spi";
1815                                 reg = <0 0x00a80000 0 0x4000>;
1816                                 clock-names = "se";
1817                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1818                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1819                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1820                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1821                                 dma-names = "tx", "rx";
1822                                 power-domains = <&rpmhpd RPMHPD_CX>;
1823                                 operating-points-v2 = <&qup_opp_table>;
1824                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1825                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1826                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1827                                 interconnect-names = "qup-core",
1828                                                      "qup-config",
1829                                                      "qup-memory";
1830                                 #address-cells = <1>;
1831                                 #size-cells = <0>;
1832                                 status = "disabled";
1833                         };
1834
1835                         i2c9: i2c@a84000 {
1836                                 compatible = "qcom,geni-i2c";
1837                                 reg = <0 0x00a84000 0 0x4000>;
1838                                 clock-names = "se";
1839                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1840                                 pinctrl-names = "default";
1841                                 pinctrl-0 = <&qup_i2c9_default>;
1842                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1843                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1844                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1845                                 dma-names = "tx", "rx";
1846                                 power-domains = <&rpmhpd SM8250_CX>;
1847                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1848                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1849                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1850                                 interconnect-names = "qup-core",
1851                                                      "qup-config",
1852                                                      "qup-memory";
1853                                 #address-cells = <1>;
1854                                 #size-cells = <0>;
1855                                 status = "disabled";
1856                         };
1857
1858                         spi9: spi@a84000 {
1859                                 compatible = "qcom,geni-spi";
1860                                 reg = <0 0x00a84000 0 0x4000>;
1861                                 clock-names = "se";
1862                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1863                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1864                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1865                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1866                                 dma-names = "tx", "rx";
1867                                 power-domains = <&rpmhpd RPMHPD_CX>;
1868                                 operating-points-v2 = <&qup_opp_table>;
1869                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1870                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1871                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1872                                 interconnect-names = "qup-core",
1873                                                      "qup-config",
1874                                                      "qup-memory";
1875                                 #address-cells = <1>;
1876                                 #size-cells = <0>;
1877                                 status = "disabled";
1878                         };
1879
1880                         i2c10: i2c@a88000 {
1881                                 compatible = "qcom,geni-i2c";
1882                                 reg = <0 0x00a88000 0 0x4000>;
1883                                 clock-names = "se";
1884                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1885                                 pinctrl-names = "default";
1886                                 pinctrl-0 = <&qup_i2c10_default>;
1887                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1888                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1889                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1890                                 dma-names = "tx", "rx";
1891                                 power-domains = <&rpmhpd SM8250_CX>;
1892                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1893                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1894                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1895                                 interconnect-names = "qup-core",
1896                                                      "qup-config",
1897                                                      "qup-memory";
1898                                 #address-cells = <1>;
1899                                 #size-cells = <0>;
1900                                 status = "disabled";
1901                         };
1902
1903                         spi10: spi@a88000 {
1904                                 compatible = "qcom,geni-spi";
1905                                 reg = <0 0x00a88000 0 0x4000>;
1906                                 clock-names = "se";
1907                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1908                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1909                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1910                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1911                                 dma-names = "tx", "rx";
1912                                 power-domains = <&rpmhpd RPMHPD_CX>;
1913                                 operating-points-v2 = <&qup_opp_table>;
1914                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1915                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1916                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1917                                 interconnect-names = "qup-core",
1918                                                      "qup-config",
1919                                                      "qup-memory";
1920                                 #address-cells = <1>;
1921                                 #size-cells = <0>;
1922                                 status = "disabled";
1923                         };
1924
1925                         i2c11: i2c@a8c000 {
1926                                 compatible = "qcom,geni-i2c";
1927                                 reg = <0 0x00a8c000 0 0x4000>;
1928                                 clock-names = "se";
1929                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1930                                 pinctrl-names = "default";
1931                                 pinctrl-0 = <&qup_i2c11_default>;
1932                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1933                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1934                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1935                                 dma-names = "tx", "rx";
1936                                 power-domains = <&rpmhpd SM8250_CX>;
1937                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1938                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1939                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1940                                 interconnect-names = "qup-core",
1941                                                      "qup-config",
1942                                                      "qup-memory";
1943                                 #address-cells = <1>;
1944                                 #size-cells = <0>;
1945                                 status = "disabled";
1946                         };
1947
1948                         spi11: spi@a8c000 {
1949                                 compatible = "qcom,geni-spi";
1950                                 reg = <0 0x00a8c000 0 0x4000>;
1951                                 clock-names = "se";
1952                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1953                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1954                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1955                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1956                                 dma-names = "tx", "rx";
1957                                 power-domains = <&rpmhpd RPMHPD_CX>;
1958                                 operating-points-v2 = <&qup_opp_table>;
1959                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1960                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1961                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1962                                 interconnect-names = "qup-core",
1963                                                      "qup-config",
1964                                                      "qup-memory";
1965                                 #address-cells = <1>;
1966                                 #size-cells = <0>;
1967                                 status = "disabled";
1968                         };
1969
1970                         i2c12: i2c@a90000 {
1971                                 compatible = "qcom,geni-i2c";
1972                                 reg = <0 0x00a90000 0 0x4000>;
1973                                 clock-names = "se";
1974                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1975                                 pinctrl-names = "default";
1976                                 pinctrl-0 = <&qup_i2c12_default>;
1977                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1978                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1979                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1980                                 dma-names = "tx", "rx";
1981                                 power-domains = <&rpmhpd SM8250_CX>;
1982                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1983                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1984                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1985                                 interconnect-names = "qup-core",
1986                                                      "qup-config",
1987                                                      "qup-memory";
1988                                 #address-cells = <1>;
1989                                 #size-cells = <0>;
1990                                 status = "disabled";
1991                         };
1992
1993                         spi12: spi@a90000 {
1994                                 compatible = "qcom,geni-spi";
1995                                 reg = <0 0x00a90000 0 0x4000>;
1996                                 clock-names = "se";
1997                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1998                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2000                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2001                                 dma-names = "tx", "rx";
2002                                 power-domains = <&rpmhpd RPMHPD_CX>;
2003                                 operating-points-v2 = <&qup_opp_table>;
2004                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2005                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2006                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2007                                 interconnect-names = "qup-core",
2008                                                      "qup-config",
2009                                                      "qup-memory";
2010                                 #address-cells = <1>;
2011                                 #size-cells = <0>;
2012                                 status = "disabled";
2013                         };
2014
2015                         uart12: serial@a90000 {
2016                                 compatible = "qcom,geni-debug-uart";
2017                                 reg = <0x0 0x00a90000 0x0 0x4000>;
2018                                 clock-names = "se";
2019                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2020                                 pinctrl-names = "default";
2021                                 pinctrl-0 = <&qup_uart12_default>;
2022                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2023                                 power-domains = <&rpmhpd RPMHPD_CX>;
2024                                 operating-points-v2 = <&qup_opp_table>;
2025                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2026                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2027                                 interconnect-names = "qup-core",
2028                                                      "qup-config";
2029                                 status = "disabled";
2030                         };
2031
2032                         i2c13: i2c@a94000 {
2033                                 compatible = "qcom,geni-i2c";
2034                                 reg = <0 0x00a94000 0 0x4000>;
2035                                 clock-names = "se";
2036                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2037                                 pinctrl-names = "default";
2038                                 pinctrl-0 = <&qup_i2c13_default>;
2039                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2040                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2041                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2042                                 dma-names = "tx", "rx";
2043                                 power-domains = <&rpmhpd SM8250_CX>;
2044                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2045                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2046                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2047                                 interconnect-names = "qup-core",
2048                                                      "qup-config",
2049                                                      "qup-memory";
2050                                 #address-cells = <1>;
2051                                 #size-cells = <0>;
2052                                 status = "disabled";
2053                         };
2054
2055                         spi13: spi@a94000 {
2056                                 compatible = "qcom,geni-spi";
2057                                 reg = <0 0x00a94000 0 0x4000>;
2058                                 clock-names = "se";
2059                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2060                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2061                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2062                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2063                                 dma-names = "tx", "rx";
2064                                 power-domains = <&rpmhpd RPMHPD_CX>;
2065                                 operating-points-v2 = <&qup_opp_table>;
2066                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2067                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2068                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2069                                 interconnect-names = "qup-core",
2070                                                      "qup-config",
2071                                                      "qup-memory";
2072                                 #address-cells = <1>;
2073                                 #size-cells = <0>;
2074                                 status = "disabled";
2075                         };
2076                 };
2077
2078                 config_noc: interconnect@1500000 {
2079                         compatible = "qcom,sm8250-config-noc";
2080                         reg = <0 0x01500000 0 0xa580>;
2081                         #interconnect-cells = <2>;
2082                         qcom,bcm-voters = <&apps_bcm_voter>;
2083                 };
2084
2085                 system_noc: interconnect@1620000 {
2086                         compatible = "qcom,sm8250-system-noc";
2087                         reg = <0 0x01620000 0 0x1c200>;
2088                         #interconnect-cells = <2>;
2089                         qcom,bcm-voters = <&apps_bcm_voter>;
2090                 };
2091
2092                 mc_virt: interconnect@163d000 {
2093                         compatible = "qcom,sm8250-mc-virt";
2094                         reg = <0 0x0163d000 0 0x1000>;
2095                         #interconnect-cells = <2>;
2096                         qcom,bcm-voters = <&apps_bcm_voter>;
2097                 };
2098
2099                 aggre1_noc: interconnect@16e0000 {
2100                         compatible = "qcom,sm8250-aggre1-noc";
2101                         reg = <0 0x016e0000 0 0x1f180>;
2102                         #interconnect-cells = <2>;
2103                         qcom,bcm-voters = <&apps_bcm_voter>;
2104                 };
2105
2106                 aggre2_noc: interconnect@1700000 {
2107                         compatible = "qcom,sm8250-aggre2-noc";
2108                         reg = <0 0x01700000 0 0x33000>;
2109                         #interconnect-cells = <2>;
2110                         qcom,bcm-voters = <&apps_bcm_voter>;
2111                 };
2112
2113                 compute_noc: interconnect@1733000 {
2114                         compatible = "qcom,sm8250-compute-noc";
2115                         reg = <0 0x01733000 0 0xa180>;
2116                         #interconnect-cells = <2>;
2117                         qcom,bcm-voters = <&apps_bcm_voter>;
2118                 };
2119
2120                 mmss_noc: interconnect@1740000 {
2121                         compatible = "qcom,sm8250-mmss-noc";
2122                         reg = <0 0x01740000 0 0x1f080>;
2123                         #interconnect-cells = <2>;
2124                         qcom,bcm-voters = <&apps_bcm_voter>;
2125                 };
2126
2127                 pcie0: pcie@1c00000 {
2128                         compatible = "qcom,pcie-sm8250";
2129                         reg = <0 0x01c00000 0 0x3000>,
2130                               <0 0x60000000 0 0xf1d>,
2131                               <0 0x60000f20 0 0xa8>,
2132                               <0 0x60001000 0 0x1000>,
2133                               <0 0x60100000 0 0x100000>,
2134                               <0 0x01c03000 0 0x1000>;
2135                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2136                         device_type = "pci";
2137                         linux,pci-domain = <0>;
2138                         bus-range = <0x00 0xff>;
2139                         num-lanes = <1>;
2140
2141                         #address-cells = <3>;
2142                         #size-cells = <2>;
2143
2144                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2145                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2146
2147                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2148                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2149                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2150                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2151                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2152                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2153                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2154                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2155                         interrupt-names = "msi0",
2156                                           "msi1",
2157                                           "msi2",
2158                                           "msi3",
2159                                           "msi4",
2160                                           "msi5",
2161                                           "msi6",
2162                                           "msi7";
2163                         #interrupt-cells = <1>;
2164                         interrupt-map-mask = <0 0 0 0x7>;
2165                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2166                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2167                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2168                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2169
2170                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2171                                  <&gcc GCC_PCIE_0_AUX_CLK>,
2172                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2173                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2174                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2175                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2176                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2177                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2178                         clock-names = "pipe",
2179                                       "aux",
2180                                       "cfg",
2181                                       "bus_master",
2182                                       "bus_slave",
2183                                       "slave_q2a",
2184                                       "tbu",
2185                                       "ddrss_sf_tbu";
2186
2187                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
2188                                     <0x100 &apps_smmu 0x1c01 0x1>;
2189
2190                         resets = <&gcc GCC_PCIE_0_BCR>;
2191                         reset-names = "pci";
2192
2193                         power-domains = <&gcc PCIE_0_GDSC>;
2194
2195                         phys = <&pcie0_phy>;
2196                         phy-names = "pciephy";
2197
2198                         perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2199                         wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2200
2201                         pinctrl-names = "default";
2202                         pinctrl-0 = <&pcie0_default_state>;
2203                         dma-coherent;
2204
2205                         status = "disabled";
2206                 };
2207
2208                 pcie0_phy: phy@1c06000 {
2209                         compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2210                         reg = <0 0x01c06000 0 0x1000>;
2211
2212                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2213                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2214                                  <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2215                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
2216                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
2217                         clock-names = "aux",
2218                                       "cfg_ahb",
2219                                       "ref",
2220                                       "refgen",
2221                                       "pipe";
2222
2223                         clock-output-names = "pcie_0_pipe_clk";
2224                         #clock-cells = <0>;
2225
2226                         #phy-cells = <0>;
2227
2228                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2229                         reset-names = "phy";
2230
2231                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2232                         assigned-clock-rates = <100000000>;
2233
2234                         status = "disabled";
2235                 };
2236
2237                 pcie1: pcie@1c08000 {
2238                         compatible = "qcom,pcie-sm8250";
2239                         reg = <0 0x01c08000 0 0x3000>,
2240                               <0 0x40000000 0 0xf1d>,
2241                               <0 0x40000f20 0 0xa8>,
2242                               <0 0x40001000 0 0x1000>,
2243                               <0 0x40100000 0 0x100000>,
2244                               <0 0x01c0b000 0 0x1000>;
2245                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2246                         device_type = "pci";
2247                         linux,pci-domain = <1>;
2248                         bus-range = <0x00 0xff>;
2249                         num-lanes = <2>;
2250
2251                         #address-cells = <3>;
2252                         #size-cells = <2>;
2253
2254                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2255                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2256
2257                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2258                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2259                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
2260                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
2261                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
2262                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
2263                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
2264                                      <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2265                         interrupt-names = "msi0",
2266                                           "msi1",
2267                                           "msi2",
2268                                           "msi3",
2269                                           "msi4",
2270                                           "msi5",
2271                                           "msi6",
2272                                           "msi7";
2273                         #interrupt-cells = <1>;
2274                         interrupt-map-mask = <0 0 0 0x7>;
2275                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2276                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2277                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2278                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2279
2280                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2281                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2282                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2283                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2284                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2285                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2286                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2287                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2288                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2289                         clock-names = "pipe",
2290                                       "aux",
2291                                       "cfg",
2292                                       "bus_master",
2293                                       "bus_slave",
2294                                       "slave_q2a",
2295                                       "ref",
2296                                       "tbu",
2297                                       "ddrss_sf_tbu";
2298
2299                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2300                         assigned-clock-rates = <19200000>;
2301
2302                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
2303                                     <0x100 &apps_smmu 0x1c81 0x1>;
2304
2305                         resets = <&gcc GCC_PCIE_1_BCR>;
2306                         reset-names = "pci";
2307
2308                         power-domains = <&gcc PCIE_1_GDSC>;
2309
2310                         phys = <&pcie1_phy>;
2311                         phy-names = "pciephy";
2312
2313                         perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2314                         wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2315
2316                         pinctrl-names = "default";
2317                         pinctrl-0 = <&pcie1_default_state>;
2318                         dma-coherent;
2319
2320                         status = "disabled";
2321                 };
2322
2323                 pcie1_phy: phy@1c0e000 {
2324                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2325                         reg = <0 0x01c0e000 0 0x1000>;
2326
2327                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2328                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2329                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2330                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2331                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
2332                         clock-names = "aux",
2333                                       "cfg_ahb",
2334                                       "ref",
2335                                       "refgen",
2336                                       "pipe";
2337
2338                         clock-output-names = "pcie_1_pipe_clk";
2339                         #clock-cells = <0>;
2340
2341                         #phy-cells = <0>;
2342
2343                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2344                         reset-names = "phy";
2345
2346                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2347                         assigned-clock-rates = <100000000>;
2348
2349                         status = "disabled";
2350                 };
2351
2352                 pcie2: pcie@1c10000 {
2353                         compatible = "qcom,pcie-sm8250";
2354                         reg = <0 0x01c10000 0 0x3000>,
2355                               <0 0x64000000 0 0xf1d>,
2356                               <0 0x64000f20 0 0xa8>,
2357                               <0 0x64001000 0 0x1000>,
2358                               <0 0x64100000 0 0x100000>,
2359                               <0 0x01c13000 0 0x1000>;
2360                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2361                         device_type = "pci";
2362                         linux,pci-domain = <2>;
2363                         bus-range = <0x00 0xff>;
2364                         num-lanes = <2>;
2365
2366                         #address-cells = <3>;
2367                         #size-cells = <2>;
2368
2369                         ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2370                                  <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2371
2372                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
2373                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2374                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2375                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2376                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2377                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
2378                                      <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
2379                                      <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
2380                         interrupt-names = "msi0",
2381                                           "msi1",
2382                                           "msi2",
2383                                           "msi3",
2384                                           "msi4",
2385                                           "msi5",
2386                                           "msi6",
2387                                           "msi7";
2388                         #interrupt-cells = <1>;
2389                         interrupt-map-mask = <0 0 0 0x7>;
2390                         interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2391                                         <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2392                                         <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2393                                         <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2394
2395                         clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2396                                  <&gcc GCC_PCIE_2_AUX_CLK>,
2397                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2398                                  <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2399                                  <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2400                                  <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2401                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2402                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2403                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2404                         clock-names = "pipe",
2405                                       "aux",
2406                                       "cfg",
2407                                       "bus_master",
2408                                       "bus_slave",
2409                                       "slave_q2a",
2410                                       "ref",
2411                                       "tbu",
2412                                       "ddrss_sf_tbu";
2413
2414                         assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2415                         assigned-clock-rates = <19200000>;
2416
2417                         iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
2418                                     <0x100 &apps_smmu 0x1d01 0x1>;
2419
2420                         resets = <&gcc GCC_PCIE_2_BCR>;
2421                         reset-names = "pci";
2422
2423                         power-domains = <&gcc PCIE_2_GDSC>;
2424
2425                         phys = <&pcie2_phy>;
2426                         phy-names = "pciephy";
2427
2428                         perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2429                         wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2430
2431                         pinctrl-names = "default";
2432                         pinctrl-0 = <&pcie2_default_state>;
2433                         dma-coherent;
2434
2435                         status = "disabled";
2436                 };
2437
2438                 pcie2_phy: phy@1c16000 {
2439                         compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2440                         reg = <0 0x01c16000 0 0x1000>;
2441
2442                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2443                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2444                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2445                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2446                                  <&gcc GCC_PCIE_2_PIPE_CLK>;
2447                         clock-names = "aux",
2448                                       "cfg_ahb",
2449                                       "ref",
2450                                       "refgen",
2451                                       "pipe";
2452
2453                         clock-output-names = "pcie_2_pipe_clk";
2454                         #clock-cells = <0>;
2455
2456                         #phy-cells = <0>;
2457
2458                         resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2459                         reset-names = "phy";
2460
2461                         assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2462                         assigned-clock-rates = <100000000>;
2463
2464                         status = "disabled";
2465                 };
2466
2467                 ufs_mem_hc: ufshc@1d84000 {
2468                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2469                                      "jedec,ufs-2.0";
2470                         reg = <0 0x01d84000 0 0x3000>;
2471                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2472                         phys = <&ufs_mem_phy>;
2473                         phy-names = "ufsphy";
2474                         lanes-per-direction = <2>;
2475                         #reset-cells = <1>;
2476                         resets = <&gcc GCC_UFS_PHY_BCR>;
2477                         reset-names = "rst";
2478
2479                         power-domains = <&gcc UFS_PHY_GDSC>;
2480
2481                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2482
2483                         clock-names =
2484                                 "core_clk",
2485                                 "bus_aggr_clk",
2486                                 "iface_clk",
2487                                 "core_clk_unipro",
2488                                 "ref_clk",
2489                                 "tx_lane0_sync_clk",
2490                                 "rx_lane0_sync_clk",
2491                                 "rx_lane1_sync_clk";
2492                         clocks =
2493                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2494                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2495                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2496                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2497                                 <&rpmhcc RPMH_CXO_CLK>,
2498                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2499                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2500                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2501
2502                         operating-points-v2 = <&ufs_opp_table>;
2503
2504                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2505                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2506                         interconnect-names = "ufs-ddr", "cpu-ufs";
2507
2508                         status = "disabled";
2509
2510                         ufs_opp_table: opp-table {
2511                                 compatible = "operating-points-v2";
2512
2513                                 opp-37500000 {
2514                                         opp-hz = /bits/ 64 <37500000>,
2515                                                  /bits/ 64 <0>,
2516                                                  /bits/ 64 <0>,
2517                                                  /bits/ 64 <37500000>,
2518                                                  /bits/ 64 <0>,
2519                                                  /bits/ 64 <0>,
2520                                                  /bits/ 64 <0>,
2521                                                  /bits/ 64 <0>;
2522                                         required-opps = <&rpmhpd_opp_low_svs>;
2523                                 };
2524
2525                                 opp-300000000 {
2526                                         opp-hz = /bits/ 64 <300000000>,
2527                                                  /bits/ 64 <0>,
2528                                                  /bits/ 64 <0>,
2529                                                  /bits/ 64 <300000000>,
2530                                                  /bits/ 64 <0>,
2531                                                  /bits/ 64 <0>,
2532                                                  /bits/ 64 <0>,
2533                                                  /bits/ 64 <0>;
2534                                         required-opps = <&rpmhpd_opp_nom>;
2535                                 };
2536                         };
2537                 };
2538
2539                 ufs_mem_phy: phy@1d87000 {
2540                         compatible = "qcom,sm8250-qmp-ufs-phy";
2541                         reg = <0 0x01d87000 0 0x1000>;
2542
2543                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2544                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2545                                  <&gcc GCC_UFS_1X_CLKREF_EN>;
2546                         clock-names = "ref",
2547                                       "ref_aux",
2548                                       "qref";
2549
2550                         resets = <&ufs_mem_hc 0>;
2551                         reset-names = "ufsphy";
2552
2553                         #phy-cells = <0>;
2554
2555                         status = "disabled";
2556                 };
2557
2558                 cryptobam: dma-controller@1dc4000 {
2559                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2560                         reg = <0 0x01dc4000 0 0x24000>;
2561                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2562                         #dma-cells = <1>;
2563                         qcom,ee = <0>;
2564                         qcom,controlled-remotely;
2565                         num-channels = <8>;
2566                         qcom,num-ees = <2>;
2567                         iommus = <&apps_smmu 0x592 0x0000>,
2568                                  <&apps_smmu 0x598 0x0000>,
2569                                  <&apps_smmu 0x599 0x0000>,
2570                                  <&apps_smmu 0x59f 0x0000>,
2571                                  <&apps_smmu 0x586 0x0011>,
2572                                  <&apps_smmu 0x596 0x0011>;
2573                 };
2574
2575                 crypto: crypto@1dfa000 {
2576                         compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2577                         reg = <0 0x01dfa000 0 0x6000>;
2578                         dmas = <&cryptobam 4>, <&cryptobam 5>;
2579                         dma-names = "rx", "tx";
2580                         iommus = <&apps_smmu 0x592 0x0000>,
2581                                  <&apps_smmu 0x598 0x0000>,
2582                                  <&apps_smmu 0x599 0x0000>,
2583                                  <&apps_smmu 0x59f 0x0000>,
2584                                  <&apps_smmu 0x586 0x0011>,
2585                                  <&apps_smmu 0x596 0x0011>;
2586                         interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2587                         interconnect-names = "memory";
2588                 };
2589
2590                 tcsr_mutex: hwlock@1f40000 {
2591                         compatible = "qcom,tcsr-mutex";
2592                         reg = <0x0 0x01f40000 0x0 0x40000>;
2593                         #hwlock-cells = <1>;
2594                 };
2595
2596                 tcsr: syscon@1fc0000 {
2597                         compatible = "qcom,sm8250-tcsr", "syscon";
2598                         reg = <0x0 0x1fc0000 0x0 0x30000>;
2599                 };
2600
2601                 wsamacro: codec@3240000 {
2602                         compatible = "qcom,sm8250-lpass-wsa-macro";
2603                         reg = <0 0x03240000 0 0x1000>;
2604                         clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2605                                  <&audiocc LPASS_CDC_WSA_NPL>,
2606                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2607                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2608                                  <&aoncc LPASS_CDC_VA_MCLK>,
2609                                  <&vamacro>;
2610
2611                         clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2612
2613                         #clock-cells = <0>;
2614                         clock-output-names = "mclk";
2615                         #sound-dai-cells = <1>;
2616
2617                         pinctrl-names = "default";
2618                         pinctrl-0 = <&wsa_swr_active>;
2619
2620                         status = "disabled";
2621                 };
2622
2623                 swr0: soundwire@3250000 {
2624                         reg = <0 0x03250000 0 0x2000>;
2625                         compatible = "qcom,soundwire-v1.5.1";
2626                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2627                         clocks = <&wsamacro>;
2628                         clock-names = "iface";
2629
2630                         qcom,din-ports = <2>;
2631                         qcom,dout-ports = <6>;
2632
2633                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2634                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2635                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2636                         qcom,ports-block-pack-mode =    /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2637
2638                         #sound-dai-cells = <1>;
2639                         #address-cells = <2>;
2640                         #size-cells = <0>;
2641
2642                         status = "disabled";
2643                 };
2644
2645                 audiocc: clock-controller@3300000 {
2646                         compatible = "qcom,sm8250-lpass-audiocc";
2647                         reg = <0 0x03300000 0 0x30000>;
2648                         #clock-cells = <1>;
2649                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2650                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2651                                 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2652                         clock-names = "core", "audio", "bus";
2653                 };
2654
2655                 vamacro: codec@3370000 {
2656                         compatible = "qcom,sm8250-lpass-va-macro";
2657                         reg = <0 0x03370000 0 0x1000>;
2658                         clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2659                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2660                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2661
2662                         clock-names = "mclk", "macro", "dcodec";
2663
2664                         #clock-cells = <0>;
2665                         clock-output-names = "fsgen";
2666                         #sound-dai-cells = <1>;
2667                 };
2668
2669                 rxmacro: rxmacro@3200000 {
2670                         pinctrl-names = "default";
2671                         pinctrl-0 = <&rx_swr_active>;
2672                         compatible = "qcom,sm8250-lpass-rx-macro";
2673                         reg = <0 0x03200000 0 0x1000>;
2674                         status = "disabled";
2675
2676                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2677                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2678                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2680                                 <&vamacro>;
2681
2682                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2683
2684                         #clock-cells = <0>;
2685                         clock-output-names = "mclk";
2686                         #sound-dai-cells = <1>;
2687                 };
2688
2689                 swr1: soundwire@3210000 {
2690                         reg = <0 0x03210000 0 0x2000>;
2691                         compatible = "qcom,soundwire-v1.5.1";
2692                         status = "disabled";
2693                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2694                         clocks = <&rxmacro>;
2695                         clock-names = "iface";
2696                         label = "RX";
2697                         qcom,din-ports = <0>;
2698                         qcom,dout-ports = <5>;
2699
2700                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2701                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2702                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2703                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2704                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2705                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2706                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2707                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2708                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2709
2710                         #sound-dai-cells = <1>;
2711                         #address-cells = <2>;
2712                         #size-cells = <0>;
2713                 };
2714
2715                 txmacro: txmacro@3220000 {
2716                         pinctrl-names = "default";
2717                         pinctrl-0 = <&tx_swr_active>;
2718                         compatible = "qcom,sm8250-lpass-tx-macro";
2719                         reg = <0 0x03220000 0 0x1000>;
2720                         status = "disabled";
2721
2722                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2723                                  <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2724                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2725                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2726                                  <&vamacro>;
2727
2728                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2729
2730                         #clock-cells = <0>;
2731                         clock-output-names = "mclk";
2732                         #sound-dai-cells = <1>;
2733                 };
2734
2735                 /* tx macro */
2736                 swr2: soundwire@3230000 {
2737                         reg = <0 0x03230000 0 0x2000>;
2738                         compatible = "qcom,soundwire-v1.5.1";
2739                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2740                         interrupt-names = "core";
2741                         status = "disabled";
2742
2743                         clocks = <&txmacro>;
2744                         clock-names = "iface";
2745                         label = "TX";
2746
2747                         qcom,din-ports = <5>;
2748                         qcom,dout-ports = <0>;
2749                         qcom,ports-sinterval-low =      /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2750                         qcom,ports-offset1 =            /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2751                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2752                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2753                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2754                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2755                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2756                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2757                         qcom,ports-lane-control =       /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2758                         #sound-dai-cells = <1>;
2759                         #address-cells = <2>;
2760                         #size-cells = <0>;
2761                 };
2762
2763                 aoncc: clock-controller@3380000 {
2764                         compatible = "qcom,sm8250-lpass-aoncc";
2765                         reg = <0 0x03380000 0 0x40000>;
2766                         #clock-cells = <1>;
2767                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2768                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2769                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2770                         clock-names = "core", "audio", "bus";
2771                 };
2772
2773                 lpass_tlmm: pinctrl@33c0000 {
2774                         compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2775                         reg = <0 0x033c0000 0x0 0x20000>,
2776                               <0 0x03550000 0x0 0x10000>;
2777                         gpio-controller;
2778                         #gpio-cells = <2>;
2779                         gpio-ranges = <&lpass_tlmm 0 0 14>;
2780
2781                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2782                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2783                         clock-names = "core", "audio";
2784
2785                         wsa_swr_active: wsa-swr-active-state {
2786                                 clk-pins {
2787                                         pins = "gpio10";
2788                                         function = "wsa_swr_clk";
2789                                         drive-strength = <2>;
2790                                         slew-rate = <1>;
2791                                         bias-disable;
2792                                 };
2793
2794                                 data-pins {
2795                                         pins = "gpio11";
2796                                         function = "wsa_swr_data";
2797                                         drive-strength = <2>;
2798                                         slew-rate = <1>;
2799                                         bias-bus-hold;
2800                                 };
2801                         };
2802
2803                         wsa_swr_sleep: wsa-swr-sleep-state {
2804                                 clk-pins {
2805                                         pins = "gpio10";
2806                                         function = "wsa_swr_clk";
2807                                         drive-strength = <2>;
2808                                         bias-pull-down;
2809                                 };
2810
2811                                 data-pins {
2812                                         pins = "gpio11";
2813                                         function = "wsa_swr_data";
2814                                         drive-strength = <2>;
2815                                         bias-pull-down;
2816                                 };
2817                         };
2818
2819                         dmic01_active: dmic01-active-state {
2820                                 clk-pins {
2821                                         pins = "gpio6";
2822                                         function = "dmic1_clk";
2823                                         drive-strength = <8>;
2824                                         output-high;
2825                                 };
2826                                 data-pins {
2827                                         pins = "gpio7";
2828                                         function = "dmic1_data";
2829                                         drive-strength = <8>;
2830                                 };
2831                         };
2832
2833                         dmic01_sleep: dmic01-sleep-state {
2834                                 clk-pins {
2835                                         pins = "gpio6";
2836                                         function = "dmic1_clk";
2837                                         drive-strength = <2>;
2838                                         bias-disable;
2839                                         output-low;
2840                                 };
2841
2842                                 data-pins {
2843                                         pins = "gpio7";
2844                                         function = "dmic1_data";
2845                                         drive-strength = <2>;
2846                                         bias-pull-down;
2847                                 };
2848                         };
2849
2850                         rx_swr_active: rx-swr-active-state {
2851                                 clk-pins {
2852                                         pins = "gpio3";
2853                                         function = "swr_rx_clk";
2854                                         drive-strength = <2>;
2855                                         slew-rate = <1>;
2856                                         bias-disable;
2857                                 };
2858
2859                                 data-pins {
2860                                         pins = "gpio4", "gpio5";
2861                                         function = "swr_rx_data";
2862                                         drive-strength = <2>;
2863                                         slew-rate = <1>;
2864                                         bias-bus-hold;
2865                                 };
2866                         };
2867
2868                         tx_swr_active: tx-swr-active-state {
2869                                 clk-pins {
2870                                         pins = "gpio0";
2871                                         function = "swr_tx_clk";
2872                                         drive-strength = <2>;
2873                                         slew-rate = <1>;
2874                                         bias-disable;
2875                                 };
2876
2877                                 data-pins {
2878                                         pins = "gpio1", "gpio2";
2879                                         function = "swr_tx_data";
2880                                         drive-strength = <2>;
2881                                         slew-rate = <1>;
2882                                         bias-bus-hold;
2883                                 };
2884                         };
2885
2886                         tx_swr_sleep: tx-swr-sleep-state {
2887                                 clk-pins {
2888                                         pins = "gpio0";
2889                                         function = "swr_tx_clk";
2890                                         drive-strength = <2>;
2891                                         bias-pull-down;
2892                                 };
2893
2894                                 data1-pins {
2895                                         pins = "gpio1";
2896                                         function = "swr_tx_data";
2897                                         drive-strength = <2>;
2898                                         bias-bus-hold;
2899                                 };
2900
2901                                 data2-pins {
2902                                         pins = "gpio2";
2903                                         function = "swr_tx_data";
2904                                         drive-strength = <2>;
2905                                         bias-pull-down;
2906                                 };
2907                         };
2908                 };
2909
2910                 gpu: gpu@3d00000 {
2911                         compatible = "qcom,adreno-650.2",
2912                                      "qcom,adreno";
2913
2914                         reg = <0 0x03d00000 0 0x40000>;
2915                         reg-names = "kgsl_3d0_reg_memory";
2916
2917                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2918
2919                         iommus = <&adreno_smmu 0 0x401>;
2920
2921                         operating-points-v2 = <&gpu_opp_table>;
2922
2923                         qcom,gmu = <&gmu>;
2924
2925                         nvmem-cells = <&gpu_speed_bin>;
2926                         nvmem-cell-names = "speed_bin";
2927                         #cooling-cells = <2>;
2928
2929                         status = "disabled";
2930
2931                         zap-shader {
2932                                 memory-region = <&gpu_mem>;
2933                         };
2934
2935                         gpu_opp_table: opp-table {
2936                                 compatible = "operating-points-v2";
2937
2938                                 opp-670000000 {
2939                                         opp-hz = /bits/ 64 <670000000>;
2940                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2941                                         opp-supported-hw = <0xa>;
2942                                 };
2943
2944                                 opp-587000000 {
2945                                         opp-hz = /bits/ 64 <587000000>;
2946                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2947                                         opp-supported-hw = <0xb>;
2948                                 };
2949
2950                                 opp-525000000 {
2951                                         opp-hz = /bits/ 64 <525000000>;
2952                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2953                                         opp-supported-hw = <0xf>;
2954                                 };
2955
2956                                 opp-490000000 {
2957                                         opp-hz = /bits/ 64 <490000000>;
2958                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2959                                         opp-supported-hw = <0xf>;
2960                                 };
2961
2962                                 opp-441600000 {
2963                                         opp-hz = /bits/ 64 <441600000>;
2964                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2965                                         opp-supported-hw = <0xf>;
2966                                 };
2967
2968                                 opp-400000000 {
2969                                         opp-hz = /bits/ 64 <400000000>;
2970                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2971                                         opp-supported-hw = <0xf>;
2972                                 };
2973
2974                                 opp-305000000 {
2975                                         opp-hz = /bits/ 64 <305000000>;
2976                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2977                                         opp-supported-hw = <0xf>;
2978                                 };
2979                         };
2980                 };
2981
2982                 gmu: gmu@3d6a000 {
2983                         compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2984
2985                         reg = <0 0x03d6a000 0 0x30000>,
2986                               <0 0x3de0000 0 0x10000>,
2987                               <0 0xb290000 0 0x10000>,
2988                               <0 0xb490000 0 0x10000>;
2989                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2990
2991                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2992                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2993                         interrupt-names = "hfi", "gmu";
2994
2995                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2996                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2997                                  <&gpucc GPU_CC_CXO_CLK>,
2998                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2999                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3000                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3001
3002                         power-domains = <&gpucc GPU_CX_GDSC>,
3003                                         <&gpucc GPU_GX_GDSC>;
3004                         power-domain-names = "cx", "gx";
3005
3006                         iommus = <&adreno_smmu 5 0x400>;
3007
3008                         operating-points-v2 = <&gmu_opp_table>;
3009
3010                         status = "disabled";
3011
3012                         gmu_opp_table: opp-table {
3013                                 compatible = "operating-points-v2";
3014
3015                                 opp-200000000 {
3016                                         opp-hz = /bits/ 64 <200000000>;
3017                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3018                                 };
3019                         };
3020                 };
3021
3022                 gpucc: clock-controller@3d90000 {
3023                         compatible = "qcom,sm8250-gpucc";
3024                         reg = <0 0x03d90000 0 0x9000>;
3025                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3026                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3027                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3028                         clock-names = "bi_tcxo",
3029                                       "gcc_gpu_gpll0_clk_src",
3030                                       "gcc_gpu_gpll0_div_clk_src";
3031                         #clock-cells = <1>;
3032                         #reset-cells = <1>;
3033                         #power-domain-cells = <1>;
3034                 };
3035
3036                 adreno_smmu: iommu@3da0000 {
3037                         compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3038                                      "qcom,smmu-500", "arm,mmu-500";
3039                         reg = <0 0x03da0000 0 0x10000>;
3040                         #iommu-cells = <2>;
3041                         #global-interrupts = <2>;
3042                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3043                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3044                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3045                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3046                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3047                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3048                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3049                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3050                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3051                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3052                         clocks = <&gpucc GPU_CC_AHB_CLK>,
3053                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3054                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3055                         clock-names = "ahb", "bus", "iface";
3056
3057                         power-domains = <&gpucc GPU_CX_GDSC>;
3058                         dma-coherent;
3059                 };
3060
3061                 slpi: remoteproc@5c00000 {
3062                         compatible = "qcom,sm8250-slpi-pas";
3063                         reg = <0 0x05c00000 0 0x4000>;
3064
3065                         interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
3066                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3067                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3068                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3069                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3070                         interrupt-names = "wdog", "fatal", "ready",
3071                                           "handover", "stop-ack";
3072
3073                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3074                         clock-names = "xo";
3075
3076                         power-domains = <&rpmhpd RPMHPD_LCX>,
3077                                         <&rpmhpd RPMHPD_LMX>;
3078                         power-domain-names = "lcx", "lmx";
3079
3080                         memory-region = <&slpi_mem>;
3081
3082                         qcom,qmp = <&aoss_qmp>;
3083
3084                         qcom,smem-states = <&smp2p_slpi_out 0>;
3085                         qcom,smem-state-names = "stop";
3086
3087                         status = "disabled";
3088
3089                         glink-edge {
3090                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3091                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3092                                                              IRQ_TYPE_EDGE_RISING>;
3093                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
3094                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3095
3096                                 label = "slpi";
3097                                 qcom,remote-pid = <3>;
3098
3099                                 fastrpc {
3100                                         compatible = "qcom,fastrpc";
3101                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3102                                         label = "sdsp";
3103                                         qcom,non-secure-domain;
3104                                         #address-cells = <1>;
3105                                         #size-cells = <0>;
3106
3107                                         compute-cb@1 {
3108                                                 compatible = "qcom,fastrpc-compute-cb";
3109                                                 reg = <1>;
3110                                                 iommus = <&apps_smmu 0x0541 0x0>;
3111                                         };
3112
3113                                         compute-cb@2 {
3114                                                 compatible = "qcom,fastrpc-compute-cb";
3115                                                 reg = <2>;
3116                                                 iommus = <&apps_smmu 0x0542 0x0>;
3117                                         };
3118
3119                                         compute-cb@3 {
3120                                                 compatible = "qcom,fastrpc-compute-cb";
3121                                                 reg = <3>;
3122                                                 iommus = <&apps_smmu 0x0543 0x0>;
3123                                                 /* note: shared-cb = <4> in downstream */
3124                                         };
3125                                 };
3126                         };
3127                 };
3128
3129                 stm@6002000 {
3130                         compatible = "arm,coresight-stm", "arm,primecell";
3131                         reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3132                         reg-names = "stm-base", "stm-stimulus-base";
3133
3134                         clocks = <&aoss_qmp>;
3135                         clock-names = "apb_pclk";
3136
3137                         out-ports {
3138                                 port {
3139                                         stm_out: endpoint {
3140                                                 remote-endpoint = <&funnel0_in7>;
3141                                         };
3142                                 };
3143                         };
3144                 };
3145
3146                 tpda@6004000 {
3147                         compatible = "qcom,coresight-tpda", "arm,primecell";
3148                         reg = <0 0x06004000 0 0x1000>;
3149
3150                         clocks = <&aoss_qmp>;
3151                         clock-names = "apb_pclk";
3152
3153                         out-ports {
3154
3155                                 port {
3156                                         tpda_out_funnel_qatb: endpoint {
3157                                                 remote-endpoint = <&funnel_qatb_in_tpda>;
3158                                         };
3159                                 };
3160                         };
3161
3162                         in-ports {
3163                                 #address-cells = <1>;
3164                                 #size-cells = <0>;
3165
3166                                 port@9 {
3167                                         reg = <9>;
3168                                         tpda_9_in_tpdm_mm: endpoint {
3169                                                 remote-endpoint = <&tpdm_mm_out_tpda9>;
3170                                         };
3171                                 };
3172
3173                                 port@17 {
3174                                         reg = <23>;
3175                                         tpda_23_in_tpdm_prng: endpoint {
3176                                                 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3177                                         };
3178                                 };
3179                         };
3180                 };
3181
3182                 funnel@6005000 {
3183                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3184                         reg = <0 0x06005000 0 0x1000>;
3185
3186                         clocks = <&aoss_qmp>;
3187                         clock-names = "apb_pclk";
3188
3189                         out-ports {
3190                                 port {
3191                                         funnel_qatb_out_funnel_in0: endpoint {
3192                                                 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3193                                         };
3194                                 };
3195                         };
3196
3197                         in-ports {
3198                                 port {
3199                                         funnel_qatb_in_tpda: endpoint {
3200                                                 remote-endpoint = <&tpda_out_funnel_qatb>;
3201                                         };
3202                                 };
3203                         };
3204                 };
3205
3206                 funnel@6041000 {
3207                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3208                         reg = <0 0x06041000 0 0x1000>;
3209
3210                         clocks = <&aoss_qmp>;
3211                         clock-names = "apb_pclk";
3212
3213                         out-ports {
3214                                 port {
3215                                         funnel_in0_out_funnel_merg: endpoint {
3216                                                 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3217                                         };
3218                                 };
3219                         };
3220
3221                         in-ports {
3222                                 #address-cells = <1>;
3223                                 #size-cells = <0>;
3224
3225                                 port@6 {
3226                                         reg = <6>;
3227                                         funnel_in0_in_funnel_qatb: endpoint {
3228                                                 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3229                                         };
3230                                 };
3231
3232                                 port@7 {
3233                                         reg = <7>;
3234                                         funnel0_in7: endpoint {
3235                                                 remote-endpoint = <&stm_out>;
3236                                         };
3237                                 };
3238                         };
3239                 };
3240
3241                 funnel@6042000 {
3242                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3243                         reg = <0 0x06042000 0 0x1000>;
3244
3245                         clocks = <&aoss_qmp>;
3246                         clock-names = "apb_pclk";
3247
3248                         out-ports {
3249                                 port {
3250                                         funnel_in1_out_funnel_merg: endpoint {
3251                                                 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3252                                         };
3253                                 };
3254                         };
3255
3256                         in-ports {
3257                                 #address-cells = <1>;
3258                                 #size-cells = <0>;
3259
3260                                 port@4 {
3261                                         reg = <4>;
3262                                         funnel_in1_in_funnel_apss_merg: endpoint {
3263                                         remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3264                                         };
3265                                 };
3266                         };
3267                 };
3268
3269                 funnel@6045000 {
3270                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3271                         reg = <0 0x06045000 0 0x1000>;
3272
3273                         clocks = <&aoss_qmp>;
3274                         clock-names = "apb_pclk";
3275
3276                         out-ports {
3277                                 port {
3278                                         funnel_merg_out_funnel_swao: endpoint {
3279                                         remote-endpoint = <&funnel_swao_in_funnel_merg>;
3280                                         };
3281                                 };
3282                         };
3283
3284                         in-ports {
3285                                 #address-cells = <1>;
3286                                 #size-cells = <0>;
3287
3288                                 port@0 {
3289                                         reg = <0>;
3290                                         funnel_merg_in_funnel_in0: endpoint {
3291                                         remote-endpoint = <&funnel_in0_out_funnel_merg>;
3292                                         };
3293                                 };
3294
3295                                 port@1 {
3296                                         reg = <1>;
3297                                         funnel_merg_in_funnel_in1: endpoint {
3298                                         remote-endpoint = <&funnel_in1_out_funnel_merg>;
3299                                         };
3300                                 };
3301                         };
3302                 };
3303
3304                 replicator@6046000 {
3305                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3306                         reg = <0 0x06046000 0 0x1000>;
3307
3308                         clocks = <&aoss_qmp>;
3309                         clock-names = "apb_pclk";
3310
3311                         out-ports {
3312                                 port {
3313                                         replicator_out: endpoint {
3314                                                 remote-endpoint = <&etr_in>;
3315                                         };
3316                                 };
3317                         };
3318
3319                         in-ports {
3320                                 port {
3321                                         replicator_cx_in_swao_out: endpoint {
3322                                                 remote-endpoint = <&replicator_swao_out_cx_in>;
3323                                         };
3324                                 };
3325                         };
3326                 };
3327
3328                 etr@6048000 {
3329                         compatible = "arm,coresight-tmc", "arm,primecell";
3330                         reg = <0 0x06048000 0 0x1000>;
3331
3332                         clocks = <&aoss_qmp>;
3333                         clock-names = "apb_pclk";
3334                         arm,scatter-gather;
3335
3336                         in-ports {
3337                                 port {
3338                                         etr_in: endpoint {
3339                                                 remote-endpoint = <&replicator_out>;
3340                                         };
3341                                 };
3342                         };
3343                 };
3344
3345                 tpdm@684c000 {
3346                         compatible = "qcom,coresight-tpdm", "arm,primecell";
3347                         reg = <0 0x0684c000 0 0x1000>;
3348
3349                         clocks = <&aoss_qmp>;
3350                         clock-names = "apb_pclk";
3351
3352                         out-ports {
3353                                 port {
3354                                         tpdm_prng_out_tpda_23: endpoint {
3355                                                 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3356                                         };
3357                                 };
3358                         };
3359                 };
3360
3361                 funnel@6b04000 {
3362                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3363                         arm,primecell-periphid = <0x000bb908>;
3364
3365                         reg = <0 0x06b04000 0 0x1000>;
3366
3367                         clocks = <&aoss_qmp>;
3368                         clock-names = "apb_pclk";
3369
3370                         out-ports {
3371                                 port {
3372                                         funnel_swao_out_etf: endpoint {
3373                                                 remote-endpoint = <&etf_in_funnel_swao_out>;
3374                                         };
3375                                 };
3376                         };
3377
3378                         in-ports {
3379                                 #address-cells = <1>;
3380                                 #size-cells = <0>;
3381
3382                                 port@7 {
3383                                         reg = <7>;
3384                                         funnel_swao_in_funnel_merg: endpoint {
3385                                                 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3386                                         };
3387                                 };
3388                         };
3389                 };
3390
3391                 etf@6b05000 {
3392                         compatible = "arm,coresight-tmc", "arm,primecell";
3393                         reg = <0 0x06b05000 0 0x1000>;
3394
3395                         clocks = <&aoss_qmp>;
3396                         clock-names = "apb_pclk";
3397
3398                         out-ports {
3399                                 port {
3400                                         etf_out: endpoint {
3401                                                 remote-endpoint = <&replicator_in>;
3402                                         };
3403                                 };
3404                         };
3405
3406                         in-ports {
3407
3408                                 port {
3409                                         etf_in_funnel_swao_out: endpoint {
3410                                                 remote-endpoint = <&funnel_swao_out_etf>;
3411                                         };
3412                                 };
3413                         };
3414                 };
3415
3416                 replicator@6b06000 {
3417                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3418                         reg = <0 0x06b06000 0 0x1000>;
3419
3420                         clocks = <&aoss_qmp>;
3421                         clock-names = "apb_pclk";
3422
3423                         out-ports {
3424                                 port {
3425                                         replicator_swao_out_cx_in: endpoint {
3426                                                 remote-endpoint = <&replicator_cx_in_swao_out>;
3427                                         };
3428                                 };
3429                         };
3430
3431                         in-ports {
3432                                 port {
3433                                         replicator_in: endpoint {
3434                                                 remote-endpoint = <&etf_out>;
3435                                         };
3436                                 };
3437                         };
3438                 };
3439
3440                 tpdm@6c08000 {
3441                         compatible = "qcom,coresight-tpdm", "arm,primecell";
3442                         reg = <0 0x06c08000 0 0x1000>;
3443
3444                         clocks = <&aoss_qmp>;
3445                         clock-names = "apb_pclk";
3446
3447                         out-ports {
3448                                 port {
3449                                         tpdm_mm_out_funnel_dl_mm: endpoint {
3450                                                 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3451                                         };
3452                                 };
3453                         };
3454                 };
3455
3456                 funnel@6c0b000 {
3457                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3458                         reg = <0 0x06c0b000 0 0x1000>;
3459
3460                         clocks = <&aoss_qmp>;
3461                         clock-names = "apb_pclk";
3462
3463                         out-ports {
3464                                 port {
3465                                         funnel_dl_mm_out_funnel_dl_center: endpoint {
3466                                         remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3467                                         };
3468                                 };
3469                         };
3470
3471                         in-ports {
3472                                 #address-cells = <1>;
3473                                 #size-cells = <0>;
3474
3475                                 port@3 {
3476                                         reg = <3>;
3477                                         funnel_dl_mm_in_tpdm_mm: endpoint {
3478                                                 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3479                                         };
3480                                 };
3481                         };
3482                 };
3483
3484                 funnel@6c2d000 {
3485                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3486                         reg = <0 0x06c2d000 0 0x1000>;
3487
3488                         clocks = <&aoss_qmp>;
3489                         clock-names = "apb_pclk";
3490
3491                         out-ports {
3492                                 port {
3493                                         tpdm_mm_out_tpda9: endpoint {
3494                                                 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3495                                         };
3496                                 };
3497                         };
3498
3499                         in-ports {
3500                                 #address-cells = <1>;
3501                                 #size-cells = <0>;
3502
3503                                 port@2 {
3504                                         reg = <2>;
3505                                         funnel_dl_center_in_funnel_dl_mm: endpoint {
3506                                         remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3507                                         };
3508                                 };
3509                         };
3510                 };
3511
3512                 etm@7040000 {
3513                         compatible = "arm,coresight-etm4x", "arm,primecell";
3514                         reg = <0 0x07040000 0 0x1000>;
3515
3516                         cpu = <&CPU0>;
3517
3518                         clocks = <&aoss_qmp>;
3519                         clock-names = "apb_pclk";
3520                         arm,coresight-loses-context-with-cpu;
3521
3522                         out-ports {
3523                                 port {
3524                                         etm0_out: endpoint {
3525                                                 remote-endpoint = <&apss_funnel_in0>;
3526                                         };
3527                                 };
3528                         };
3529                 };
3530
3531                 etm@7140000 {
3532                         compatible = "arm,coresight-etm4x", "arm,primecell";
3533                         reg = <0 0x07140000 0 0x1000>;
3534
3535                         cpu = <&CPU1>;
3536
3537                         clocks = <&aoss_qmp>;
3538                         clock-names = "apb_pclk";
3539                         arm,coresight-loses-context-with-cpu;
3540
3541                         out-ports {
3542                                 port {
3543                                         etm1_out: endpoint {
3544                                                 remote-endpoint = <&apss_funnel_in1>;
3545                                         };
3546                                 };
3547                         };
3548                 };
3549
3550                 etm@7240000 {
3551                         compatible = "arm,coresight-etm4x", "arm,primecell";
3552                         reg = <0 0x07240000 0 0x1000>;
3553
3554                         cpu = <&CPU2>;
3555
3556                         clocks = <&aoss_qmp>;
3557                         clock-names = "apb_pclk";
3558                         arm,coresight-loses-context-with-cpu;
3559
3560                         out-ports {
3561                                 port {
3562                                         etm2_out: endpoint {
3563                                                 remote-endpoint = <&apss_funnel_in2>;
3564                                         };
3565                                 };
3566                         };
3567                 };
3568
3569                 etm@7340000 {
3570                         compatible = "arm,coresight-etm4x", "arm,primecell";
3571                         reg = <0 0x07340000 0 0x1000>;
3572
3573                         cpu = <&CPU3>;
3574
3575                         clocks = <&aoss_qmp>;
3576                         clock-names = "apb_pclk";
3577                         arm,coresight-loses-context-with-cpu;
3578
3579                         out-ports {
3580                                 port {
3581                                         etm3_out: endpoint {
3582                                                 remote-endpoint = <&apss_funnel_in3>;
3583                                         };
3584                                 };
3585                         };
3586                 };
3587
3588                 etm@7440000 {
3589                         compatible = "arm,coresight-etm4x", "arm,primecell";
3590                         reg = <0 0x07440000 0 0x1000>;
3591
3592                         cpu = <&CPU4>;
3593
3594                         clocks = <&aoss_qmp>;
3595                         clock-names = "apb_pclk";
3596                         arm,coresight-loses-context-with-cpu;
3597
3598                         out-ports {
3599                                 port {
3600                                         etm4_out: endpoint {
3601                                                 remote-endpoint = <&apss_funnel_in4>;
3602                                         };
3603                                 };
3604                         };
3605                 };
3606
3607                 etm@7540000 {
3608                         compatible = "arm,coresight-etm4x", "arm,primecell";
3609                         reg = <0 0x07540000 0 0x1000>;
3610
3611                         cpu = <&CPU5>;
3612
3613                         clocks = <&aoss_qmp>;
3614                         clock-names = "apb_pclk";
3615                         arm,coresight-loses-context-with-cpu;
3616
3617                         out-ports {
3618                                 port {
3619                                         etm5_out: endpoint {
3620                                                 remote-endpoint = <&apss_funnel_in5>;
3621                                         };
3622                                 };
3623                         };
3624                 };
3625
3626                 etm@7640000 {
3627                         compatible = "arm,coresight-etm4x", "arm,primecell";
3628                         reg = <0 0x07640000 0 0x1000>;
3629
3630                         cpu = <&CPU6>;
3631
3632                         clocks = <&aoss_qmp>;
3633                         clock-names = "apb_pclk";
3634                         arm,coresight-loses-context-with-cpu;
3635
3636                         out-ports {
3637                                 port {
3638                                         etm6_out: endpoint {
3639                                                 remote-endpoint = <&apss_funnel_in6>;
3640                                         };
3641                                 };
3642                         };
3643                 };
3644
3645                 etm@7740000 {
3646                         compatible = "arm,coresight-etm4x", "arm,primecell";
3647                         reg = <0 0x07740000 0 0x1000>;
3648
3649                         cpu = <&CPU7>;
3650
3651                         clocks = <&aoss_qmp>;
3652                         clock-names = "apb_pclk";
3653                         arm,coresight-loses-context-with-cpu;
3654
3655                         out-ports {
3656                                 port {
3657                                         etm7_out: endpoint {
3658                                                 remote-endpoint = <&apss_funnel_in7>;
3659                                         };
3660                                 };
3661                         };
3662                 };
3663
3664                 funnel@7800000 {
3665                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3666                         reg = <0 0x07800000 0 0x1000>;
3667
3668                         clocks = <&aoss_qmp>;
3669                         clock-names = "apb_pclk";
3670
3671                         out-ports {
3672                                 port {
3673                                         funnel_apss_out_funnel_apss_merg: endpoint {
3674                                         remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3675                                         };
3676                                 };
3677                         };
3678
3679                         in-ports {
3680                                 #address-cells = <1>;
3681                                 #size-cells = <0>;
3682
3683                                 port@0 {
3684                                         reg = <0>;
3685                                         apss_funnel_in0: endpoint {
3686                                                 remote-endpoint = <&etm0_out>;
3687                                         };
3688                                 };
3689
3690                                 port@1 {
3691                                         reg = <1>;
3692                                         apss_funnel_in1: endpoint {
3693                                                 remote-endpoint = <&etm1_out>;
3694                                         };
3695                                 };
3696
3697                                 port@2 {
3698                                         reg = <2>;
3699                                         apss_funnel_in2: endpoint {
3700                                                 remote-endpoint = <&etm2_out>;
3701                                         };
3702                                 };
3703
3704                                 port@3 {
3705                                         reg = <3>;
3706                                         apss_funnel_in3: endpoint {
3707                                                 remote-endpoint = <&etm3_out>;
3708                                         };
3709                                 };
3710
3711                                 port@4 {
3712                                         reg = <4>;
3713                                         apss_funnel_in4: endpoint {
3714                                                 remote-endpoint = <&etm4_out>;
3715                                         };
3716                                 };
3717
3718                                 port@5 {
3719                                         reg = <5>;
3720                                         apss_funnel_in5: endpoint {
3721                                                 remote-endpoint = <&etm5_out>;
3722                                         };
3723                                 };
3724
3725                                 port@6 {
3726                                         reg = <6>;
3727                                         apss_funnel_in6: endpoint {
3728                                                 remote-endpoint = <&etm6_out>;
3729                                         };
3730                                 };
3731
3732                                 port@7 {
3733                                         reg = <7>;
3734                                         apss_funnel_in7: endpoint {
3735                                                 remote-endpoint = <&etm7_out>;
3736                                         };
3737                                 };
3738                         };
3739                 };
3740
3741                 funnel@7810000 {
3742                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3743                         reg = <0 0x07810000 0 0x1000>;
3744
3745                         clocks = <&aoss_qmp>;
3746                         clock-names = "apb_pclk";
3747
3748                         out-ports {
3749                                 port {
3750                                         funnel_apss_merg_out_funnel_in1: endpoint {
3751                                         remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3752                                         };
3753                                 };
3754                         };
3755
3756                         in-ports {
3757                                 port {
3758                                         funnel_apss_merg_in_funnel_apss: endpoint {
3759                                         remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3760                                         };
3761                                 };
3762                         };
3763                 };
3764
3765                 cdsp: remoteproc@8300000 {
3766                         compatible = "qcom,sm8250-cdsp-pas";
3767                         reg = <0 0x08300000 0 0x10000>;
3768
3769                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3770                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3771                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3772                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3773                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3774                         interrupt-names = "wdog", "fatal", "ready",
3775                                           "handover", "stop-ack";
3776
3777                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3778                         clock-names = "xo";
3779
3780                         power-domains = <&rpmhpd RPMHPD_CX>;
3781
3782                         memory-region = <&cdsp_mem>;
3783
3784                         qcom,qmp = <&aoss_qmp>;
3785
3786                         qcom,smem-states = <&smp2p_cdsp_out 0>;
3787                         qcom,smem-state-names = "stop";
3788
3789                         status = "disabled";
3790
3791                         glink-edge {
3792                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3793                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3794                                                              IRQ_TYPE_EDGE_RISING>;
3795                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
3796                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3797
3798                                 label = "cdsp";
3799                                 qcom,remote-pid = <5>;
3800
3801                                 fastrpc {
3802                                         compatible = "qcom,fastrpc";
3803                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3804                                         label = "cdsp";
3805                                         qcom,non-secure-domain;
3806                                         #address-cells = <1>;
3807                                         #size-cells = <0>;
3808
3809                                         compute-cb@1 {
3810                                                 compatible = "qcom,fastrpc-compute-cb";
3811                                                 reg = <1>;
3812                                                 iommus = <&apps_smmu 0x1001 0x0460>;
3813                                         };
3814
3815                                         compute-cb@2 {
3816                                                 compatible = "qcom,fastrpc-compute-cb";
3817                                                 reg = <2>;
3818                                                 iommus = <&apps_smmu 0x1002 0x0460>;
3819                                         };
3820
3821                                         compute-cb@3 {
3822                                                 compatible = "qcom,fastrpc-compute-cb";
3823                                                 reg = <3>;
3824                                                 iommus = <&apps_smmu 0x1003 0x0460>;
3825                                         };
3826
3827                                         compute-cb@4 {
3828                                                 compatible = "qcom,fastrpc-compute-cb";
3829                                                 reg = <4>;
3830                                                 iommus = <&apps_smmu 0x1004 0x0460>;
3831                                         };
3832
3833                                         compute-cb@5 {
3834                                                 compatible = "qcom,fastrpc-compute-cb";
3835                                                 reg = <5>;
3836                                                 iommus = <&apps_smmu 0x1005 0x0460>;
3837                                         };
3838
3839                                         compute-cb@6 {
3840                                                 compatible = "qcom,fastrpc-compute-cb";
3841                                                 reg = <6>;
3842                                                 iommus = <&apps_smmu 0x1006 0x0460>;
3843                                         };
3844
3845                                         compute-cb@7 {
3846                                                 compatible = "qcom,fastrpc-compute-cb";
3847                                                 reg = <7>;
3848                                                 iommus = <&apps_smmu 0x1007 0x0460>;
3849                                         };
3850
3851                                         compute-cb@8 {
3852                                                 compatible = "qcom,fastrpc-compute-cb";
3853                                                 reg = <8>;
3854                                                 iommus = <&apps_smmu 0x1008 0x0460>;
3855                                         };
3856
3857                                         /* note: secure cb9 in downstream */
3858                                 };
3859                         };
3860                 };
3861
3862                 usb_1_hsphy: phy@88e3000 {
3863                         compatible = "qcom,sm8250-usb-hs-phy",
3864                                      "qcom,usb-snps-hs-7nm-phy";
3865                         reg = <0 0x088e3000 0 0x400>;
3866                         status = "disabled";
3867                         #phy-cells = <0>;
3868
3869                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3870                         clock-names = "ref";
3871
3872                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3873                 };
3874
3875                 usb_2_hsphy: phy@88e4000 {
3876                         compatible = "qcom,sm8250-usb-hs-phy",
3877                                      "qcom,usb-snps-hs-7nm-phy";
3878                         reg = <0 0x088e4000 0 0x400>;
3879                         status = "disabled";
3880                         #phy-cells = <0>;
3881
3882                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3883                         clock-names = "ref";
3884
3885                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3886                 };
3887
3888                 usb_1_qmpphy: phy@88e8000 {
3889                         compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3890                         reg = <0 0x088e8000 0 0x3000>;
3891                         status = "disabled";
3892
3893                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3894                                  <&rpmhcc RPMH_CXO_CLK>,
3895                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3896                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3897                         clock-names = "aux",
3898                                       "ref",
3899                                       "com_aux",
3900                                       "usb3_pipe";
3901
3902                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3903                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3904                         reset-names = "phy", "common";
3905
3906                         #clock-cells = <1>;
3907                         #phy-cells = <1>;
3908
3909                         ports {
3910                                 #address-cells = <1>;
3911                                 #size-cells = <0>;
3912
3913                                 port@0 {
3914                                         reg = <0>;
3915                                         usb_1_qmpphy_out: endpoint {};
3916                                 };
3917
3918                                 port@1 {
3919                                         reg = <1>;
3920                                 };
3921
3922                                 port@2 {
3923                                         reg = <2>;
3924
3925                                         usb_1_qmpphy_dp_in: endpoint {};
3926                                 };
3927                         };
3928                 };
3929
3930                 usb_2_qmpphy: phy@88eb000 {
3931                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3932                         reg = <0 0x088eb000 0 0x1000>;
3933
3934                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3935                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
3936                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3937                                  <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3938                         clock-names = "aux",
3939                                       "ref",
3940                                       "com_aux",
3941                                       "pipe";
3942                         clock-output-names = "usb3_uni_phy_pipe_clk_src";
3943                         #clock-cells = <0>;
3944                         #phy-cells = <0>;
3945
3946                         resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3947                                  <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3948                         reset-names = "phy",
3949                                       "phy_phy";
3950
3951                         status = "disabled";
3952                 };
3953
3954                 sdhc_2: mmc@8804000 {
3955                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3956                         reg = <0 0x08804000 0 0x1000>;
3957
3958                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3959                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3960                         interrupt-names = "hc_irq", "pwr_irq";
3961
3962                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3963                                  <&gcc GCC_SDCC2_APPS_CLK>,
3964                                  <&rpmhcc RPMH_CXO_CLK>;
3965                         clock-names = "iface", "core", "xo";
3966                         iommus = <&apps_smmu 0x4a0 0x0>;
3967                         qcom,dll-config = <0x0007642c>;
3968                         qcom,ddr-config = <0x80040868>;
3969                         power-domains = <&rpmhpd RPMHPD_CX>;
3970                         operating-points-v2 = <&sdhc2_opp_table>;
3971
3972                         status = "disabled";
3973
3974                         sdhc2_opp_table: opp-table {
3975                                 compatible = "operating-points-v2";
3976
3977                                 opp-19200000 {
3978                                         opp-hz = /bits/ 64 <19200000>;
3979                                         required-opps = <&rpmhpd_opp_min_svs>;
3980                                 };
3981
3982                                 opp-50000000 {
3983                                         opp-hz = /bits/ 64 <50000000>;
3984                                         required-opps = <&rpmhpd_opp_low_svs>;
3985                                 };
3986
3987                                 opp-100000000 {
3988                                         opp-hz = /bits/ 64 <100000000>;
3989                                         required-opps = <&rpmhpd_opp_svs>;
3990                                 };
3991
3992                                 opp-202000000 {
3993                                         opp-hz = /bits/ 64 <202000000>;
3994                                         required-opps = <&rpmhpd_opp_svs_l1>;
3995                                 };
3996                         };
3997                 };
3998
3999                 pmu@9091000 {
4000                         compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4001                         reg = <0 0x09091000 0 0x1000>;
4002
4003                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4004
4005                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
4006
4007                         operating-points-v2 = <&llcc_bwmon_opp_table>;
4008
4009                         llcc_bwmon_opp_table: opp-table {
4010                                 compatible = "operating-points-v2";
4011
4012                                 opp-800000 {
4013                                         opp-peak-kBps = <(200 * 4 * 1000)>;
4014                                 };
4015
4016                                 opp-1200000 {
4017                                         opp-peak-kBps = <(300 * 4 * 1000)>;
4018                                 };
4019
4020                                 opp-1804000 {
4021                                         opp-peak-kBps = <(451 * 4 * 1000)>;
4022                                 };
4023
4024                                 opp-2188000 {
4025                                         opp-peak-kBps = <(547 * 4 * 1000)>;
4026                                 };
4027
4028                                 opp-2724000 {
4029                                         opp-peak-kBps = <(681 * 4 * 1000)>;
4030                                 };
4031
4032                                 opp-3072000 {
4033                                         opp-peak-kBps = <(768 * 4 * 1000)>;
4034                                 };
4035
4036                                 opp-4068000 {
4037                                         opp-peak-kBps = <(1017 * 4 * 1000)>;
4038                                 };
4039
4040                                 /* 1353 MHz, LPDDR4X */
4041
4042                                 opp-6220000 {
4043                                         opp-peak-kBps = <(1555 * 4 * 1000)>;
4044                                 };
4045
4046                                 opp-7216000 {
4047                                         opp-peak-kBps = <(1804 * 4 * 1000)>;
4048                                 };
4049
4050                                 opp-8368000 {
4051                                         opp-peak-kBps = <(2092 * 4 * 1000)>;
4052                                 };
4053
4054                                 /* LPDDR5 */
4055                                 opp-10944000 {
4056                                         opp-peak-kBps = <(2736 * 4 * 1000)>;
4057                                 };
4058                         };
4059                 };
4060
4061                 pmu@90b6400 {
4062                         compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4063                         reg = <0 0x090b6400 0 0x600>;
4064
4065                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4066
4067                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
4068                         operating-points-v2 = <&cpu_bwmon_opp_table>;
4069
4070                         cpu_bwmon_opp_table: opp-table {
4071                                 compatible = "operating-points-v2";
4072
4073                                 opp-800000 {
4074                                         opp-peak-kBps = <(200 * 4 * 1000)>;
4075                                 };
4076
4077                                 opp-1804000 {
4078                                         opp-peak-kBps = <(451 * 4 * 1000)>;
4079                                 };
4080
4081                                 opp-2188000 {
4082                                         opp-peak-kBps = <(547 * 4 * 1000)>;
4083                                 };
4084
4085                                 opp-2724000 {
4086                                         opp-peak-kBps = <(681 * 4 * 1000)>;
4087                                 };
4088
4089                                 opp-3072000 {
4090                                         opp-peak-kBps = <(768 * 4 * 1000)>;
4091                                 };
4092
4093                                 /* 1017MHz, 1353 MHz, LPDDR4X */
4094
4095                                 opp-6220000 {
4096                                         opp-peak-kBps = <(1555 * 4 * 1000)>;
4097                                 };
4098
4099                                 opp-6832000 {
4100                                         opp-peak-kBps = <(1708 * 4 * 1000)>;
4101                                 };
4102
4103                                 opp-8368000 {
4104                                         opp-peak-kBps = <(2092 * 4 * 1000)>;
4105                                 };
4106
4107                                 /* 2133MHz, LPDDR4X */
4108
4109                                 /* LPDDR5 */
4110                                 opp-10944000 {
4111                                         opp-peak-kBps = <(2736 * 4 * 1000)>;
4112                                 };
4113
4114                                 /* LPDDR5 */
4115                                 opp-12784000 {
4116                                         opp-peak-kBps = <(3196 * 4 * 1000)>;
4117                                 };
4118                         };
4119                 };
4120
4121                 dc_noc: interconnect@90c0000 {
4122                         compatible = "qcom,sm8250-dc-noc";
4123                         reg = <0 0x090c0000 0 0x4200>;
4124                         #interconnect-cells = <2>;
4125                         qcom,bcm-voters = <&apps_bcm_voter>;
4126                 };
4127
4128                 gem_noc: interconnect@9100000 {
4129                         compatible = "qcom,sm8250-gem-noc";
4130                         reg = <0 0x09100000 0 0xb4000>;
4131                         #interconnect-cells = <2>;
4132                         qcom,bcm-voters = <&apps_bcm_voter>;
4133                 };
4134
4135                 npu_noc: interconnect@9990000 {
4136                         compatible = "qcom,sm8250-npu-noc";
4137                         reg = <0 0x09990000 0 0x1600>;
4138                         #interconnect-cells = <2>;
4139                         qcom,bcm-voters = <&apps_bcm_voter>;
4140                 };
4141
4142                 usb_1: usb@a6f8800 {
4143                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4144                         reg = <0 0x0a6f8800 0 0x400>;
4145                         status = "disabled";
4146                         #address-cells = <2>;
4147                         #size-cells = <2>;
4148                         ranges;
4149                         dma-ranges;
4150
4151                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4152                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4153                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4154                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4155                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4156                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
4157                         clock-names = "cfg_noc",
4158                                       "core",
4159                                       "iface",
4160                                       "sleep",
4161                                       "mock_utmi",
4162                                       "xo";
4163
4164                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4165                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4166                         assigned-clock-rates = <19200000>, <200000000>;
4167
4168                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4169                                               <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4170                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4171                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4172                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4173                         interrupt-names = "pwr_event",
4174                                           "hs_phy_irq",
4175                                           "dp_hs_phy_irq",
4176                                           "dm_hs_phy_irq",
4177                                           "ss_phy_irq";
4178
4179                         power-domains = <&gcc USB30_PRIM_GDSC>;
4180                         wakeup-source;
4181
4182                         resets = <&gcc GCC_USB30_PRIM_BCR>;
4183
4184                         interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4185                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4186                         interconnect-names = "usb-ddr", "apps-usb";
4187
4188                         usb_1_dwc3: usb@a600000 {
4189                                 compatible = "snps,dwc3";
4190                                 reg = <0 0x0a600000 0 0xcd00>;
4191                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4192                                 iommus = <&apps_smmu 0x0 0x0>;
4193                                 snps,dis_u2_susphy_quirk;
4194                                 snps,dis_enblslpm_quirk;
4195                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4196                                 phy-names = "usb2-phy", "usb3-phy";
4197
4198                                 port {
4199                                         usb_1_role_switch_out: endpoint {};
4200                                 };
4201                         };
4202                 };
4203
4204                 system-cache-controller@9200000 {
4205                         compatible = "qcom,sm8250-llcc";
4206                         reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4207                               <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4208                               <0 0x09600000 0 0x50000>;
4209                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4210                                     "llcc3_base", "llcc_broadcast_base";
4211                 };
4212
4213                 usb_2: usb@a8f8800 {
4214                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4215                         reg = <0 0x0a8f8800 0 0x400>;
4216                         status = "disabled";
4217                         #address-cells = <2>;
4218                         #size-cells = <2>;
4219                         ranges;
4220                         dma-ranges;
4221
4222                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4223                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
4224                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4225                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4226                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4227                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
4228                         clock-names = "cfg_noc",
4229                                       "core",
4230                                       "iface",
4231                                       "sleep",
4232                                       "mock_utmi",
4233                                       "xo";
4234
4235                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4236                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
4237                         assigned-clock-rates = <19200000>, <200000000>;
4238
4239                         interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4240                                               <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4241                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4242                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4243                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4244                         interrupt-names = "pwr_event",
4245                                           "hs_phy_irq",
4246                                           "dp_hs_phy_irq",
4247                                           "dm_hs_phy_irq",
4248                                           "ss_phy_irq";
4249
4250                         power-domains = <&gcc USB30_SEC_GDSC>;
4251                         wakeup-source;
4252
4253                         resets = <&gcc GCC_USB30_SEC_BCR>;
4254
4255                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4256                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4257                         interconnect-names = "usb-ddr", "apps-usb";
4258
4259                         usb_2_dwc3: usb@a800000 {
4260                                 compatible = "snps,dwc3";
4261                                 reg = <0 0x0a800000 0 0xcd00>;
4262                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4263                                 iommus = <&apps_smmu 0x20 0>;
4264                                 snps,dis_u2_susphy_quirk;
4265                                 snps,dis_enblslpm_quirk;
4266                                 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
4267                                 phy-names = "usb2-phy", "usb3-phy";
4268                         };
4269                 };
4270
4271                 venus: video-codec@aa00000 {
4272                         compatible = "qcom,sm8250-venus";
4273                         reg = <0 0x0aa00000 0 0x100000>;
4274                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4275                         power-domains = <&videocc MVS0C_GDSC>,
4276                                         <&videocc MVS0_GDSC>,
4277                                         <&rpmhpd RPMHPD_MX>;
4278                         power-domain-names = "venus", "vcodec0", "mx";
4279                         operating-points-v2 = <&venus_opp_table>;
4280
4281                         clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4282                                  <&videocc VIDEO_CC_MVS0C_CLK>,
4283                                  <&videocc VIDEO_CC_MVS0_CLK>;
4284                         clock-names = "iface", "core", "vcodec0_core";
4285
4286                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4287                                         <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4288                         interconnect-names = "cpu-cfg", "video-mem";
4289
4290                         iommus = <&apps_smmu 0x2100 0x0400>;
4291                         memory-region = <&video_mem>;
4292
4293                         resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4294                                  <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4295                         reset-names = "bus", "core";
4296
4297                         status = "disabled";
4298
4299                         video-decoder {
4300                                 compatible = "venus-decoder";
4301                         };
4302
4303                         video-encoder {
4304                                 compatible = "venus-encoder";
4305                         };
4306
4307                         venus_opp_table: opp-table {
4308                                 compatible = "operating-points-v2";
4309
4310                                 opp-720000000 {
4311                                         opp-hz = /bits/ 64 <720000000>;
4312                                         required-opps = <&rpmhpd_opp_low_svs>;
4313                                 };
4314
4315                                 opp-1014000000 {
4316                                         opp-hz = /bits/ 64 <1014000000>;
4317                                         required-opps = <&rpmhpd_opp_svs>;
4318                                 };
4319
4320                                 opp-1098000000 {
4321                                         opp-hz = /bits/ 64 <1098000000>;
4322                                         required-opps = <&rpmhpd_opp_svs_l1>;
4323                                 };
4324
4325                                 opp-1332000000 {
4326                                         opp-hz = /bits/ 64 <1332000000>;
4327                                         required-opps = <&rpmhpd_opp_nom>;
4328                                 };
4329                         };
4330                 };
4331
4332                 videocc: clock-controller@abf0000 {
4333                         compatible = "qcom,sm8250-videocc";
4334                         reg = <0 0x0abf0000 0 0x10000>;
4335                         clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4336                                  <&rpmhcc RPMH_CXO_CLK>,
4337                                  <&rpmhcc RPMH_CXO_CLK_A>;
4338                         power-domains = <&rpmhpd RPMHPD_MMCX>;
4339                         required-opps = <&rpmhpd_opp_low_svs>;
4340                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4341                         #clock-cells = <1>;
4342                         #reset-cells = <1>;
4343                         #power-domain-cells = <1>;
4344                 };
4345
4346                 cci0: cci@ac4f000 {
4347                         compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4348                         #address-cells = <1>;
4349                         #size-cells = <0>;
4350
4351                         reg = <0 0x0ac4f000 0 0x1000>;
4352                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4353                         power-domains = <&camcc TITAN_TOP_GDSC>;
4354
4355                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4356                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4357                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
4358                                  <&camcc CAM_CC_CCI_0_CLK>,
4359                                  <&camcc CAM_CC_CCI_0_CLK_SRC>;
4360                         clock-names = "camnoc_axi",
4361                                       "slow_ahb_src",
4362                                       "cpas_ahb",
4363                                       "cci",
4364                                       "cci_src";
4365
4366                         pinctrl-0 = <&cci0_default>;
4367                         pinctrl-1 = <&cci0_sleep>;
4368                         pinctrl-names = "default", "sleep";
4369
4370                         status = "disabled";
4371
4372                         cci0_i2c0: i2c-bus@0 {
4373                                 reg = <0>;
4374                                 clock-frequency = <1000000>;
4375                                 #address-cells = <1>;
4376                                 #size-cells = <0>;
4377                         };
4378
4379                         cci0_i2c1: i2c-bus@1 {
4380                                 reg = <1>;
4381                                 clock-frequency = <1000000>;
4382                                 #address-cells = <1>;
4383                                 #size-cells = <0>;
4384                         };
4385                 };
4386
4387                 cci1: cci@ac50000 {
4388                         compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4389                         #address-cells = <1>;
4390                         #size-cells = <0>;
4391
4392                         reg = <0 0x0ac50000 0 0x1000>;
4393                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4394                         power-domains = <&camcc TITAN_TOP_GDSC>;
4395
4396                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4397                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4398                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
4399                                  <&camcc CAM_CC_CCI_1_CLK>,
4400                                  <&camcc CAM_CC_CCI_1_CLK_SRC>;
4401                         clock-names = "camnoc_axi",
4402                                       "slow_ahb_src",
4403                                       "cpas_ahb",
4404                                       "cci",
4405                                       "cci_src";
4406
4407                         pinctrl-0 = <&cci1_default>;
4408                         pinctrl-1 = <&cci1_sleep>;
4409                         pinctrl-names = "default", "sleep";
4410
4411                         status = "disabled";
4412
4413                         cci1_i2c0: i2c-bus@0 {
4414                                 reg = <0>;
4415                                 clock-frequency = <1000000>;
4416                                 #address-cells = <1>;
4417                                 #size-cells = <0>;
4418                         };
4419
4420                         cci1_i2c1: i2c-bus@1 {
4421                                 reg = <1>;
4422                                 clock-frequency = <1000000>;
4423                                 #address-cells = <1>;
4424                                 #size-cells = <0>;
4425                         };
4426                 };
4427
4428                 camss: camss@ac6a000 {
4429                         compatible = "qcom,sm8250-camss";
4430                         status = "disabled";
4431
4432                         reg = <0 0x0ac6a000 0 0x2000>,
4433                               <0 0x0ac6c000 0 0x2000>,
4434                               <0 0x0ac6e000 0 0x1000>,
4435                               <0 0x0ac70000 0 0x1000>,
4436                               <0 0x0ac72000 0 0x1000>,
4437                               <0 0x0ac74000 0 0x1000>,
4438                               <0 0x0acb4000 0 0xd000>,
4439                               <0 0x0acc3000 0 0xd000>,
4440                               <0 0x0acd9000 0 0x2200>,
4441                               <0 0x0acdb200 0 0x2200>;
4442                         reg-names = "csiphy0",
4443                                     "csiphy1",
4444                                     "csiphy2",
4445                                     "csiphy3",
4446                                     "csiphy4",
4447                                     "csiphy5",
4448                                     "vfe0",
4449                                     "vfe1",
4450                                     "vfe_lite0",
4451                                     "vfe_lite1";
4452
4453                         interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4454                                      <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4455                                      <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4456                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4457                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4458                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4459                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4460                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4461                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4462                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4463                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4464                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4465                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4466                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4467                         interrupt-names = "csiphy0",
4468                                           "csiphy1",
4469                                           "csiphy2",
4470                                           "csiphy3",
4471                                           "csiphy4",
4472                                           "csiphy5",
4473                                           "csid0",
4474                                           "csid1",
4475                                           "csid2",
4476                                           "csid3",
4477                                           "vfe0",
4478                                           "vfe1",
4479                                           "vfe_lite0",
4480                                           "vfe_lite1";
4481
4482                         power-domains = <&camcc IFE_0_GDSC>,
4483                                         <&camcc IFE_1_GDSC>,
4484                                         <&camcc TITAN_TOP_GDSC>;
4485
4486                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4487                                  <&gcc GCC_CAMERA_HF_AXI_CLK>,
4488                                  <&gcc GCC_CAMERA_SF_AXI_CLK>,
4489                                  <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4490                                  <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4491                                  <&camcc CAM_CC_CORE_AHB_CLK>,
4492                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
4493                                  <&camcc CAM_CC_CSIPHY0_CLK>,
4494                                  <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4495                                  <&camcc CAM_CC_CSIPHY1_CLK>,
4496                                  <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4497                                  <&camcc CAM_CC_CSIPHY2_CLK>,
4498                                  <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4499                                  <&camcc CAM_CC_CSIPHY3_CLK>,
4500                                  <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4501                                  <&camcc CAM_CC_CSIPHY4_CLK>,
4502                                  <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4503                                  <&camcc CAM_CC_CSIPHY5_CLK>,
4504                                  <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4505                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4506                                  <&camcc CAM_CC_IFE_0_AHB_CLK>,
4507                                  <&camcc CAM_CC_IFE_0_AXI_CLK>,
4508                                  <&camcc CAM_CC_IFE_0_CLK>,
4509                                  <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4510                                  <&camcc CAM_CC_IFE_0_CSID_CLK>,
4511                                  <&camcc CAM_CC_IFE_0_AREG_CLK>,
4512                                  <&camcc CAM_CC_IFE_1_AHB_CLK>,
4513                                  <&camcc CAM_CC_IFE_1_AXI_CLK>,
4514                                  <&camcc CAM_CC_IFE_1_CLK>,
4515                                  <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4516                                  <&camcc CAM_CC_IFE_1_CSID_CLK>,
4517                                  <&camcc CAM_CC_IFE_1_AREG_CLK>,
4518                                  <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4519                                  <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4520                                  <&camcc CAM_CC_IFE_LITE_CLK>,
4521                                  <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4522                                  <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4523
4524                         clock-names = "cam_ahb_clk",
4525                                       "cam_hf_axi",
4526                                       "cam_sf_axi",
4527                                       "camnoc_axi",
4528                                       "camnoc_axi_src",
4529                                       "core_ahb",
4530                                       "cpas_ahb",
4531                                       "csiphy0",
4532                                       "csiphy0_timer",
4533                                       "csiphy1",
4534                                       "csiphy1_timer",
4535                                       "csiphy2",
4536                                       "csiphy2_timer",
4537                                       "csiphy3",
4538                                       "csiphy3_timer",
4539                                       "csiphy4",
4540                                       "csiphy4_timer",
4541                                       "csiphy5",
4542                                       "csiphy5_timer",
4543                                       "slow_ahb_src",
4544                                       "vfe0_ahb",
4545                                       "vfe0_axi",
4546                                       "vfe0",
4547                                       "vfe0_cphy_rx",
4548                                       "vfe0_csid",
4549                                       "vfe0_areg",
4550                                       "vfe1_ahb",
4551                                       "vfe1_axi",
4552                                       "vfe1",
4553                                       "vfe1_cphy_rx",
4554                                       "vfe1_csid",
4555                                       "vfe1_areg",
4556                                       "vfe_lite_ahb",
4557                                       "vfe_lite_axi",
4558                                       "vfe_lite",
4559                                       "vfe_lite_cphy_rx",
4560                                       "vfe_lite_csid";
4561
4562                         iommus = <&apps_smmu 0x800 0x400>,
4563                                  <&apps_smmu 0x801 0x400>,
4564                                  <&apps_smmu 0x840 0x400>,
4565                                  <&apps_smmu 0x841 0x400>,
4566                                  <&apps_smmu 0xc00 0x400>,
4567                                  <&apps_smmu 0xc01 0x400>,
4568                                  <&apps_smmu 0xc40 0x400>,
4569                                  <&apps_smmu 0xc41 0x400>;
4570
4571                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4572                                         <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4573                                         <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4574                                         <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4575                         interconnect-names = "cam_ahb",
4576                                              "cam_hf_0_mnoc",
4577                                              "cam_sf_0_mnoc",
4578                                              "cam_sf_icp_mnoc";
4579
4580                         ports {
4581                                 #address-cells = <1>;
4582                                 #size-cells = <0>;
4583
4584                                 port@0 {
4585                                         reg = <0>;
4586                                 };
4587
4588                                 port@1 {
4589                                         reg = <1>;
4590                                 };
4591
4592                                 port@2 {
4593                                         reg = <2>;
4594                                 };
4595
4596                                 port@3 {
4597                                         reg = <3>;
4598                                 };
4599
4600                                 port@4 {
4601                                         reg = <4>;
4602                                 };
4603
4604                                 port@5 {
4605                                         reg = <5>;
4606                                 };
4607                         };
4608                 };
4609
4610                 camcc: clock-controller@ad00000 {
4611                         compatible = "qcom,sm8250-camcc";
4612                         reg = <0 0x0ad00000 0 0x10000>;
4613                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4614                                  <&rpmhcc RPMH_CXO_CLK>,
4615                                  <&rpmhcc RPMH_CXO_CLK_A>,
4616                                  <&sleep_clk>;
4617                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4618                         power-domains = <&rpmhpd RPMHPD_MMCX>;
4619                         required-opps = <&rpmhpd_opp_low_svs>;
4620                         status = "disabled";
4621                         #clock-cells = <1>;
4622                         #reset-cells = <1>;
4623                         #power-domain-cells = <1>;
4624                 };
4625
4626                 mdss: display-subsystem@ae00000 {
4627                         compatible = "qcom,sm8250-mdss";
4628                         reg = <0 0x0ae00000 0 0x1000>;
4629                         reg-names = "mdss";
4630
4631                         interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4632                                         <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4633                         interconnect-names = "mdp0-mem", "mdp1-mem";
4634
4635                         power-domains = <&dispcc MDSS_GDSC>;
4636
4637                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4638                                  <&gcc GCC_DISP_HF_AXI_CLK>,
4639                                  <&gcc GCC_DISP_SF_AXI_CLK>,
4640                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
4641                         clock-names = "iface", "bus", "nrt_bus", "core";
4642
4643                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4644                         interrupt-controller;
4645                         #interrupt-cells = <1>;
4646
4647                         iommus = <&apps_smmu 0x820 0x402>;
4648
4649                         status = "disabled";
4650
4651                         #address-cells = <2>;
4652                         #size-cells = <2>;
4653                         ranges;
4654
4655                         mdss_mdp: display-controller@ae01000 {
4656                                 compatible = "qcom,sm8250-dpu";
4657                                 reg = <0 0x0ae01000 0 0x8f000>,
4658                                       <0 0x0aeb0000 0 0x2008>;
4659                                 reg-names = "mdp", "vbif";
4660
4661                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4662                                          <&gcc GCC_DISP_HF_AXI_CLK>,
4663                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
4664                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4665                                 clock-names = "iface", "bus", "core", "vsync";
4666
4667                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4668                                 assigned-clock-rates = <19200000>;
4669
4670                                 operating-points-v2 = <&mdp_opp_table>;
4671                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
4672
4673                                 interrupt-parent = <&mdss>;
4674                                 interrupts = <0>;
4675
4676                                 ports {
4677                                         #address-cells = <1>;
4678                                         #size-cells = <0>;
4679
4680                                         port@0 {
4681                                                 reg = <0>;
4682                                                 dpu_intf1_out: endpoint {
4683                                                         remote-endpoint = <&mdss_dsi0_in>;
4684                                                 };
4685                                         };
4686
4687                                         port@1 {
4688                                                 reg = <1>;
4689                                                 dpu_intf2_out: endpoint {
4690                                                         remote-endpoint = <&mdss_dsi1_in>;
4691                                                 };
4692                                         };
4693
4694                                         port@2 {
4695                                                 reg = <2>;
4696
4697                                                 dpu_intf0_out: endpoint {
4698                                                         remote-endpoint = <&mdss_dp_in>;
4699                                                 };
4700                                         };
4701                                 };
4702
4703                                 mdp_opp_table: opp-table {
4704                                         compatible = "operating-points-v2";
4705
4706                                         opp-200000000 {
4707                                                 opp-hz = /bits/ 64 <200000000>;
4708                                                 required-opps = <&rpmhpd_opp_low_svs>;
4709                                         };
4710
4711                                         opp-300000000 {
4712                                                 opp-hz = /bits/ 64 <300000000>;
4713                                                 required-opps = <&rpmhpd_opp_svs>;
4714                                         };
4715
4716                                         opp-345000000 {
4717                                                 opp-hz = /bits/ 64 <345000000>;
4718                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4719                                         };
4720
4721                                         opp-460000000 {
4722                                                 opp-hz = /bits/ 64 <460000000>;
4723                                                 required-opps = <&rpmhpd_opp_nom>;
4724                                         };
4725                                 };
4726                         };
4727
4728                         mdss_dp: displayport-controller@ae90000 {
4729                                 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4730                                 reg = <0 0xae90000 0 0x200>,
4731                                       <0 0xae90200 0 0x200>,
4732                                       <0 0xae90400 0 0x600>,
4733                                       <0 0xae91000 0 0x400>,
4734                                       <0 0xae91400 0 0x400>;
4735                                 interrupt-parent = <&mdss>;
4736                                 interrupts = <12>;
4737                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4738                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4739                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4740                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4741                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4742                                 clock-names = "core_iface",
4743                                               "core_aux",
4744                                               "ctrl_link",
4745                                               "ctrl_link_iface",
4746                                               "stream_pixel";
4747
4748                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4749                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4750                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4751                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4752
4753                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4754                                 phy-names = "dp";
4755
4756                                 #sound-dai-cells = <0>;
4757
4758                                 operating-points-v2 = <&dp_opp_table>;
4759                                 power-domains = <&rpmhpd SM8250_MMCX>;
4760
4761                                 status = "disabled";
4762
4763                                 ports {
4764                                         #address-cells = <1>;
4765                                         #size-cells = <0>;
4766
4767                                         port@0 {
4768                                                 reg = <0>;
4769                                                 mdss_dp_in: endpoint {
4770                                                         remote-endpoint = <&dpu_intf0_out>;
4771                                                 };
4772                                         };
4773
4774                                         port@1 {
4775                                                 reg = <1>;
4776
4777                                                 mdss_dp_out: endpoint {
4778                                                 };
4779                                         };
4780                                 };
4781
4782                                 dp_opp_table: opp-table {
4783                                         compatible = "operating-points-v2";
4784
4785                                         opp-160000000 {
4786                                                 opp-hz = /bits/ 64 <160000000>;
4787                                                 required-opps = <&rpmhpd_opp_low_svs>;
4788                                         };
4789
4790                                         opp-270000000 {
4791                                                 opp-hz = /bits/ 64 <270000000>;
4792                                                 required-opps = <&rpmhpd_opp_svs>;
4793                                         };
4794
4795                                         opp-540000000 {
4796                                                 opp-hz = /bits/ 64 <540000000>;
4797                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4798                                         };
4799
4800                                         opp-810000000 {
4801                                                 opp-hz = /bits/ 64 <810000000>;
4802                                                 required-opps = <&rpmhpd_opp_nom>;
4803                                         };
4804                                 };
4805                         };
4806
4807                         mdss_dsi0: dsi@ae94000 {
4808                                 compatible = "qcom,sm8250-dsi-ctrl",
4809                                              "qcom,mdss-dsi-ctrl";
4810                                 reg = <0 0x0ae94000 0 0x400>;
4811                                 reg-names = "dsi_ctrl";
4812
4813                                 interrupt-parent = <&mdss>;
4814                                 interrupts = <4>;
4815
4816                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4817                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4818                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4819                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4820                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4821                                         <&gcc GCC_DISP_HF_AXI_CLK>;
4822                                 clock-names = "byte",
4823                                               "byte_intf",
4824                                               "pixel",
4825                                               "core",
4826                                               "iface",
4827                                               "bus";
4828
4829                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4830                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4831
4832                                 operating-points-v2 = <&dsi_opp_table>;
4833                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
4834
4835                                 phys = <&mdss_dsi0_phy>;
4836
4837                                 status = "disabled";
4838
4839                                 #address-cells = <1>;
4840                                 #size-cells = <0>;
4841
4842                                 ports {
4843                                         #address-cells = <1>;
4844                                         #size-cells = <0>;
4845
4846                                         port@0 {
4847                                                 reg = <0>;
4848                                                 mdss_dsi0_in: endpoint {
4849                                                         remote-endpoint = <&dpu_intf1_out>;
4850                                                 };
4851                                         };
4852
4853                                         port@1 {
4854                                                 reg = <1>;
4855                                                 mdss_dsi0_out: endpoint {
4856                                                 };
4857                                         };
4858                                 };
4859
4860                                 dsi_opp_table: opp-table {
4861                                         compatible = "operating-points-v2";
4862
4863                                         opp-187500000 {
4864                                                 opp-hz = /bits/ 64 <187500000>;
4865                                                 required-opps = <&rpmhpd_opp_low_svs>;
4866                                         };
4867
4868                                         opp-300000000 {
4869                                                 opp-hz = /bits/ 64 <300000000>;
4870                                                 required-opps = <&rpmhpd_opp_svs>;
4871                                         };
4872
4873                                         opp-358000000 {
4874                                                 opp-hz = /bits/ 64 <358000000>;
4875                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4876                                         };
4877                                 };
4878                         };
4879
4880                         mdss_dsi0_phy: phy@ae94400 {
4881                                 compatible = "qcom,dsi-phy-7nm";
4882                                 reg = <0 0x0ae94400 0 0x200>,
4883                                       <0 0x0ae94600 0 0x280>,
4884                                       <0 0x0ae94900 0 0x260>;
4885                                 reg-names = "dsi_phy",
4886                                             "dsi_phy_lane",
4887                                             "dsi_pll";
4888
4889                                 #clock-cells = <1>;
4890                                 #phy-cells = <0>;
4891
4892                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4893                                          <&rpmhcc RPMH_CXO_CLK>;
4894                                 clock-names = "iface", "ref";
4895
4896                                 status = "disabled";
4897                         };
4898
4899                         mdss_dsi1: dsi@ae96000 {
4900                                 compatible = "qcom,sm8250-dsi-ctrl",
4901                                              "qcom,mdss-dsi-ctrl";
4902                                 reg = <0 0x0ae96000 0 0x400>;
4903                                 reg-names = "dsi_ctrl";
4904
4905                                 interrupt-parent = <&mdss>;
4906                                 interrupts = <5>;
4907
4908                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4909                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4910                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4911                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4912                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4913                                          <&gcc GCC_DISP_HF_AXI_CLK>;
4914                                 clock-names = "byte",
4915                                               "byte_intf",
4916                                               "pixel",
4917                                               "core",
4918                                               "iface",
4919                                               "bus";
4920
4921                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4922                                 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4923
4924                                 operating-points-v2 = <&dsi_opp_table>;
4925                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
4926
4927                                 phys = <&mdss_dsi1_phy>;
4928
4929                                 status = "disabled";
4930
4931                                 #address-cells = <1>;
4932                                 #size-cells = <0>;
4933
4934                                 ports {
4935                                         #address-cells = <1>;
4936                                         #size-cells = <0>;
4937
4938                                         port@0 {
4939                                                 reg = <0>;
4940                                                 mdss_dsi1_in: endpoint {
4941                                                         remote-endpoint = <&dpu_intf2_out>;
4942                                                 };
4943                                         };
4944
4945                                         port@1 {
4946                                                 reg = <1>;
4947                                                 mdss_dsi1_out: endpoint {
4948                                                 };
4949                                         };
4950                                 };
4951                         };
4952
4953                         mdss_dsi1_phy: phy@ae96400 {
4954                                 compatible = "qcom,dsi-phy-7nm";
4955                                 reg = <0 0x0ae96400 0 0x200>,
4956                                       <0 0x0ae96600 0 0x280>,
4957                                       <0 0x0ae96900 0 0x260>;
4958                                 reg-names = "dsi_phy",
4959                                             "dsi_phy_lane",
4960                                             "dsi_pll";
4961
4962                                 #clock-cells = <1>;
4963                                 #phy-cells = <0>;
4964
4965                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4966                                          <&rpmhcc RPMH_CXO_CLK>;
4967                                 clock-names = "iface", "ref";
4968
4969                                 status = "disabled";
4970                         };
4971                 };
4972
4973                 dispcc: clock-controller@af00000 {
4974                         compatible = "qcom,sm8250-dispcc";
4975                         reg = <0 0x0af00000 0 0x10000>;
4976                         power-domains = <&rpmhpd RPMHPD_MMCX>;
4977                         required-opps = <&rpmhpd_opp_low_svs>;
4978                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4979                                  <&mdss_dsi0_phy 0>,
4980                                  <&mdss_dsi0_phy 1>,
4981                                  <&mdss_dsi1_phy 0>,
4982                                  <&mdss_dsi1_phy 1>,
4983                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4984                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4985                         clock-names = "bi_tcxo",
4986                                       "dsi0_phy_pll_out_byteclk",
4987                                       "dsi0_phy_pll_out_dsiclk",
4988                                       "dsi1_phy_pll_out_byteclk",
4989                                       "dsi1_phy_pll_out_dsiclk",
4990                                       "dp_phy_pll_link_clk",
4991                                       "dp_phy_pll_vco_div_clk";
4992                         #clock-cells = <1>;
4993                         #reset-cells = <1>;
4994                         #power-domain-cells = <1>;
4995                 };
4996
4997                 pdc: interrupt-controller@b220000 {
4998                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
4999                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5000                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5001                                           <125 63 1>, <126 716 12>;
5002                         #interrupt-cells = <2>;
5003                         interrupt-parent = <&intc>;
5004                         interrupt-controller;
5005                 };
5006
5007                 tsens0: thermal-sensor@c263000 {
5008                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5009                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
5010                               <0 0x0c222000 0 0x1ff>; /* SROT */
5011                         #qcom,sensors = <16>;
5012                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5013                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5014                         interrupt-names = "uplow", "critical";
5015                         #thermal-sensor-cells = <1>;
5016                 };
5017
5018                 tsens1: thermal-sensor@c265000 {
5019                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5020                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
5021                               <0 0x0c223000 0 0x1ff>; /* SROT */
5022                         #qcom,sensors = <9>;
5023                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5024                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5025                         interrupt-names = "uplow", "critical";
5026                         #thermal-sensor-cells = <1>;
5027                 };
5028
5029                 aoss_qmp: power-management@c300000 {
5030                         compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5031                         reg = <0 0x0c300000 0 0x400>;
5032                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5033                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
5034                                                      IRQ_TYPE_EDGE_RISING>;
5035                         mboxes = <&ipcc IPCC_CLIENT_AOP
5036                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
5037
5038                         #clock-cells = <0>;
5039                 };
5040
5041                 sram@c3f0000 {
5042                         compatible = "qcom,rpmh-stats";
5043                         reg = <0 0x0c3f0000 0 0x400>;
5044                 };
5045
5046                 spmi_bus: spmi@c440000 {
5047                         compatible = "qcom,spmi-pmic-arb";
5048                         reg = <0x0 0x0c440000 0x0 0x0001100>,
5049                               <0x0 0x0c600000 0x0 0x2000000>,
5050                               <0x0 0x0e600000 0x0 0x0100000>,
5051                               <0x0 0x0e700000 0x0 0x00a0000>,
5052                               <0x0 0x0c40a000 0x0 0x0026000>;
5053                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5054                         interrupt-names = "periph_irq";
5055                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5056                         qcom,ee = <0>;
5057                         qcom,channel = <0>;
5058                         #address-cells = <2>;
5059                         #size-cells = <0>;
5060                         interrupt-controller;
5061                         #interrupt-cells = <4>;
5062                 };
5063
5064                 tlmm: pinctrl@f100000 {
5065                         compatible = "qcom,sm8250-pinctrl";
5066                         reg = <0 0x0f100000 0 0x300000>,
5067                               <0 0x0f500000 0 0x300000>,
5068                               <0 0x0f900000 0 0x300000>;
5069                         reg-names = "west", "south", "north";
5070                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5071                         gpio-controller;
5072                         #gpio-cells = <2>;
5073                         interrupt-controller;
5074                         #interrupt-cells = <2>;
5075                         gpio-ranges = <&tlmm 0 0 181>;
5076                         wakeup-parent = <&pdc>;
5077
5078                         cam2_default: cam2-default-state {
5079                                 rst-pins {
5080                                         pins = "gpio78";
5081                                         function = "gpio";
5082                                         drive-strength = <2>;
5083                                         bias-disable;
5084                                 };
5085
5086                                 mclk-pins {
5087                                         pins = "gpio96";
5088                                         function = "cam_mclk";
5089                                         drive-strength = <16>;
5090                                         bias-disable;
5091                                 };
5092                         };
5093
5094                         cam2_suspend: cam2-suspend-state {
5095                                 rst-pins {
5096                                         pins = "gpio78";
5097                                         function = "gpio";
5098                                         drive-strength = <2>;
5099                                         bias-pull-down;
5100                                         output-low;
5101                                 };
5102
5103                                 mclk-pins {
5104                                         pins = "gpio96";
5105                                         function = "cam_mclk";
5106                                         drive-strength = <2>;
5107                                         bias-disable;
5108                                 };
5109                         };
5110
5111                         cci0_default: cci0-default-state {
5112                                 cci0_i2c0_default: cci0-i2c0-default-pins {
5113                                         /* SDA, SCL */
5114                                         pins = "gpio101", "gpio102";
5115                                         function = "cci_i2c";
5116
5117                                         bias-pull-up;
5118                                         drive-strength = <2>; /* 2 mA */
5119                                 };
5120
5121                                 cci0_i2c1_default: cci0-i2c1-default-pins {
5122                                         /* SDA, SCL */
5123                                         pins = "gpio103", "gpio104";
5124                                         function = "cci_i2c";
5125
5126                                         bias-pull-up;
5127                                         drive-strength = <2>; /* 2 mA */
5128                                 };
5129                         };
5130
5131                         cci0_sleep: cci0-sleep-state {
5132                                 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5133                                         /* SDA, SCL */
5134                                         pins = "gpio101", "gpio102";
5135                                         function = "cci_i2c";
5136
5137                                         drive-strength = <2>; /* 2 mA */
5138                                         bias-pull-down;
5139                                 };
5140
5141                                 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5142                                         /* SDA, SCL */
5143                                         pins = "gpio103", "gpio104";
5144                                         function = "cci_i2c";
5145
5146                                         drive-strength = <2>; /* 2 mA */
5147                                         bias-pull-down;
5148                                 };
5149                         };
5150
5151                         cci1_default: cci1-default-state {
5152                                 cci1_i2c0_default: cci1-i2c0-default-pins {
5153                                         /* SDA, SCL */
5154                                         pins = "gpio105","gpio106";
5155                                         function = "cci_i2c";
5156
5157                                         bias-pull-up;
5158                                         drive-strength = <2>; /* 2 mA */
5159                                 };
5160
5161                                 cci1_i2c1_default: cci1-i2c1-default-pins {
5162                                         /* SDA, SCL */
5163                                         pins = "gpio107","gpio108";
5164                                         function = "cci_i2c";
5165
5166                                         bias-pull-up;
5167                                         drive-strength = <2>; /* 2 mA */
5168                                 };
5169                         };
5170
5171                         cci1_sleep: cci1-sleep-state {
5172                                 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5173                                         /* SDA, SCL */
5174                                         pins = "gpio105","gpio106";
5175                                         function = "cci_i2c";
5176
5177                                         bias-pull-down;
5178                                         drive-strength = <2>; /* 2 mA */
5179                                 };
5180
5181                                 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5182                                         /* SDA, SCL */
5183                                         pins = "gpio107","gpio108";
5184                                         function = "cci_i2c";
5185
5186                                         bias-pull-down;
5187                                         drive-strength = <2>; /* 2 mA */
5188                                 };
5189                         };
5190
5191                         pri_mi2s_active: pri-mi2s-active-state {
5192                                 sclk-pins {
5193                                         pins = "gpio138";
5194                                         function = "mi2s0_sck";
5195                                         drive-strength = <8>;
5196                                         bias-disable;
5197                                 };
5198
5199                                 ws-pins {
5200                                         pins = "gpio141";
5201                                         function = "mi2s0_ws";
5202                                         drive-strength = <8>;
5203                                         output-high;
5204                                 };
5205
5206                                 data0-pins {
5207                                         pins = "gpio139";
5208                                         function = "mi2s0_data0";
5209                                         drive-strength = <8>;
5210                                         bias-disable;
5211                                         output-high;
5212                                 };
5213
5214                                 data1-pins {
5215                                         pins = "gpio140";
5216                                         function = "mi2s0_data1";
5217                                         drive-strength = <8>;
5218                                         output-high;
5219                                 };
5220                         };
5221
5222                         qup_i2c0_default: qup-i2c0-default-state {
5223                                 pins = "gpio28", "gpio29";
5224                                 function = "qup0";
5225                                 drive-strength = <2>;
5226                                 bias-disable;
5227                         };
5228
5229                         qup_i2c1_default: qup-i2c1-default-state {
5230                                 pins = "gpio4", "gpio5";
5231                                 function = "qup1";
5232                                 drive-strength = <2>;
5233                                 bias-disable;
5234                         };
5235
5236                         qup_i2c2_default: qup-i2c2-default-state {
5237                                 pins = "gpio115", "gpio116";
5238                                 function = "qup2";
5239                                 drive-strength = <2>;
5240                                 bias-disable;
5241                         };
5242
5243                         qup_i2c3_default: qup-i2c3-default-state {
5244                                 pins = "gpio119", "gpio120";
5245                                 function = "qup3";
5246                                 drive-strength = <2>;
5247                                 bias-disable;
5248                         };
5249
5250                         qup_i2c4_default: qup-i2c4-default-state {
5251                                 pins = "gpio8", "gpio9";
5252                                 function = "qup4";
5253                                 drive-strength = <2>;
5254                                 bias-disable;
5255                         };
5256
5257                         qup_i2c5_default: qup-i2c5-default-state {
5258                                 pins = "gpio12", "gpio13";
5259                                 function = "qup5";
5260                                 drive-strength = <2>;
5261                                 bias-disable;
5262                         };
5263
5264                         qup_i2c6_default: qup-i2c6-default-state {
5265                                 pins = "gpio16", "gpio17";
5266                                 function = "qup6";
5267                                 drive-strength = <2>;
5268                                 bias-disable;
5269                         };
5270
5271                         qup_i2c7_default: qup-i2c7-default-state {
5272                                 pins = "gpio20", "gpio21";
5273                                 function = "qup7";
5274                                 drive-strength = <2>;
5275                                 bias-disable;
5276                         };
5277
5278                         qup_i2c8_default: qup-i2c8-default-state {
5279                                 pins = "gpio24", "gpio25";
5280                                 function = "qup8";
5281                                 drive-strength = <2>;
5282                                 bias-disable;
5283                         };
5284
5285                         qup_i2c9_default: qup-i2c9-default-state {
5286                                 pins = "gpio125", "gpio126";
5287                                 function = "qup9";
5288                                 drive-strength = <2>;
5289                                 bias-disable;
5290                         };
5291
5292                         qup_i2c10_default: qup-i2c10-default-state {
5293                                 pins = "gpio129", "gpio130";
5294                                 function = "qup10";
5295                                 drive-strength = <2>;
5296                                 bias-disable;
5297                         };
5298
5299                         qup_i2c11_default: qup-i2c11-default-state {
5300                                 pins = "gpio60", "gpio61";
5301                                 function = "qup11";
5302                                 drive-strength = <2>;
5303                                 bias-disable;
5304                         };
5305
5306                         qup_i2c12_default: qup-i2c12-default-state {
5307                                 pins = "gpio32", "gpio33";
5308                                 function = "qup12";
5309                                 drive-strength = <2>;
5310                                 bias-disable;
5311                         };
5312
5313                         qup_i2c13_default: qup-i2c13-default-state {
5314                                 pins = "gpio36", "gpio37";
5315                                 function = "qup13";
5316                                 drive-strength = <2>;
5317                                 bias-disable;
5318                         };
5319
5320                         qup_i2c14_default: qup-i2c14-default-state {
5321                                 pins = "gpio40", "gpio41";
5322                                 function = "qup14";
5323                                 drive-strength = <2>;
5324                                 bias-disable;
5325                         };
5326
5327                         qup_i2c15_default: qup-i2c15-default-state {
5328                                 pins = "gpio44", "gpio45";
5329                                 function = "qup15";
5330                                 drive-strength = <2>;
5331                                 bias-disable;
5332                         };
5333
5334                         qup_i2c16_default: qup-i2c16-default-state {
5335                                 pins = "gpio48", "gpio49";
5336                                 function = "qup16";
5337                                 drive-strength = <2>;
5338                                 bias-disable;
5339                         };
5340
5341                         qup_i2c17_default: qup-i2c17-default-state {
5342                                 pins = "gpio52", "gpio53";
5343                                 function = "qup17";
5344                                 drive-strength = <2>;
5345                                 bias-disable;
5346                         };
5347
5348                         qup_i2c18_default: qup-i2c18-default-state {
5349                                 pins = "gpio56", "gpio57";
5350                                 function = "qup18";
5351                                 drive-strength = <2>;
5352                                 bias-disable;
5353                         };
5354
5355                         qup_i2c19_default: qup-i2c19-default-state {
5356                                 pins = "gpio0", "gpio1";
5357                                 function = "qup19";
5358                                 drive-strength = <2>;
5359                                 bias-disable;
5360                         };
5361
5362                         qup_spi0_cs: qup-spi0-cs-state {
5363                                 pins = "gpio31";
5364                                 function = "qup0";
5365                         };
5366
5367                         qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5368                                 pins = "gpio31";
5369                                 function = "gpio";
5370                         };
5371
5372                         qup_spi0_data_clk: qup-spi0-data-clk-state {
5373                                 pins = "gpio28", "gpio29",
5374                                        "gpio30";
5375                                 function = "qup0";
5376                         };
5377
5378                         qup_spi1_cs: qup-spi1-cs-state {
5379                                 pins = "gpio7";
5380                                 function = "qup1";
5381                         };
5382
5383                         qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5384                                 pins = "gpio7";
5385                                 function = "gpio";
5386                         };
5387
5388                         qup_spi1_data_clk: qup-spi1-data-clk-state {
5389                                 pins = "gpio4", "gpio5",
5390                                        "gpio6";
5391                                 function = "qup1";
5392                         };
5393
5394                         qup_spi2_cs: qup-spi2-cs-state {
5395                                 pins = "gpio118";
5396                                 function = "qup2";
5397                         };
5398
5399                         qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5400                                 pins = "gpio118";
5401                                 function = "gpio";
5402                         };
5403
5404                         qup_spi2_data_clk: qup-spi2-data-clk-state {
5405                                 pins = "gpio115", "gpio116",
5406                                        "gpio117";
5407                                 function = "qup2";
5408                         };
5409
5410                         qup_spi3_cs: qup-spi3-cs-state {
5411                                 pins = "gpio122";
5412                                 function = "qup3";
5413                         };
5414
5415                         qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5416                                 pins = "gpio122";
5417                                 function = "gpio";
5418                         };
5419
5420                         qup_spi3_data_clk: qup-spi3-data-clk-state {
5421                                 pins = "gpio119", "gpio120",
5422                                        "gpio121";
5423                                 function = "qup3";
5424                         };
5425
5426                         qup_spi4_cs: qup-spi4-cs-state {
5427                                 pins = "gpio11";
5428                                 function = "qup4";
5429                         };
5430
5431                         qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5432                                 pins = "gpio11";
5433                                 function = "gpio";
5434                         };
5435
5436                         qup_spi4_data_clk: qup-spi4-data-clk-state {
5437                                 pins = "gpio8", "gpio9",
5438                                        "gpio10";
5439                                 function = "qup4";
5440                         };
5441
5442                         qup_spi5_cs: qup-spi5-cs-state {
5443                                 pins = "gpio15";
5444                                 function = "qup5";
5445                         };
5446
5447                         qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5448                                 pins = "gpio15";
5449                                 function = "gpio";
5450                         };
5451
5452                         qup_spi5_data_clk: qup-spi5-data-clk-state {
5453                                 pins = "gpio12", "gpio13",
5454                                        "gpio14";
5455                                 function = "qup5";
5456                         };
5457
5458                         qup_spi6_cs: qup-spi6-cs-state {
5459                                 pins = "gpio19";
5460                                 function = "qup6";
5461                         };
5462
5463                         qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5464                                 pins = "gpio19";
5465                                 function = "gpio";
5466                         };
5467
5468                         qup_spi6_data_clk: qup-spi6-data-clk-state {
5469                                 pins = "gpio16", "gpio17",
5470                                        "gpio18";
5471                                 function = "qup6";
5472                         };
5473
5474                         qup_spi7_cs: qup-spi7-cs-state {
5475                                 pins = "gpio23";
5476                                 function = "qup7";
5477                         };
5478
5479                         qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5480                                 pins = "gpio23";
5481                                 function = "gpio";
5482                         };
5483
5484                         qup_spi7_data_clk: qup-spi7-data-clk-state {
5485                                 pins = "gpio20", "gpio21",
5486                                        "gpio22";
5487                                 function = "qup7";
5488                         };
5489
5490                         qup_spi8_cs: qup-spi8-cs-state {
5491                                 pins = "gpio27";
5492                                 function = "qup8";
5493                         };
5494
5495                         qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5496                                 pins = "gpio27";
5497                                 function = "gpio";
5498                         };
5499
5500                         qup_spi8_data_clk: qup-spi8-data-clk-state {
5501                                 pins = "gpio24", "gpio25",
5502                                        "gpio26";
5503                                 function = "qup8";
5504                         };
5505
5506                         qup_spi9_cs: qup-spi9-cs-state {
5507                                 pins = "gpio128";
5508                                 function = "qup9";
5509                         };
5510
5511                         qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5512                                 pins = "gpio128";
5513                                 function = "gpio";
5514                         };
5515
5516                         qup_spi9_data_clk: qup-spi9-data-clk-state {
5517                                 pins = "gpio125", "gpio126",
5518                                        "gpio127";
5519                                 function = "qup9";
5520                         };
5521
5522                         qup_spi10_cs: qup-spi10-cs-state {
5523                                 pins = "gpio132";
5524                                 function = "qup10";
5525                         };
5526
5527                         qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5528                                 pins = "gpio132";
5529                                 function = "gpio";
5530                         };
5531
5532                         qup_spi10_data_clk: qup-spi10-data-clk-state {
5533                                 pins = "gpio129", "gpio130",
5534                                        "gpio131";
5535                                 function = "qup10";
5536                         };
5537
5538                         qup_spi11_cs: qup-spi11-cs-state {
5539                                 pins = "gpio63";
5540                                 function = "qup11";
5541                         };
5542
5543                         qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5544                                 pins = "gpio63";
5545                                 function = "gpio";
5546                         };
5547
5548                         qup_spi11_data_clk: qup-spi11-data-clk-state {
5549                                 pins = "gpio60", "gpio61",
5550                                        "gpio62";
5551                                 function = "qup11";
5552                         };
5553
5554                         qup_spi12_cs: qup-spi12-cs-state {
5555                                 pins = "gpio35";
5556                                 function = "qup12";
5557                         };
5558
5559                         qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5560                                 pins = "gpio35";
5561                                 function = "gpio";
5562                         };
5563
5564                         qup_spi12_data_clk: qup-spi12-data-clk-state {
5565                                 pins = "gpio32", "gpio33",
5566                                        "gpio34";
5567                                 function = "qup12";
5568                         };
5569
5570                         qup_spi13_cs: qup-spi13-cs-state {
5571                                 pins = "gpio39";
5572                                 function = "qup13";
5573                         };
5574
5575                         qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5576                                 pins = "gpio39";
5577                                 function = "gpio";
5578                         };
5579
5580                         qup_spi13_data_clk: qup-spi13-data-clk-state {
5581                                 pins = "gpio36", "gpio37",
5582                                        "gpio38";
5583                                 function = "qup13";
5584                         };
5585
5586                         qup_spi14_cs: qup-spi14-cs-state {
5587                                 pins = "gpio43";
5588                                 function = "qup14";
5589                         };
5590
5591                         qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5592                                 pins = "gpio43";
5593                                 function = "gpio";
5594                         };
5595
5596                         qup_spi14_data_clk: qup-spi14-data-clk-state {
5597                                 pins = "gpio40", "gpio41",
5598                                        "gpio42";
5599                                 function = "qup14";
5600                         };
5601
5602                         qup_spi15_cs: qup-spi15-cs-state {
5603                                 pins = "gpio47";
5604                                 function = "qup15";
5605                         };
5606
5607                         qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5608                                 pins = "gpio47";
5609                                 function = "gpio";
5610                         };
5611
5612                         qup_spi15_data_clk: qup-spi15-data-clk-state {
5613                                 pins = "gpio44", "gpio45",
5614                                        "gpio46";
5615                                 function = "qup15";
5616                         };
5617
5618                         qup_spi16_cs: qup-spi16-cs-state {
5619                                 pins = "gpio51";
5620                                 function = "qup16";
5621                         };
5622
5623                         qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5624                                 pins = "gpio51";
5625                                 function = "gpio";
5626                         };
5627
5628                         qup_spi16_data_clk: qup-spi16-data-clk-state {
5629                                 pins = "gpio48", "gpio49",
5630                                        "gpio50";
5631                                 function = "qup16";
5632                         };
5633
5634                         qup_spi17_cs: qup-spi17-cs-state {
5635                                 pins = "gpio55";
5636                                 function = "qup17";
5637                         };
5638
5639                         qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5640                                 pins = "gpio55";
5641                                 function = "gpio";
5642                         };
5643
5644                         qup_spi17_data_clk: qup-spi17-data-clk-state {
5645                                 pins = "gpio52", "gpio53",
5646                                        "gpio54";
5647                                 function = "qup17";
5648                         };
5649
5650                         qup_spi18_cs: qup-spi18-cs-state {
5651                                 pins = "gpio59";
5652                                 function = "qup18";
5653                         };
5654
5655                         qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5656                                 pins = "gpio59";
5657                                 function = "gpio";
5658                         };
5659
5660                         qup_spi18_data_clk: qup-spi18-data-clk-state {
5661                                 pins = "gpio56", "gpio57",
5662                                        "gpio58";
5663                                 function = "qup18";
5664                         };
5665
5666                         qup_spi19_cs: qup-spi19-cs-state {
5667                                 pins = "gpio3";
5668                                 function = "qup19";
5669                         };
5670
5671                         qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5672                                 pins = "gpio3";
5673                                 function = "gpio";
5674                         };
5675
5676                         qup_spi19_data_clk: qup-spi19-data-clk-state {
5677                                 pins = "gpio0", "gpio1",
5678                                        "gpio2";
5679                                 function = "qup19";
5680                         };
5681
5682                         qup_uart2_default: qup-uart2-default-state {
5683                                 pins = "gpio117", "gpio118";
5684                                 function = "qup2";
5685                         };
5686
5687                         qup_uart6_default: qup-uart6-default-state {
5688                                 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5689                                 function = "qup6";
5690                         };
5691
5692                         qup_uart12_default: qup-uart12-default-state {
5693                                 pins = "gpio34", "gpio35";
5694                                 function = "qup12";
5695                         };
5696
5697                         qup_uart17_default: qup-uart17-default-state {
5698                                 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5699                                 function = "qup17";
5700                         };
5701
5702                         qup_uart18_default: qup-uart18-default-state {
5703                                 pins = "gpio58", "gpio59";
5704                                 function = "qup18";
5705                         };
5706
5707                         tert_mi2s_active: tert-mi2s-active-state {
5708                                 sck-pins {
5709                                         pins = "gpio133";
5710                                         function = "mi2s2_sck";
5711                                         drive-strength = <8>;
5712                                         bias-disable;
5713                                 };
5714
5715                                 data0-pins {
5716                                         pins = "gpio134";
5717                                         function = "mi2s2_data0";
5718                                         drive-strength = <8>;
5719                                         bias-disable;
5720                                         output-high;
5721                                 };
5722
5723                                 ws-pins {
5724                                         pins = "gpio135";
5725                                         function = "mi2s2_ws";
5726                                         drive-strength = <8>;
5727                                         output-high;
5728                                 };
5729                         };
5730
5731                         sdc2_sleep_state: sdc2-sleep-state {
5732                                 clk-pins {
5733                                         pins = "sdc2_clk";
5734                                         drive-strength = <2>;
5735                                         bias-disable;
5736                                 };
5737
5738                                 cmd-pins {
5739                                         pins = "sdc2_cmd";
5740                                         drive-strength = <2>;
5741                                         bias-pull-up;
5742                                 };
5743
5744                                 data-pins {
5745                                         pins = "sdc2_data";
5746                                         drive-strength = <2>;
5747                                         bias-pull-up;
5748                                 };
5749                         };
5750
5751                         pcie0_default_state: pcie0-default-state {
5752                                 perst-pins {
5753                                         pins = "gpio79";
5754                                         function = "gpio";
5755                                         drive-strength = <2>;
5756                                         bias-pull-down;
5757                                 };
5758
5759                                 clkreq-pins {
5760                                         pins = "gpio80";
5761                                         function = "pci_e0";
5762                                         drive-strength = <2>;
5763                                         bias-pull-up;
5764                                 };
5765
5766                                 wake-pins {
5767                                         pins = "gpio81";
5768                                         function = "gpio";
5769                                         drive-strength = <2>;
5770                                         bias-pull-up;
5771                                 };
5772                         };
5773
5774                         pcie1_default_state: pcie1-default-state {
5775                                 perst-pins {
5776                                         pins = "gpio82";
5777                                         function = "gpio";
5778                                         drive-strength = <2>;
5779                                         bias-pull-down;
5780                                 };
5781
5782                                 clkreq-pins {
5783                                         pins = "gpio83";
5784                                         function = "pci_e1";
5785                                         drive-strength = <2>;
5786                                         bias-pull-up;
5787                                 };
5788
5789                                 wake-pins {
5790                                         pins = "gpio84";
5791                                         function = "gpio";
5792                                         drive-strength = <2>;
5793                                         bias-pull-up;
5794                                 };
5795                         };
5796
5797                         pcie2_default_state: pcie2-default-state {
5798                                 perst-pins {
5799                                         pins = "gpio85";
5800                                         function = "gpio";
5801                                         drive-strength = <2>;
5802                                         bias-pull-down;
5803                                 };
5804
5805                                 clkreq-pins {
5806                                         pins = "gpio86";
5807                                         function = "pci_e2";
5808                                         drive-strength = <2>;
5809                                         bias-pull-up;
5810                                 };
5811
5812                                 wake-pins {
5813                                         pins = "gpio87";
5814                                         function = "gpio";
5815                                         drive-strength = <2>;
5816                                         bias-pull-up;
5817                                 };
5818                         };
5819                 };
5820
5821                 apps_smmu: iommu@15000000 {
5822                         compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5823                         reg = <0 0x15000000 0 0x100000>;
5824                         #iommu-cells = <2>;
5825                         #global-interrupts = <2>;
5826                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5827                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5828                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5829                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5830                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5831                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5832                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5833                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5834                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5835                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5836                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5837                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5838                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5839                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5840                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5841                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5842                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5843                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5844                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5845                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5846                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5847                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5848                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5849                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5850                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5851                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5852                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5853                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5854                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5855                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5856                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5857                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5858                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5859                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5860                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5861                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5862                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5863                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5864                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5865                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5866                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5867                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5868                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5869                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5870                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5871                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5872                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5873                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5874                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5875                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5876                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5877                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5878                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5879                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5880                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5881                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5882                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5883                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5884                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5885                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5886                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5887                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5888                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5889                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5890                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5891                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5892                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5893                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5894                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5895                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5896                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5897                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5898                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5899                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5900                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5901                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5902                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5903                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5904                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5905                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5906                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5907                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5908                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5909                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5910                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5911                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5912                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5913                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5914                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5915                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5916                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5917                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5918                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5919                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5920                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5921                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5922                                      <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5923                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5924                         dma-coherent;
5925                 };
5926
5927                 adsp: remoteproc@17300000 {
5928                         compatible = "qcom,sm8250-adsp-pas";
5929                         reg = <0 0x17300000 0 0x100>;
5930
5931                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5932                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5933                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5934                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5935                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5936                         interrupt-names = "wdog", "fatal", "ready",
5937                                           "handover", "stop-ack";
5938
5939                         clocks = <&rpmhcc RPMH_CXO_CLK>;
5940                         clock-names = "xo";
5941
5942                         power-domains = <&rpmhpd RPMHPD_LCX>,
5943                                         <&rpmhpd RPMHPD_LMX>;
5944                         power-domain-names = "lcx", "lmx";
5945
5946                         memory-region = <&adsp_mem>;
5947
5948                         qcom,qmp = <&aoss_qmp>;
5949
5950                         qcom,smem-states = <&smp2p_adsp_out 0>;
5951                         qcom,smem-state-names = "stop";
5952
5953                         status = "disabled";
5954
5955                         glink-edge {
5956                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5957                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
5958                                                              IRQ_TYPE_EDGE_RISING>;
5959                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
5960                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5961
5962                                 label = "lpass";
5963                                 qcom,remote-pid = <2>;
5964
5965                                 apr {
5966                                         compatible = "qcom,apr-v2";
5967                                         qcom,glink-channels = "apr_audio_svc";
5968                                         qcom,domain = <APR_DOMAIN_ADSP>;
5969                                         #address-cells = <1>;
5970                                         #size-cells = <0>;
5971
5972                                         service@3 {
5973                                                 reg = <APR_SVC_ADSP_CORE>;
5974                                                 compatible = "qcom,q6core";
5975                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5976                                         };
5977
5978                                         q6afe: service@4 {
5979                                                 compatible = "qcom,q6afe";
5980                                                 reg = <APR_SVC_AFE>;
5981                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5982                                                 q6afedai: dais {
5983                                                         compatible = "qcom,q6afe-dais";
5984                                                         #address-cells = <1>;
5985                                                         #size-cells = <0>;
5986                                                         #sound-dai-cells = <1>;
5987                                                 };
5988
5989                                                 q6afecc: clock-controller {
5990                                                         compatible = "qcom,q6afe-clocks";
5991                                                         #clock-cells = <2>;
5992                                                 };
5993                                         };
5994
5995                                         q6asm: service@7 {
5996                                                 compatible = "qcom,q6asm";
5997                                                 reg = <APR_SVC_ASM>;
5998                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5999                                                 q6asmdai: dais {
6000                                                         compatible = "qcom,q6asm-dais";
6001                                                         #address-cells = <1>;
6002                                                         #size-cells = <0>;
6003                                                         #sound-dai-cells = <1>;
6004                                                         iommus = <&apps_smmu 0x1801 0x0>;
6005                                                 };
6006                                         };
6007
6008                                         q6adm: service@8 {
6009                                                 compatible = "qcom,q6adm";
6010                                                 reg = <APR_SVC_ADM>;
6011                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6012                                                 q6routing: routing {
6013                                                         compatible = "qcom,q6adm-routing";
6014                                                         #sound-dai-cells = <0>;
6015                                                 };
6016                                         };
6017                                 };
6018
6019                                 fastrpc {
6020                                         compatible = "qcom,fastrpc";
6021                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
6022                                         label = "adsp";
6023                                         qcom,non-secure-domain;
6024                                         #address-cells = <1>;
6025                                         #size-cells = <0>;
6026
6027                                         compute-cb@3 {
6028                                                 compatible = "qcom,fastrpc-compute-cb";
6029                                                 reg = <3>;
6030                                                 iommus = <&apps_smmu 0x1803 0x0>;
6031                                         };
6032
6033                                         compute-cb@4 {
6034                                                 compatible = "qcom,fastrpc-compute-cb";
6035                                                 reg = <4>;
6036                                                 iommus = <&apps_smmu 0x1804 0x0>;
6037                                         };
6038
6039                                         compute-cb@5 {
6040                                                 compatible = "qcom,fastrpc-compute-cb";
6041                                                 reg = <5>;
6042                                                 iommus = <&apps_smmu 0x1805 0x0>;
6043                                         };
6044                                 };
6045                         };
6046                 };
6047
6048                 intc: interrupt-controller@17a00000 {
6049                         compatible = "arm,gic-v3";
6050                         #interrupt-cells = <3>;
6051                         interrupt-controller;
6052                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
6053                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
6054                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6055                 };
6056
6057                 watchdog@17c10000 {
6058                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6059                         reg = <0 0x17c10000 0 0x1000>;
6060                         clocks = <&sleep_clk>;
6061                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6062                 };
6063
6064                 timer@17c20000 {
6065                         #address-cells = <1>;
6066                         #size-cells = <1>;
6067                         ranges = <0 0 0 0x20000000>;
6068                         compatible = "arm,armv7-timer-mem";
6069                         reg = <0x0 0x17c20000 0x0 0x1000>;
6070                         clock-frequency = <19200000>;
6071
6072                         frame@17c21000 {
6073                                 frame-number = <0>;
6074                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6075                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6076                                 reg = <0x17c21000 0x1000>,
6077                                       <0x17c22000 0x1000>;
6078                         };
6079
6080                         frame@17c23000 {
6081                                 frame-number = <1>;
6082                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6083                                 reg = <0x17c23000 0x1000>;
6084                                 status = "disabled";
6085                         };
6086
6087                         frame@17c25000 {
6088                                 frame-number = <2>;
6089                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6090                                 reg = <0x17c25000 0x1000>;
6091                                 status = "disabled";
6092                         };
6093
6094                         frame@17c27000 {
6095                                 frame-number = <3>;
6096                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6097                                 reg = <0x17c27000 0x1000>;
6098                                 status = "disabled";
6099                         };
6100
6101                         frame@17c29000 {
6102                                 frame-number = <4>;
6103                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6104                                 reg = <0x17c29000 0x1000>;
6105                                 status = "disabled";
6106                         };
6107
6108                         frame@17c2b000 {
6109                                 frame-number = <5>;
6110                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6111                                 reg = <0x17c2b000 0x1000>;
6112                                 status = "disabled";
6113                         };
6114
6115                         frame@17c2d000 {
6116                                 frame-number = <6>;
6117                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6118                                 reg = <0x17c2d000 0x1000>;
6119                                 status = "disabled";
6120                         };
6121                 };
6122
6123                 apps_rsc: rsc@18200000 {
6124                         label = "apps_rsc";
6125                         compatible = "qcom,rpmh-rsc";
6126                         reg = <0x0 0x18200000 0x0 0x10000>,
6127                                 <0x0 0x18210000 0x0 0x10000>,
6128                                 <0x0 0x18220000 0x0 0x10000>;
6129                         reg-names = "drv-0", "drv-1", "drv-2";
6130                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6131                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6132                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6133                         qcom,tcs-offset = <0xd00>;
6134                         qcom,drv-id = <2>;
6135                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
6136                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
6137                         power-domains = <&CLUSTER_PD>;
6138
6139                         rpmhcc: clock-controller {
6140                                 compatible = "qcom,sm8250-rpmh-clk";
6141                                 #clock-cells = <1>;
6142                                 clock-names = "xo";
6143                                 clocks = <&xo_board>;
6144                         };
6145
6146                         rpmhpd: power-controller {
6147                                 compatible = "qcom,sm8250-rpmhpd";
6148                                 #power-domain-cells = <1>;
6149                                 operating-points-v2 = <&rpmhpd_opp_table>;
6150
6151                                 rpmhpd_opp_table: opp-table {
6152                                         compatible = "operating-points-v2";
6153
6154                                         rpmhpd_opp_ret: opp1 {
6155                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6156                                         };
6157
6158                                         rpmhpd_opp_min_svs: opp2 {
6159                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6160                                         };
6161
6162                                         rpmhpd_opp_low_svs: opp3 {
6163                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6164                                         };
6165
6166                                         rpmhpd_opp_svs: opp4 {
6167                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6168                                         };
6169
6170                                         rpmhpd_opp_svs_l1: opp5 {
6171                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6172                                         };
6173
6174                                         rpmhpd_opp_nom: opp6 {
6175                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6176                                         };
6177
6178                                         rpmhpd_opp_nom_l1: opp7 {
6179                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6180                                         };
6181
6182                                         rpmhpd_opp_nom_l2: opp8 {
6183                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6184                                         };
6185
6186                                         rpmhpd_opp_turbo: opp9 {
6187                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6188                                         };
6189
6190                                         rpmhpd_opp_turbo_l1: opp10 {
6191                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6192                                         };
6193                                 };
6194                         };
6195
6196                         apps_bcm_voter: bcm-voter {
6197                                 compatible = "qcom,bcm-voter";
6198                         };
6199                 };
6200
6201                 epss_l3: interconnect@18590000 {
6202                         compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6203                         reg = <0 0x18590000 0 0x1000>;
6204
6205                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6206                         clock-names = "xo", "alternate";
6207
6208                         #interconnect-cells = <1>;
6209                 };
6210
6211                 cpufreq_hw: cpufreq@18591000 {
6212                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6213                         reg = <0 0x18591000 0 0x1000>,
6214                               <0 0x18592000 0 0x1000>,
6215                               <0 0x18593000 0 0x1000>;
6216                         reg-names = "freq-domain0", "freq-domain1",
6217                                     "freq-domain2";
6218
6219                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6220                         clock-names = "xo", "alternate";
6221                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6222                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6223                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6224                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6225                         #freq-domain-cells = <1>;
6226                         #clock-cells = <1>;
6227                 };
6228         };
6229
6230         sound: sound {
6231         };
6232
6233         timer {
6234                 compatible = "arm,armv8-timer";
6235                 interrupts = <GIC_PPI 13
6236                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6237                              <GIC_PPI 14
6238                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6239                              <GIC_PPI 11
6240                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6241                              <GIC_PPI 10
6242                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6243         };
6244
6245         thermal-zones {
6246                 cpu0-thermal {
6247                         polling-delay-passive = <250>;
6248                         polling-delay = <1000>;
6249
6250                         thermal-sensors = <&tsens0 1>;
6251
6252                         trips {
6253                                 cpu0_alert0: trip-point0 {
6254                                         temperature = <90000>;
6255                                         hysteresis = <2000>;
6256                                         type = "passive";
6257                                 };
6258
6259                                 cpu0_alert1: trip-point1 {
6260                                         temperature = <95000>;
6261                                         hysteresis = <2000>;
6262                                         type = "passive";
6263                                 };
6264
6265                                 cpu0_crit: cpu-crit {
6266                                         temperature = <110000>;
6267                                         hysteresis = <1000>;
6268                                         type = "critical";
6269                                 };
6270                         };
6271
6272                         cooling-maps {
6273                                 map0 {
6274                                         trip = <&cpu0_alert0>;
6275                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6276                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6277                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6278                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6279                                 };
6280                                 map1 {
6281                                         trip = <&cpu0_alert1>;
6282                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6283                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6284                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6285                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6286                                 };
6287                         };
6288                 };
6289
6290                 cpu1-thermal {
6291                         polling-delay-passive = <250>;
6292                         polling-delay = <1000>;
6293
6294                         thermal-sensors = <&tsens0 2>;
6295
6296                         trips {
6297                                 cpu1_alert0: trip-point0 {
6298                                         temperature = <90000>;
6299                                         hysteresis = <2000>;
6300                                         type = "passive";
6301                                 };
6302
6303                                 cpu1_alert1: trip-point1 {
6304                                         temperature = <95000>;
6305                                         hysteresis = <2000>;
6306                                         type = "passive";
6307                                 };
6308
6309                                 cpu1_crit: cpu-crit {
6310                                         temperature = <110000>;
6311                                         hysteresis = <1000>;
6312                                         type = "critical";
6313                                 };
6314                         };
6315
6316                         cooling-maps {
6317                                 map0 {
6318                                         trip = <&cpu1_alert0>;
6319                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6320                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6321                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6322                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6323                                 };
6324                                 map1 {
6325                                         trip = <&cpu1_alert1>;
6326                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6327                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6328                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6329                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6330                                 };
6331                         };
6332                 };
6333
6334                 cpu2-thermal {
6335                         polling-delay-passive = <250>;
6336                         polling-delay = <1000>;
6337
6338                         thermal-sensors = <&tsens0 3>;
6339
6340                         trips {
6341                                 cpu2_alert0: trip-point0 {
6342                                         temperature = <90000>;
6343                                         hysteresis = <2000>;
6344                                         type = "passive";
6345                                 };
6346
6347                                 cpu2_alert1: trip-point1 {
6348                                         temperature = <95000>;
6349                                         hysteresis = <2000>;
6350                                         type = "passive";
6351                                 };
6352
6353                                 cpu2_crit: cpu-crit {
6354                                         temperature = <110000>;
6355                                         hysteresis = <1000>;
6356                                         type = "critical";
6357                                 };
6358                         };
6359
6360                         cooling-maps {
6361                                 map0 {
6362                                         trip = <&cpu2_alert0>;
6363                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6364                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6365                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6366                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6367                                 };
6368                                 map1 {
6369                                         trip = <&cpu2_alert1>;
6370                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6371                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6372                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6373                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6374                                 };
6375                         };
6376                 };
6377
6378                 cpu3-thermal {
6379                         polling-delay-passive = <250>;
6380                         polling-delay = <1000>;
6381
6382                         thermal-sensors = <&tsens0 4>;
6383
6384                         trips {
6385                                 cpu3_alert0: trip-point0 {
6386                                         temperature = <90000>;
6387                                         hysteresis = <2000>;
6388                                         type = "passive";
6389                                 };
6390
6391                                 cpu3_alert1: trip-point1 {
6392                                         temperature = <95000>;
6393                                         hysteresis = <2000>;
6394                                         type = "passive";
6395                                 };
6396
6397                                 cpu3_crit: cpu-crit {
6398                                         temperature = <110000>;
6399                                         hysteresis = <1000>;
6400                                         type = "critical";
6401                                 };
6402                         };
6403
6404                         cooling-maps {
6405                                 map0 {
6406                                         trip = <&cpu3_alert0>;
6407                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6408                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6409                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6410                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6411                                 };
6412                                 map1 {
6413                                         trip = <&cpu3_alert1>;
6414                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6415                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6416                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6417                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6418                                 };
6419                         };
6420                 };
6421
6422                 cpu4-top-thermal {
6423                         polling-delay-passive = <250>;
6424                         polling-delay = <1000>;
6425
6426                         thermal-sensors = <&tsens0 7>;
6427
6428                         trips {
6429                                 cpu4_top_alert0: trip-point0 {
6430                                         temperature = <90000>;
6431                                         hysteresis = <2000>;
6432                                         type = "passive";
6433                                 };
6434
6435                                 cpu4_top_alert1: trip-point1 {
6436                                         temperature = <95000>;
6437                                         hysteresis = <2000>;
6438                                         type = "passive";
6439                                 };
6440
6441                                 cpu4_top_crit: cpu-crit {
6442                                         temperature = <110000>;
6443                                         hysteresis = <1000>;
6444                                         type = "critical";
6445                                 };
6446                         };
6447
6448                         cooling-maps {
6449                                 map0 {
6450                                         trip = <&cpu4_top_alert0>;
6451                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6452                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6453                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6454                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6455                                 };
6456                                 map1 {
6457                                         trip = <&cpu4_top_alert1>;
6458                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6459                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6460                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6461                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6462                                 };
6463                         };
6464                 };
6465
6466                 cpu5-top-thermal {
6467                         polling-delay-passive = <250>;
6468                         polling-delay = <1000>;
6469
6470                         thermal-sensors = <&tsens0 8>;
6471
6472                         trips {
6473                                 cpu5_top_alert0: trip-point0 {
6474                                         temperature = <90000>;
6475                                         hysteresis = <2000>;
6476                                         type = "passive";
6477                                 };
6478
6479                                 cpu5_top_alert1: trip-point1 {
6480                                         temperature = <95000>;
6481                                         hysteresis = <2000>;
6482                                         type = "passive";
6483                                 };
6484
6485                                 cpu5_top_crit: cpu-crit {
6486                                         temperature = <110000>;
6487                                         hysteresis = <1000>;
6488                                         type = "critical";
6489                                 };
6490                         };
6491
6492                         cooling-maps {
6493                                 map0 {
6494                                         trip = <&cpu5_top_alert0>;
6495                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6496                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6497                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6498                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6499                                 };
6500                                 map1 {
6501                                         trip = <&cpu5_top_alert1>;
6502                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6503                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6504                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6505                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6506                                 };
6507                         };
6508                 };
6509
6510                 cpu6-top-thermal {
6511                         polling-delay-passive = <250>;
6512                         polling-delay = <1000>;
6513
6514                         thermal-sensors = <&tsens0 9>;
6515
6516                         trips {
6517                                 cpu6_top_alert0: trip-point0 {
6518                                         temperature = <90000>;
6519                                         hysteresis = <2000>;
6520                                         type = "passive";
6521                                 };
6522
6523                                 cpu6_top_alert1: trip-point1 {
6524                                         temperature = <95000>;
6525                                         hysteresis = <2000>;
6526                                         type = "passive";
6527                                 };
6528
6529                                 cpu6_top_crit: cpu-crit {
6530                                         temperature = <110000>;
6531                                         hysteresis = <1000>;
6532                                         type = "critical";
6533                                 };
6534                         };
6535
6536                         cooling-maps {
6537                                 map0 {
6538                                         trip = <&cpu6_top_alert0>;
6539                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6540                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6541                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6542                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6543                                 };
6544                                 map1 {
6545                                         trip = <&cpu6_top_alert1>;
6546                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6547                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6548                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6549                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6550                                 };
6551                         };
6552                 };
6553
6554                 cpu7-top-thermal {
6555                         polling-delay-passive = <250>;
6556                         polling-delay = <1000>;
6557
6558                         thermal-sensors = <&tsens0 10>;
6559
6560                         trips {
6561                                 cpu7_top_alert0: trip-point0 {
6562                                         temperature = <90000>;
6563                                         hysteresis = <2000>;
6564                                         type = "passive";
6565                                 };
6566
6567                                 cpu7_top_alert1: trip-point1 {
6568                                         temperature = <95000>;
6569                                         hysteresis = <2000>;
6570                                         type = "passive";
6571                                 };
6572
6573                                 cpu7_top_crit: cpu-crit {
6574                                         temperature = <110000>;
6575                                         hysteresis = <1000>;
6576                                         type = "critical";
6577                                 };
6578                         };
6579
6580                         cooling-maps {
6581                                 map0 {
6582                                         trip = <&cpu7_top_alert0>;
6583                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6584                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6585                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6586                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6587                                 };
6588                                 map1 {
6589                                         trip = <&cpu7_top_alert1>;
6590                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6591                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6592                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6593                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6594                                 };
6595                         };
6596                 };
6597
6598                 cpu4-bottom-thermal {
6599                         polling-delay-passive = <250>;
6600                         polling-delay = <1000>;
6601
6602                         thermal-sensors = <&tsens0 11>;
6603
6604                         trips {
6605                                 cpu4_bottom_alert0: trip-point0 {
6606                                         temperature = <90000>;
6607                                         hysteresis = <2000>;
6608                                         type = "passive";
6609                                 };
6610
6611                                 cpu4_bottom_alert1: trip-point1 {
6612                                         temperature = <95000>;
6613                                         hysteresis = <2000>;
6614                                         type = "passive";
6615                                 };
6616
6617                                 cpu4_bottom_crit: cpu-crit {
6618                                         temperature = <110000>;
6619                                         hysteresis = <1000>;
6620                                         type = "critical";
6621                                 };
6622                         };
6623
6624                         cooling-maps {
6625                                 map0 {
6626                                         trip = <&cpu4_bottom_alert0>;
6627                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6628                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6629                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6630                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6631                                 };
6632                                 map1 {
6633                                         trip = <&cpu4_bottom_alert1>;
6634                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6635                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6636                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6637                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6638                                 };
6639                         };
6640                 };
6641
6642                 cpu5-bottom-thermal {
6643                         polling-delay-passive = <250>;
6644                         polling-delay = <1000>;
6645
6646                         thermal-sensors = <&tsens0 12>;
6647
6648                         trips {
6649                                 cpu5_bottom_alert0: trip-point0 {
6650                                         temperature = <90000>;
6651                                         hysteresis = <2000>;
6652                                         type = "passive";
6653                                 };
6654
6655                                 cpu5_bottom_alert1: trip-point1 {
6656                                         temperature = <95000>;
6657                                         hysteresis = <2000>;
6658                                         type = "passive";
6659                                 };
6660
6661                                 cpu5_bottom_crit: cpu-crit {
6662                                         temperature = <110000>;
6663                                         hysteresis = <1000>;
6664                                         type = "critical";
6665                                 };
6666                         };
6667
6668                         cooling-maps {
6669                                 map0 {
6670                                         trip = <&cpu5_bottom_alert0>;
6671                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6672                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6673                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6674                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6675                                 };
6676                                 map1 {
6677                                         trip = <&cpu5_bottom_alert1>;
6678                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6679                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6680                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6681                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6682                                 };
6683                         };
6684                 };
6685
6686                 cpu6-bottom-thermal {
6687                         polling-delay-passive = <250>;
6688                         polling-delay = <1000>;
6689
6690                         thermal-sensors = <&tsens0 13>;
6691
6692                         trips {
6693                                 cpu6_bottom_alert0: trip-point0 {
6694                                         temperature = <90000>;
6695                                         hysteresis = <2000>;
6696                                         type = "passive";
6697                                 };
6698
6699                                 cpu6_bottom_alert1: trip-point1 {
6700                                         temperature = <95000>;
6701                                         hysteresis = <2000>;
6702                                         type = "passive";
6703                                 };
6704
6705                                 cpu6_bottom_crit: cpu-crit {
6706                                         temperature = <110000>;
6707                                         hysteresis = <1000>;
6708                                         type = "critical";
6709                                 };
6710                         };
6711
6712                         cooling-maps {
6713                                 map0 {
6714                                         trip = <&cpu6_bottom_alert0>;
6715                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6716                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6717                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6718                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6719                                 };
6720                                 map1 {
6721                                         trip = <&cpu6_bottom_alert1>;
6722                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6723                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6724                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6725                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6726                                 };
6727                         };
6728                 };
6729
6730                 cpu7-bottom-thermal {
6731                         polling-delay-passive = <250>;
6732                         polling-delay = <1000>;
6733
6734                         thermal-sensors = <&tsens0 14>;
6735
6736                         trips {
6737                                 cpu7_bottom_alert0: trip-point0 {
6738                                         temperature = <90000>;
6739                                         hysteresis = <2000>;
6740                                         type = "passive";
6741                                 };
6742
6743                                 cpu7_bottom_alert1: trip-point1 {
6744                                         temperature = <95000>;
6745                                         hysteresis = <2000>;
6746                                         type = "passive";
6747                                 };
6748
6749                                 cpu7_bottom_crit: cpu-crit {
6750                                         temperature = <110000>;
6751                                         hysteresis = <1000>;
6752                                         type = "critical";
6753                                 };
6754                         };
6755
6756                         cooling-maps {
6757                                 map0 {
6758                                         trip = <&cpu7_bottom_alert0>;
6759                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6760                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6761                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6762                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6763                                 };
6764                                 map1 {
6765                                         trip = <&cpu7_bottom_alert1>;
6766                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6767                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6768                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6769                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6770                                 };
6771                         };
6772                 };
6773
6774                 aoss0-thermal {
6775                         polling-delay-passive = <250>;
6776                         polling-delay = <1000>;
6777
6778                         thermal-sensors = <&tsens0 0>;
6779
6780                         trips {
6781                                 aoss0_alert0: trip-point0 {
6782                                         temperature = <90000>;
6783                                         hysteresis = <2000>;
6784                                         type = "hot";
6785                                 };
6786                         };
6787                 };
6788
6789                 cluster0-thermal {
6790                         polling-delay-passive = <250>;
6791                         polling-delay = <1000>;
6792
6793                         thermal-sensors = <&tsens0 5>;
6794
6795                         trips {
6796                                 cluster0_alert0: trip-point0 {
6797                                         temperature = <90000>;
6798                                         hysteresis = <2000>;
6799                                         type = "hot";
6800                                 };
6801                                 cluster0_crit: cluster0-crit {
6802                                         temperature = <110000>;
6803                                         hysteresis = <2000>;
6804                                         type = "critical";
6805                                 };
6806                         };
6807                 };
6808
6809                 cluster1-thermal {
6810                         polling-delay-passive = <250>;
6811                         polling-delay = <1000>;
6812
6813                         thermal-sensors = <&tsens0 6>;
6814
6815                         trips {
6816                                 cluster1_alert0: trip-point0 {
6817                                         temperature = <90000>;
6818                                         hysteresis = <2000>;
6819                                         type = "hot";
6820                                 };
6821                                 cluster1_crit: cluster1-crit {
6822                                         temperature = <110000>;
6823                                         hysteresis = <2000>;
6824                                         type = "critical";
6825                                 };
6826                         };
6827                 };
6828
6829                 gpu-top-thermal {
6830                         polling-delay-passive = <250>;
6831                         polling-delay = <1000>;
6832
6833                         thermal-sensors = <&tsens0 15>;
6834
6835                         cooling-maps {
6836                                 map0 {
6837                                         trip = <&gpu_top_alert0>;
6838                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6839                                 };
6840                         };
6841
6842                         trips {
6843                                 gpu_top_alert0: trip-point0 {
6844                                         temperature = <90000>;
6845                                         hysteresis = <2000>;
6846                                         type = "hot";
6847                                 };
6848                         };
6849                 };
6850
6851                 aoss1-thermal {
6852                         polling-delay-passive = <250>;
6853                         polling-delay = <1000>;
6854
6855                         thermal-sensors = <&tsens1 0>;
6856
6857                         trips {
6858                                 aoss1_alert0: trip-point0 {
6859                                         temperature = <90000>;
6860                                         hysteresis = <2000>;
6861                                         type = "hot";
6862                                 };
6863                         };
6864                 };
6865
6866                 wlan-thermal {
6867                         polling-delay-passive = <250>;
6868                         polling-delay = <1000>;
6869
6870                         thermal-sensors = <&tsens1 1>;
6871
6872                         trips {
6873                                 wlan_alert0: trip-point0 {
6874                                         temperature = <90000>;
6875                                         hysteresis = <2000>;
6876                                         type = "hot";
6877                                 };
6878                         };
6879                 };
6880
6881                 video-thermal {
6882                         polling-delay-passive = <250>;
6883                         polling-delay = <1000>;
6884
6885                         thermal-sensors = <&tsens1 2>;
6886
6887                         trips {
6888                                 video_alert0: trip-point0 {
6889                                         temperature = <90000>;
6890                                         hysteresis = <2000>;
6891                                         type = "hot";
6892                                 };
6893                         };
6894                 };
6895
6896                 mem-thermal {
6897                         polling-delay-passive = <250>;
6898                         polling-delay = <1000>;
6899
6900                         thermal-sensors = <&tsens1 3>;
6901
6902                         trips {
6903                                 mem_alert0: trip-point0 {
6904                                         temperature = <90000>;
6905                                         hysteresis = <2000>;
6906                                         type = "hot";
6907                                 };
6908                         };
6909                 };
6910
6911                 q6-hvx-thermal {
6912                         polling-delay-passive = <250>;
6913                         polling-delay = <1000>;
6914
6915                         thermal-sensors = <&tsens1 4>;
6916
6917                         trips {
6918                                 q6_hvx_alert0: trip-point0 {
6919                                         temperature = <90000>;
6920                                         hysteresis = <2000>;
6921                                         type = "hot";
6922                                 };
6923                         };
6924                 };
6925
6926                 camera-thermal {
6927                         polling-delay-passive = <250>;
6928                         polling-delay = <1000>;
6929
6930                         thermal-sensors = <&tsens1 5>;
6931
6932                         trips {
6933                                 camera_alert0: trip-point0 {
6934                                         temperature = <90000>;
6935                                         hysteresis = <2000>;
6936                                         type = "hot";
6937                                 };
6938                         };
6939                 };
6940
6941                 compute-thermal {
6942                         polling-delay-passive = <250>;
6943                         polling-delay = <1000>;
6944
6945                         thermal-sensors = <&tsens1 6>;
6946
6947                         trips {
6948                                 compute_alert0: trip-point0 {
6949                                         temperature = <90000>;
6950                                         hysteresis = <2000>;
6951                                         type = "hot";
6952                                 };
6953                         };
6954                 };
6955
6956                 npu-thermal {
6957                         polling-delay-passive = <250>;
6958                         polling-delay = <1000>;
6959
6960                         thermal-sensors = <&tsens1 7>;
6961
6962                         trips {
6963                                 npu_alert0: trip-point0 {
6964                                         temperature = <90000>;
6965                                         hysteresis = <2000>;
6966                                         type = "hot";
6967                                 };
6968                         };
6969                 };
6970
6971                 gpu-bottom-thermal {
6972                         polling-delay-passive = <250>;
6973                         polling-delay = <1000>;
6974
6975                         thermal-sensors = <&tsens1 8>;
6976
6977                         cooling-maps {
6978                                 map0 {
6979                                         trip = <&gpu_bottom_alert0>;
6980                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6981                                 };
6982                         };
6983
6984                         trips {
6985                                 gpu_bottom_alert0: trip-point0 {
6986                                         temperature = <90000>;
6987                                         hysteresis = <2000>;
6988                                         type = "hot";
6989                                 };
6990                         };
6991                 };
6992         };
6993 };