arch/arm64/boot/dts/qcom/sm6115.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
   4  */
   5
   6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
   7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
   8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
   9 #include <dt-bindings/clock/qcom,rpmcc.h>
  10 #include <dt-bindings/dma/qcom-gpi.h>
  11 #include <dt-bindings/firmware/qcom,scm.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
  14 #include <dt-bindings/interconnect/qcom,sm6115.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/power/qcom-rpmpd.h>
  17 #include <dt-bindings/thermal/thermal.h>
  18
  19 / {
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         chosen { };
  26
  27         clocks {
  28                 xo_board: xo-board {
  29                         compatible = "fixed-clock";
  30                         #clock-cells = <0>;
  31                 };
  32
  33                 sleep_clk: sleep-clk {
  34                         compatible = "fixed-clock";
  35                         #clock-cells = <0>;
  36                 };
  37         };
  38
  39         cpus {
  40                 #address-cells = <2>;
  41                 #size-cells = <0>;
  42
  43                 CPU0: cpu@0 {
  44                         device_type = "cpu";
  45                         compatible = "qcom,kryo260";
  46                         reg = <0x0 0x0>;
  47                         clocks = <&cpufreq_hw 0>;
  48                         capacity-dmips-mhz = <1024>;
  49                         dynamic-power-coefficient = <100>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&L2_0>;
  52                         qcom,freq-domain = <&cpufreq_hw 0>;
  53                         power-domains = <&CPU_PD0>;
  54                         power-domain-names = "psci";
  55                         L2_0: l2-cache {
  56                                 compatible = "cache";
  57                                 cache-level = <2>;
  58                                 cache-unified;
  59                         };
  60                 };
  61
  62                 CPU1: cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "qcom,kryo260";
  65                         reg = <0x0 0x1>;
  66                         clocks = <&cpufreq_hw 0>;
  67                         capacity-dmips-mhz = <1024>;
  68                         dynamic-power-coefficient = <100>;
  69                         enable-method = "psci";
  70                         next-level-cache = <&L2_0>;
  71                         qcom,freq-domain = <&cpufreq_hw 0>;
  72                         power-domains = <&CPU_PD1>;
  73                         power-domain-names = "psci";
  74                 };
  75
  76                 CPU2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "qcom,kryo260";
  79                         reg = <0x0 0x2>;
  80                         clocks = <&cpufreq_hw 0>;
  81                         capacity-dmips-mhz = <1024>;
  82                         dynamic-power-coefficient = <100>;
  83                         enable-method = "psci";
  84                         next-level-cache = <&L2_0>;
  85                         qcom,freq-domain = <&cpufreq_hw 0>;
  86                         power-domains = <&CPU_PD2>;
  87                         power-domain-names = "psci";
  88                 };
  89
  90                 CPU3: cpu@3 {
  91                         device_type = "cpu";
  92                         compatible = "qcom,kryo260";
  93                         reg = <0x0 0x3>;
  94                         clocks = <&cpufreq_hw 0>;
  95                         capacity-dmips-mhz = <1024>;
  96                         dynamic-power-coefficient = <100>;
  97                         enable-method = "psci";
  98                         next-level-cache = <&L2_0>;
  99                         qcom,freq-domain = <&cpufreq_hw 0>;
 100                         power-domains = <&CPU_PD3>;
 101                         power-domain-names = "psci";
 102                 };
 103
 104                 CPU4: cpu@100 {
 105                         device_type = "cpu";
 106                         compatible = "qcom,kryo260";
 107                         reg = <0x0 0x100>;
 108                         clocks = <&cpufreq_hw 1>;
 109                         enable-method = "psci";
 110                         capacity-dmips-mhz = <1638>;
 111                         dynamic-power-coefficient = <282>;
 112                         next-level-cache = <&L2_1>;
 113                         qcom,freq-domain = <&cpufreq_hw 1>;
 114                         power-domains = <&CPU_PD4>;
 115                         power-domain-names = "psci";
 116                         L2_1: l2-cache {
 117                                 compatible = "cache";
 118                                 cache-level = <2>;
 119                                 cache-unified;
 120                         };
 121                 };
 122
 123                 CPU5: cpu@101 {
 124                         device_type = "cpu";
 125                         compatible = "qcom,kryo260";
 126                         reg = <0x0 0x101>;
 127                         clocks = <&cpufreq_hw 1>;
 128                         capacity-dmips-mhz = <1638>;
 129                         dynamic-power-coefficient = <282>;
 130                         enable-method = "psci";
 131                         next-level-cache = <&L2_1>;
 132                         qcom,freq-domain = <&cpufreq_hw 1>;
 133                         power-domains = <&CPU_PD5>;
 134                         power-domain-names = "psci";
 135                 };
 136
 137                 CPU6: cpu@102 {
 138                         device_type = "cpu";
 139                         compatible = "qcom,kryo260";
 140                         reg = <0x0 0x102>;
 141                         clocks = <&cpufreq_hw 1>;
 142                         capacity-dmips-mhz = <1638>;
 143                         dynamic-power-coefficient = <282>;
 144                         enable-method = "psci";
 145                         next-level-cache = <&L2_1>;
 146                         qcom,freq-domain = <&cpufreq_hw 1>;
 147                         power-domains = <&CPU_PD6>;
 148                         power-domain-names = "psci";
 149                 };
 150
 151                 CPU7: cpu@103 {
 152                         device_type = "cpu";
 153                         compatible = "qcom,kryo260";
 154                         reg = <0x0 0x103>;
 155                         clocks = <&cpufreq_hw 1>;
 156                         capacity-dmips-mhz = <1638>;
 157                         dynamic-power-coefficient = <282>;
 158                         enable-method = "psci";
 159                         next-level-cache = <&L2_1>;
 160                         qcom,freq-domain = <&cpufreq_hw 1>;
 161                         power-domains = <&CPU_PD7>;
 162                         power-domain-names = "psci";
 163                 };
 164
 165                 cpu-map {
 166                         cluster0 {
 167                                 core0 {
 168                                         cpu = <&CPU0>;
 169                                 };
 170
 171                                 core1 {
 172                                         cpu = <&CPU1>;
 173                                 };
 174
 175                                 core2 {
 176                                         cpu = <&CPU2>;
 177                                 };
 178
 179                                 core3 {
 180                                         cpu = <&CPU3>;
 181                                 };
 182                         };
 183
 184                         cluster1 {
 185                                 core0 {
 186                                         cpu = <&CPU4>;
 187                                 };
 188
 189                                 core1 {
 190                                         cpu = <&CPU5>;
 191                                 };
 192
 193                                 core2 {
 194                                         cpu = <&CPU6>;
 195                                 };
 196
 197                                 core3 {
 198                                         cpu = <&CPU7>;
 199                                 };
 200                         };
 201                 };
 202
 203                 idle-states {
 204                         entry-method = "psci";
 205
 206                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 207                                 compatible = "arm,idle-state";
 208                                 idle-state-name = "silver-rail-power-collapse";
 209                                 arm,psci-suspend-param = <0x40000003>;
 210                                 entry-latency-us = <290>;
 211                                 exit-latency-us = <376>;
 212                                 min-residency-us = <1182>;
 213                                 local-timer-stop;
 214                         };
 215
 216                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 217                                 compatible = "arm,idle-state";
 218                                 idle-state-name = "gold-rail-power-collapse";
 219                                 arm,psci-suspend-param = <0x40000003>;
 220                                 entry-latency-us = <297>;
 221                                 exit-latency-us = <324>;
 222                                 min-residency-us = <1110>;
 223                                 local-timer-stop;
 224                         };
 225                 };
 226
 227                 domain-idle-states {
 228                         CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
 229                                 /* GDHS */
 230                                 compatible = "domain-idle-state";
 231                                 arm,psci-suspend-param = <0x40000022>;
 232                                 entry-latency-us = <360>;
 233                                 exit-latency-us = <421>;
 234                                 min-residency-us = <782>;
 235                         };
 236
 237                         CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
 238                                 /* Power Collapse */
 239                                 compatible = "domain-idle-state";
 240                                 arm,psci-suspend-param = <0x41000044>;
 241                                 entry-latency-us = <800>;
 242                                 exit-latency-us = <2118>;
 243                                 min-residency-us = <7376>;
 244                         };
 245
 246                         CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
 247                                 /* GDHS */
 248                                 compatible = "domain-idle-state";
 249                                 arm,psci-suspend-param = <0x40000042>;
 250                                 entry-latency-us = <314>;
 251                                 exit-latency-us = <345>;
 252                                 min-residency-us = <660>;
 253                         };
 254
 255                         CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {
 256                                 /* Power Collapse */
 257                                 compatible = "domain-idle-state";
 258                                 arm,psci-suspend-param = <0x41000044>;
 259                                 entry-latency-us = <640>;
 260                                 exit-latency-us = <1654>;
 261                                 min-residency-us = <8094>;
 262                         };
 263                 };
 264         };
 265
 266         firmware {
 267                 scm: scm {
 268                         compatible = "qcom,scm-sm6115", "qcom,scm";
 269                         #reset-cells = <1>;
 270                         interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
 271                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
 272                 };
 273         };
 274
 275         memory@80000000 {
 276                 device_type = "memory";
 277                 /* We expect the bootloader to fill in the size */
 278                 reg = <0 0x80000000 0 0>;
 279         };
 280
 281         qup_opp_table: opp-table-qup {
 282                 compatible = "operating-points-v2";
 283
 284                 opp-75000000 {
 285                         opp-hz = /bits/ 64 <75000000>;
 286                         required-opps = <&rpmpd_opp_low_svs>;
 287                 };
 288
 289                 opp-100000000 {
 290                         opp-hz = /bits/ 64 <100000000>;
 291                         required-opps = <&rpmpd_opp_svs>;
 292                 };
 293
 294                 opp-128000000 {
 295                         opp-hz = /bits/ 64 <128000000>;
 296                         required-opps = <&rpmpd_opp_nom>;
 297                 };
 298         };
 299
 300         pmu {
 301                 compatible = "arm,armv8-pmuv3";
 302                 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 303         };
 304
 305         psci {
 306                 compatible = "arm,psci-1.0";
 307                 method = "smc";
 308
 309                 CPU_PD0: power-domain-cpu0 {
 310                         #power-domain-cells = <0>;
 311                         power-domains = <&CLUSTER_0_PD>;
 312                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 313                 };
 314
 315                 CPU_PD1: power-domain-cpu1 {
 316                         #power-domain-cells = <0>;
 317                         power-domains = <&CLUSTER_0_PD>;
 318                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 319                 };
 320
 321                 CPU_PD2: power-domain-cpu2 {
 322                         #power-domain-cells = <0>;
 323                         power-domains = <&CLUSTER_0_PD>;
 324                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 325                 };
 326
 327                 CPU_PD3: power-domain-cpu3 {
 328                         #power-domain-cells = <0>;
 329                         power-domains = <&CLUSTER_0_PD>;
 330                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 331                 };
 332
 333                 CPU_PD4: power-domain-cpu4 {
 334                         #power-domain-cells = <0>;
 335                         power-domains = <&CLUSTER_1_PD>;
 336                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 337                 };
 338
 339                 CPU_PD5: power-domain-cpu5 {
 340                         #power-domain-cells = <0>;
 341                         power-domains = <&CLUSTER_1_PD>;
 342                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 343                 };
 344
 345                 CPU_PD6: power-domain-cpu6 {
 346                         #power-domain-cells = <0>;
 347                         power-domains = <&CLUSTER_1_PD>;
 348                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 349                 };
 350
 351                 CPU_PD7: power-domain-cpu7 {
 352                         #power-domain-cells = <0>;
 353                         power-domains = <&CLUSTER_1_PD>;
 354                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 355                 };
 356
 357                 CLUSTER_0_PD: power-domain-cpu-cluster0 {
 358                         #power-domain-cells = <0>;
 359                         domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;
 360                 };
 361
 362                 CLUSTER_1_PD: power-domain-cpu-cluster1 {
 363                         #power-domain-cells = <0>;
 364                         domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;
 365                 };
 366         };
 367
 368         rpm: remoteproc {
 369                 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
 370
 371                 glink-edge {
 372                         compatible = "qcom,glink-rpm";
 373
 374                         interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
 375                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 376                         mboxes = <&apcs_glb 0>;
 377
 378                         rpm_requests: rpm-requests {
 379                                 compatible = "qcom,rpm-sm6115";
 380                                 qcom,glink-channels = "rpm_requests";
 381
 382                                 rpmcc: clock-controller {
 383                                         compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
 384                                         clocks = <&xo_board>;
 385                                         clock-names = "xo";
 386                                         #clock-cells = <1>;
 387                                 };
 388
 389                                 rpmpd: power-controller {
 390                                         compatible = "qcom,sm6115-rpmpd";
 391                                         #power-domain-cells = <1>;
 392                                         operating-points-v2 = <&rpmpd_opp_table>;
 393
 394                                         rpmpd_opp_table: opp-table {
 395                                                 compatible = "operating-points-v2";
 396
 397                                                 rpmpd_opp_min_svs: opp1 {
 398                                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 399                                                 };
 400
 401                                                 rpmpd_opp_low_svs: opp2 {
 402                                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 403                                                 };
 404
 405                                                 rpmpd_opp_svs: opp3 {
 406                                                         opp-level = <RPM_SMD_LEVEL_SVS>;
 407                                                 };
 408
 409                                                 rpmpd_opp_svs_plus: opp4 {
 410                                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 411                                                 };
 412
 413                                                 rpmpd_opp_nom: opp5 {
 414                                                         opp-level = <RPM_SMD_LEVEL_NOM>;
 415                                                 };
 416
 417                                                 rpmpd_opp_nom_plus: opp6 {
 418                                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 419                                                 };
 420
 421                                                 rpmpd_opp_turbo: opp7 {
 422                                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
 423                                                 };
 424
 425                                                 rpmpd_opp_turbo_plus: opp8 {
 426                                                         opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
 427                                                 };
 428                                         };
 429                                 };
 430                         };
 431                 };
 432         };
 433
 434         reserved_memory: reserved-memory {
 435                 #address-cells = <2>;
 436                 #size-cells = <2>;
 437                 ranges;
 438
 439                 hyp_mem: memory@45700000 {
 440                         reg = <0x0 0x45700000 0x0 0x600000>;
 441                         no-map;
 442                 };
 443
 444                 xbl_aop_mem: memory@45e00000 {
 445                         reg = <0x0 0x45e00000 0x0 0x140000>;
 446                         no-map;
 447                 };
 448
 449                 sec_apps_mem: memory@45fff000 {
 450                         reg = <0x0 0x45fff000 0x0 0x1000>;
 451                         no-map;
 452                 };
 453
 454                 smem_mem: memory@46000000 {
 455                         compatible = "qcom,smem";
 456                         reg = <0x0 0x46000000 0x0 0x200000>;
 457                         no-map;
 458
 459                         hwlocks = <&tcsr_mutex 3>;
 460                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 461                 };
 462
 463                 cdsp_sec_mem: memory@46200000 {
 464                         reg = <0x0 0x46200000 0x0 0x1e00000>;
 465                         no-map;
 466                 };
 467
 468                 pil_modem_mem: memory@4ab00000 {
 469                         reg = <0x0 0x4ab00000 0x0 0x6900000>;
 470                         no-map;
 471                 };
 472
 473                 pil_video_mem: memory@51400000 {
 474                         reg = <0x0 0x51400000 0x0 0x500000>;
 475                         no-map;
 476                 };
 477
 478                 wlan_msa_mem: memory@51900000 {
 479                         reg = <0x0 0x51900000 0x0 0x100000>;
 480                         no-map;
 481                 };
 482
 483                 pil_cdsp_mem: memory@51a00000 {
 484                         reg = <0x0 0x51a00000 0x0 0x1e00000>;
 485                         no-map;
 486                 };
 487
 488                 pil_adsp_mem: memory@53800000 {
 489                         reg = <0x0 0x53800000 0x0 0x2800000>;
 490                         no-map;
 491                 };
 492
 493                 pil_ipa_fw_mem: memory@56100000 {
 494                         reg = <0x0 0x56100000 0x0 0x10000>;
 495                         no-map;
 496                 };
 497
 498                 pil_ipa_gsi_mem: memory@56110000 {
 499                         reg = <0x0 0x56110000 0x0 0x5000>;
 500                         no-map;
 501                 };
 502
 503                 pil_gpu_mem: memory@56115000 {
 504                         reg = <0x0 0x56115000 0x0 0x2000>;
 505                         no-map;
 506                 };
 507
 508                 cont_splash_memory: memory@5c000000 {
 509                         reg = <0x0 0x5c000000 0x0 0x00f00000>;
 510                         no-map;
 511                 };
 512
 513                 dfps_data_memory: memory@5cf00000 {
 514                         reg = <0x0 0x5cf00000 0x0 0x0100000>;
 515                         no-map;
 516                 };
 517
 518                 removed_mem: memory@60000000 {
 519                         reg = <0x0 0x60000000 0x0 0x3900000>;
 520                         no-map;
 521                 };
 522
 523                 rmtfs_mem: memory@89b01000 {
 524                         compatible = "qcom,rmtfs-mem";
 525                         reg = <0x0 0x89b01000 0x0 0x200000>;
 526                         no-map;
 527
 528                         qcom,client-id = <1>;
 529                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
 530                 };
 531         };
 532
 533         smp2p-adsp {
 534                 compatible = "qcom,smp2p";
 535                 qcom,smem = <443>, <429>;
 536
 537                 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
 538
 539                 mboxes = <&apcs_glb 10>;
 540
 541                 qcom,local-pid = <0>;
 542                 qcom,remote-pid = <2>;
 543
 544                 adsp_smp2p_out: master-kernel {
 545                         qcom,entry-name = "master-kernel";
 546                         #qcom,smem-state-cells = <1>;
 547                 };
 548
 549                 adsp_smp2p_in: slave-kernel {
 550                         qcom,entry-name = "slave-kernel";
 551
 552                         interrupt-controller;
 553                         #interrupt-cells = <2>;
 554                 };
 555         };
 556
 557         smp2p-cdsp {
 558                 compatible = "qcom,smp2p";
 559                 qcom,smem = <94>, <432>;
 560
 561                 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
 562
 563                 mboxes = <&apcs_glb 30>;
 564
 565                 qcom,local-pid = <0>;
 566                 qcom,remote-pid = <5>;
 567
 568                 cdsp_smp2p_out: master-kernel {
 569                         qcom,entry-name = "master-kernel";
 570                         #qcom,smem-state-cells = <1>;
 571                 };
 572
 573                 cdsp_smp2p_in: slave-kernel {
 574                         qcom,entry-name = "slave-kernel";
 575
 576                         interrupt-controller;
 577                         #interrupt-cells = <2>;
 578                 };
 579         };
 580
 581         smp2p-mpss {
 582                 compatible = "qcom,smp2p";
 583                 qcom,smem = <435>, <428>;
 584
 585                 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
 586
 587                 mboxes = <&apcs_glb 14>;
 588
 589                 qcom,local-pid = <0>;
 590                 qcom,remote-pid = <1>;
 591
 592                 modem_smp2p_out: master-kernel {
 593                         qcom,entry-name = "master-kernel";
 594                         #qcom,smem-state-cells = <1>;
 595                 };
 596
 597                 modem_smp2p_in: slave-kernel {
 598                         qcom,entry-name = "slave-kernel";
 599
 600                         interrupt-controller;
 601                         #interrupt-cells = <2>;
 602                 };
 603         };
 604
 605         soc: soc@0 {
 606                 compatible = "simple-bus";
 607                 #address-cells = <2>;
 608                 #size-cells = <2>;
 609                 ranges = <0 0 0 0 0x10 0>;
 610                 dma-ranges = <0 0 0 0 0x10 0>;
 611
 612                 tcsr_mutex: hwlock@340000 {
 613                         compatible = "qcom,tcsr-mutex";
 614                         reg = <0x0 0x00340000 0x0 0x20000>;
 615                         #hwlock-cells = <1>;
 616                 };
 617
 618                 tcsr_regs: syscon@3c0000 {
 619                         compatible = "qcom,sm6115-tcsr", "syscon";
 620                         reg = <0x0 0x003c0000 0x0 0x40000>;
 621                 };
 622
 623                 tlmm: pinctrl@500000 {
 624                         compatible = "qcom,sm6115-tlmm";
 625                         reg = <0x0 0x00500000 0x0 0x400000>,
 626                               <0x0 0x00900000 0x0 0x400000>,
 627                               <0x0 0x00d00000 0x0 0x400000>;
 628                         reg-names = "west", "south", "east";
 629                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 630                         gpio-controller;
 631                         gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
 632                         #gpio-cells = <2>;
 633                         interrupt-controller;
 634                         #interrupt-cells = <2>;
 635
 636                         qup_i2c0_default: qup-i2c0-default-state {
 637                                 pins = "gpio0", "gpio1";
 638                                 function = "qup0";
 639                                 drive-strength = <2>;
 640                                 bias-pull-up;
 641                         };
 642
 643                         qup_i2c1_default: qup-i2c1-default-state {
 644                                 pins = "gpio4", "gpio5";
 645                                 function = "qup1";
 646                                 drive-strength = <2>;
 647                                 bias-pull-up;
 648                         };
 649
 650                         qup_i2c2_default: qup-i2c2-default-state {
 651                                 pins = "gpio6", "gpio7";
 652                                 function = "qup2";
 653                                 drive-strength = <2>;
 654                                 bias-pull-up;
 655                         };
 656
 657                         qup_i2c3_default: qup-i2c3-default-state {
 658                                 pins = "gpio8", "gpio9";
 659                                 function = "qup3";
 660                                 drive-strength = <2>;
 661                                 bias-pull-up;
 662                         };
 663
 664                         qup_i2c4_default: qup-i2c4-default-state {
 665                                 pins = "gpio12", "gpio13";
 666                                 function = "qup4";
 667                                 drive-strength = <2>;
 668                                 bias-pull-up;
 669                         };
 670
 671                         qup_i2c5_default: qup-i2c5-default-state {
 672                                 pins = "gpio14", "gpio15";
 673                                 function = "qup5";
 674                                 drive-strength = <2>;
 675                                 bias-pull-up;
 676                         };
 677
 678                         qup_spi0_default: qup-spi0-default-state {
 679                                 pins = "gpio0", "gpio1","gpio2", "gpio3";
 680                                 function = "qup0";
 681                                 drive-strength = <2>;
 682                                 bias-pull-up;
 683                         };
 684
 685                         qup_spi1_default: qup-spi1-default-state {
 686                                 pins = "gpio4", "gpio5", "gpio69", "gpio70";
 687                                 function = "qup1";
 688                                 drive-strength = <2>;
 689                                 bias-pull-up;
 690                         };
 691
 692                         qup_spi2_default: qup-spi2-default-state {
 693                                 pins = "gpio6", "gpio7", "gpio71", "gpio80";
 694                                 function = "qup2";
 695                                 drive-strength = <2>;
 696                                 bias-pull-up;
 697                         };
 698
 699                         qup_spi3_default: qup-spi3-default-state {
 700                                 pins = "gpio8", "gpio9", "gpio10", "gpio11";
 701                                 function = "qup3";
 702                                 drive-strength = <2>;
 703                                 bias-pull-up;
 704                         };
 705
 706                         qup_spi4_default: qup-spi4-default-state {
 707                                 pins = "gpio12", "gpio13", "gpio96", "gpio97";
 708                                 function = "qup4";
 709                                 drive-strength = <2>;
 710                                 bias-pull-up;
 711                         };
 712
 713                         qup_spi5_default: qup-spi5-default-state {
 714                                 pins = "gpio14", "gpio15", "gpio16", "gpio17";
 715                                 function = "qup5";
 716                                 drive-strength = <2>;
 717                                 bias-pull-up;
 718                         };
 719
 720                         sdc1_state_on: sdc1-on-state {
 721                                 clk-pins {
 722                                         pins = "sdc1_clk";
 723                                         bias-disable;
 724                                         drive-strength = <16>;
 725                                 };
 726
 727                                 cmd-pins {
 728                                         pins = "sdc1_cmd";
 729                                         bias-pull-up;
 730                                         drive-strength = <10>;
 731                                 };
 732
 733                                 data-pins {
 734                                         pins = "sdc1_data";
 735                                         bias-pull-up;
 736                                         drive-strength = <10>;
 737                                 };
 738
 739                                 rclk-pins {
 740                                         pins = "sdc1_rclk";
 741                                         bias-pull-down;
 742                                 };
 743                         };
 744
 745                         sdc1_state_off: sdc1-off-state {
 746                                 clk-pins {
 747                                         pins = "sdc1_clk";
 748                                         bias-disable;
 749                                         drive-strength = <2>;
 750                                 };
 751
 752                                 cmd-pins {
 753                                         pins = "sdc1_cmd";
 754                                         bias-pull-up;
 755                                         drive-strength = <2>;
 756                                 };
 757
 758                                 data-pins {
 759                                         pins = "sdc1_data";
 760                                         bias-pull-up;
 761                                         drive-strength = <2>;
 762                                 };
 763
 764                                 rclk-pins {
 765                                         pins = "sdc1_rclk";
 766                                         bias-pull-down;
 767                                 };
 768                         };
 769
 770                         sdc2_state_on: sdc2-on-state {
 771                                 clk-pins {
 772                                         pins = "sdc2_clk";
 773                                         bias-disable;
 774                                         drive-strength = <16>;
 775                                 };
 776
 777                                 cmd-pins {
 778                                         pins = "sdc2_cmd";
 779                                         bias-pull-up;
 780                                         drive-strength = <10>;
 781                                 };
 782
 783                                 data-pins {
 784                                         pins = "sdc2_data";
 785                                         bias-pull-up;
 786                                         drive-strength = <10>;
 787                                 };
 788                         };
 789
 790                         sdc2_state_off: sdc2-off-state {
 791                                 clk-pins {
 792                                         pins = "sdc2_clk";
 793                                         bias-disable;
 794                                         drive-strength = <2>;
 795                                 };
 796
 797                                 cmd-pins {
 798                                         pins = "sdc2_cmd";
 799                                         bias-pull-up;
 800                                         drive-strength = <2>;
 801                                 };
 802
 803                                 data-pins {
 804                                         pins = "sdc2_data";
 805                                         bias-pull-up;
 806                                         drive-strength = <2>;
 807                                 };
 808                         };
 809                 };
 810
 811                 gcc: clock-controller@1400000 {
 812                         compatible = "qcom,gcc-sm6115";
 813                         reg = <0x0 0x01400000 0x0 0x1f0000>;
 814                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
 815                         clock-names = "bi_tcxo", "sleep_clk";
 816                         #clock-cells = <1>;
 817                         #reset-cells = <1>;
 818                         #power-domain-cells = <1>;
 819                 };
 820
 821                 usb_hsphy: phy@1613000 {
 822                         compatible = "qcom,sm6115-qusb2-phy";
 823                         reg = <0x0 0x01613000 0x0 0x180>;
 824                         #phy-cells = <0>;
 825
 826                         clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
 827                         clock-names = "cfg_ahb", "ref";
 828
 829                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 830                         nvmem-cells = <&qusb2_hstx_trim>;
 831
 832                         status = "disabled";
 833                 };
 834
 835                 cryptobam: dma-controller@1b04000 {
 836                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 837                         reg = <0x0 0x01b04000 0x0 0x24000>;
 838                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 839                         clocks = <&rpmcc RPM_SMD_CE1_CLK>;
 840                         clock-names = "bam_clk";
 841                         #dma-cells = <1>;
 842                         qcom,ee = <0>;
 843                         qcom,controlled-remotely;
 844                         iommus = <&apps_smmu 0x92 0>,
 845                                  <&apps_smmu 0x94 0x11>,
 846                                  <&apps_smmu 0x96 0x11>,
 847                                  <&apps_smmu 0x98 0x1>,
 848                                  <&apps_smmu 0x9F 0>;
 849                 };
 850
 851                 crypto: crypto@1b3a000 {
 852                         compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
 853                         reg = <0x0 0x01b3a000 0x0 0x6000>;
 854                         clocks = <&rpmcc RPM_SMD_CE1_CLK>;
 855                         clock-names = "core";
 856
 857                         dmas = <&cryptobam 6>, <&cryptobam 7>;
 858                         dma-names = "rx", "tx";
 859                         iommus = <&apps_smmu 0x92 0>,
 860                                  <&apps_smmu 0x94 0x11>,
 861                                  <&apps_smmu 0x96 0x11>,
 862                                  <&apps_smmu 0x98 0x1>,
 863                                  <&apps_smmu 0x9F 0>;
 864                 };
 865
 866                 usb_qmpphy: phy@1615000 {
 867                         compatible = "qcom,sm6115-qmp-usb3-phy";
 868                         reg = <0x0 0x01615000 0x0 0x1000>;
 869
 870                         clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
 871                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 872                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
 873                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 874                         clock-names = "cfg_ahb",
 875                                       "ref",
 876                                       "com_aux",
 877                                       "pipe";
 878
 879                         resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
 880                                  <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
 881                         reset-names = "phy", "phy_phy";
 882
 883                         #clock-cells = <0>;
 884                         clock-output-names = "usb3_phy_pipe_clk_src";
 885
 886                         #phy-cells = <0>;
 887                         orientation-switch;
 888
 889                         qcom,tcsr-reg = <&tcsr_regs 0xb244>;
 890
 891                         status = "disabled";
 892
 893                         ports {
 894                                 #address-cells = <1>;
 895                                 #size-cells = <0>;
 896
 897                                 port@0 {
 898                                         reg = <0>;
 899
 900                                         usb_qmpphy_out: endpoint {
 901                                         };
 902                                 };
 903
 904                                 port@1 {
 905                                         reg = <1>;
 906
 907                                         usb_qmpphy_usb_ss_in: endpoint {
 908                                                 remote-endpoint = <&usb_dwc3_ss>;
 909                                         };
 910                                 };
 911                         };
 912                 };
 913
 914                 system_noc: interconnect@1880000 {
 915                         compatible = "qcom,sm6115-snoc";
 916                         reg = <0x0 0x01880000 0x0 0x5f080>;
 917                         clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
 918                                  <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
 919                                  <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
 920                                  <&rpmcc RPM_SMD_IPA_CLK>;
 921                         clock-names = "cpu_axi",
 922                                       "ufs_axi",
 923                                       "usb_axi",
 924                                       "ipa";
 925                         #interconnect-cells = <2>;
 926
 927                         clk_virt: interconnect-clk {
 928                                 compatible = "qcom,sm6115-clk-virt";
 929                                 #interconnect-cells = <2>;
 930                         };
 931
 932                         mmrt_virt: interconnect-mmrt {
 933                                 compatible = "qcom,sm6115-mmrt-virt";
 934                                 #interconnect-cells = <2>;
 935                         };
 936
 937                         mmnrt_virt: interconnect-mmnrt {
 938                                 compatible = "qcom,sm6115-mmnrt-virt";
 939                                 #interconnect-cells = <2>;
 940                         };
 941                 };
 942
 943                 config_noc: interconnect@1900000 {
 944                         compatible = "qcom,sm6115-cnoc";
 945                         reg = <0x0 0x01900000 0x0 0x6200>;
 946                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>;
 947                         clock-names = "usb_axi";
 948                         #interconnect-cells = <2>;
 949                 };
 950
 951                 qfprom@1b40000 {
 952                         compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
 953                         reg = <0x0 0x01b40000 0x0 0x7000>;
 954                         #address-cells = <1>;
 955                         #size-cells = <1>;
 956
 957                         qusb2_hstx_trim: hstx-trim@25b {
 958                                 reg = <0x25b 0x1>;
 959                                 bits = <1 4>;
 960                         };
 961
 962                         gpu_speed_bin: gpu-speed-bin@6006 {
 963                                 reg = <0x6006 0x2>;
 964                                 bits = <5 8>;
 965                         };
 966                 };
 967
 968                 rng: rng@1b53000 {
 969                         compatible = "qcom,prng-ee";
 970                         reg = <0x0 0x01b53000 0x0 0x1000>;
 971                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 972                         clock-names = "core";
 973                 };
 974
 975                 pmu@1b8e300 {
 976                         compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
 977                         reg = <0x0 0x01b8e300 0x0 0x600>;
 978                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 979
 980                         operating-points-v2 = <&cpu_bwmon_opp_table>;
 981                         interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
 982                                          &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
 983
 984                         cpu_bwmon_opp_table: opp-table {
 985                                 compatible = "operating-points-v2";
 986
 987                                 opp-0 {
 988                                         opp-peak-kBps = <(200 * 4 * 1000)>;
 989                                 };
 990
 991                                 opp-1 {
 992                                         opp-peak-kBps = <(300 * 4 * 1000)>;
 993                                 };
 994
 995                                 opp-2 {
 996                                         opp-peak-kBps = <(451 * 4 * 1000)>;
 997                                 };
 998
 999                                 opp-3 {
1000                                         opp-peak-kBps = <(547 * 4 * 1000)>;
1001                                 };
1002
1003                                 opp-4 {
1004                                         opp-peak-kBps = <(681 * 4 * 1000)>;
1005                                 };
1006
1007                                 opp-5 {
1008                                         opp-peak-kBps = <(768 * 4 * 1000)>;
1009                                 };
1010
1011                                 opp-6 {
1012                                         opp-peak-kBps = <(1017 * 4 * 1000)>;
1013                                 };
1014
1015                                 opp-7 {
1016                                         opp-peak-kBps = <(1353 * 4 * 1000)>;
1017                                 };
1018
1019                                 opp-8 {
1020                                         opp-peak-kBps = <(1555 * 4 * 1000)>;
1021                                 };
1022
1023                                 opp-9 {
1024                                         opp-peak-kBps = <(1804 * 4 * 1000)>;
1025                                 };
1026                         };
1027                 };
1028
1029                 spmi_bus: spmi@1c40000 {
1030                         compatible = "qcom,spmi-pmic-arb";
1031                         reg = <0x0 0x01c40000 0x0 0x1100>,
1032                               <0x0 0x01e00000 0x0 0x2000000>,
1033                               <0x0 0x03e00000 0x0 0x100000>,
1034                               <0x0 0x03f00000 0x0 0xa0000>,
1035                               <0x0 0x01c0a000 0x0 0x26000>;
1036                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1037                         interrupt-names = "periph_irq";
1038                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
1039                         qcom,ee = <0>;
1040                         qcom,channel = <0>;
1041                         #address-cells = <2>;
1042                         #size-cells = <0>;
1043                         interrupt-controller;
1044                         #interrupt-cells = <4>;
1045                 };
1046
1047                 tsens0: thermal-sensor@4411000 {
1048                         compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
1049                         reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
1050                               <0x0 0x04410000 0x0 0x8>; /* SROT */
1051                         #qcom,sensors = <16>;
1052                         interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1053                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1054                         interrupt-names = "uplow", "critical";
1055                         #thermal-sensor-cells = <1>;
1056                 };
1057
1058                 bimc: interconnect@4480000 {
1059                         compatible = "qcom,sm6115-bimc";
1060                         reg = <0x0 0x04480000 0x0 0x80000>;
1061                         #interconnect-cells = <2>;
1062                 };
1063
1064                 rpm_msg_ram: sram@45f0000 {
1065                         compatible = "qcom,rpm-msg-ram";
1066                         reg = <0x0 0x045f0000 0x0 0x7000>;
1067                 };
1068
1069                 sram@4690000 {
1070                         compatible = "qcom,rpm-stats";
1071                         reg = <0x0 0x04690000 0x0 0x10000>;
1072                 };
1073
1074                 sdhc_1: mmc@4744000 {
1075                         compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1076                         reg = <0x0 0x04744000 0x0 0x1000>,
1077                               <0x0 0x04745000 0x0 0x1000>,
1078                               <0x0 0x04748000 0x0 0x8000>;
1079                         reg-names = "hc", "cqhci", "ice";
1080
1081                         interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
1082                                      <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1083                         interrupt-names = "hc_irq", "pwr_irq";
1084
1085                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1086                                  <&gcc GCC_SDCC1_APPS_CLK>,
1087                                  <&rpmcc RPM_SMD_XO_CLK_SRC>,
1088                                  <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1089                         clock-names = "iface", "core", "xo", "ice";
1090
1091                         power-domains = <&rpmpd SM6115_VDDCX>;
1092                         operating-points-v2 = <&sdhc1_opp_table>;
1093                         interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
1094                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1095                                         <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1096                                          &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
1097                         interconnect-names = "sdhc-ddr",
1098                                              "cpu-sdhc";
1099
1100                         bus-width = <8>;
1101                         status = "disabled";
1102
1103                         sdhc1_opp_table: opp-table {
1104                                 compatible = "operating-points-v2";
1105
1106                                 opp-100000000 {
1107                                         opp-hz = /bits/ 64 <100000000>;
1108                                         required-opps = <&rpmpd_opp_low_svs>;
1109                                         opp-peak-kBps = <250000 133320>;
1110                                         opp-avg-kBps = <102400 65000>;
1111                                 };
1112
1113                                 opp-192000000 {
1114                                         opp-hz = /bits/ 64 <192000000>;
1115                                         required-opps = <&rpmpd_opp_low_svs>;
1116                                         opp-peak-kBps = <800000 300000>;
1117                                         opp-avg-kBps = <204800 200000>;
1118                                 };
1119
1120                                 opp-384000000 {
1121                                         opp-hz = /bits/ 64 <384000000>;
1122                                         required-opps = <&rpmpd_opp_svs_plus>;
1123                                         opp-peak-kBps = <800000 300000>;
1124                                         opp-avg-kBps = <204800 200000>;
1125                                 };
1126                         };
1127                 };
1128
1129                 sdhc_2: mmc@4784000 {
1130                         compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1131                         reg = <0x0 0x04784000 0x0 0x1000>;
1132                         reg-names = "hc";
1133
1134                         interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1135                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1136                         interrupt-names = "hc_irq", "pwr_irq";
1137
1138                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1139                                  <&gcc GCC_SDCC2_APPS_CLK>,
1140                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1141                         clock-names = "iface", "core", "xo";
1142
1143                         power-domains = <&rpmpd SM6115_VDDCX>;
1144                         operating-points-v2 = <&sdhc2_opp_table>;
1145                         iommus = <&apps_smmu 0x00a0 0x0>;
1146                         resets = <&gcc GCC_SDCC2_BCR>;
1147                         interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
1148                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1149                                         <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1150                                          &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
1151                         interconnect-names = "sdhc-ddr",
1152                                              "cpu-sdhc";
1153
1154                         bus-width = <4>;
1155                         qcom,dll-config = <0x0007642c>;
1156                         qcom,ddr-config = <0x80040868>;
1157                         status = "disabled";
1158
1159                         sdhc2_opp_table: opp-table {
1160                                 compatible = "operating-points-v2";
1161
1162                                 opp-100000000 {
1163                                         opp-hz = /bits/ 64 <100000000>;
1164                                         required-opps = <&rpmpd_opp_low_svs>;
1165                                         opp-peak-kBps = <250000 133320>;
1166                                         opp-avg-kBps = <261438 150000>;
1167                                 };
1168
1169                                 opp-202000000 {
1170                                         opp-hz = /bits/ 64 <202000000>;
1171                                         required-opps = <&rpmpd_opp_nom>;
1172                                         opp-peak-kBps = <800000 300000>;
1173                                         opp-avg-kBps = <261438 300000>;
1174                                 };
1175                         };
1176                 };
1177
1178                 ufs_mem_hc: ufs@4804000 {
1179                         compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1180                         reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
1181                         reg-names = "std", "ice";
1182                         interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1183                         phys = <&ufs_mem_phy>;
1184                         phy-names = "ufsphy";
1185                         lanes-per-direction = <1>;
1186                         #reset-cells = <1>;
1187                         resets = <&gcc GCC_UFS_PHY_BCR>;
1188                         reset-names = "rst";
1189
1190                         power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1191                         iommus = <&apps_smmu 0x100 0>;
1192
1193                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1194                                  <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
1195                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1196                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1197                                  <&rpmcc RPM_SMD_XO_CLK_SRC>,
1198                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1199                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1200                                  <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1201                         clock-names = "core_clk",
1202                                       "bus_aggr_clk",
1203                                       "iface_clk",
1204                                       "core_clk_unipro",
1205                                       "ref_clk",
1206                                       "tx_lane0_sync_clk",
1207                                       "rx_lane0_sync_clk",
1208                                       "ice_core_clk";
1209
1210                         freq-table-hz = <50000000 200000000>,
1211                                         <0 0>,
1212                                         <0 0>,
1213                                         <37500000 150000000>,
1214                                         <0 0>,
1215                                         <0 0>,
1216                                         <0 0>,
1217                                         <75000000 300000000>;
1218
1219                         status = "disabled";
1220                 };
1221
1222                 ufs_mem_phy: phy@4807000 {
1223                         compatible = "qcom,sm6115-qmp-ufs-phy";
1224                         reg = <0x0 0x04807000 0x0 0x1000>;
1225
1226                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1227                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1228                                  <&gcc GCC_UFS_CLKREF_CLK>;
1229                         clock-names = "ref",
1230                                       "ref_aux",
1231                                       "qref";
1232
1233                         resets = <&ufs_mem_hc 0>;
1234                         reset-names = "ufsphy";
1235
1236                         #phy-cells = <0>;
1237
1238                         status = "disabled";
1239                 };
1240
1241                 gpi_dma0: dma-controller@4a00000 {
1242                         compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1243                         reg = <0x0 0x04a00000 0x0 0x60000>;
1244                         interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1245                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1246                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1247                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1248                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1249                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1250                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1251                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1252                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1253                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1254                         dma-channels = <10>;
1255                         dma-channel-mask = <0xf>;
1256                         iommus = <&apps_smmu 0xf6 0x0>;
1257                         #dma-cells = <3>;
1258                         status = "disabled";
1259                 };
1260
1261                 qupv3_id_0: geniqup@4ac0000 {
1262                         compatible = "qcom,geni-se-qup";
1263                         reg = <0x0 0x04ac0000 0x0 0x2000>;
1264                         clock-names = "m-ahb", "s-ahb";
1265                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1266                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1267                         #address-cells = <2>;
1268                         #size-cells = <2>;
1269                         iommus = <&apps_smmu 0xe3 0x0>;
1270                         ranges;
1271                         status = "disabled";
1272
1273                         i2c0: i2c@4a80000 {
1274                                 compatible = "qcom,geni-i2c";
1275                                 reg = <0x0 0x04a80000 0x0 0x4000>;
1276                                 clock-names = "se";
1277                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1278                                 pinctrl-names = "default";
1279                                 pinctrl-0 = <&qup_i2c0_default>;
1280                                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1281                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1282                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1283                                 dma-names = "tx", "rx";
1284                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1285                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1286                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1287                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1288                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1289                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1290                                 interconnect-names = "qup-core",
1291                                                      "qup-config",
1292                                                      "qup-memory";
1293                                 #address-cells = <1>;
1294                                 #size-cells = <0>;
1295                                 status = "disabled";
1296                         };
1297
1298                         spi0: spi@4a80000 {
1299                                 compatible = "qcom,geni-spi";
1300                                 reg = <0x0 0x04a80000 0x0 0x4000>;
1301                                 clock-names = "se";
1302                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303                                 pinctrl-names = "default";
1304                                 pinctrl-0 = <&qup_spi0_default>;
1305                                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1306                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1307                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1308                                 dma-names = "tx", "rx";
1309                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1310                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1311                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1312                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1313                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1314                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1315                                 interconnect-names = "qup-core",
1316                                                      "qup-config",
1317                                                      "qup-memory";
1318                                 #address-cells = <1>;
1319                                 #size-cells = <0>;
1320                                 status = "disabled";
1321                         };
1322
1323                         i2c1: i2c@4a84000 {
1324                                 compatible = "qcom,geni-i2c";
1325                                 reg = <0x0 0x04a84000 0x0 0x4000>;
1326                                 clock-names = "se";
1327                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1328                                 pinctrl-names = "default";
1329                                 pinctrl-0 = <&qup_i2c1_default>;
1330                                 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1331                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1332                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1333                                 dma-names = "tx", "rx";
1334                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1335                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1336                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1337                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1338                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1339                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1340                                 interconnect-names = "qup-core",
1341                                                      "qup-config",
1342                                                      "qup-memory";
1343                                 #address-cells = <1>;
1344                                 #size-cells = <0>;
1345                                 status = "disabled";
1346                         };
1347
1348                         spi1: spi@4a84000 {
1349                                 compatible = "qcom,geni-spi";
1350                                 reg = <0x0 0x04a84000 0x0 0x4000>;
1351                                 clock-names = "se";
1352                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1353                                 pinctrl-names = "default";
1354                                 pinctrl-0 = <&qup_spi1_default>;
1355                                 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1356                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1357                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1358                                 dma-names = "tx", "rx";
1359                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1360                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1361                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1362                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1363                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1364                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1365                                 interconnect-names = "qup-core",
1366                                                      "qup-config",
1367                                                      "qup-memory";
1368                                 #address-cells = <1>;
1369                                 #size-cells = <0>;
1370                                 status = "disabled";
1371                         };
1372
1373                         i2c2: i2c@4a88000 {
1374                                 compatible = "qcom,geni-i2c";
1375                                 reg = <0x0 0x04a88000 0x0 0x4000>;
1376                                 clock-names = "se";
1377                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1378                                 pinctrl-names = "default";
1379                                 pinctrl-0 = <&qup_i2c2_default>;
1380                                 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1381                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1382                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1383                                 dma-names = "tx", "rx";
1384                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1385                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1386                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1387                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1388                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1389                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1390                                 interconnect-names = "qup-core",
1391                                                      "qup-config",
1392                                                      "qup-memory";
1393                                 #address-cells = <1>;
1394                                 #size-cells = <0>;
1395                                 status = "disabled";
1396                         };
1397
1398                         spi2: spi@4a88000 {
1399                                 compatible = "qcom,geni-spi";
1400                                 reg = <0x0 0x04a88000 0x0 0x4000>;
1401                                 clock-names = "se";
1402                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1403                                 pinctrl-names = "default";
1404                                 pinctrl-0 = <&qup_spi2_default>;
1405                                 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1406                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1407                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1408                                 dma-names = "tx", "rx";
1409                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1410                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1411                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1412                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1413                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1414                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1415                                 interconnect-names = "qup-core",
1416                                                      "qup-config",
1417                                                      "qup-memory";
1418                                 #address-cells = <1>;
1419                                 #size-cells = <0>;
1420                                 status = "disabled";
1421                         };
1422
1423                         i2c3: i2c@4a8c000 {
1424                                 compatible = "qcom,geni-i2c";
1425                                 reg = <0x0 0x04a8c000 0x0 0x4000>;
1426                                 clock-names = "se";
1427                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1428                                 pinctrl-names = "default";
1429                                 pinctrl-0 = <&qup_i2c3_default>;
1430                                 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1431                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1432                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1433                                 dma-names = "tx", "rx";
1434                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1435                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1436                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1437                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1438                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1439                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1440                                 interconnect-names = "qup-core",
1441                                                      "qup-config",
1442                                                      "qup-memory";
1443                                 #address-cells = <1>;
1444                                 #size-cells = <0>;
1445                                 status = "disabled";
1446                         };
1447
1448                         spi3: spi@4a8c000 {
1449                                 compatible = "qcom,geni-spi";
1450                                 reg = <0x0 0x04a8c000 0x0 0x4000>;
1451                                 clock-names = "se";
1452                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1453                                 pinctrl-names = "default";
1454                                 pinctrl-0 = <&qup_spi3_default>;
1455                                 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1456                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1457                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1458                                 dma-names = "tx", "rx";
1459                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1460                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1461                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1462                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1463                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1464                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1465                                 interconnect-names = "qup-core",
1466                                                      "qup-config",
1467                                                      "qup-memory";
1468                                 #address-cells = <1>;
1469                                 #size-cells = <0>;
1470                                 status = "disabled";
1471                         };
1472
1473                         uart3: serial@4a8c000 {
1474                                 compatible = "qcom,geni-uart";
1475                                 reg = <0x0 0x04a8c000 0x0 0x4000>;
1476                                 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1477                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1478                                 clock-names = "se";
1479                                 power-domains = <&rpmpd SM6115_VDDCX>;
1480                                 operating-points-v2 = <&qup_opp_table>;
1481                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1482                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1483                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1484                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
1485                                 interconnect-names = "qup-core",
1486                                                      "qup-config";
1487                                 status = "disabled";
1488                         };
1489
1490                         i2c4: i2c@4a90000 {
1491                                 compatible = "qcom,geni-i2c";
1492                                 reg = <0x0 0x04a90000 0x0 0x4000>;
1493                                 clock-names = "se";
1494                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1495                                 pinctrl-names = "default";
1496                                 pinctrl-0 = <&qup_i2c4_default>;
1497                                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1498                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1499                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1500                                 dma-names = "tx", "rx";
1501                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1502                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1503                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1504                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1505                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1506                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1507                                 interconnect-names = "qup-core",
1508                                                      "qup-config",
1509                                                      "qup-memory";
1510                                 #address-cells = <1>;
1511                                 #size-cells = <0>;
1512                                 status = "disabled";
1513                         };
1514
1515                         spi4: spi@4a90000 {
1516                                 compatible = "qcom,geni-spi";
1517                                 reg = <0x0 0x04a90000 0x0 0x4000>;
1518                                 clock-names = "se";
1519                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1520                                 pinctrl-names = "default";
1521                                 pinctrl-0 = <&qup_spi4_default>;
1522                                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1523                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1524                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1525                                 dma-names = "tx", "rx";
1526                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1527                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1528                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1529                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1530                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1531                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1532                                 interconnect-names = "qup-core",
1533                                                      "qup-config",
1534                                                      "qup-memory";
1535                                 #address-cells = <1>;
1536                                 #size-cells = <0>;
1537                                 status = "disabled";
1538                         };
1539
1540                         uart4: serial@4a90000 {
1541                                 compatible = "qcom,geni-debug-uart";
1542                                 reg = <0x0 0x04a90000 0x0 0x4000>;
1543                                 clock-names = "se";
1544                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1545                                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1546                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1547                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1548                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1549                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
1550                                 interconnect-names = "qup-core",
1551                                                      "qup-config";
1552                                 status = "disabled";
1553                         };
1554
1555                         i2c5: i2c@4a94000 {
1556                                 compatible = "qcom,geni-i2c";
1557                                 reg = <0x0 0x04a94000 0x0 0x4000>;
1558                                 clock-names = "se";
1559                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1560                                 pinctrl-names = "default";
1561                                 pinctrl-0 = <&qup_i2c5_default>;
1562                                 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1563                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1564                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1565                                 dma-names = "tx", "rx";
1566                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1567                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1568                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1569                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1570                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1571                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1572                                 interconnect-names = "qup-core",
1573                                                      "qup-config",
1574                                                      "qup-memory";
1575                                 #address-cells = <1>;
1576                                 #size-cells = <0>;
1577                                 status = "disabled";
1578                         };
1579
1580                         spi5: spi@4a94000 {
1581                                 compatible = "qcom,geni-spi";
1582                                 reg = <0x0 0x04a94000 0x0 0x4000>;
1583                                 clock-names = "se";
1584                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1585                                 pinctrl-names = "default";
1586                                 pinctrl-0 = <&qup_spi5_default>;
1587                                 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1588                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1589                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1590                                 dma-names = "tx", "rx";
1591                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1592                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1593                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1594                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1595                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1596                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1597                                 interconnect-names = "qup-core",
1598                                                      "qup-config",
1599                                                      "qup-memory";
1600                                 #address-cells = <1>;
1601                                 #size-cells = <0>;
1602                                 status = "disabled";
1603                         };
1604                 };
1605
1606                 usb: usb@4ef8800 {
1607                         compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1608                         reg = <0x0 0x04ef8800 0x0 0x400>;
1609                         #address-cells = <2>;
1610                         #size-cells = <2>;
1611                         ranges;
1612
1613                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1614                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1615                                  <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1616                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1617                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1618                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1619                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1620
1621                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1622                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1623                         assigned-clock-rates = <19200000>, <66666667>;
1624
1625                         interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1626                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1627                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1628                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1629                         interrupt-names = "pwr_event",
1630                                           "qusb2_phy",
1631                                           "hs_phy_irq",
1632                                           "ss_phy_irq";
1633
1634                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1635                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1636                          /* TODO: USB<->IPA path */
1637                         interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG
1638                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1639                                         <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1640                                          &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
1641                         interconnect-names = "usb-ddr",
1642                                              "apps-usb";
1643
1644                         status = "disabled";
1645
1646                         usb_dwc3: usb@4e00000 {
1647                                 compatible = "snps,dwc3";
1648                                 reg = <0x0 0x04e00000 0x0 0xcd00>;
1649                                 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1650                                 phys = <&usb_hsphy>, <&usb_qmpphy>;
1651                                 phy-names = "usb2-phy", "usb3-phy";
1652                                 iommus = <&apps_smmu 0x120 0x0>;
1653                                 snps,dis_u2_susphy_quirk;
1654                                 snps,dis_enblslpm_quirk;
1655                                 snps,has-lpm-erratum;
1656                                 snps,hird-threshold = /bits/ 8 <0x10>;
1657                                 snps,usb3_lpm_capable;
1658
1659                                 usb-role-switch;
1660
1661                                 ports {
1662                                         #address-cells = <1>;
1663                                         #size-cells = <0>;
1664
1665                                         port@0 {
1666                                                 reg = <0>;
1667
1668                                                 usb_dwc3_hs: endpoint {
1669                                                 };
1670                                         };
1671
1672                                         port@1 {
1673                                                 reg = <1>;
1674
1675                                                 usb_dwc3_ss: endpoint {
1676                                                         remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1677                                                 };
1678                                         };
1679                                 };
1680                         };
1681                 };
1682
1683                 gpu: gpu@5900000 {
1684                         compatible = "qcom,adreno-610.0", "qcom,adreno";
1685                         reg = <0x0 0x05900000 0x0 0x40000>;
1686                         reg-names = "kgsl_3d0_reg_memory";
1687
1688                         /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
1689                         clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
1690                                  <&gpucc GPU_CC_AHB_CLK>,
1691                                  <&gcc GCC_BIMC_GPU_AXI_CLK>,
1692                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1693                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1694                                  <&gpucc GPU_CC_CXO_CLK>;
1695                         clock-names = "core",
1696                                       "iface",
1697                                       "mem_iface",
1698                                       "alt_mem_iface",
1699                                       "gmu",
1700                                       "xo";
1701
1702                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
1703
1704                         iommus = <&adreno_smmu 0 1>;
1705                         operating-points-v2 = <&gpu_opp_table>;
1706                         power-domains = <&rpmpd SM6115_VDDCX>;
1707                         qcom,gmu = <&gmu_wrapper>;
1708
1709                         nvmem-cells = <&gpu_speed_bin>;
1710                         nvmem-cell-names = "speed_bin";
1711                         #cooling-cells = <2>;
1712
1713                         status = "disabled";
1714
1715                         zap-shader {
1716                                 memory-region = <&pil_gpu_mem>;
1717                         };
1718
1719                         gpu_opp_table: opp-table {
1720                                 compatible = "operating-points-v2";
1721
1722                                 opp-320000000 {
1723                                         opp-hz = /bits/ 64 <320000000>;
1724                                         required-opps = <&rpmpd_opp_low_svs>;
1725                                         opp-supported-hw = <0x1f>;
1726                                 };
1727
1728                                 opp-465000000 {
1729                                         opp-hz = /bits/ 64 <465000000>;
1730                                         required-opps = <&rpmpd_opp_svs>;
1731                                         opp-supported-hw = <0x1f>;
1732                                 };
1733
1734                                 opp-600000000 {
1735                                         opp-hz = /bits/ 64 <600000000>;
1736                                         required-opps = <&rpmpd_opp_svs_plus>;
1737                                         opp-supported-hw = <0x1f>;
1738                                 };
1739
1740                                 opp-745000000 {
1741                                         opp-hz = /bits/ 64 <745000000>;
1742                                         required-opps = <&rpmpd_opp_nom>;
1743                                         opp-supported-hw = <0xf>;
1744                                 };
1745
1746                                 opp-820000000 {
1747                                         opp-hz = /bits/ 64 <820000000>;
1748                                         required-opps = <&rpmpd_opp_nom_plus>;
1749                                         opp-supported-hw = <0x7>;
1750                                 };
1751
1752                                 opp-900000000 {
1753                                         opp-hz = /bits/ 64 <900000000>;
1754                                         required-opps = <&rpmpd_opp_turbo>;
1755                                         opp-supported-hw = <0x7>;
1756                                 };
1757
1758                                 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */
1759                                 opp-950000000 {
1760                                         opp-hz = /bits/ 64 <950000000>;
1761                                         required-opps = <&rpmpd_opp_turbo_plus>;
1762                                         opp-supported-hw = <0x4>;
1763                                 };
1764
1765                                 opp-980000000 {
1766                                         opp-hz = /bits/ 64 <980000000>;
1767                                         required-opps = <&rpmpd_opp_turbo_plus>;
1768                                         opp-supported-hw = <0x3>;
1769                                 };
1770                         };
1771                 };
1772
1773                 gmu_wrapper: gmu@596a000 {
1774                         compatible = "qcom,adreno-gmu-wrapper";
1775                         reg = <0x0 0x0596a000 0x0 0x30000>;
1776                         reg-names = "gmu";
1777                         power-domains = <&gpucc GPU_CX_GDSC>,
1778                                         <&gpucc GPU_GX_GDSC>;
1779                         power-domain-names = "cx", "gx";
1780                 };
1781
1782                 gpucc: clock-controller@5990000 {
1783                         compatible = "qcom,sm6115-gpucc";
1784                         reg = <0x0 0x05990000 0x0 0x9000>;
1785                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1786                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1787                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1788                         #clock-cells = <1>;
1789                         #reset-cells = <1>;
1790                         #power-domain-cells = <1>;
1791                 };
1792
1793                 adreno_smmu: iommu@59a0000 {
1794                         compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1795                                      "qcom,smmu-500", "arm,mmu-500";
1796                         reg = <0x0 0x059a0000 0x0 0x10000>;
1797                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1798                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1799                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1800                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1801                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1802                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1803                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1804                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1805                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1806
1807                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1808                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1809                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1810                         clock-names = "mem",
1811                                       "hlos",
1812                                       "iface";
1813                         power-domains = <&gpucc GPU_CX_GDSC>;
1814
1815                         #global-interrupts = <1>;
1816                         #iommu-cells = <2>;
1817                 };
1818
1819                 mdss: display-subsystem@5e00000 {
1820                         compatible = "qcom,sm6115-mdss";
1821                         reg = <0x0 0x05e00000 0x0 0x1000>;
1822                         reg-names = "mdss";
1823
1824                         power-domains = <&dispcc MDSS_GDSC>;
1825
1826                         clocks = <&gcc GCC_DISP_AHB_CLK>,
1827                                  <&gcc GCC_DISP_HF_AXI_CLK>,
1828                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
1829
1830                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1831                         interrupt-controller;
1832                         #interrupt-cells = <1>;
1833
1834                         iommus = <&apps_smmu 0x420 0x2>,
1835                                  <&apps_smmu 0x421 0x0>;
1836
1837                         interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG
1838                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1839                                         <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1840                                          &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
1841                         interconnect-names = "mdp0-mem",
1842                                              "cpu-cfg";
1843
1844                         #address-cells = <2>;
1845                         #size-cells = <2>;
1846                         ranges;
1847
1848                         status = "disabled";
1849
1850                         mdp: display-controller@5e01000 {
1851                                 compatible = "qcom,sm6115-dpu";
1852                                 reg = <0x0 0x05e01000 0x0 0x8f000>,
1853                                       <0x0 0x05eb0000 0x0 0x2008>;
1854                                 reg-names = "mdp", "vbif";
1855
1856                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1857                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
1858                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
1859                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1860                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
1861                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1862                                 clock-names = "bus",
1863                                               "iface",
1864                                               "core",
1865                                               "lut",
1866                                               "rot",
1867                                               "vsync";
1868
1869                                 operating-points-v2 = <&mdp_opp_table>;
1870                                 power-domains = <&rpmpd SM6115_VDDCX>;
1871
1872                                 interrupt-parent = <&mdss>;
1873                                 interrupts = <0>;
1874
1875                                 ports {
1876                                         #address-cells = <1>;
1877                                         #size-cells = <0>;
1878
1879                                         port@0 {
1880                                                 reg = <0>;
1881                                                 dpu_intf1_out: endpoint {
1882                                                         remote-endpoint = <&mdss_dsi0_in>;
1883                                                 };
1884                                         };
1885                                 };
1886
1887                                 mdp_opp_table: opp-table {
1888                                         compatible = "operating-points-v2";
1889
1890                                         opp-19200000 {
1891                                                 opp-hz = /bits/ 64 <19200000>;
1892                                                 required-opps = <&rpmpd_opp_min_svs>;
1893                                         };
1894
1895                                         opp-192000000 {
1896                                                 opp-hz = /bits/ 64 <192000000>;
1897                                                 required-opps = <&rpmpd_opp_low_svs>;
1898                                         };
1899
1900                                         opp-256000000 {
1901                                                 opp-hz = /bits/ 64 <256000000>;
1902                                                 required-opps = <&rpmpd_opp_svs>;
1903                                         };
1904
1905                                         opp-307200000 {
1906                                                 opp-hz = /bits/ 64 <307200000>;
1907                                                 required-opps = <&rpmpd_opp_svs_plus>;
1908                                         };
1909
1910                                         opp-384000000 {
1911                                                 opp-hz = /bits/ 64 <384000000>;
1912                                                 required-opps = <&rpmpd_opp_nom>;
1913                                         };
1914                                 };
1915                         };
1916
1917                         mdss_dsi0: dsi@5e94000 {
1918                                 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1919                                 reg = <0x0 0x05e94000 0x0 0x400>;
1920                                 reg-names = "dsi_ctrl";
1921
1922                                 interrupt-parent = <&mdss>;
1923                                 interrupts = <4>;
1924
1925                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1926                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1927                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1928                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1929                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
1930                                          <&gcc GCC_DISP_HF_AXI_CLK>;
1931                                 clock-names = "byte",
1932                                               "byte_intf",
1933                                               "pixel",
1934                                               "core",
1935                                               "iface",
1936                                               "bus";
1937
1938                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1939                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1940                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1941
1942                                 operating-points-v2 = <&dsi_opp_table>;
1943                                 power-domains = <&rpmpd SM6115_VDDCX>;
1944                                 phys = <&mdss_dsi0_phy>;
1945
1946                                 #address-cells = <1>;
1947                                 #size-cells = <0>;
1948
1949                                 status = "disabled";
1950
1951                                 ports {
1952                                         #address-cells = <1>;
1953                                         #size-cells = <0>;
1954
1955                                         port@0 {
1956                                                 reg = <0>;
1957                                                 mdss_dsi0_in: endpoint {
1958                                                         remote-endpoint = <&dpu_intf1_out>;
1959                                                 };
1960                                         };
1961
1962                                         port@1 {
1963                                                 reg = <1>;
1964                                                 mdss_dsi0_out: endpoint {
1965                                                 };
1966                                         };
1967                                 };
1968
1969                                 dsi_opp_table: opp-table {
1970                                         compatible = "operating-points-v2";
1971
1972                                         opp-19200000 {
1973                                                 opp-hz = /bits/ 64 <19200000>;
1974                                                 required-opps = <&rpmpd_opp_min_svs>;
1975                                         };
1976
1977                                         opp-164000000 {
1978                                                 opp-hz = /bits/ 64 <164000000>;
1979                                                 required-opps = <&rpmpd_opp_low_svs>;
1980                                         };
1981
1982                                         opp-187500000 {
1983                                                 opp-hz = /bits/ 64 <187500000>;
1984                                                 required-opps = <&rpmpd_opp_svs>;
1985                                         };
1986                                 };
1987                         };
1988
1989                         mdss_dsi0_phy: phy@5e94400 {
1990                                 compatible = "qcom,dsi-phy-14nm-2290";
1991                                 reg = <0x0 0x05e94400 0x0 0x100>,
1992                                       <0x0 0x05e94500 0x0 0x300>,
1993                                       <0x0 0x05e94800 0x0 0x188>;
1994                                 reg-names = "dsi_phy",
1995                                             "dsi_phy_lane",
1996                                             "dsi_pll";
1997
1998                                 #clock-cells = <1>;
1999                                 #phy-cells = <0>;
2000
2001                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2002                                          <&rpmcc RPM_SMD_XO_CLK_SRC>;
2003                                 clock-names = "iface", "ref";
2004
2005                                 status = "disabled";
2006                         };
2007                 };
2008
2009                 dispcc: clock-controller@5f00000 {
2010                         compatible = "qcom,sm6115-dispcc";
2011                         reg = <0x0 0x05f00000 0 0x20000>;
2012                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2013                                  <&sleep_clk>,
2014                                  <&mdss_dsi0_phy 0>,
2015                                  <&mdss_dsi0_phy 1>,
2016                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
2017                         #clock-cells = <1>;
2018                         #reset-cells = <1>;
2019                         #power-domain-cells = <1>;
2020                 };
2021
2022                 remoteproc_mpss: remoteproc@6080000 {
2023                         compatible = "qcom,sm6115-mpss-pas";
2024                         reg = <0x0 0x06080000 0x0 0x100>;
2025
2026                         interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
2027                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2028                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2029                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2030                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2031                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2032                         interrupt-names = "wdog", "fatal", "ready", "handover",
2033                                           "stop-ack", "shutdown-ack";
2034
2035                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2036                         clock-names = "xo";
2037
2038                         power-domains = <&rpmpd SM6115_VDDCX>;
2039
2040                         memory-region = <&pil_modem_mem>;
2041
2042                         qcom,smem-states = <&modem_smp2p_out 0>;
2043                         qcom,smem-state-names = "stop";
2044
2045                         status = "disabled";
2046
2047                         glink-edge {
2048                                 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
2049                                 label = "mpss";
2050                                 qcom,remote-pid = <1>;
2051                                 mboxes = <&apcs_glb 12>;
2052                         };
2053                 };
2054
2055                 stm@8002000 {
2056                         compatible = "arm,coresight-stm", "arm,primecell";
2057                         reg = <0x0 0x08002000 0x0 0x1000>,
2058                               <0x0 0x0e280000 0x0 0x180000>;
2059                         reg-names = "stm-base", "stm-stimulus-base";
2060
2061                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2062                         clock-names = "apb_pclk";
2063
2064                         status = "disabled";
2065
2066                         out-ports {
2067                                 port {
2068                                         stm_out: endpoint {
2069                                                 remote-endpoint = <&funnel_in0_in>;
2070                                         };
2071                                 };
2072                         };
2073                 };
2074
2075                 cti0: cti@8010000 {
2076                         compatible = "arm,coresight-cti", "arm,primecell";
2077                         reg = <0x0 0x08010000 0x0 0x1000>;
2078
2079                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2080                         clock-names = "apb_pclk";
2081
2082                         status = "disabled";
2083                 };
2084
2085                 cti1: cti@8011000 {
2086                         compatible = "arm,coresight-cti", "arm,primecell";
2087                         reg = <0x0 0x08011000 0x0 0x1000>;
2088
2089                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2090                         clock-names = "apb_pclk";
2091
2092                         status = "disabled";
2093                 };
2094
2095                 cti2: cti@8012000 {
2096                         compatible = "arm,coresight-cti", "arm,primecell";
2097                         reg = <0x0 0x08012000 0x0 0x1000>;
2098
2099                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2100                         clock-names = "apb_pclk";
2101
2102                         status = "disabled";
2103                 };
2104
2105                 cti3: cti@8013000 {
2106                         compatible = "arm,coresight-cti", "arm,primecell";
2107                         reg = <0x0 0x08013000 0x0 0x1000>;
2108
2109                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2110                         clock-names = "apb_pclk";
2111
2112                         status = "disabled";
2113                 };
2114
2115                 cti4: cti@8014000 {
2116                         compatible = "arm,coresight-cti", "arm,primecell";
2117                         reg = <0x0 0x08014000 0x0 0x1000>;
2118
2119                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2120                         clock-names = "apb_pclk";
2121
2122                         status = "disabled";
2123                 };
2124
2125                 cti5: cti@8015000 {
2126                         compatible = "arm,coresight-cti", "arm,primecell";
2127                         reg = <0x0 0x08015000 0x0 0x1000>;
2128
2129                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2130                         clock-names = "apb_pclk";
2131
2132                         status = "disabled";
2133                 };
2134
2135                 cti6: cti@8016000 {
2136                         compatible = "arm,coresight-cti", "arm,primecell";
2137                         reg = <0x0 0x08016000 0x0 0x1000>;
2138
2139                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2140                         clock-names = "apb_pclk";
2141
2142                         status = "disabled";
2143                 };
2144
2145                 cti7: cti@8017000 {
2146                         compatible = "arm,coresight-cti", "arm,primecell";
2147                         reg = <0x0 0x08017000 0x0 0x1000>;
2148
2149                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2150                         clock-names = "apb_pclk";
2151
2152                         status = "disabled";
2153                 };
2154
2155                 cti8: cti@8018000 {
2156                         compatible = "arm,coresight-cti", "arm,primecell";
2157                         reg = <0x0 0x08018000 0x0 0x1000>;
2158
2159                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2160                         clock-names = "apb_pclk";
2161
2162                         status = "disabled";
2163                 };
2164
2165                 cti9: cti@8019000 {
2166                         compatible = "arm,coresight-cti", "arm,primecell";
2167                         reg = <0x0 0x08019000 0x0 0x1000>;
2168
2169                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2170                         clock-names = "apb_pclk";
2171
2172                         status = "disabled";
2173                 };
2174
2175                 cti10: cti@801a000 {
2176                         compatible = "arm,coresight-cti", "arm,primecell";
2177                         reg = <0x0 0x0801a000 0x0 0x1000>;
2178
2179                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2180                         clock-names = "apb_pclk";
2181
2182                         status = "disabled";
2183                 };
2184
2185                 cti11: cti@801b000 {
2186                         compatible = "arm,coresight-cti", "arm,primecell";
2187                         reg = <0x0 0x0801b000 0x0 0x1000>;
2188
2189                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2190                         clock-names = "apb_pclk";
2191
2192                         status = "disabled";
2193                 };
2194
2195                 cti12: cti@801c000 {
2196                         compatible = "arm,coresight-cti", "arm,primecell";
2197                         reg = <0x0 0x0801c000 0x0 0x1000>;
2198
2199                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2200                         clock-names = "apb_pclk";
2201
2202                         status = "disabled";
2203                 };
2204
2205                 cti13: cti@801d000 {
2206                         compatible = "arm,coresight-cti", "arm,primecell";
2207                         reg = <0x0 0x0801d000 0x0 0x1000>;
2208
2209                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2210                         clock-names = "apb_pclk";
2211
2212                         status = "disabled";
2213                 };
2214
2215                 cti14: cti@801e000 {
2216                         compatible = "arm,coresight-cti", "arm,primecell";
2217                         reg = <0x0 0x0801e000 0x0 0x1000>;
2218
2219                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2220                         clock-names = "apb_pclk";
2221
2222                         status = "disabled";
2223                 };
2224
2225                 cti15: cti@801f000 {
2226                         compatible = "arm,coresight-cti", "arm,primecell";
2227                         reg = <0x0 0x0801f000 0x0 0x1000>;
2228
2229                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2230                         clock-names = "apb_pclk";
2231
2232                         status = "disabled";
2233                 };
2234
2235                 replicator@8046000 {
2236                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2237                         reg = <0x0 0x08046000 0x0 0x1000>;
2238
2239                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2240                         clock-names = "apb_pclk";
2241
2242                         status = "disabled";
2243
2244                         out-ports {
2245                                 port {
2246                                         replicator_out: endpoint {
2247                                                 remote-endpoint = <&etr_in>;
2248                                         };
2249                                 };
2250                         };
2251
2252                         in-ports {
2253                                 port {
2254                                         replicator_in: endpoint {
2255                                                 remote-endpoint = <&etf_out>;
2256                                         };
2257                                 };
2258                         };
2259                 };
2260
2261                 etf@8047000 {
2262                         compatible = "arm,coresight-tmc", "arm,primecell";
2263                         reg = <0x0 0x08047000 0x0 0x1000>;
2264
2265                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2266                         clock-names = "apb_pclk";
2267
2268                         status = "disabled";
2269
2270                         in-ports {
2271                                 port {
2272                                         etf_in: endpoint {
2273                                                 remote-endpoint = <&merge_funnel_out>;
2274                                         };
2275                                 };
2276                         };
2277
2278                         out-ports {
2279                                 port {
2280                                         etf_out: endpoint {
2281                                                 remote-endpoint = <&replicator_in>;
2282                                         };
2283                                 };
2284                         };
2285                 };
2286
2287                 etr@8048000 {
2288                         compatible = "arm,coresight-tmc", "arm,primecell";
2289                         reg = <0x0 0x08048000 0x0 0x1000>;
2290
2291                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2292                         clock-names = "apb_pclk";
2293
2294                         status = "disabled";
2295
2296                         in-ports {
2297                                 port {
2298                                         etr_in: endpoint {
2299                                                 remote-endpoint = <&replicator_out>;
2300                                         };
2301                                 };
2302                         };
2303                 };
2304
2305                 funnel@8041000 {
2306                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2307                         reg = <0x0 0x08041000 0x0 0x1000>;
2308
2309                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2310                         clock-names = "apb_pclk";
2311
2312                         status = "disabled";
2313
2314                         out-ports {
2315                                 port {
2316                                         funnel_in0_out: endpoint {
2317                                                 remote-endpoint = <&merge_funnel_in0>;
2318                                         };
2319                                 };
2320                         };
2321
2322                         in-ports {
2323                                 port {
2324                                         funnel_in0_in: endpoint {
2325                                                 remote-endpoint = <&stm_out>;
2326                                         };
2327                                 };
2328                         };
2329                 };
2330
2331                 funnel@8042000 {
2332                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2333                         reg = <0x0 0x08042000 0x0 0x1000>;
2334
2335                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2336                         clock-names = "apb_pclk";
2337
2338                         status = "disabled";
2339
2340                         out-ports {
2341                                 port {
2342                                         funnel_in1_out: endpoint {
2343                                                 remote-endpoint = <&merge_funnel_in1>;
2344                                         };
2345                                 };
2346                         };
2347
2348                         in-ports {
2349                                 port {
2350                                         funnel_in1_in: endpoint {
2351                                                 remote-endpoint = <&funnel_apss1_out>;
2352                                         };
2353                                 };
2354                         };
2355                 };
2356
2357                 funnel@8045000 {
2358                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2359                         reg = <0x0 0x08045000 0x0 0x1000>;
2360
2361                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2362                         clock-names = "apb_pclk";
2363
2364                         status = "disabled";
2365
2366                         out-ports {
2367                                 port {
2368                                         merge_funnel_out: endpoint {
2369                                                 remote-endpoint = <&etf_in>;
2370                                         };
2371                                 };
2372                         };
2373
2374                         in-ports {
2375                                 #address-cells = <1>;
2376                                 #size-cells = <0>;
2377
2378                                 port@0 {
2379                                         reg = <0>;
2380                                         merge_funnel_in0: endpoint {
2381                                                 remote-endpoint = <&funnel_in0_out>;
2382                                         };
2383                                 };
2384
2385                                 port@1 {
2386                                         reg = <1>;
2387                                         merge_funnel_in1: endpoint {
2388                                                 remote-endpoint = <&funnel_in1_out>;
2389                                         };
2390                                 };
2391                         };
2392                 };
2393
2394                 etm@9040000 {
2395                         compatible = "arm,coresight-etm4x", "arm,primecell";
2396                         reg = <0x0 0x09040000 0x0 0x1000>;
2397
2398                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2399                         clock-names = "apb_pclk";
2400                         arm,coresight-loses-context-with-cpu;
2401
2402                         cpu = <&CPU0>;
2403
2404                         status = "disabled";
2405
2406                         out-ports {
2407                                 port {
2408                                         etm0_out: endpoint {
2409                                                 remote-endpoint = <&funnel_apss0_in0>;
2410                                         };
2411                                 };
2412                         };
2413                 };
2414
2415                 etm@9140000 {
2416                         compatible = "arm,coresight-etm4x", "arm,primecell";
2417                         reg = <0x0 0x09140000 0x0 0x1000>;
2418
2419                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2420                         clock-names = "apb_pclk";
2421                         arm,coresight-loses-context-with-cpu;
2422
2423                         cpu = <&CPU1>;
2424
2425                         status = "disabled";
2426
2427                         out-ports {
2428                                 port {
2429                                         etm1_out: endpoint {
2430                                                 remote-endpoint = <&funnel_apss0_in1>;
2431                                         };
2432                                 };
2433                         };
2434                 };
2435
2436                 etm@9240000 {
2437                         compatible = "arm,coresight-etm4x", "arm,primecell";
2438                         reg = <0x0 0x09240000 0x0 0x1000>;
2439
2440                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2441                         clock-names = "apb_pclk";
2442                         arm,coresight-loses-context-with-cpu;
2443
2444                         cpu = <&CPU2>;
2445
2446                         status = "disabled";
2447
2448                         out-ports {
2449                                 port {
2450                                         etm2_out: endpoint {
2451                                                 remote-endpoint = <&funnel_apss0_in2>;
2452                                         };
2453                                 };
2454                         };
2455                 };
2456
2457                 etm@9340000 {
2458                         compatible = "arm,coresight-etm4x", "arm,primecell";
2459                         reg = <0x0 0x09340000 0x0 0x1000>;
2460
2461                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2462                         clock-names = "apb_pclk";
2463                         arm,coresight-loses-context-with-cpu;
2464
2465                         cpu = <&CPU3>;
2466
2467                         status = "disabled";
2468
2469                         out-ports {
2470                                 port {
2471                                         etm3_out: endpoint {
2472                                                 remote-endpoint = <&funnel_apss0_in3>;
2473                                         };
2474                                 };
2475                         };
2476                 };
2477
2478                 etm@9440000 {
2479                         compatible = "arm,coresight-etm4x", "arm,primecell";
2480                         reg = <0x0 0x09440000 0x0 0x1000>;
2481
2482                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2483                         clock-names = "apb_pclk";
2484                         arm,coresight-loses-context-with-cpu;
2485
2486                         cpu = <&CPU4>;
2487
2488                         status = "disabled";
2489
2490                         out-ports {
2491                                 port {
2492                                         etm4_out: endpoint {
2493                                                 remote-endpoint = <&funnel_apss0_in4>;
2494                                         };
2495                                 };
2496                         };
2497                 };
2498
2499                 etm@9540000 {
2500                         compatible = "arm,coresight-etm4x", "arm,primecell";
2501                         reg = <0x0 0x09540000 0x0 0x1000>;
2502
2503                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2504                         clock-names = "apb_pclk";
2505                         arm,coresight-loses-context-with-cpu;
2506
2507                         cpu = <&CPU5>;
2508
2509                         status = "disabled";
2510
2511                         out-ports {
2512                                 port {
2513                                         etm5_out: endpoint {
2514                                                 remote-endpoint = <&funnel_apss0_in5>;
2515                                         };
2516                                 };
2517                         };
2518                 };
2519
2520                 etm@9640000 {
2521                         compatible = "arm,coresight-etm4x", "arm,primecell";
2522                         reg = <0x0 0x09640000 0x0 0x1000>;
2523
2524                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2525                         clock-names = "apb_pclk";
2526                         arm,coresight-loses-context-with-cpu;
2527
2528                         cpu = <&CPU6>;
2529
2530                         status = "disabled";
2531
2532                         out-ports {
2533                                 port {
2534                                         etm6_out: endpoint {
2535                                                 remote-endpoint = <&funnel_apss0_in6>;
2536                                         };
2537                                 };
2538                         };
2539                 };
2540
2541                 etm@9740000 {
2542                         compatible = "arm,coresight-etm4x", "arm,primecell";
2543                         reg = <0x0 0x09740000 0x0 0x1000>;
2544
2545                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2546                         clock-names = "apb_pclk";
2547                         arm,coresight-loses-context-with-cpu;
2548
2549                         cpu = <&CPU7>;
2550
2551                         status = "disabled";
2552
2553                         out-ports {
2554                                 port {
2555                                         etm7_out: endpoint {
2556                                                 remote-endpoint = <&funnel_apss0_in7>;
2557                                         };
2558                                 };
2559                         };
2560                 };
2561
2562                 funnel@9800000 {
2563                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2564                         reg = <0x0 0x09800000 0x0 0x1000>;
2565
2566                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2567                         clock-names = "apb_pclk";
2568
2569                         status = "disabled";
2570
2571                         out-ports {
2572                                 port {
2573                                         funnel_apss0_out: endpoint {
2574                                                 remote-endpoint = <&funnel_apss1_in>;
2575                                         };
2576                                 };
2577                         };
2578
2579                         in-ports {
2580                                 #address-cells = <1>;
2581                                 #size-cells = <0>;
2582
2583                                 port@0 {
2584                                         reg = <0>;
2585                                         funnel_apss0_in0: endpoint {
2586                                                 remote-endpoint = <&etm0_out>;
2587                                         };
2588                                 };
2589
2590                                 port@1 {
2591                                         reg = <1>;
2592                                         funnel_apss0_in1: endpoint {
2593                                                 remote-endpoint = <&etm1_out>;
2594                                         };
2595                                 };
2596
2597                                 port@2 {
2598                                         reg = <2>;
2599                                         funnel_apss0_in2: endpoint {
2600                                                 remote-endpoint = <&etm2_out>;
2601                                         };
2602                                 };
2603
2604                                 port@3 {
2605                                         reg = <3>;
2606                                         funnel_apss0_in3: endpoint {
2607                                                 remote-endpoint = <&etm3_out>;
2608                                         };
2609                                 };
2610
2611                                 port@4 {
2612                                         reg = <4>;
2613                                         funnel_apss0_in4: endpoint {
2614                                                 remote-endpoint = <&etm4_out>;
2615                                         };
2616                                 };
2617
2618                                 port@5 {
2619                                         reg = <5>;
2620                                         funnel_apss0_in5: endpoint {
2621                                                 remote-endpoint = <&etm5_out>;
2622                                         };
2623                                 };
2624
2625                                 port@6 {
2626                                         reg = <6>;
2627                                         funnel_apss0_in6: endpoint {
2628                                                 remote-endpoint = <&etm6_out>;
2629                                         };
2630                                 };
2631
2632                                 port@7 {
2633                                         reg = <7>;
2634                                         funnel_apss0_in7: endpoint {
2635                                                 remote-endpoint = <&etm7_out>;
2636                                         };
2637                                 };
2638                         };
2639                 };
2640
2641                 funnel@9810000 {
2642                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643                         reg = <0x0 0x09810000 0x0 0x1000>;
2644
2645                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2646                         clock-names = "apb_pclk";
2647
2648                         status = "disabled";
2649
2650                         out-ports {
2651                                 port {
2652                                         funnel_apss1_out: endpoint {
2653                                                 remote-endpoint = <&funnel_in1_in>;
2654                                         };
2655                                 };
2656                         };
2657
2658                         in-ports {
2659                                 port {
2660                                         funnel_apss1_in: endpoint {
2661                                                 remote-endpoint = <&funnel_apss0_out>;
2662                                         };
2663                                 };
2664                         };
2665                 };
2666
2667                 remoteproc_adsp: remoteproc@ab00000 {
2668                         compatible = "qcom,sm6115-adsp-pas";
2669                         reg = <0x0 0x0ab00000 0x0 0x100>;
2670
2671                         interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2672                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2673                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2674                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2675                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2676                         interrupt-names = "wdog", "fatal", "ready",
2677                                           "handover", "stop-ack";
2678
2679                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2680                         clock-names = "xo";
2681
2682                         power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2683                                         <&rpmpd SM6115_VDD_LPI_MX>;
2684
2685                         memory-region = <&pil_adsp_mem>;
2686
2687                         qcom,smem-states = <&adsp_smp2p_out 0>;
2688                         qcom,smem-state-names = "stop";
2689
2690                         status = "disabled";
2691
2692                         glink-edge {
2693                                 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
2694                                 label = "lpass";
2695                                 qcom,remote-pid = <2>;
2696                                 mboxes = <&apcs_glb 8>;
2697
2698                                 fastrpc {
2699                                         compatible = "qcom,fastrpc";
2700                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2701                                         label = "adsp";
2702                                         qcom,non-secure-domain;
2703                                         #address-cells = <1>;
2704                                         #size-cells = <0>;
2705
2706                                         compute-cb@3 {
2707                                                 compatible = "qcom,fastrpc-compute-cb";
2708                                                 reg = <3>;
2709                                                 iommus = <&apps_smmu 0x01c3 0x0>;
2710                                         };
2711
2712                                         compute-cb@4 {
2713                                                 compatible = "qcom,fastrpc-compute-cb";
2714                                                 reg = <4>;
2715                                                 iommus = <&apps_smmu 0x01c4 0x0>;
2716                                         };
2717
2718                                         compute-cb@5 {
2719                                                 compatible = "qcom,fastrpc-compute-cb";
2720                                                 reg = <5>;
2721                                                 iommus = <&apps_smmu 0x01c5 0x0>;
2722                                         };
2723
2724                                         compute-cb@6 {
2725                                                 compatible = "qcom,fastrpc-compute-cb";
2726                                                 reg = <6>;
2727                                                 iommus = <&apps_smmu 0x01c6 0x0>;
2728                                         };
2729
2730                                         compute-cb@7 {
2731                                                 compatible = "qcom,fastrpc-compute-cb";
2732                                                 reg = <7>;
2733                                                 iommus = <&apps_smmu 0x01c7 0x0>;
2734                                         };
2735                                 };
2736                         };
2737                 };
2738
2739                 remoteproc_cdsp: remoteproc@b300000 {
2740                         compatible = "qcom,sm6115-cdsp-pas";
2741                         reg = <0x0 0x0b300000 0x0 0x100000>;
2742
2743                         interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2744                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2745                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2746                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2747                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2748                         interrupt-names = "wdog", "fatal", "ready",
2749                                           "handover", "stop-ack";
2750
2751                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2752                         clock-names = "xo";
2753
2754                         power-domains = <&rpmpd SM6115_VDDCX>;
2755
2756                         memory-region = <&pil_cdsp_mem>;
2757
2758                         qcom,smem-states = <&cdsp_smp2p_out 0>;
2759                         qcom,smem-state-names = "stop";
2760
2761                         status = "disabled";
2762
2763                         glink-edge {
2764                                 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
2765                                 label = "cdsp";
2766                                 qcom,remote-pid = <5>;
2767                                 mboxes = <&apcs_glb 28>;
2768
2769                                 fastrpc {
2770                                         compatible = "qcom,fastrpc";
2771                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2772                                         label = "cdsp";
2773                                         qcom,non-secure-domain;
2774                                         #address-cells = <1>;
2775                                         #size-cells = <0>;
2776
2777                                         compute-cb@1 {
2778                                                 compatible = "qcom,fastrpc-compute-cb";
2779                                                 reg = <1>;
2780                                                 iommus = <&apps_smmu 0x0c01 0x0>;
2781                                         };
2782
2783                                         compute-cb@2 {
2784                                                 compatible = "qcom,fastrpc-compute-cb";
2785                                                 reg = <2>;
2786                                                 iommus = <&apps_smmu 0x0c02 0x0>;
2787                                         };
2788
2789                                         compute-cb@3 {
2790                                                 compatible = "qcom,fastrpc-compute-cb";
2791                                                 reg = <3>;
2792                                                 iommus = <&apps_smmu 0x0c03 0x0>;
2793                                         };
2794
2795                                         compute-cb@4 {
2796                                                 compatible = "qcom,fastrpc-compute-cb";
2797                                                 reg = <4>;
2798                                                 iommus = <&apps_smmu 0x0c04 0x0>;
2799                                         };
2800
2801                                         compute-cb@5 {
2802                                                 compatible = "qcom,fastrpc-compute-cb";
2803                                                 reg = <5>;
2804                                                 iommus = <&apps_smmu 0x0c05 0x0>;
2805                                         };
2806
2807                                         compute-cb@6 {
2808                                                 compatible = "qcom,fastrpc-compute-cb";
2809                                                 reg = <6>;
2810                                                 iommus = <&apps_smmu 0x0c06 0x0>;
2811                                         };
2812
2813                                         /* note: secure cb9 in downstream */
2814                                 };
2815                         };
2816                 };
2817
2818                 apps_smmu: iommu@c600000 {
2819                         compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2820                         reg = <0x0 0x0c600000 0x0 0x80000>;
2821                         #iommu-cells = <2>;
2822                         #global-interrupts = <1>;
2823
2824                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
2825                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
2826                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
2827                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
2828                                      <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
2829                                      <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
2830                                      <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
2831                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
2832                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
2833                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
2834                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2835                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2836                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2837                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2838                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2839                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2840                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2841                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2842                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2843                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2844                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2845                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2846                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2847                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2848                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2849                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2850                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2851                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2852                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2853                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2854                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2855                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2856                                      <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
2857                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
2858                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
2859                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
2860                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2861                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2862                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2863                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2864                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2865                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
2866                                      <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
2867                                      <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2868                                      <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2869                                      <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
2870                                      <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2871                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2872                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2873                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2874                                      <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
2875                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
2876                                      <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2877                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
2878                                      <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2879                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2880                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2881                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2882                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2883                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2884                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2885                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2886                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2887                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
2888                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
2889                 };
2890
2891                 wifi: wifi@c800000 {
2892                         compatible = "qcom,wcn3990-wifi";
2893                         reg = <0x0 0x0c800000 0x0 0x800000>;
2894                         reg-names = "membase";
2895                         memory-region = <&wlan_msa_mem>;
2896                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
2897                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
2898                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
2899                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
2900                                      <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
2901                                      <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
2902                                      <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
2903                                      <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
2904                                      <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
2905                                      <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
2906                                      <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
2907                                      <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
2908                         iommus = <&apps_smmu 0x1a0 0x1>;
2909                         qcom,msa-fixed-perm;
2910                         status = "disabled";
2911                 };
2912
2913                 watchdog@f017000 {
2914                         compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
2915                         reg = <0x0 0x0f017000 0x0 0x1000>;
2916                         clocks = <&sleep_clk>;
2917                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2918                 };
2919
2920                 apcs_glb: mailbox@f111000 {
2921                         compatible = "qcom,sm6115-apcs-hmss-global",
2922                                      "qcom,msm8994-apcs-kpss-global";
2923                         reg = <0x0 0x0f111000 0x0 0x1000>;
2924
2925                         #mbox-cells = <1>;
2926                 };
2927
2928                 timer@f120000 {
2929                         compatible = "arm,armv7-timer-mem";
2930                         reg = <0x0 0x0f120000 0x0 0x1000>;
2931                         #address-cells = <2>;
2932                         #size-cells = <1>;
2933                         ranges = <0x0 0x0 0x0 0x0 0x20000000>;
2934                         clock-frequency = <19200000>;
2935
2936                         frame@f121000 {
2937                                 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
2938                                 frame-number = <0>;
2939                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2940                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2941                         };
2942
2943                         frame@f123000 {
2944                                 reg = <0x0 0x0f123000 0x1000>;
2945                                 frame-number = <1>;
2946                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2947                                 status = "disabled";
2948                         };
2949
2950                         frame@f124000 {
2951                                 reg = <0x0 0x0f124000 0x1000>;
2952                                 frame-number = <2>;
2953                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2954                                 status = "disabled";
2955                         };
2956
2957                         frame@f125000 {
2958                                 reg = <0x0 0x0f125000 0x1000>;
2959                                 frame-number = <3>;
2960                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2961                                 status = "disabled";
2962                         };
2963
2964                         frame@f126000 {
2965                                 reg = <0x0 0x0f126000 0x1000>;
2966                                 frame-number = <4>;
2967                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2968                                 status = "disabled";
2969                         };
2970
2971                         frame@f127000 {
2972                                 reg = <0x0 0x0f127000 0x1000>;
2973                                 frame-number = <5>;
2974                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2975                                 status = "disabled";
2976                         };
2977
2978                         frame@f128000 {
2979                                 reg = <0x0 0x0f128000 0x1000>;
2980                                 frame-number = <6>;
2981                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2982                                 status = "disabled";
2983                         };
2984                 };
2985
2986                 intc: interrupt-controller@f200000 {
2987                         compatible = "arm,gic-v3";
2988                         reg = <0x0 0x0f200000 0x0 0x10000>,
2989                               <0x0 0x0f300000 0x0 0x100000>;
2990                         #interrupt-cells = <3>;
2991                         interrupt-controller;
2992                         interrupt-parent = <&intc>;
2993                         #redistributor-regions = <1>;
2994                         redistributor-stride = <0x0 0x20000>;
2995                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2996                 };
2997
2998                 cpufreq_hw: cpufreq@f521000 {
2999                         compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
3000                         reg = <0x0 0x0f521000 0x0 0x1000>,
3001                               <0x0 0x0f523000 0x0 0x1000>;
3002
3003                         reg-names = "freq-domain0", "freq-domain1";
3004                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
3005                         clock-names = "xo", "alternate";
3006
3007                         #freq-domain-cells = <1>;
3008                         #clock-cells = <1>;
3009                 };
3010         };
3011
3012         thermal-zones {
3013                 mapss-thermal {
3014                         polling-delay-passive = <0>;
3015                         polling-delay = <0>;
3016                         thermal-sensors = <&tsens0 0>;
3017
3018                         trips {
3019                                 trip-point0 {
3020                                         temperature = <115000>;
3021                                         hysteresis = <5000>;
3022                                         type = "passive";
3023                                 };
3024
3025                                 trip-point1 {
3026                                         temperature = <125000>;
3027                                         hysteresis = <1000>;
3028                                         type = "passive";
3029                                 };
3030                         };
3031                 };
3032
3033                 cdsp-hvx-thermal {
3034                         polling-delay-passive = <0>;
3035                         polling-delay = <0>;
3036                         thermal-sensors = <&tsens0 1>;
3037
3038                         trips {
3039                                 trip-point0 {
3040                                         temperature = <115000>;
3041                                         hysteresis = <5000>;
3042                                         type = "passive";
3043                                 };
3044
3045                                 trip-point1 {
3046                                         temperature = <125000>;
3047                                         hysteresis = <1000>;
3048                                         type = "passive";
3049                                 };
3050                         };
3051                 };
3052
3053                 wlan-thermal {
3054                         polling-delay-passive = <0>;
3055                         polling-delay = <0>;
3056                         thermal-sensors = <&tsens0 2>;
3057
3058                         trips {
3059                                 trip-point0 {
3060                                         temperature = <115000>;
3061                                         hysteresis = <5000>;
3062                                         type = "passive";
3063                                 };
3064
3065                                 trip-point1 {
3066                                         temperature = <125000>;
3067                                         hysteresis = <1000>;
3068                                         type = "passive";
3069                                 };
3070                         };
3071                 };
3072
3073                 camera-thermal {
3074                         polling-delay-passive = <0>;
3075                         polling-delay = <0>;
3076                         thermal-sensors = <&tsens0 3>;
3077
3078                         trips {
3079                                 trip-point0 {
3080                                         temperature = <115000>;
3081                                         hysteresis = <5000>;
3082                                         type = "passive";
3083                                 };
3084
3085                                 trip-point1 {
3086                                         temperature = <125000>;
3087                                         hysteresis = <1000>;
3088                                         type = "passive";
3089                                 };
3090                         };
3091                 };
3092
3093                 video-thermal {
3094                         polling-delay-passive = <0>;
3095                         polling-delay = <0>;
3096                         thermal-sensors = <&tsens0 4>;
3097
3098                         trips {
3099                                 trip-point0 {
3100                                         temperature = <115000>;
3101                                         hysteresis = <5000>;
3102                                         type = "passive";
3103                                 };
3104
3105                                 trip-point1 {
3106                                         temperature = <125000>;
3107                                         hysteresis = <1000>;
3108                                         type = "passive";
3109                                 };
3110                         };
3111                 };
3112
3113                 modem1-thermal {
3114                         polling-delay-passive = <0>;
3115                         polling-delay = <0>;
3116                         thermal-sensors = <&tsens0 5>;
3117
3118                         trips {
3119                                 trip-point0 {
3120                                         temperature = <115000>;
3121                                         hysteresis = <5000>;
3122                                         type = "passive";
3123                                 };
3124
3125                                 trip-point1 {
3126                                         temperature = <125000>;
3127                                         hysteresis = <1000>;
3128                                         type = "passive";
3129                                 };
3130                         };
3131                 };
3132
3133                 cpu4-thermal {
3134                         polling-delay-passive = <0>;
3135                         polling-delay = <0>;
3136                         thermal-sensors = <&tsens0 6>;
3137
3138                         trips {
3139                                 cpu4_alert0: trip-point0 {
3140                                         temperature = <90000>;
3141                                         hysteresis = <2000>;
3142                                         type = "passive";
3143                                 };
3144
3145                                 cpu4_alert1: trip-point1 {
3146                                         temperature = <95000>;
3147                                         hysteresis = <2000>;
3148                                         type = "passive";
3149                                 };
3150
3151                                 cpu4_crit: cpu-crit {
3152                                         temperature = <110000>;
3153                                         hysteresis = <1000>;
3154                                         type = "critical";
3155                                 };
3156                         };
3157                 };
3158
3159                 cpu5-thermal {
3160                         polling-delay-passive = <0>;
3161                         polling-delay = <0>;
3162                         thermal-sensors = <&tsens0 7>;
3163
3164                         trips {
3165                                 cpu5_alert0: trip-point0 {
3166                                         temperature = <90000>;
3167                                         hysteresis = <2000>;
3168                                         type = "passive";
3169                                 };
3170
3171                                 cpu5_alert1: trip-point1 {
3172                                         temperature = <95000>;
3173                                         hysteresis = <2000>;
3174                                         type = "passive";
3175                                 };
3176
3177                                 cpu5_crit: cpu-crit {
3178                                         temperature = <110000>;
3179                                         hysteresis = <1000>;
3180                                         type = "critical";
3181                                 };
3182                         };
3183                 };
3184
3185                 cpu6-thermal {
3186                         polling-delay-passive = <0>;
3187                         polling-delay = <0>;
3188                         thermal-sensors = <&tsens0 8>;
3189
3190                         trips {
3191                                 cpu6_alert0: trip-point0 {
3192                                         temperature = <90000>;
3193                                         hysteresis = <2000>;
3194                                         type = "passive";
3195                                 };
3196
3197                                 cpu6_alert1: trip-point1 {
3198                                         temperature = <95000>;
3199                                         hysteresis = <2000>;
3200                                         type = "passive";
3201                                 };
3202
3203                                 cpu6_crit: cpu-crit {
3204                                         temperature = <110000>;
3205                                         hysteresis = <1000>;
3206                                         type = "critical";
3207                                 };
3208                         };
3209                 };
3210
3211                 cpu7-thermal {
3212                         polling-delay-passive = <0>;
3213                         polling-delay = <0>;
3214                         thermal-sensors = <&tsens0 9>;
3215
3216                         trips {
3217                                 cpu7_alert0: trip-point0 {
3218                                         temperature = <90000>;
3219                                         hysteresis = <2000>;
3220                                         type = "passive";
3221                                 };
3222
3223                                 cpu7_alert1: trip-point1 {
3224                                         temperature = <95000>;
3225                                         hysteresis = <2000>;
3226                                         type = "passive";
3227                                 };
3228
3229                                 cpu7_crit: cpu-crit {
3230                                         temperature = <110000>;
3231                                         hysteresis = <1000>;
3232                                         type = "critical";
3233                                 };
3234                         };
3235                 };
3236
3237                 cpu45-thermal {
3238                         polling-delay-passive = <0>;
3239                         polling-delay = <0>;
3240                         thermal-sensors = <&tsens0 10>;
3241
3242                         trips {
3243                                 cpu45_alert0: trip-point0 {
3244                                         temperature = <90000>;
3245                                         hysteresis = <2000>;
3246                                         type = "passive";
3247                                 };
3248
3249                                 cpu45_alert1: trip-point1 {
3250                                         temperature = <95000>;
3251                                         hysteresis = <2000>;
3252                                         type = "passive";
3253                                 };
3254
3255                                 cpu45_crit: cpu-crit {
3256                                         temperature = <110000>;
3257                                         hysteresis = <1000>;
3258                                         type = "critical";
3259                                 };
3260                         };
3261                 };
3262
3263                 cpu67-thermal {
3264                         polling-delay-passive = <0>;
3265                         polling-delay = <0>;
3266                         thermal-sensors = <&tsens0 11>;
3267
3268                         trips {
3269                                 cpu67_alert0: trip-point0 {
3270                                         temperature = <90000>;
3271                                         hysteresis = <2000>;
3272                                         type = "passive";
3273                                 };
3274
3275                                 cpu67_alert1: trip-point1 {
3276                                         temperature = <95000>;
3277                                         hysteresis = <2000>;
3278                                         type = "passive";
3279                                 };
3280
3281                                 cpu67_crit: cpu-crit {
3282                                         temperature = <110000>;
3283                                         hysteresis = <1000>;
3284                                         type = "critical";
3285                                 };
3286                         };
3287                 };
3288
3289                 cpu0123-thermal {
3290                         polling-delay-passive = <0>;
3291                         polling-delay = <0>;
3292                         thermal-sensors = <&tsens0 12>;
3293
3294                         trips {
3295                                 cpu0123_alert0: trip-point0 {
3296                                         temperature = <90000>;
3297                                         hysteresis = <2000>;
3298                                         type = "passive";
3299                                 };
3300
3301                                 cpu0123_alert1: trip-point1 {
3302                                         temperature = <95000>;
3303                                         hysteresis = <2000>;
3304                                         type = "passive";
3305                                 };
3306
3307                                 cpu0123_crit: cpu-crit {
3308                                         temperature = <110000>;
3309                                         hysteresis = <1000>;
3310                                         type = "critical";
3311                                 };
3312                         };
3313                 };
3314
3315                 modem0-thermal {
3316                         polling-delay-passive = <0>;
3317                         polling-delay = <0>;
3318                         thermal-sensors = <&tsens0 13>;
3319
3320                         trips {
3321                                 trip-point0 {
3322                                         temperature = <115000>;
3323                                         hysteresis = <5000>;
3324                                         type = "passive";
3325                                 };
3326
3327                                 trip-point1 {
3328                                         temperature = <125000>;
3329                                         hysteresis = <1000>;
3330                                         type = "passive";
3331                                 };
3332                         };
3333                 };
3334
3335                 display-thermal {
3336                         polling-delay-passive = <0>;
3337                         polling-delay = <0>;
3338                         thermal-sensors = <&tsens0 14>;
3339
3340                         trips {
3341                                 trip-point0 {
3342                                         temperature = <115000>;
3343                                         hysteresis = <5000>;
3344                                         type = "passive";
3345                                 };
3346
3347                                 trip-point1 {
3348                                         temperature = <125000>;
3349                                         hysteresis = <1000>;
3350                                         type = "passive";
3351                                 };
3352                         };
3353                 };
3354
3355                 gpu-thermal {
3356                         polling-delay-passive = <0>;
3357                         polling-delay = <0>;
3358                         thermal-sensors = <&tsens0 15>;
3359
3360                         cooling-maps {
3361                                 map0 {
3362                                         trip = <&gpu_alert0>;
3363                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3364                                 };
3365                         };
3366
3367                         trips {
3368                                 gpu_alert0: trip-point0 {
3369                                         temperature = <115000>;
3370                                         hysteresis = <5000>;
3371                                         type = "passive";
3372                                 };
3373
3374                                 trip-point1 {
3375                                         temperature = <125000>;
3376                                         hysteresis = <1000>;
3377                                         type = "critical";
3378                                 };
3379                         };
3380                 };
3381         };
3382
3383         timer {
3384                 compatible = "arm,armv8-timer";
3385                 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3386                              <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3387                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3388                              <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3389         };
3390 };