arch/arm64/boot/dts/mediatek/mt8183.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Ben Ho <ben.ho@mediatek.com>
   5  *         Erin Lo <erin.lo@mediatek.com>
   6  */
   7
   8 #include <dt-bindings/clock/mt8183-clk.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/reset-controller/mt8183-resets.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include "mt8183-pinfunc.h"
  14
  15 / {
  16         compatible = "mediatek,mt8183";
  17         interrupt-parent = <&sysirq>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 i2c6 = &i2c6;
  29                 i2c7 = &i2c7;
  30                 i2c8 = &i2c8;
  31                 i2c9 = &i2c9;
  32                 i2c10 = &i2c10;
  33                 i2c11 = &i2c11;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu-map {
  41                         cluster0 {
  42                                 core0 {
  43                                         cpu = <&cpu0>;
  44                                 };
  45                                 core1 {
  46                                         cpu = <&cpu1>;
  47                                 };
  48                                 core2 {
  49                                         cpu = <&cpu2>;
  50                                 };
  51                                 core3 {
  52                                         cpu = <&cpu3>;
  53                                 };
  54                         };
  55
  56                         cluster1 {
  57                                 core0 {
  58                                         cpu = <&cpu4>;
  59                                 };
  60                                 core1 {
  61                                         cpu = <&cpu5>;
  62                                 };
  63                                 core2 {
  64                                         cpu = <&cpu6>;
  65                                 };
  66                                 core3 {
  67                                         cpu = <&cpu7>;
  68                                 };
  69                         };
  70                 };
  71
  72                 cpu0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53";
  75                         reg = <0x000>;
  76                         enable-method = "psci";
  77                         capacity-dmips-mhz = <741>;
  78                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
  79                         dynamic-power-coefficient = <84>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53";
  86                         reg = <0x001>;
  87                         enable-method = "psci";
  88                         capacity-dmips-mhz = <741>;
  89                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
  90                         dynamic-power-coefficient = <84>;
  91                         #cooling-cells = <2>;
  92                 };
  93
  94                 cpu2: cpu@2 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53";
  97                         reg = <0x002>;
  98                         enable-method = "psci";
  99                         capacity-dmips-mhz = <741>;
 100                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
 101                         dynamic-power-coefficient = <84>;
 102                         #cooling-cells = <2>;
 103                 };
 104
 105                 cpu3: cpu@3 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53";
 108                         reg = <0x003>;
 109                         enable-method = "psci";
 110                         capacity-dmips-mhz = <741>;
 111                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
 112                         dynamic-power-coefficient = <84>;
 113                         #cooling-cells = <2>;
 114                 };
 115
 116                 cpu4: cpu@100 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a73";
 119                         reg = <0x100>;
 120                         enable-method = "psci";
 121                         capacity-dmips-mhz = <1024>;
 122                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
 123                         dynamic-power-coefficient = <211>;
 124                         #cooling-cells = <2>;
 125                 };
 126
 127                 cpu5: cpu@101 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a73";
 130                         reg = <0x101>;
 131                         enable-method = "psci";
 132                         capacity-dmips-mhz = <1024>;
 133                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
 134                         dynamic-power-coefficient = <211>;
 135                         #cooling-cells = <2>;
 136                 };
 137
 138                 cpu6: cpu@102 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a73";
 141                         reg = <0x102>;
 142                         enable-method = "psci";
 143                         capacity-dmips-mhz = <1024>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
 145                         dynamic-power-coefficient = <211>;
 146                         #cooling-cells = <2>;
 147                 };
 148
 149                 cpu7: cpu@103 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a73";
 152                         reg = <0x103>;
 153                         enable-method = "psci";
 154                         capacity-dmips-mhz = <1024>;
 155                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
 156                         dynamic-power-coefficient = <211>;
 157                         #cooling-cells = <2>;
 158                 };
 159
 160                 idle-states {
 161                         entry-method = "psci";
 162
 163                         CPU_SLEEP: cpu-sleep {
 164                                 compatible = "arm,idle-state";
 165                                 local-timer-stop;
 166                                 arm,psci-suspend-param = <0x00010001>;
 167                                 entry-latency-us = <200>;
 168                                 exit-latency-us = <200>;
 169                                 min-residency-us = <800>;
 170                         };
 171
 172                         CLUSTER_SLEEP0: cluster-sleep-0 {
 173                                 compatible = "arm,idle-state";
 174                                 local-timer-stop;
 175                                 arm,psci-suspend-param = <0x01010001>;
 176                                 entry-latency-us = <250>;
 177                                 exit-latency-us = <400>;
 178                                 min-residency-us = <1000>;
 179                         };
 180                         CLUSTER_SLEEP1: cluster-sleep-1 {
 181                                 compatible = "arm,idle-state";
 182                                 local-timer-stop;
 183                                 arm,psci-suspend-param = <0x01010001>;
 184                                 entry-latency-us = <250>;
 185                                 exit-latency-us = <400>;
 186                                 min-residency-us = <1300>;
 187                         };
 188                 };
 189         };
 190
 191         pmu-a53 {
 192                 compatible = "arm,cortex-a53-pmu";
 193                 interrupt-parent = <&gic>;
 194                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 195         };
 196
 197         pmu-a73 {
 198                 compatible = "arm,cortex-a73-pmu";
 199                 interrupt-parent = <&gic>;
 200                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 201         };
 202
 203         psci {
 204                 compatible      = "arm,psci-1.0";
 205                 method          = "smc";
 206         };
 207
 208         clk26m: oscillator {
 209                 compatible = "fixed-clock";
 210                 #clock-cells = <0>;
 211                 clock-frequency = <26000000>;
 212                 clock-output-names = "clk26m";
 213         };
 214
 215         timer {
 216                 compatible = "arm,armv8-timer";
 217                 interrupt-parent = <&gic>;
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 222         };
 223
 224         soc {
 225                 #address-cells = <2>;
 226                 #size-cells = <2>;
 227                 compatible = "simple-bus";
 228                 ranges;
 229
 230                 soc_data: soc_data@8000000 {
 231                         compatible = "mediatek,mt8183-efuse",
 232                                      "mediatek,efuse";
 233                         reg = <0 0x08000000 0 0x0010>;
 234                         #address-cells = <1>;
 235                         #size-cells = <1>;
 236                         status = "disabled";
 237                 };
 238
 239                 gic: interrupt-controller@c000000 {
 240                         compatible = "arm,gic-v3";
 241                         #interrupt-cells = <4>;
 242                         interrupt-parent = <&gic>;
 243                         interrupt-controller;
 244                         reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 245                               <0 0x0c100000 0 0x200000>, /* GICR */
 246                               <0 0x0c400000 0 0x2000>,   /* GICC */
 247                               <0 0x0c410000 0 0x1000>,   /* GICH */
 248                               <0 0x0c420000 0 0x2000>;   /* GICV */
 249
 250                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 251                         ppi-partitions {
 252                                 ppi_cluster0: interrupt-partition-0 {
 253                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 254                                 };
 255                                 ppi_cluster1: interrupt-partition-1 {
 256                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 257                                 };
 258                         };
 259                 };
 260
 261                 mcucfg: syscon@c530000 {
 262                         compatible = "mediatek,mt8183-mcucfg", "syscon";
 263                         reg = <0 0x0c530000 0 0x1000>;
 264                         #clock-cells = <1>;
 265                 };
 266
 267                 sysirq: interrupt-controller@c530a80 {
 268                         compatible = "mediatek,mt8183-sysirq",
 269                                      "mediatek,mt6577-sysirq";
 270                         interrupt-controller;
 271                         #interrupt-cells = <3>;
 272                         interrupt-parent = <&gic>;
 273                         reg = <0 0x0c530a80 0 0x50>;
 274                 };
 275
 276                 topckgen: syscon@10000000 {
 277                         compatible = "mediatek,mt8183-topckgen", "syscon";
 278                         reg = <0 0x10000000 0 0x1000>;
 279                         #clock-cells = <1>;
 280                 };
 281
 282                 infracfg: syscon@10001000 {
 283                         compatible = "mediatek,mt8183-infracfg", "syscon";
 284                         reg = <0 0x10001000 0 0x1000>;
 285                         #clock-cells = <1>;
 286                         #reset-cells = <1>;
 287                 };
 288
 289                 pericfg: syscon@10003000 {
 290                         compatible = "mediatek,mt8183-pericfg", "syscon";
 291                         reg = <0 0x10003000 0 0x1000>;
 292                         #clock-cells = <1>;
 293                 };
 294
 295                 pio: pinctrl@10005000 {
 296                         compatible = "mediatek,mt8183-pinctrl";
 297                         reg = <0 0x10005000 0 0x1000>,
 298                               <0 0x11f20000 0 0x1000>,
 299                               <0 0x11e80000 0 0x1000>,
 300                               <0 0x11e70000 0 0x1000>,
 301                               <0 0x11e90000 0 0x1000>,
 302                               <0 0x11d30000 0 0x1000>,
 303                               <0 0x11d20000 0 0x1000>,
 304                               <0 0x11c50000 0 0x1000>,
 305                               <0 0x11f30000 0 0x1000>,
 306                               <0 0x1000b000 0 0x1000>;
 307                         reg-names = "iocfg0", "iocfg1", "iocfg2",
 308                                     "iocfg3", "iocfg4", "iocfg5",
 309                                     "iocfg6", "iocfg7", "iocfg8",
 310                                     "eint";
 311                         gpio-controller;
 312                         #gpio-cells = <2>;
 313                         gpio-ranges = <&pio 0 0 192>;
 314                         interrupt-controller;
 315                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 316                         #interrupt-cells = <2>;
 317                 };
 318
 319                 watchdog: watchdog@10007000 {
 320                         compatible = "mediatek,mt8183-wdt";
 321                         reg = <0 0x10007000 0 0x100>;
 322                         #reset-cells = <1>;
 323                 };
 324
 325                 apmixedsys: syscon@1000c000 {
 326                         compatible = "mediatek,mt8183-apmixedsys", "syscon";
 327                         reg = <0 0x1000c000 0 0x1000>;
 328                         #clock-cells = <1>;
 329                 };
 330
 331                 pwrap: pwrap@1000d000 {
 332                         compatible = "mediatek,mt8183-pwrap";
 333                         reg = <0 0x1000d000 0 0x1000>;
 334                         reg-names = "pwrap";
 335                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
 337                                  <&infracfg CLK_INFRA_PMIC_AP>;
 338                         clock-names = "spi", "wrap";
 339                 };
 340
 341                 scp: scp@10500000 {
 342                         compatible = "mediatek,mt8183-scp";
 343                         reg = <0 0x10500000 0 0x80000>,
 344                               <0 0x105c0000 0 0x19080>;
 345                         reg-names = "sram", "cfg";
 346                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 347                         clocks = <&infracfg CLK_INFRA_SCPSYS>;
 348                         clock-names = "main";
 349                         memory-region = <&scp_mem_reserved>;
 350                         status = "disabled";
 351                 };
 352
 353                 systimer: timer@10017000 {
 354                         compatible = "mediatek,mt8183-timer",
 355                                      "mediatek,mt6765-timer";
 356                         reg = <0 0x10017000 0 0x1000>;
 357                         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 358                         clocks = <&topckgen CLK_TOP_CLK13M>;
 359                         clock-names = "clk13m";
 360                 };
 361
 362                 gce: mailbox@10238000 {
 363                         compatible = "mediatek,mt8183-gce";
 364                         reg = <0 0x10238000 0 0x4000>;
 365                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
 366                         #mbox-cells = <3>;
 367                         clocks = <&infracfg CLK_INFRA_GCE>;
 368                         clock-names = "gce";
 369                 };
 370
 371                 auxadc: auxadc@11001000 {
 372                         compatible = "mediatek,mt8183-auxadc",
 373                                      "mediatek,mt8173-auxadc";
 374                         reg = <0 0x11001000 0 0x1000>;
 375                         clocks = <&infracfg CLK_INFRA_AUXADC>;
 376                         clock-names = "main";
 377                         #io-channel-cells = <1>;
 378                         status = "disabled";
 379                 };
 380
 381                 uart0: serial@11002000 {
 382                         compatible = "mediatek,mt8183-uart",
 383                                      "mediatek,mt6577-uart";
 384                         reg = <0 0x11002000 0 0x1000>;
 385                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 386                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 387                         clock-names = "baud", "bus";
 388                         status = "disabled";
 389                 };
 390
 391                 uart1: serial@11003000 {
 392                         compatible = "mediatek,mt8183-uart",
 393                                      "mediatek,mt6577-uart";
 394                         reg = <0 0x11003000 0 0x1000>;
 395                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 396                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
 397                         clock-names = "baud", "bus";
 398                         status = "disabled";
 399                 };
 400
 401                 uart2: serial@11004000 {
 402                         compatible = "mediatek,mt8183-uart",
 403                                      "mediatek,mt6577-uart";
 404                         reg = <0 0x11004000 0 0x1000>;
 405                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 406                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
 407                         clock-names = "baud", "bus";
 408                         status = "disabled";
 409                 };
 410
 411                 i2c6: i2c@11005000 {
 412                         compatible = "mediatek,mt8183-i2c";
 413                         reg = <0 0x11005000 0 0x1000>,
 414                               <0 0x11000600 0 0x80>;
 415                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 416                         clocks = <&infracfg CLK_INFRA_I2C6>,
 417                                  <&infracfg CLK_INFRA_AP_DMA>;
 418                         clock-names = "main", "dma";
 419                         clock-div = <1>;
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         status = "disabled";
 423                 };
 424
 425                 i2c0: i2c@11007000 {
 426                         compatible = "mediatek,mt8183-i2c";
 427                         reg = <0 0x11007000 0 0x1000>,
 428                               <0 0x11000080 0 0x80>;
 429                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 430                         clocks = <&infracfg CLK_INFRA_I2C0>,
 431                                  <&infracfg CLK_INFRA_AP_DMA>;
 432                         clock-names = "main", "dma";
 433                         clock-div = <1>;
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         status = "disabled";
 437                 };
 438
 439                 i2c4: i2c@11008000 {
 440                         compatible = "mediatek,mt8183-i2c";
 441                         reg = <0 0x11008000 0 0x1000>,
 442                               <0 0x11000100 0 0x80>;
 443                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 444                         clocks = <&infracfg CLK_INFRA_I2C1>,
 445                                  <&infracfg CLK_INFRA_AP_DMA>,
 446                                  <&infracfg CLK_INFRA_I2C1_ARBITER>;
 447                         clock-names = "main", "dma","arb";
 448                         clock-div = <1>;
 449                         #address-cells = <1>;
 450                         #size-cells = <0>;
 451                         status = "disabled";
 452                 };
 453
 454                 i2c2: i2c@11009000 {
 455                         compatible = "mediatek,mt8183-i2c";
 456                         reg = <0 0x11009000 0 0x1000>,
 457                               <0 0x11000280 0 0x80>;
 458                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 459                         clocks = <&infracfg CLK_INFRA_I2C2>,
 460                                  <&infracfg CLK_INFRA_AP_DMA>,
 461                                  <&infracfg CLK_INFRA_I2C2_ARBITER>;
 462                         clock-names = "main", "dma", "arb";
 463                         clock-div = <1>;
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         status = "disabled";
 467                 };
 468
 469                 spi0: spi@1100a000 {
 470                         compatible = "mediatek,mt8183-spi";
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         reg = <0 0x1100a000 0 0x1000>;
 474                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
 475                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 476                                  <&topckgen CLK_TOP_MUX_SPI>,
 477                                  <&infracfg CLK_INFRA_SPI0>;
 478                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 479                         status = "disabled";
 480                 };
 481
 482                 i2c3: i2c@1100f000 {
 483                         compatible = "mediatek,mt8183-i2c";
 484                         reg = <0 0x1100f000 0 0x1000>,
 485                               <0 0x11000400 0 0x80>;
 486                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 487                         clocks = <&infracfg CLK_INFRA_I2C3>,
 488                                  <&infracfg CLK_INFRA_AP_DMA>;
 489                         clock-names = "main", "dma";
 490                         clock-div = <1>;
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         status = "disabled";
 494                 };
 495
 496                 spi1: spi@11010000 {
 497                         compatible = "mediatek,mt8183-spi";
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         reg = <0 0x11010000 0 0x1000>;
 501                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
 502                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 503                                  <&topckgen CLK_TOP_MUX_SPI>,
 504                                  <&infracfg CLK_INFRA_SPI1>;
 505                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 506                         status = "disabled";
 507                 };
 508
 509                 i2c1: i2c@11011000 {
 510                         compatible = "mediatek,mt8183-i2c";
 511                         reg = <0 0x11011000 0 0x1000>,
 512                               <0 0x11000480 0 0x80>;
 513                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 514                         clocks = <&infracfg CLK_INFRA_I2C4>,
 515                                  <&infracfg CLK_INFRA_AP_DMA>;
 516                         clock-names = "main", "dma";
 517                         clock-div = <1>;
 518                         #address-cells = <1>;
 519                         #size-cells = <0>;
 520                         status = "disabled";
 521                 };
 522
 523                 spi2: spi@11012000 {
 524                         compatible = "mediatek,mt8183-spi";
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         reg = <0 0x11012000 0 0x1000>;
 528                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
 529                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 530                                  <&topckgen CLK_TOP_MUX_SPI>,
 531                                  <&infracfg CLK_INFRA_SPI2>;
 532                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 533                         status = "disabled";
 534                 };
 535
 536                 spi3: spi@11013000 {
 537                         compatible = "mediatek,mt8183-spi";
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         reg = <0 0x11013000 0 0x1000>;
 541                         interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
 542                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 543                                  <&topckgen CLK_TOP_MUX_SPI>,
 544                                  <&infracfg CLK_INFRA_SPI3>;
 545                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 546                         status = "disabled";
 547                 };
 548
 549                 i2c9: i2c@11014000 {
 550                         compatible = "mediatek,mt8183-i2c";
 551                         reg = <0 0x11014000 0 0x1000>,
 552                               <0 0x11000180 0 0x80>;
 553                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
 554                         clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
 555                                  <&infracfg CLK_INFRA_AP_DMA>,
 556                                  <&infracfg CLK_INFRA_I2C1_ARBITER>;
 557                         clock-names = "main", "dma", "arb";
 558                         clock-div = <1>;
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         status = "disabled";
 562                 };
 563
 564                 i2c10: i2c@11015000 {
 565                         compatible = "mediatek,mt8183-i2c";
 566                         reg = <0 0x11015000 0 0x1000>,
 567                               <0 0x11000300 0 0x80>;
 568                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 569                         clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
 570                                  <&infracfg CLK_INFRA_AP_DMA>,
 571                                  <&infracfg CLK_INFRA_I2C2_ARBITER>;
 572                         clock-names = "main", "dma", "arb";
 573                         clock-div = <1>;
 574                         #address-cells = <1>;
 575                         #size-cells = <0>;
 576                         status = "disabled";
 577                 };
 578
 579                 i2c5: i2c@11016000 {
 580                         compatible = "mediatek,mt8183-i2c";
 581                         reg = <0 0x11016000 0 0x1000>,
 582                               <0 0x11000500 0 0x80>;
 583                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 584                         clocks = <&infracfg CLK_INFRA_I2C5>,
 585                                  <&infracfg CLK_INFRA_AP_DMA>,
 586                                  <&infracfg CLK_INFRA_I2C5_ARBITER>;
 587                         clock-names = "main", "dma", "arb";
 588                         clock-div = <1>;
 589                         #address-cells = <1>;
 590                         #size-cells = <0>;
 591                         status = "disabled";
 592                 };
 593
 594                 i2c11: i2c@11017000 {
 595                         compatible = "mediatek,mt8183-i2c";
 596                         reg = <0 0x11017000 0 0x1000>,
 597                               <0 0x11000580 0 0x80>;
 598                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
 599                         clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
 600                                  <&infracfg CLK_INFRA_AP_DMA>,
 601                                  <&infracfg CLK_INFRA_I2C5_ARBITER>;
 602                         clock-names = "main", "dma", "arb";
 603                         clock-div = <1>;
 604                         #address-cells = <1>;
 605                         #size-cells = <0>;
 606                         status = "disabled";
 607                 };
 608
 609                 spi4: spi@11018000 {
 610                         compatible = "mediatek,mt8183-spi";
 611                         #address-cells = <1>;
 612                         #size-cells = <0>;
 613                         reg = <0 0x11018000 0 0x1000>;
 614                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
 615                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 616                                  <&topckgen CLK_TOP_MUX_SPI>,
 617                                  <&infracfg CLK_INFRA_SPI4>;
 618                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 619                         status = "disabled";
 620                 };
 621
 622                 spi5: spi@11019000 {
 623                         compatible = "mediatek,mt8183-spi";
 624                         #address-cells = <1>;
 625                         #size-cells = <0>;
 626                         reg = <0 0x11019000 0 0x1000>;
 627                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
 628                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 629                                  <&topckgen CLK_TOP_MUX_SPI>,
 630                                  <&infracfg CLK_INFRA_SPI5>;
 631                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 632                         status = "disabled";
 633                 };
 634
 635                 i2c7: i2c@1101a000 {
 636                         compatible = "mediatek,mt8183-i2c";
 637                         reg = <0 0x1101a000 0 0x1000>,
 638                               <0 0x11000680 0 0x80>;
 639                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
 640                         clocks = <&infracfg CLK_INFRA_I2C7>,
 641                                  <&infracfg CLK_INFRA_AP_DMA>;
 642                         clock-names = "main", "dma";
 643                         clock-div = <1>;
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                         status = "disabled";
 647                 };
 648
 649                 i2c8: i2c@1101b000 {
 650                         compatible = "mediatek,mt8183-i2c";
 651                         reg = <0 0x1101b000 0 0x1000>,
 652                               <0 0x11000700 0 0x80>;
 653                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
 654                         clocks = <&infracfg CLK_INFRA_I2C8>,
 655                                  <&infracfg CLK_INFRA_AP_DMA>;
 656                         clock-names = "main", "dma";
 657                         clock-div = <1>;
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                         status = "disabled";
 661                 };
 662
 663                 ssusb: usb@11201000 {
 664                         compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
 665                         reg = <0 0x11201000 0 0x2e00>,
 666                               <0 0x11203e00 0 0x0100>;
 667                         reg-names = "mac", "ippc";
 668                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 669                         phys = <&u2port0 PHY_TYPE_USB2>,
 670                                <&u3port0 PHY_TYPE_USB3>;
 671                         clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
 672                                  <&infracfg CLK_INFRA_USB>;
 673                         clock-names = "sys_ck", "ref_ck";
 674                         mediatek,syscon-wakeup = <&pericfg 0x400 0>;
 675                         #address-cells = <2>;
 676                         #size-cells = <2>;
 677                         ranges;
 678                         status = "disabled";
 679
 680                         usb_host: xhci@11200000 {
 681                                 compatible = "mediatek,mt8183-xhci",
 682                                              "mediatek,mtk-xhci";
 683                                 reg = <0 0x11200000 0 0x1000>;
 684                                 reg-names = "mac";
 685                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 686                                 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
 687                                          <&infracfg CLK_INFRA_USB>;
 688                                 clock-names = "sys_ck", "ref_ck";
 689                                 status = "disabled";
 690                         };
 691                 };
 692
 693                 audiosys: syscon@11220000 {
 694                         compatible = "mediatek,mt8183-audiosys", "syscon";
 695                         reg = <0 0x11220000 0 0x1000>;
 696                         #clock-cells = <1>;
 697                 };
 698
 699                 mmc0: mmc@11230000 {
 700                         compatible = "mediatek,mt8183-mmc";
 701                         reg = <0 0x11230000 0 0x1000>,
 702                               <0 0x11f50000 0 0x1000>;
 703                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 704                         clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
 705                                  <&infracfg CLK_INFRA_MSDC0>,
 706                                  <&infracfg CLK_INFRA_MSDC0_SCK>;
 707                         clock-names = "source", "hclk", "source_cg";
 708                         status = "disabled";
 709                 };
 710
 711                 mmc1: mmc@11240000 {
 712                         compatible = "mediatek,mt8183-mmc";
 713                         reg = <0 0x11240000 0 0x1000>,
 714                               <0 0x11e10000 0 0x1000>;
 715                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 716                         clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
 717                                  <&infracfg CLK_INFRA_MSDC1>,
 718                                  <&infracfg CLK_INFRA_MSDC1_SCK>;
 719                         clock-names = "source", "hclk", "source_cg";
 720                         status = "disabled";
 721                 };
 722
 723                 efuse: efuse@11f10000 {
 724                         compatible = "mediatek,mt8183-efuse",
 725                                      "mediatek,efuse";
 726                         reg = <0 0x11f10000 0 0x1000>;
 727                 };
 728
 729                 u3phy: usb-phy@11f40000 {
 730                         compatible = "mediatek,mt8183-tphy",
 731                                      "mediatek,generic-tphy-v2";
 732                         #address-cells = <1>;
 733                         #phy-cells = <1>;
 734                         #size-cells = <1>;
 735                         ranges = <0 0 0x11f40000 0x1000>;
 736                         status = "okay";
 737
 738                         u2port0: usb-phy@0 {
 739                                 reg = <0x0 0x700>;
 740                                 clocks = <&clk26m>;
 741                                 clock-names = "ref";
 742                                 #phy-cells = <1>;
 743                                 mediatek,discth = <15>;
 744                                 status = "okay";
 745                         };
 746
 747                         u3port0: usb-phy@0700 {
 748                                 reg = <0x0700 0x900>;
 749                                 clocks = <&clk26m>;
 750                                 clock-names = "ref";
 751                                 #phy-cells = <1>;
 752                                 status = "okay";
 753                         };
 754                 };
 755
 756                 mfgcfg: syscon@13000000 {
 757                         compatible = "mediatek,mt8183-mfgcfg", "syscon";
 758                         reg = <0 0x13000000 0 0x1000>;
 759                         #clock-cells = <1>;
 760                 };
 761
 762                 mmsys: syscon@14000000 {
 763                         compatible = "mediatek,mt8183-mmsys", "syscon";
 764                         reg = <0 0x14000000 0 0x1000>;
 765                         #clock-cells = <1>;
 766                 };
 767
 768                 imgsys: syscon@15020000 {
 769                         compatible = "mediatek,mt8183-imgsys", "syscon";
 770                         reg = <0 0x15020000 0 0x1000>;
 771                         #clock-cells = <1>;
 772                 };
 773
 774                 vdecsys: syscon@16000000 {
 775                         compatible = "mediatek,mt8183-vdecsys", "syscon";
 776                         reg = <0 0x16000000 0 0x1000>;
 777                         #clock-cells = <1>;
 778                 };
 779
 780                 vencsys: syscon@17000000 {
 781                         compatible = "mediatek,mt8183-vencsys", "syscon";
 782                         reg = <0 0x17000000 0 0x1000>;
 783                         #clock-cells = <1>;
 784                 };
 785
 786                 ipu_conn: syscon@19000000 {
 787                         compatible = "mediatek,mt8183-ipu_conn", "syscon";
 788                         reg = <0 0x19000000 0 0x1000>;
 789                         #clock-cells = <1>;
 790                 };
 791
 792                 ipu_adl: syscon@19010000 {
 793                         compatible = "mediatek,mt8183-ipu_adl", "syscon";
 794                         reg = <0 0x19010000 0 0x1000>;
 795                         #clock-cells = <1>;
 796                 };
 797
 798                 ipu_core0: syscon@19180000 {
 799                         compatible = "mediatek,mt8183-ipu_core0", "syscon";
 800                         reg = <0 0x19180000 0 0x1000>;
 801                         #clock-cells = <1>;
 802                 };
 803
 804                 ipu_core1: syscon@19280000 {
 805                         compatible = "mediatek,mt8183-ipu_core1", "syscon";
 806                         reg = <0 0x19280000 0 0x1000>;
 807                         #clock-cells = <1>;
 808                 };
 809
 810                 camsys: syscon@1a000000 {
 811                         compatible = "mediatek,mt8183-camsys", "syscon";
 812                         reg = <0 0x1a000000 0 0x1000>;
 813                         #clock-cells = <1>;
 814                 };
 815         };
 816 };