arch/arm64/boot/dts/hisilicon/hi6220.dtsi

   1 /*
   2  * dts file for Hisilicon Hi6220 SoC
   3  *
   4  * Copyright (C) 2015, Hisilicon Ltd.
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/reset/hisi,hi6220-resets.h>
   9 #include <dt-bindings/clock/hi6220-clock.h>
  10 #include <dt-bindings/pinctrl/hisi.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "hisilicon,hi6220";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         psci {
  20                 compatible = "arm,psci-0.2";
  21                 method = "smc";
  22         };
  23
  24         cpus {
  25                 #address-cells = <2>;
  26                 #size-cells = <0>;
  27
  28                 cpu-map {
  29                         cluster0 {
  30                                 core0 {
  31                                         cpu = <&cpu0>;
  32                                 };
  33                                 core1 {
  34                                         cpu = <&cpu1>;
  35                                 };
  36                                 core2 {
  37                                         cpu = <&cpu2>;
  38                                 };
  39                                 core3 {
  40                                         cpu = <&cpu3>;
  41                                 };
  42                         };
  43                         cluster1 {
  44                                 core0 {
  45                                         cpu = <&cpu4>;
  46                                 };
  47                                 core1 {
  48                                         cpu = <&cpu5>;
  49                                 };
  50                                 core2 {
  51                                         cpu = <&cpu6>;
  52                                 };
  53                                 core3 {
  54                                         cpu = <&cpu7>;
  55                                 };
  56                         };
  57                 };
  58
  59                 idle-states {
  60                         entry-method = "psci";
  61
  62                         CPU_SLEEP: cpu-sleep {
  63                                 compatible = "arm,idle-state";
  64                                 local-timer-stop;
  65                                 arm,psci-suspend-param = <0x0010000>;
  66                                 entry-latency-us = <700>;
  67                                 exit-latency-us = <250>;
  68                                 min-residency-us = <1000>;
  69                         };
  70
  71                         CLUSTER_SLEEP: cluster-sleep {
  72                                 compatible = "arm,idle-state";
  73                                 local-timer-stop;
  74                                 arm,psci-suspend-param = <0x1010000>;
  75                                 entry-latency-us = <1000>;
  76                                 exit-latency-us = <700>;
  77                                 min-residency-us = <2700>;
  78                                 wakeup-latency-us = <1500>;
  79                         };
  80                 };
  81
  82                 cpu0: cpu@0 {
  83                         compatible = "arm,cortex-a53", "arm,armv8";
  84                         device_type = "cpu";
  85                         reg = <0x0 0x0>;
  86                         enable-method = "psci";
  87                         next-level-cache = <&CLUSTER0_L2>;
  88                         clocks = <&stub_clock 0>;
  89                         operating-points-v2 = <&cpu_opp_table>;
  90                         cooling-min-level = <4>;
  91                         cooling-max-level = <0>;
  92                         #cooling-cells = <2>; /* min followed by max */
  93                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  94                         dynamic-power-coefficient = <311>;
  95                 };
  96
  97                 cpu1: cpu@1 {
  98                         compatible = "arm,cortex-a53", "arm,armv8";
  99                         device_type = "cpu";
 100                         reg = <0x0 0x1>;
 101                         enable-method = "psci";
 102                         next-level-cache = <&CLUSTER0_L2>;
 103                         operating-points-v2 = <&cpu_opp_table>;
 104                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 105                 };
 106
 107                 cpu2: cpu@2 {
 108                         compatible = "arm,cortex-a53", "arm,armv8";
 109                         device_type = "cpu";
 110                         reg = <0x0 0x2>;
 111                         enable-method = "psci";
 112                         next-level-cache = <&CLUSTER0_L2>;
 113                         operating-points-v2 = <&cpu_opp_table>;
 114                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 115                 };
 116
 117                 cpu3: cpu@3 {
 118                         compatible = "arm,cortex-a53", "arm,armv8";
 119                         device_type = "cpu";
 120                         reg = <0x0 0x3>;
 121                         enable-method = "psci";
 122                         next-level-cache = <&CLUSTER0_L2>;
 123                         operating-points-v2 = <&cpu_opp_table>;
 124                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 125                 };
 126
 127                 cpu4: cpu@100 {
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         device_type = "cpu";
 130                         reg = <0x0 0x100>;
 131                         enable-method = "psci";
 132                         next-level-cache = <&CLUSTER1_L2>;
 133                         operating-points-v2 = <&cpu_opp_table>;
 134                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 135                 };
 136
 137                 cpu5: cpu@101 {
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         device_type = "cpu";
 140                         reg = <0x0 0x101>;
 141                         enable-method = "psci";
 142                         next-level-cache = <&CLUSTER1_L2>;
 143                         operating-points-v2 = <&cpu_opp_table>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 145                 };
 146
 147                 cpu6: cpu@102 {
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         device_type = "cpu";
 150                         reg = <0x0 0x102>;
 151                         enable-method = "psci";
 152                         next-level-cache = <&CLUSTER1_L2>;
 153                         operating-points-v2 = <&cpu_opp_table>;
 154                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 155                 };
 156
 157                 cpu7: cpu@103 {
 158                         compatible = "arm,cortex-a53", "arm,armv8";
 159                         device_type = "cpu";
 160                         reg = <0x0 0x103>;
 161                         enable-method = "psci";
 162                         next-level-cache = <&CLUSTER1_L2>;
 163                         operating-points-v2 = <&cpu_opp_table>;
 164                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 165                 };
 166
 167                 CLUSTER0_L2: l2-cache0 {
 168                         compatible = "cache";
 169                 };
 170
 171                 CLUSTER1_L2: l2-cache1 {
 172                         compatible = "cache";
 173                 };
 174         };
 175
 176         cpu_opp_table: cpu_opp_table {
 177                 compatible = "operating-points-v2";
 178                 opp-shared;
 179
 180                 opp00 {
 181                         opp-hz = /bits/ 64 <208000000>;
 182                         opp-microvolt = <1040000>;
 183                         clock-latency-ns = <500000>;
 184                 };
 185                 opp01 {
 186                         opp-hz = /bits/ 64 <432000000>;
 187                         opp-microvolt = <1040000>;
 188                         clock-latency-ns = <500000>;
 189                 };
 190                 opp02 {
 191                         opp-hz = /bits/ 64 <729000000>;
 192                         opp-microvolt = <1090000>;
 193                         clock-latency-ns = <500000>;
 194                 };
 195                 opp03 {
 196                         opp-hz = /bits/ 64 <960000000>;
 197                         opp-microvolt = <1180000>;
 198                         clock-latency-ns = <500000>;
 199                 };
 200                 opp04 {
 201                         opp-hz = /bits/ 64 <1200000000>;
 202                         opp-microvolt = <1330000>;
 203                         clock-latency-ns = <500000>;
 204                 };
 205         };
 206
 207         gic: interrupt-controller@f6801000 {
 208                 compatible = "arm,gic-400";
 209                 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
 210                       <0x0 0xf6802000 0 0x2000>, /* GICC */
 211                       <0x0 0xf6804000 0 0x2000>, /* GICH */
 212                       <0x0 0xf6806000 0 0x2000>; /* GICV */
 213                 #address-cells = <0>;
 214                 #interrupt-cells = <3>;
 215                 interrupt-controller;
 216                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 217         };
 218
 219         timer {
 220                 compatible = "arm,armv8-timer";
 221                 interrupt-parent = <&gic>;
 222                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 223                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 224                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 225                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 226         };
 227
 228         soc {
 229                 compatible = "simple-bus";
 230                 #address-cells = <2>;
 231                 #size-cells = <2>;
 232                 ranges;
 233
 234                 sram: sram@fff80000 {
 235                         compatible = "hisilicon,hi6220-sramctrl", "syscon";
 236                         reg = <0x0 0xfff80000 0x0 0x12000>;
 237                 };
 238
 239                 ao_ctrl: ao_ctrl@f7800000 {
 240                         compatible = "hisilicon,hi6220-aoctrl", "syscon";
 241                         reg = <0x0 0xf7800000 0x0 0x2000>;
 242                         #clock-cells = <1>;
 243                 };
 244
 245                 sys_ctrl: sys_ctrl@f7030000 {
 246                         compatible = "hisilicon,hi6220-sysctrl", "syscon";
 247                         reg = <0x0 0xf7030000 0x0 0x2000>;
 248                         #clock-cells = <1>;
 249                         #reset-cells = <1>;
 250                 };
 251
 252                 media_ctrl: media_ctrl@f4410000 {
 253                         compatible = "hisilicon,hi6220-mediactrl", "syscon";
 254                         reg = <0x0 0xf4410000 0x0 0x1000>;
 255                         #clock-cells = <1>;
 256                         #reset-cells = <1>;
 257                 };
 258
 259                 pm_ctrl: pm_ctrl@f7032000 {
 260                         compatible = "hisilicon,hi6220-pmctrl", "syscon";
 261                         reg = <0x0 0xf7032000 0x0 0x1000>;
 262                         #clock-cells = <1>;
 263                 };
 264
 265                 acpu_sctrl: acpu_sctrl@f6504000 {
 266                         compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
 267                         reg = <0x0 0xf6504000 0x0 0x1000>;
 268                         #clock-cells = <1>;
 269                 };
 270
 271                 medianoc_ade: medianoc_ade@f4520000 {
 272                         compatible = "syscon";
 273                         reg = <0x0 0xf4520000 0x0 0x4000>;
 274                 };
 275
 276                 stub_clock: stub_clock {
 277                         compatible = "hisilicon,hi6220-stub-clk";
 278                         hisilicon,hi6220-clk-sram = <&sram>;
 279                         #clock-cells = <1>;
 280                         mbox-names = "mbox-tx";
 281                         mboxes = <&mailbox 1 0 11>;
 282                 };
 283
 284                 uart0: uart@f8015000 {  /* console */
 285                         compatible = "arm,pl011", "arm,primecell";
 286                         reg = <0x0 0xf8015000 0x0 0x1000>;
 287                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 289                                  <&ao_ctrl HI6220_UART0_PCLK>;
 290                         clock-names = "uartclk", "apb_pclk";
 291                 };
 292
 293                 uart1: uart@f7111000 {
 294                         compatible = "arm,pl011", "arm,primecell";
 295                         reg = <0x0 0xf7111000 0x0 0x1000>;
 296                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 297                         clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 298                                  <&sys_ctrl HI6220_UART1_PCLK>;
 299                         clock-names = "uartclk", "apb_pclk";
 300                         pinctrl-names = "default";
 301                         pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
 302                         status = "disabled";
 303                 };
 304
 305                 uart2: uart@f7112000 {
 306                         compatible = "arm,pl011", "arm,primecell";
 307                         reg = <0x0 0xf7112000 0x0 0x1000>;
 308                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 309                         clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 310                                  <&sys_ctrl HI6220_UART2_PCLK>;
 311                         clock-names = "uartclk", "apb_pclk";
 312                         pinctrl-names = "default";
 313                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 314                         status = "disabled";
 315                 };
 316
 317                 uart3: uart@f7113000 {
 318                         compatible = "arm,pl011", "arm,primecell";
 319                         reg = <0x0 0xf7113000 0x0 0x1000>;
 320                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 321                         clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 322                                  <&sys_ctrl HI6220_UART3_PCLK>;
 323                         clock-names = "uartclk", "apb_pclk";
 324                         pinctrl-names = "default";
 325                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 326                         status = "disabled";
 327                 };
 328
 329                 uart4: uart@f7114000 {
 330                         compatible = "arm,pl011", "arm,primecell";
 331                         reg = <0x0 0xf7114000 0x0 0x1000>;
 332                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 334                                  <&sys_ctrl HI6220_UART4_PCLK>;
 335                         clock-names = "uartclk", "apb_pclk";
 336                         pinctrl-names = "default";
 337                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 338                         status = "disabled";
 339                 };
 340
 341                 dma0: dma@f7370000 {
 342                         compatible = "hisilicon,k3-dma-1.0";
 343                         reg = <0x0 0xf7370000 0x0 0x1000>;
 344                         #dma-cells = <1>;
 345                         dma-channels = <15>;
 346                         dma-requests = <32>;
 347                         interrupts = <0 84 4>;
 348                         clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
 349                         dma-no-cci;
 350                         dma-type = "hi6220_dma";
 351                         status = "ok";
 352                 };
 353
 354                 dual_timer0: timer@f8008000 {
 355                         compatible = "arm,sp804", "arm,primecell";
 356                         reg = <0x0 0xf8008000 0x0 0x1000>;
 357                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 358                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 359                         clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
 360                                  <&ao_ctrl HI6220_TIMER0_PCLK>,
 361                                  <&ao_ctrl HI6220_TIMER0_PCLK>;
 362                         clock-names = "timer1", "timer2", "apb_pclk";
 363                 };
 364
 365                 rtc0: rtc@f8003000 {
 366                         compatible = "arm,pl031", "arm,primecell";
 367                         reg = <0x0 0xf8003000 0x0 0x1000>;
 368                         interrupts = <0 12 4>;
 369                         clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
 370                         clock-names = "apb_pclk";
 371                 };
 372
 373                 rtc1: rtc@f8004000 {
 374                         compatible = "arm,pl031", "arm,primecell";
 375                         reg = <0x0 0xf8004000 0x0 0x1000>;
 376                         interrupts = <0 8 4>;
 377                         clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
 378                         clock-names = "apb_pclk";
 379                 };
 380
 381                 pmx0: pinmux@f7010000 {
 382                         compatible = "pinctrl-single";
 383                         reg = <0x0 0xf7010000  0x0 0x27c>;
 384                         #address-cells = <1>;
 385                         #size-cells = <1>;
 386                         #pinctrl-cells = <1>;
 387                         #gpio-range-cells = <3>;
 388                         pinctrl-single,register-width = <32>;
 389                         pinctrl-single,function-mask = <7>;
 390                         pinctrl-single,gpio-range = <
 391                                 &range  80  8 MUX_M0 /* gpio  3: [0..7] */
 392                                 &range  88  8 MUX_M0 /* gpio  4: [0..7] */
 393                                 &range  96  8 MUX_M0 /* gpio  5: [0..7] */
 394                                 &range 104  8 MUX_M0 /* gpio  6: [0..7] */
 395                                 &range 112  8 MUX_M0 /* gpio  7: [0..7] */
 396                                 &range 120  2 MUX_M0 /* gpio  8: [0..1] */
 397                                 &range   2  6 MUX_M1 /* gpio  8: [2..7] */
 398                                 &range   8  8 MUX_M1 /* gpio  9: [0..7] */
 399                                 &range   0  1 MUX_M1 /* gpio 10: [0]    */
 400                                 &range  16  7 MUX_M1 /* gpio 10: [1..7] */
 401                                 &range  23  3 MUX_M1 /* gpio 11: [0..2] */
 402                                 &range  28  5 MUX_M1 /* gpio 11: [3..7] */
 403                                 &range  33  3 MUX_M1 /* gpio 12: [0..2] */
 404                                 &range  43  5 MUX_M1 /* gpio 12: [3..7] */
 405                                 &range  48  8 MUX_M1 /* gpio 13: [0..7] */
 406                                 &range  56  8 MUX_M1 /* gpio 14: [0..7] */
 407                                 &range  74  6 MUX_M1 /* gpio 15: [0..5] */
 408                                 &range 122  1 MUX_M1 /* gpio 15: [6]    */
 409                                 &range 126  1 MUX_M1 /* gpio 15: [7]    */
 410                                 &range 127  8 MUX_M1 /* gpio 16: [0..7] */
 411                                 &range 135  8 MUX_M1 /* gpio 17: [0..7] */
 412                                 &range 143  8 MUX_M1 /* gpio 18: [0..7] */
 413                                 &range 151  8 MUX_M1 /* gpio 19: [0..7] */
 414                         >;
 415                         range: gpio-range {
 416                                 #pinctrl-single,gpio-range-cells = <3>;
 417                         };
 418                 };
 419
 420                 pmx1: pinmux@f7010800 {
 421                         compatible = "pinconf-single";
 422                         reg = <0x0 0xf7010800 0x0 0x28c>;
 423                         #address-cells = <1>;
 424                         #size-cells = <1>;
 425                         #pinctrl-cells = <1>;
 426                         pinctrl-single,register-width = <32>;
 427                 };
 428
 429                 pmx2: pinmux@f8001800 {
 430                         compatible = "pinconf-single";
 431                         reg = <0x0 0xf8001800 0x0 0x78>;
 432                         #address-cells = <1>;
 433                         #size-cells = <1>;
 434                         #pinctrl-cells = <1>;
 435                         pinctrl-single,register-width = <32>;
 436                 };
 437
 438                 gpio0: gpio@f8011000 {
 439                         compatible = "arm,pl061", "arm,primecell";
 440                         reg = <0x0 0xf8011000 0x0 0x1000>;
 441                         interrupts = <0 52 0x4>;
 442                         gpio-controller;
 443                         #gpio-cells = <2>;
 444                         interrupt-controller;
 445                         #interrupt-cells = <2>;
 446                         clocks = <&ao_ctrl 2>;
 447                         clock-names = "apb_pclk";
 448                 };
 449
 450                 gpio1: gpio@f8012000 {
 451                         compatible = "arm,pl061", "arm,primecell";
 452                         reg = <0x0 0xf8012000 0x0 0x1000>;
 453                         interrupts = <0 53 0x4>;
 454                         gpio-controller;
 455                         #gpio-cells = <2>;
 456                         interrupt-controller;
 457                         #interrupt-cells = <2>;
 458                         clocks = <&ao_ctrl 2>;
 459                         clock-names = "apb_pclk";
 460                 };
 461
 462                 gpio2: gpio@f8013000 {
 463                         compatible = "arm,pl061", "arm,primecell";
 464                         reg = <0x0 0xf8013000 0x0 0x1000>;
 465                         interrupts = <0 54 0x4>;
 466                         gpio-controller;
 467                         #gpio-cells = <2>;
 468                         interrupt-controller;
 469                         #interrupt-cells = <2>;
 470                         clocks = <&ao_ctrl 2>;
 471                         clock-names = "apb_pclk";
 472                 };
 473
 474                 gpio3: gpio@f8014000 {
 475                         compatible = "arm,pl061", "arm,primecell";
 476                         reg = <0x0 0xf8014000 0x0 0x1000>;
 477                         interrupts = <0 55 0x4>;
 478                         gpio-controller;
 479                         #gpio-cells = <2>;
 480                         gpio-ranges = <&pmx0 0 80 8>;
 481                         interrupt-controller;
 482                         #interrupt-cells = <2>;
 483                         clocks = <&ao_ctrl 2>;
 484                         clock-names = "apb_pclk";
 485                 };
 486
 487                 gpio4: gpio@f7020000 {
 488                         compatible = "arm,pl061", "arm,primecell";
 489                         reg = <0x0 0xf7020000 0x0 0x1000>;
 490                         interrupts = <0 56 0x4>;
 491                         gpio-controller;
 492                         #gpio-cells = <2>;
 493                         gpio-ranges = <&pmx0 0 88 8>;
 494                         interrupt-controller;
 495                         #interrupt-cells = <2>;
 496                         clocks = <&ao_ctrl 2>;
 497                         clock-names = "apb_pclk";
 498                 };
 499
 500                 gpio5: gpio@f7021000 {
 501                         compatible = "arm,pl061", "arm,primecell";
 502                         reg = <0x0 0xf7021000 0x0 0x1000>;
 503                         interrupts = <0 57 0x4>;
 504                         gpio-controller;
 505                         #gpio-cells = <2>;
 506                         gpio-ranges = <&pmx0 0 96 8>;
 507                         interrupt-controller;
 508                         #interrupt-cells = <2>;
 509                         clocks = <&ao_ctrl 2>;
 510                         clock-names = "apb_pclk";
 511                 };
 512
 513                 gpio6: gpio@f7022000 {
 514                         compatible = "arm,pl061", "arm,primecell";
 515                         reg = <0x0 0xf7022000 0x0 0x1000>;
 516                         interrupts = <0 58 0x4>;
 517                         gpio-controller;
 518                         #gpio-cells = <2>;
 519                         gpio-ranges = <&pmx0 0 104 8>;
 520                         interrupt-controller;
 521                         #interrupt-cells = <2>;
 522                         clocks = <&ao_ctrl 2>;
 523                         clock-names = "apb_pclk";
 524                 };
 525
 526                 gpio7: gpio@f7023000 {
 527                         compatible = "arm,pl061", "arm,primecell";
 528                         reg = <0x0 0xf7023000 0x0 0x1000>;
 529                         interrupts = <0 59 0x4>;
 530                         gpio-controller;
 531                         #gpio-cells = <2>;
 532                         gpio-ranges = <&pmx0 0 112 8>;
 533                         interrupt-controller;
 534                         #interrupt-cells = <2>;
 535                         clocks = <&ao_ctrl 2>;
 536                         clock-names = "apb_pclk";
 537                 };
 538
 539                 gpio8: gpio@f7024000 {
 540                         compatible = "arm,pl061", "arm,primecell";
 541                         reg = <0x0 0xf7024000 0x0 0x1000>;
 542                         interrupts = <0 60 0x4>;
 543                         gpio-controller;
 544                         #gpio-cells = <2>;
 545                         gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
 546                         interrupt-controller;
 547                         #interrupt-cells = <2>;
 548                         clocks = <&ao_ctrl 2>;
 549                         clock-names = "apb_pclk";
 550                 };
 551
 552                 gpio9: gpio@f7025000 {
 553                         compatible = "arm,pl061", "arm,primecell";
 554                         reg = <0x0 0xf7025000 0x0 0x1000>;
 555                         interrupts = <0 61 0x4>;
 556                         gpio-controller;
 557                         #gpio-cells = <2>;
 558                         gpio-ranges = <&pmx0 0 8 8>;
 559                         interrupt-controller;
 560                         #interrupt-cells = <2>;
 561                         clocks = <&ao_ctrl 2>;
 562                         clock-names = "apb_pclk";
 563                 };
 564
 565                 gpio10: gpio@f7026000 {
 566                         compatible = "arm,pl061", "arm,primecell";
 567                         reg = <0x0 0xf7026000 0x0 0x1000>;
 568                         interrupts = <0 62 0x4>;
 569                         gpio-controller;
 570                         #gpio-cells = <2>;
 571                         gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
 572                         interrupt-controller;
 573                         #interrupt-cells = <2>;
 574                         clocks = <&ao_ctrl 2>;
 575                         clock-names = "apb_pclk";
 576                 };
 577
 578                 gpio11: gpio@f7027000 {
 579                         compatible = "arm,pl061", "arm,primecell";
 580                         reg = <0x0 0xf7027000 0x0 0x1000>;
 581                         interrupts = <0 63 0x4>;
 582                         gpio-controller;
 583                         #gpio-cells = <2>;
 584                         gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
 585                         interrupt-controller;
 586                         #interrupt-cells = <2>;
 587                         clocks = <&ao_ctrl 2>;
 588                         clock-names = "apb_pclk";
 589                 };
 590
 591                 gpio12: gpio@f7028000 {
 592                         compatible = "arm,pl061", "arm,primecell";
 593                         reg = <0x0 0xf7028000 0x0 0x1000>;
 594                         interrupts = <0 64 0x4>;
 595                         gpio-controller;
 596                         #gpio-cells = <2>;
 597                         gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
 598                         interrupt-controller;
 599                         #interrupt-cells = <2>;
 600                         clocks = <&ao_ctrl 2>;
 601                         clock-names = "apb_pclk";
 602                 };
 603
 604                 gpio13: gpio@f7029000 {
 605                         compatible = "arm,pl061", "arm,primecell";
 606                         reg = <0x0 0xf7029000 0x0 0x1000>;
 607                         interrupts = <0 65 0x4>;
 608                         gpio-controller;
 609                         #gpio-cells = <2>;
 610                         gpio-ranges = <&pmx0 0 48 8>;
 611                         interrupt-controller;
 612                         #interrupt-cells = <2>;
 613                         clocks = <&ao_ctrl 2>;
 614                         clock-names = "apb_pclk";
 615                 };
 616
 617                 gpio14: gpio@f702a000 {
 618                         compatible = "arm,pl061", "arm,primecell";
 619                         reg = <0x0 0xf702a000 0x0 0x1000>;
 620                         interrupts = <0 66 0x4>;
 621                         gpio-controller;
 622                         #gpio-cells = <2>;
 623                         gpio-ranges = <&pmx0 0 56 8>;
 624                         interrupt-controller;
 625                         #interrupt-cells = <2>;
 626                         clocks = <&ao_ctrl 2>;
 627                         clock-names = "apb_pclk";
 628                 };
 629
 630                 gpio15: gpio@f702b000 {
 631                         compatible = "arm,pl061", "arm,primecell";
 632                         reg = <0x0 0xf702b000 0x0 0x1000>;
 633                         interrupts = <0 67 0x4>;
 634                         gpio-controller;
 635                         #gpio-cells = <2>;
 636                         gpio-ranges = <
 637                                 &pmx0 0 74 6
 638                                 &pmx0 6 122 1
 639                                 &pmx0 7 126 1
 640                         >;
 641                         interrupt-controller;
 642                         #interrupt-cells = <2>;
 643                         clocks = <&ao_ctrl 2>;
 644                         clock-names = "apb_pclk";
 645                 };
 646
 647                 gpio16: gpio@f702c000 {
 648                         compatible = "arm,pl061", "arm,primecell";
 649                         reg = <0x0 0xf702c000 0x0 0x1000>;
 650                         interrupts = <0 68 0x4>;
 651                         gpio-controller;
 652                         #gpio-cells = <2>;
 653                         gpio-ranges = <&pmx0 0 127 8>;
 654                         interrupt-controller;
 655                         #interrupt-cells = <2>;
 656                         clocks = <&ao_ctrl 2>;
 657                         clock-names = "apb_pclk";
 658                 };
 659
 660                 gpio17: gpio@f702d000 {
 661                         compatible = "arm,pl061", "arm,primecell";
 662                         reg = <0x0 0xf702d000 0x0 0x1000>;
 663                         interrupts = <0 69 0x4>;
 664                         gpio-controller;
 665                         #gpio-cells = <2>;
 666                         gpio-ranges = <&pmx0 0 135 8>;
 667                         interrupt-controller;
 668                         #interrupt-cells = <2>;
 669                         clocks = <&ao_ctrl 2>;
 670                         clock-names = "apb_pclk";
 671                 };
 672
 673                 gpio18: gpio@f702e000 {
 674                         compatible = "arm,pl061", "arm,primecell";
 675                         reg = <0x0 0xf702e000 0x0 0x1000>;
 676                         interrupts = <0 70 0x4>;
 677                         gpio-controller;
 678                         #gpio-cells = <2>;
 679                         gpio-ranges = <&pmx0 0 143 8>;
 680                         interrupt-controller;
 681                         #interrupt-cells = <2>;
 682                         clocks = <&ao_ctrl 2>;
 683                         clock-names = "apb_pclk";
 684                 };
 685
 686                 gpio19: gpio@f702f000 {
 687                         compatible = "arm,pl061", "arm,primecell";
 688                         reg = <0x0 0xf702f000 0x0 0x1000>;
 689                         interrupts = <0 71 0x4>;
 690                         gpio-controller;
 691                         #gpio-cells = <2>;
 692                         gpio-ranges = <&pmx0 0 151 8>;
 693                         interrupt-controller;
 694                         #interrupt-cells = <2>;
 695                         clocks = <&ao_ctrl 2>;
 696                         clock-names = "apb_pclk";
 697                 };
 698
 699                 spi0: spi@f7106000 {
 700                         compatible = "arm,pl022", "arm,primecell";
 701                         reg = <0x0 0xf7106000 0x0 0x1000>;
 702                         interrupts = <0 50 4>;
 703                         bus-id = <0>;
 704                         enable-dma = <0>;
 705                         clocks = <&sys_ctrl HI6220_SPI_CLK>;
 706                         clock-names = "apb_pclk";
 707                         pinctrl-names = "default";
 708                         pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
 709                         num-cs = <1>;
 710                         cs-gpios = <&gpio6 2 0>;
 711                         status = "disabled";
 712                 };
 713
 714                 i2c0: i2c@f7100000 {
 715                         compatible = "snps,designware-i2c";
 716                         reg = <0x0 0xf7100000 0x0 0x1000>;
 717                         interrupts = <0 44 4>;
 718                         clocks = <&sys_ctrl HI6220_I2C0_CLK>;
 719                         i2c-sda-hold-time-ns = <300>;
 720                         pinctrl-names = "default";
 721                         pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
 722                         status = "disabled";
 723                 };
 724
 725                 i2c1: i2c@f7101000 {
 726                         compatible = "snps,designware-i2c";
 727                         reg = <0x0 0xf7101000 0x0 0x1000>;
 728                         clocks = <&sys_ctrl HI6220_I2C1_CLK>;
 729                         interrupts = <0 45 4>;
 730                         i2c-sda-hold-time-ns = <300>;
 731                         pinctrl-names = "default";
 732                         pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
 733                         status = "disabled";
 734                 };
 735
 736                 i2c2: i2c@f7102000 {
 737                         compatible = "snps,designware-i2c";
 738                         reg = <0x0 0xf7102000 0x0 0x1000>;
 739                         clocks = <&sys_ctrl HI6220_I2C2_CLK>;
 740                         interrupts = <0 46 4>;
 741                         i2c-sda-hold-time-ns = <300>;
 742                         pinctrl-names = "default";
 743                         pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
 744                         status = "disabled";
 745                 };
 746
 747                 usb_phy: usbphy {
 748                         compatible = "hisilicon,hi6220-usb-phy";
 749                         #phy-cells = <0>;
 750                         phy-supply = <&reg_5v_hub>;
 751                         hisilicon,peripheral-syscon = <&sys_ctrl>;
 752                 };
 753
 754                 usb: usb@f72c0000 {
 755                         compatible = "hisilicon,hi6220-usb";
 756                         reg = <0x0 0xf72c0000 0x0 0x40000>;
 757                         phys = <&usb_phy>;
 758                         phy-names = "usb2-phy";
 759                         clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
 760                         clock-names = "otg";
 761                         dr_mode = "otg";
 762                         g-rx-fifo-size = <512>;
 763                         g-np-tx-fifo-size = <128>;
 764                         g-tx-fifo-size = <128 128 128 128 128 128 128 128
 765                                            16  16  16  16  16  16  16>;
 766                         interrupts = <0 77 0x4>;
 767                 };
 768
 769                 mailbox: mailbox@f7510000 {
 770                         compatible = "hisilicon,hi6220-mbox";
 771                         reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
 772                               <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
 773                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 774                         #mbox-cells = <3>;
 775                 };
 776
 777                 dwmmc_0: dwmmc0@f723d000 {
 778                         compatible = "hisilicon,hi6220-dw-mshc";
 779                         reg = <0x0 0xf723d000 0x0 0x1000>;
 780                         interrupts = <0x0 0x48 0x4>;
 781                         clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
 782                         clock-names = "ciu", "biu";
 783                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
 784                         reset-names = "reset";
 785                         pinctrl-names = "default";
 786                         pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
 787                                      &emmc_cfg_func &emmc_rst_cfg_func>;
 788                 };
 789
 790                 dwmmc_1: dwmmc1@f723e000 {
 791                         compatible = "hisilicon,hi6220-dw-mshc";
 792                         hisilicon,peripheral-syscon = <&ao_ctrl>;
 793                         reg = <0x0 0xf723e000 0x0 0x1000>;
 794                         interrupts = <0x0 0x49 0x4>;
 795                         #address-cells = <0x1>;
 796                         #size-cells = <0x0>;
 797                         clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
 798                         clock-names = "ciu", "biu";
 799                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
 800                         reset-names = "reset";
 801                         pinctrl-names = "default", "idle";
 802                         pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
 803                         pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
 804                 };
 805
 806                 dwmmc_2: dwmmc2@f723f000 {
 807                         compatible = "hisilicon,hi6220-dw-mshc";
 808                         reg = <0x0 0xf723f000 0x0 0x1000>;
 809                         interrupts = <0x0 0x4a 0x4>;
 810                         clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
 811                         clock-names = "ciu", "biu";
 812                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
 813                         reset-names = "reset";
 814                         pinctrl-names = "default", "idle";
 815                         pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
 816                         pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
 817                 };
 818
 819                 tsensor: tsensor@0,f7030700 {
 820                         compatible = "hisilicon,tsensor";
 821                         reg = <0x0 0xf7030700 0x0 0x1000>;
 822                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 823                         clocks = <&sys_ctrl 22>;
 824                         clock-names = "thermal_clk";
 825                         #thermal-sensor-cells = <1>;
 826                 };
 827
 828                 i2s0: i2s@f7118000{
 829                         compatible = "hisilicon,hi6210-i2s";
 830                         reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
 831                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
 832                         clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
 833                                  <&sys_ctrl HI6220_BBPPLL0_DIV>;
 834                         clock-names = "dacodec", "i2s-base";
 835                         dmas = <&dma0 15 &dma0 14>;
 836                         dma-names = "rx", "tx";
 837                         hisilicon,sysctrl-syscon = <&sys_ctrl>;
 838                         #sound-dai-cells = <1>;
 839                 };
 840
 841                 thermal-zones {
 842
 843                         cls0: cls0 {
 844                                 polling-delay = <1000>;
 845                                 polling-delay-passive = <100>;
 846                                 sustainable-power = <3326>;
 847
 848                                 /* sensor ID */
 849                                 thermal-sensors = <&tsensor 2>;
 850
 851                                 trips {
 852                                         threshold: trip-point@0 {
 853                                                 temperature = <65000>;
 854                                                 hysteresis = <0>;
 855                                                 type = "passive";
 856                                         };
 857
 858                                         target: trip-point@1 {
 859                                                 temperature = <75000>;
 860                                                 hysteresis = <0>;
 861                                                 type = "passive";
 862                                         };
 863                                 };
 864
 865                                 cooling-maps {
 866                                         map0 {
 867                                                 trip = <&target>;
 868                                                 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 869                                         };
 870                                 };
 871                         };
 872                 };
 873
 874                 ade: ade@f4100000 {
 875                         compatible = "hisilicon,hi6220-ade";
 876                         reg = <0x0 0xf4100000 0x0 0x7800>;
 877                         reg-names = "ade_base";
 878                         hisilicon,noc-syscon = <&medianoc_ade>;
 879                         resets = <&media_ctrl MEDIA_ADE>;
 880                         interrupts = <0 115 4>; /* ldi interrupt */
 881
 882                         clocks = <&media_ctrl HI6220_ADE_CORE>,
 883                                  <&media_ctrl HI6220_CODEC_JPEG>,
 884                                  <&media_ctrl HI6220_ADE_PIX_SRC>;
 885                         /*clock name*/
 886                         clock-names  = "clk_ade_core",
 887                                        "clk_codec_jpeg",
 888                                        "clk_ade_pix";
 889
 890                         assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
 891                                 <&media_ctrl HI6220_CODEC_JPEG>;
 892                         assigned-clock-rates = <360000000>, <288000000>;
 893                         dma-coherent;
 894                         status = "disabled";
 895
 896                         port {
 897                                 ade_out: endpoint {
 898                                         remote-endpoint = <&dsi_in>;
 899                                 };
 900                         };
 901                 };
 902
 903                 dsi: dsi@f4107800 {
 904                         compatible = "hisilicon,hi6220-dsi";
 905                         reg = <0x0 0xf4107800 0x0 0x100>;
 906                         clocks = <&media_ctrl  HI6220_DSI_PCLK>;
 907                         clock-names = "pclk";
 908                         status = "disabled";
 909
 910                         ports {
 911                                 #address-cells = <1>;
 912                                 #size-cells = <0>;
 913
 914                                 /* 0 for input port */
 915                                 port@0 {
 916                                         reg = <0>;
 917                                         dsi_in: endpoint {
 918                                                 remote-endpoint = <&ade_out>;
 919                                         };
 920                                 };
 921                         };
 922                 };
 923
 924                 debug@f6590000 {
 925                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 926                         reg = <0 0xf6590000 0 0x1000>;
 927                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 928                         clock-names = "apb_pclk";
 929                         cpu = <&cpu0>;
 930                 };
 931
 932                 debug@f6592000 {
 933                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 934                         reg = <0 0xf6592000 0 0x1000>;
 935                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 936                         clock-names = "apb_pclk";
 937                         cpu = <&cpu1>;
 938                 };
 939
 940                 debug@f6594000 {
 941                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 942                         reg = <0 0xf6594000 0 0x1000>;
 943                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 944                         clock-names = "apb_pclk";
 945                         cpu = <&cpu2>;
 946                 };
 947
 948                 debug@f6596000 {
 949                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 950                         reg = <0 0xf6596000 0 0x1000>;
 951                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 952                         clock-names = "apb_pclk";
 953                         cpu = <&cpu3>;
 954                 };
 955
 956                 debug@f65d0000 {
 957                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 958                         reg = <0 0xf65d0000 0 0x1000>;
 959                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 960                         clock-names = "apb_pclk";
 961                         cpu = <&cpu4>;
 962                 };
 963
 964                 debug@f65d2000 {
 965                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 966                         reg = <0 0xf65d2000 0 0x1000>;
 967                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 968                         clock-names = "apb_pclk";
 969                         cpu = <&cpu5>;
 970                 };
 971
 972                 debug@f65d4000 {
 973                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 974                         reg = <0 0xf65d4000 0 0x1000>;
 975                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 976                         clock-names = "apb_pclk";
 977                         cpu = <&cpu6>;
 978                 };
 979
 980                 debug@f65d6000 {
 981                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 982                         reg = <0 0xf65d6000 0 0x1000>;
 983                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 984                         clock-names = "apb_pclk";
 985                         cpu = <&cpu7>;
 986                 };
 987         };
 988 };