1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_BINFMT_ELF_STATE
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_PREP_COHERENT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_FAST_MULTIPLIER
18 select ARCH_HAS_FORTIFY_SOURCE
19 select ARCH_HAS_GCOV_PROFILE_ALL
20 select ARCH_HAS_GIGANTIC_PAGE
22 select ARCH_HAS_KEEPINITRD
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_DEVMAP
25 select ARCH_HAS_PTE_SPECIAL
26 select ARCH_HAS_SETUP_DMA_OPS
27 select ARCH_HAS_SET_DIRECT_MAP
28 select ARCH_HAS_SET_MEMORY
29 select ARCH_HAS_STRICT_KERNEL_RWX
30 select ARCH_HAS_STRICT_MODULE_RWX
31 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
32 select ARCH_HAS_SYNC_DMA_FOR_CPU
33 select ARCH_HAS_SYSCALL_WRAPPER
34 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
35 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
36 select ARCH_HAVE_ELF_PROT
37 select ARCH_HAVE_NMI_SAFE_CMPXCHG
38 select ARCH_INLINE_READ_LOCK if !PREEMPTION
39 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
40 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
41 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
42 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
43 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
44 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
45 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
46 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
47 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
48 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
49 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
50 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
51 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
52 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
53 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
54 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
55 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
56 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
57 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
58 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
60 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
61 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
62 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
64 select ARCH_KEEP_MEMBLOCK
65 select ARCH_USE_CMPXCHG_LOCKREF
66 select ARCH_USE_GNU_PROPERTY
67 select ARCH_USE_QUEUED_RWLOCKS
68 select ARCH_USE_QUEUED_SPINLOCKS
69 select ARCH_USE_SYM_ANNOTATIONS
70 select ARCH_SUPPORTS_MEMORY_FAILURE
71 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
72 select ARCH_SUPPORTS_ATOMIC_RMW
73 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
74 select ARCH_SUPPORTS_NUMA_BALANCING
75 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
76 select ARCH_WANT_DEFAULT_BPF_JIT
77 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
78 select ARCH_WANT_FRAME_POINTERS
79 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
80 select ARCH_HAS_UBSAN_SANITIZE_ALL
84 select AUDIT_ARCH_COMPAT_GENERIC
85 select ARM_GIC_V2M if PCI
87 select ARM_GIC_V3_ITS if PCI
89 select BUILDTIME_TABLE_SORT
90 select CLONE_BACKWARDS
92 select CPU_PM if (SUSPEND || CPU_IDLE)
94 select DCACHE_WORD_ACCESS
95 select DMA_DIRECT_REMAP
98 select GENERIC_ALLOCATOR
99 select GENERIC_ARCH_TOPOLOGY
100 select GENERIC_CLOCKEVENTS
101 select GENERIC_CLOCKEVENTS_BROADCAST
102 select GENERIC_CPU_AUTOPROBE
103 select GENERIC_CPU_VULNERABILITIES
104 select GENERIC_EARLY_IOREMAP
105 select GENERIC_IDLE_POLL_SETUP
106 select GENERIC_IRQ_MULTI_HANDLER
107 select GENERIC_IRQ_PROBE
108 select GENERIC_IRQ_SHOW
109 select GENERIC_IRQ_SHOW_LEVEL
110 select GENERIC_PCI_IOMAP
111 select GENERIC_PTDUMP
112 select GENERIC_SCHED_CLOCK
113 select GENERIC_SMP_IDLE_THREAD
114 select GENERIC_STRNCPY_FROM_USER
115 select GENERIC_STRNLEN_USER
116 select GENERIC_TIME_VSYSCALL
117 select GENERIC_GETTIMEOFDAY
118 select HANDLE_DOMAIN_IRQ
119 select HARDIRQS_SW_RESEND
121 select HAVE_ACPI_APEI if (ACPI && EFI)
122 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
123 select HAVE_ARCH_AUDITSYSCALL
124 select HAVE_ARCH_BITREVERSE
125 select HAVE_ARCH_COMPILER_H
126 select HAVE_ARCH_HUGE_VMAP
127 select HAVE_ARCH_JUMP_LABEL
128 select HAVE_ARCH_JUMP_LABEL_RELATIVE
129 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
130 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
131 select HAVE_ARCH_KGDB
132 select HAVE_ARCH_MMAP_RND_BITS
133 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
134 select HAVE_ARCH_PREL32_RELOCATIONS
135 select HAVE_ARCH_SECCOMP_FILTER
136 select HAVE_ARCH_STACKLEAK
137 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
138 select HAVE_ARCH_TRACEHOOK
139 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
140 select HAVE_ARCH_VMAP_STACK
141 select HAVE_ARM_SMCCC
142 select HAVE_ASM_MODVERSIONS
144 select HAVE_C_RECORDMCOUNT
145 select HAVE_CMPXCHG_DOUBLE
146 select HAVE_CMPXCHG_LOCAL
147 select HAVE_CONTEXT_TRACKING
148 select HAVE_COPY_THREAD_TLS
149 select HAVE_DEBUG_BUGVERBOSE
150 select HAVE_DEBUG_KMEMLEAK
151 select HAVE_DMA_CONTIGUOUS
152 select HAVE_DYNAMIC_FTRACE
153 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
154 if $(cc-option,-fpatchable-function-entry=2)
155 select HAVE_EFFICIENT_UNALIGNED_ACCESS
157 select HAVE_FTRACE_MCOUNT_RECORD
158 select HAVE_FUNCTION_TRACER
159 select HAVE_FUNCTION_ERROR_INJECTION
160 select HAVE_FUNCTION_GRAPH_TRACER
161 select HAVE_GCC_PLUGINS
162 select HAVE_HW_BREAKPOINT if PERF_EVENTS
163 select HAVE_IRQ_TIME_ACCOUNTING
164 select HAVE_MEMBLOCK_NODE_MAP if NUMA
166 select HAVE_PATA_PLATFORM
167 select HAVE_PERF_EVENTS
168 select HAVE_PERF_REGS
169 select HAVE_PERF_USER_STACK_DUMP
170 select HAVE_REGS_AND_STACK_ACCESS_API
171 select HAVE_FUNCTION_ARG_ACCESS_API
172 select HAVE_FUTEX_CMPXCHG if FUTEX
173 select MMU_GATHER_RCU_TABLE_FREE
175 select HAVE_STACKPROTECTOR
176 select HAVE_SYSCALL_TRACEPOINTS
178 select HAVE_KRETPROBES
179 select HAVE_GENERIC_VDSO
180 select IOMMU_DMA if IOMMU_SUPPORT
182 select IRQ_FORCED_THREADING
183 select MODULES_USE_ELF_RELA
184 select NEED_DMA_MAP_STATE
185 select NEED_SG_DMA_LENGTH
187 select OF_EARLY_FLATTREE
188 select PCI_DOMAINS_GENERIC if PCI
189 select PCI_ECAM if (ACPI && PCI)
190 select PCI_SYSCALL if PCI
195 select SYSCTL_EXCEPTION_TRACE
196 select THREAD_INFO_IN_TASK
198 ARM 64-bit (AArch64) Linux support.
206 config ARM64_PAGE_SHIFT
208 default 16 if ARM64_64K_PAGES
209 default 14 if ARM64_16K_PAGES
212 config ARM64_CONT_SHIFT
214 default 5 if ARM64_64K_PAGES
215 default 7 if ARM64_16K_PAGES
218 config ARCH_MMAP_RND_BITS_MIN
219 default 14 if ARM64_64K_PAGES
220 default 16 if ARM64_16K_PAGES
223 # max bits determined by the following formula:
224 # VA_BITS - PAGE_SHIFT - 3
225 config ARCH_MMAP_RND_BITS_MAX
226 default 19 if ARM64_VA_BITS=36
227 default 24 if ARM64_VA_BITS=39
228 default 27 if ARM64_VA_BITS=42
229 default 30 if ARM64_VA_BITS=47
230 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
231 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
232 default 33 if ARM64_VA_BITS=48
233 default 14 if ARM64_64K_PAGES
234 default 16 if ARM64_16K_PAGES
237 config ARCH_MMAP_RND_COMPAT_BITS_MIN
238 default 7 if ARM64_64K_PAGES
239 default 9 if ARM64_16K_PAGES
242 config ARCH_MMAP_RND_COMPAT_BITS_MAX
248 config STACKTRACE_SUPPORT
251 config ILLEGAL_POINTER_VALUE
253 default 0xdead000000000000
255 config LOCKDEP_SUPPORT
258 config TRACE_IRQFLAGS_SUPPORT
265 config GENERIC_BUG_RELATIVE_POINTERS
267 depends on GENERIC_BUG
269 config GENERIC_HWEIGHT
275 config GENERIC_CALIBRATE_DELAY
279 bool "Support DMA zone" if EXPERT
283 bool "Support DMA32 zone" if EXPERT
286 config ARCH_ENABLE_MEMORY_HOTPLUG
289 config ARCH_ENABLE_MEMORY_HOTREMOVE
295 config KERNEL_MODE_NEON
298 config FIX_EARLYCON_MEM
301 config PGTABLE_LEVELS
303 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
304 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
305 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
306 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
307 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
308 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
310 config ARCH_SUPPORTS_UPROBES
313 config ARCH_PROC_KCORE_TEXT
316 config BROKEN_GAS_INST
317 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
319 config KASAN_SHADOW_OFFSET
322 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
323 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
324 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
325 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
326 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
327 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
328 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
329 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
330 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
331 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
332 default 0xffffffffffffffff
334 source "arch/arm64/Kconfig.platforms"
336 menu "Kernel Features"
338 menu "ARM errata workarounds via the alternatives framework"
340 config ARM64_WORKAROUND_CLEAN_CACHE
343 config ARM64_ERRATUM_826319
344 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
346 select ARM64_WORKAROUND_CLEAN_CACHE
348 This option adds an alternative code sequence to work around ARM
349 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
350 AXI master interface and an L2 cache.
352 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
353 and is unable to accept a certain write via this interface, it will
354 not progress on read data presented on the read data channel and the
357 The workaround promotes data cache clean instructions to
358 data cache clean-and-invalidate.
359 Please note that this does not necessarily enable the workaround,
360 as it depends on the alternative framework, which will only patch
361 the kernel if an affected CPU is detected.
365 config ARM64_ERRATUM_827319
366 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
368 select ARM64_WORKAROUND_CLEAN_CACHE
370 This option adds an alternative code sequence to work around ARM
371 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
372 master interface and an L2 cache.
374 Under certain conditions this erratum can cause a clean line eviction
375 to occur at the same time as another transaction to the same address
376 on the AMBA 5 CHI interface, which can cause data corruption if the
377 interconnect reorders the two transactions.
379 The workaround promotes data cache clean instructions to
380 data cache clean-and-invalidate.
381 Please note that this does not necessarily enable the workaround,
382 as it depends on the alternative framework, which will only patch
383 the kernel if an affected CPU is detected.
387 config ARM64_ERRATUM_824069
388 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
390 select ARM64_WORKAROUND_CLEAN_CACHE
392 This option adds an alternative code sequence to work around ARM
393 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
394 to a coherent interconnect.
396 If a Cortex-A53 processor is executing a store or prefetch for
397 write instruction at the same time as a processor in another
398 cluster is executing a cache maintenance operation to the same
399 address, then this erratum might cause a clean cache line to be
400 incorrectly marked as dirty.
402 The workaround promotes data cache clean instructions to
403 data cache clean-and-invalidate.
404 Please note that this option does not necessarily enable the
405 workaround, as it depends on the alternative framework, which will
406 only patch the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_819472
411 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
413 select ARM64_WORKAROUND_CLEAN_CACHE
415 This option adds an alternative code sequence to work around ARM
416 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
417 present when it is connected to a coherent interconnect.
419 If the processor is executing a load and store exclusive sequence at
420 the same time as a processor in another cluster is executing a cache
421 maintenance operation to the same address, then this erratum might
422 cause data corruption.
424 The workaround promotes data cache clean instructions to
425 data cache clean-and-invalidate.
426 Please note that this does not necessarily enable the workaround,
427 as it depends on the alternative framework, which will only patch
428 the kernel if an affected CPU is detected.
432 config ARM64_ERRATUM_832075
433 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
436 This option adds an alternative code sequence to work around ARM
437 erratum 832075 on Cortex-A57 parts up to r1p2.
439 Affected Cortex-A57 parts might deadlock when exclusive load/store
440 instructions to Write-Back memory are mixed with Device loads.
442 The workaround is to promote device loads to use Load-Acquire
444 Please note that this does not necessarily enable the workaround,
445 as it depends on the alternative framework, which will only patch
446 the kernel if an affected CPU is detected.
450 config ARM64_ERRATUM_834220
451 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
455 This option adds an alternative code sequence to work around ARM
456 erratum 834220 on Cortex-A57 parts up to r1p2.
458 Affected Cortex-A57 parts might report a Stage 2 translation
459 fault as the result of a Stage 1 fault for load crossing a
460 page boundary when there is a permission or device memory
461 alignment fault at Stage 1 and a translation fault at Stage 2.
463 The workaround is to verify that the Stage 1 translation
464 doesn't generate a fault before handling the Stage 2 fault.
465 Please note that this does not necessarily enable the workaround,
466 as it depends on the alternative framework, which will only patch
467 the kernel if an affected CPU is detected.
471 config ARM64_ERRATUM_845719
472 bool "Cortex-A53: 845719: a load might read incorrect data"
476 This option adds an alternative code sequence to work around ARM
477 erratum 845719 on Cortex-A53 parts up to r0p4.
479 When running a compat (AArch32) userspace on an affected Cortex-A53
480 part, a load at EL0 from a virtual address that matches the bottom 32
481 bits of the virtual address used by a recent load at (AArch64) EL1
482 might return incorrect data.
484 The workaround is to write the contextidr_el1 register on exception
485 return to a 32-bit task.
486 Please note that this does not necessarily enable the workaround,
487 as it depends on the alternative framework, which will only patch
488 the kernel if an affected CPU is detected.
492 config ARM64_ERRATUM_843419
493 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
495 select ARM64_MODULE_PLTS if MODULES
497 This option links the kernel with '--fix-cortex-a53-843419' and
498 enables PLT support to replace certain ADRP instructions, which can
499 cause subsequent memory accesses to use an incorrect address on
500 Cortex-A53 parts up to r0p4.
504 config ARM64_ERRATUM_1024718
505 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
508 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
510 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
511 update of the hardware dirty bit when the DBM/AP bits are updated
512 without a break-before-make. The workaround is to disable the usage
513 of hardware DBM locally on the affected cores. CPUs not affected by
514 this erratum will continue to use the feature.
518 config ARM64_ERRATUM_1418040
519 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
523 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
524 errata 1188873 and 1418040.
526 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
527 cause register corruption when accessing the timer registers
528 from AArch32 userspace.
532 config ARM64_WORKAROUND_SPECULATIVE_AT
535 config ARM64_ERRATUM_1165522
536 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
538 select ARM64_WORKAROUND_SPECULATIVE_AT
540 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
542 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
543 corrupted TLBs by speculating an AT instruction during a guest
548 config ARM64_ERRATUM_1319367
549 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
551 select ARM64_WORKAROUND_SPECULATIVE_AT
553 This option adds work arounds for ARM Cortex-A57 erratum 1319537
554 and A72 erratum 1319367
556 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
557 speculating an AT instruction during a guest context switch.
561 config ARM64_ERRATUM_1530923
562 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
564 select ARM64_WORKAROUND_SPECULATIVE_AT
566 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
568 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
569 corrupted TLBs by speculating an AT instruction during a guest
574 config ARM64_WORKAROUND_REPEAT_TLBI
577 config ARM64_ERRATUM_1286807
578 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
580 select ARM64_WORKAROUND_REPEAT_TLBI
582 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
584 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
585 address for a cacheable mapping of a location is being
586 accessed by a core while another core is remapping the virtual
587 address to a new physical page using the recommended
588 break-before-make sequence, then under very rare circumstances
589 TLBI+DSB completes before a read using the translation being
590 invalidated has been observed by other observers. The
591 workaround repeats the TLBI+DSB operation.
593 config ARM64_ERRATUM_1463225
594 bool "Cortex-A76: Software Step might prevent interrupt recognition"
597 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
599 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
600 of a system call instruction (SVC) can prevent recognition of
601 subsequent interrupts when software stepping is disabled in the
602 exception handler of the system call and either kernel debugging
603 is enabled or VHE is in use.
605 Work around the erratum by triggering a dummy step exception
606 when handling a system call from a task that is being stepped
607 in a VHE configuration of the kernel.
611 config ARM64_ERRATUM_1542419
612 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
615 This option adds a workaround for ARM Neoverse-N1 erratum
618 Affected Neoverse-N1 cores could execute a stale instruction when
619 modified by another CPU. The workaround depends on a firmware
622 Workaround the issue by hiding the DIC feature from EL0. This
623 forces user-space to perform cache maintenance.
627 config CAVIUM_ERRATUM_22375
628 bool "Cavium erratum 22375, 24313"
631 Enable workaround for errata 22375 and 24313.
633 This implements two gicv3-its errata workarounds for ThunderX. Both
634 with a small impact affecting only ITS table allocation.
636 erratum 22375: only alloc 8MB table size
637 erratum 24313: ignore memory access type
639 The fixes are in ITS initialization and basically ignore memory access
640 type and table size provided by the TYPER and BASER registers.
644 config CAVIUM_ERRATUM_23144
645 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
649 ITS SYNC command hang for cross node io and collections/cpu mapping.
653 config CAVIUM_ERRATUM_23154
654 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
657 The gicv3 of ThunderX requires a modified version for
658 reading the IAR status to ensure data synchronization
659 (access to icc_iar1_el1 is not sync'ed before and after).
663 config CAVIUM_ERRATUM_27456
664 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
667 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
668 instructions may cause the icache to become corrupted if it
669 contains data for a non-current ASID. The fix is to
670 invalidate the icache when changing the mm context.
674 config CAVIUM_ERRATUM_30115
675 bool "Cavium erratum 30115: Guest may disable interrupts in host"
678 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
679 1.2, and T83 Pass 1.0, KVM guest execution may disable
680 interrupts in host. Trapping both GICv3 group-0 and group-1
681 accesses sidesteps the issue.
685 config CAVIUM_TX2_ERRATUM_219
686 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
689 On Cavium ThunderX2, a load, store or prefetch instruction between a
690 TTBR update and the corresponding context synchronizing operation can
691 cause a spurious Data Abort to be delivered to any hardware thread in
694 Work around the issue by avoiding the problematic code sequence and
695 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
696 trap handler performs the corresponding register access, skips the
697 instruction and ensures context synchronization by virtue of the
702 config FUJITSU_ERRATUM_010001
703 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
706 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
707 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
708 accesses may cause undefined fault (Data abort, DFSC=0b111111).
709 This fault occurs under a specific hardware condition when a
710 load/store instruction performs an address translation using:
711 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
712 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
713 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
714 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
716 The workaround is to ensure these bits are clear in TCR_ELx.
717 The workaround only affects the Fujitsu-A64FX.
721 config HISILICON_ERRATUM_161600802
722 bool "Hip07 161600802: Erroneous redistributor VLPI base"
725 The HiSilicon Hip07 SoC uses the wrong redistributor base
726 when issued ITS commands such as VMOVP and VMAPP, and requires
727 a 128kB offset to be applied to the target address in this commands.
731 config QCOM_FALKOR_ERRATUM_1003
732 bool "Falkor E1003: Incorrect translation due to ASID change"
735 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
736 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
737 in TTBR1_EL1, this situation only occurs in the entry trampoline and
738 then only for entries in the walk cache, since the leaf translation
739 is unchanged. Work around the erratum by invalidating the walk cache
740 entries for the trampoline before entering the kernel proper.
742 config QCOM_FALKOR_ERRATUM_1009
743 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
745 select ARM64_WORKAROUND_REPEAT_TLBI
747 On Falkor v1, the CPU may prematurely complete a DSB following a
748 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
749 one more time to fix the issue.
753 config QCOM_QDF2400_ERRATUM_0065
754 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
757 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
758 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
759 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
763 config QCOM_FALKOR_ERRATUM_E1041
764 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
767 Falkor CPU may speculatively fetch instructions from an improper
768 memory location when MMU translation is changed from SCTLR_ELn[M]=1
769 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
773 config SOCIONEXT_SYNQUACER_PREITS
774 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
777 Socionext Synquacer SoCs implement a separate h/w block to generate
778 MSI doorbell writes with non-zero values for the device ID.
787 default ARM64_4K_PAGES
789 Page size (translation granule) configuration.
791 config ARM64_4K_PAGES
794 This feature enables 4KB pages support.
796 config ARM64_16K_PAGES
799 The system will use 16KB pages support. AArch32 emulation
800 requires applications compiled with 16K (or a multiple of 16K)
803 config ARM64_64K_PAGES
806 This feature enables 64KB pages support (4KB by default)
807 allowing only two levels of page tables and faster TLB
808 look-up. AArch32 emulation requires applications compiled
809 with 64K aligned segments.
814 prompt "Virtual address space size"
815 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
816 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
817 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
819 Allows choosing one of multiple possible virtual address
820 space sizes. The level of translation table is determined by
821 a combination of page size and virtual address space size.
823 config ARM64_VA_BITS_36
824 bool "36-bit" if EXPERT
825 depends on ARM64_16K_PAGES
827 config ARM64_VA_BITS_39
829 depends on ARM64_4K_PAGES
831 config ARM64_VA_BITS_42
833 depends on ARM64_64K_PAGES
835 config ARM64_VA_BITS_47
837 depends on ARM64_16K_PAGES
839 config ARM64_VA_BITS_48
842 config ARM64_VA_BITS_52
844 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
846 Enable 52-bit virtual addressing for userspace when explicitly
847 requested via a hint to mmap(). The kernel will also use 52-bit
848 virtual addresses for its own mappings (provided HW support for
849 this feature is available, otherwise it reverts to 48-bit).
851 NOTE: Enabling 52-bit virtual addressing in conjunction with
852 ARMv8.3 Pointer Authentication will result in the PAC being
853 reduced from 7 bits to 3 bits, which may have a significant
854 impact on its susceptibility to brute-force attacks.
856 If unsure, select 48-bit virtual addressing instead.
860 config ARM64_FORCE_52BIT
861 bool "Force 52-bit virtual addresses for userspace"
862 depends on ARM64_VA_BITS_52 && EXPERT
864 For systems with 52-bit userspace VAs enabled, the kernel will attempt
865 to maintain compatibility with older software by providing 48-bit VAs
866 unless a hint is supplied to mmap.
868 This configuration option disables the 48-bit compatibility logic, and
869 forces all userspace addresses to be 52-bit on HW that supports it. One
870 should only enable this configuration option for stress testing userspace
871 memory management code. If unsure say N here.
875 default 36 if ARM64_VA_BITS_36
876 default 39 if ARM64_VA_BITS_39
877 default 42 if ARM64_VA_BITS_42
878 default 47 if ARM64_VA_BITS_47
879 default 48 if ARM64_VA_BITS_48
880 default 52 if ARM64_VA_BITS_52
883 prompt "Physical address space size"
884 default ARM64_PA_BITS_48
886 Choose the maximum physical address range that the kernel will
889 config ARM64_PA_BITS_48
892 config ARM64_PA_BITS_52
893 bool "52-bit (ARMv8.2)"
894 depends on ARM64_64K_PAGES
895 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
897 Enable support for a 52-bit physical address space, introduced as
898 part of the ARMv8.2-LPA extension.
900 With this enabled, the kernel will also continue to work on CPUs that
901 do not support ARMv8.2-LPA, but with some added memory overhead (and
902 minor performance overhead).
908 default 48 if ARM64_PA_BITS_48
909 default 52 if ARM64_PA_BITS_52
913 default CPU_LITTLE_ENDIAN
915 Select the endianness of data accesses performed by the CPU. Userspace
916 applications will need to be compiled and linked for the endianness
917 that is selected here.
919 config CPU_BIG_ENDIAN
920 bool "Build big-endian kernel"
922 Say Y if you plan on running a kernel with a big-endian userspace.
924 config CPU_LITTLE_ENDIAN
925 bool "Build little-endian kernel"
927 Say Y if you plan on running a kernel with a little-endian userspace.
928 This is usually the case for distributions targeting arm64.
933 bool "Multi-core scheduler support"
935 Multi-core scheduler support improves the CPU scheduler's decision
936 making when dealing with multi-core CPU chips at a cost of slightly
937 increased overhead in some places. If unsure say N here.
940 bool "SMT scheduler support"
942 Improves the CPU scheduler's decision making when dealing with
943 MultiThreading at a cost of slightly increased overhead in some
944 places. If unsure say N here.
947 int "Maximum number of CPUs (2-4096)"
952 bool "Support for hot-pluggable CPUs"
953 select GENERIC_IRQ_MIGRATION
955 Say Y here to experiment with turning CPUs off and on. CPUs
956 can be controlled through /sys/devices/system/cpu.
958 # Common NUMA Features
960 bool "NUMA Memory Allocation and Scheduler Support"
961 select ACPI_NUMA if ACPI
964 Enable NUMA (Non-Uniform Memory Access) support.
966 The kernel will try to allocate memory used by a CPU on the
967 local memory of the CPU and add some more
968 NUMA awareness to the kernel.
971 int "Maximum NUMA Nodes (as a power of 2)"
974 depends on NEED_MULTIPLE_NODES
976 Specify the maximum number of NUMA Nodes available on the target
977 system. Increases memory reserved to accommodate various tables.
979 config USE_PERCPU_NUMA_NODE_ID
983 config HAVE_SETUP_PER_CPU_AREA
987 config NEED_PER_CPU_EMBED_FIRST_CHUNK
994 source "kernel/Kconfig.hz"
996 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
999 config ARCH_SPARSEMEM_ENABLE
1001 select SPARSEMEM_VMEMMAP_ENABLE
1003 config ARCH_SPARSEMEM_DEFAULT
1004 def_bool ARCH_SPARSEMEM_ENABLE
1006 config ARCH_SELECT_MEMORY_MODEL
1007 def_bool ARCH_SPARSEMEM_ENABLE
1009 config ARCH_FLATMEM_ENABLE
1012 config HAVE_ARCH_PFN_VALID
1015 config HW_PERF_EVENTS
1019 config SYS_SUPPORTS_HUGETLBFS
1022 config ARCH_WANT_HUGE_PMD_SHARE
1024 config ARCH_HAS_CACHE_LINE_SIZE
1027 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1028 def_bool y if PGTABLE_LEVELS > 2
1030 # Supported by clang >= 7.0
1031 config CC_HAVE_SHADOW_CALL_STACK
1032 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1035 bool "Enable seccomp to safely compute untrusted bytecode"
1037 This kernel feature is useful for number crunching applications
1038 that may need to compute untrusted bytecode during their
1039 execution. By using pipes or other transports made available to
1040 the process as file descriptors supporting the read/write
1041 syscalls, it's possible to isolate those applications in
1042 their own address space using seccomp. Once seccomp is
1043 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1044 and the task is only allowed to execute a few safe syscalls
1045 defined by each seccomp mode.
1048 bool "Enable paravirtualization code"
1050 This changes the kernel so it can modify itself when it is run
1051 under a hypervisor, potentially improving performance significantly
1052 over full virtualization.
1054 config PARAVIRT_TIME_ACCOUNTING
1055 bool "Paravirtual steal time accounting"
1058 Select this option to enable fine granularity task steal time
1059 accounting. Time spent executing other tasks in parallel with
1060 the current vCPU is discounted from the vCPU power. To account for
1061 that, there can be a small performance impact.
1063 If in doubt, say N here.
1066 depends on PM_SLEEP_SMP
1068 bool "kexec system call"
1070 kexec is a system call that implements the ability to shutdown your
1071 current kernel, and to start another kernel. It is like a reboot
1072 but it is independent of the system firmware. And like a reboot
1073 you can start any kernel with it, not just Linux.
1076 bool "kexec file based system call"
1079 This is new version of kexec system call. This system call is
1080 file based and takes file descriptors as system call argument
1081 for kernel and initramfs as opposed to list of segments as
1082 accepted by previous system call.
1085 bool "Verify kernel signature during kexec_file_load() syscall"
1086 depends on KEXEC_FILE
1088 Select this option to verify a signature with loaded kernel
1089 image. If configured, any attempt of loading a image without
1090 valid signature will fail.
1092 In addition to that option, you need to enable signature
1093 verification for the corresponding kernel image type being
1094 loaded in order for this to work.
1096 config KEXEC_IMAGE_VERIFY_SIG
1097 bool "Enable Image signature verification support"
1099 depends on KEXEC_SIG
1100 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1102 Enable Image signature verification support.
1104 comment "Support for PE file signature verification disabled"
1105 depends on KEXEC_SIG
1106 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1109 bool "Build kdump crash kernel"
1111 Generate crash dump after being started by kexec. This should
1112 be normally only set in special crash dump kernels which are
1113 loaded in the main kernel with kexec-tools into a specially
1114 reserved region and then later executed after a crash by
1117 For more details see Documentation/admin-guide/kdump/kdump.rst
1124 bool "Xen guest support on ARM64"
1125 depends on ARM64 && OF
1129 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1131 config FORCE_MAX_ZONEORDER
1133 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1134 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1137 The kernel memory allocator divides physically contiguous memory
1138 blocks into "zones", where each zone is a power of two number of
1139 pages. This option selects the largest power of two that the kernel
1140 keeps in the memory allocator. If you need to allocate very large
1141 blocks of physically contiguous memory, then you may need to
1142 increase this value.
1144 This config option is actually maximum order plus one. For example,
1145 a value of 11 means that the largest free memory block is 2^10 pages.
1147 We make sure that we can allocate upto a HugePage size for each configuration.
1149 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1151 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1152 4M allocations matching the default size used by generic code.
1154 config UNMAP_KERNEL_AT_EL0
1155 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1158 Speculation attacks against some high-performance processors can
1159 be used to bypass MMU permission checks and leak kernel data to
1160 userspace. This can be defended against by unmapping the kernel
1161 when running in userspace, mapping it back in on exception entry
1162 via a trampoline page in the vector table.
1166 config HARDEN_BRANCH_PREDICTOR
1167 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1170 Speculation attacks against some high-performance processors rely on
1171 being able to manipulate the branch predictor for a victim context by
1172 executing aliasing branches in the attacker context. Such attacks
1173 can be partially mitigated against by clearing internal branch
1174 predictor state and limiting the prediction logic in some situations.
1176 This config option will take CPU-specific actions to harden the
1177 branch predictor against aliasing attacks and may rely on specific
1178 instruction sequences or control bits being set by the system
1183 config HARDEN_EL2_VECTORS
1184 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1187 Speculation attacks against some high-performance processors can
1188 be used to leak privileged information such as the vector base
1189 register, resulting in a potential defeat of the EL2 layout
1192 This config option will map the vectors to a fixed location,
1193 independent of the EL2 code mapping, so that revealing VBAR_EL2
1194 to an attacker does not give away any extra information. This
1195 only gets enabled on affected CPUs.
1200 bool "Speculative Store Bypass Disable" if EXPERT
1203 This enables mitigation of the bypassing of previous stores
1204 by speculative loads.
1208 config RODATA_FULL_DEFAULT_ENABLED
1209 bool "Apply r/o permissions of VM areas also to their linear aliases"
1212 Apply read-only attributes of VM areas to the linear alias of
1213 the backing pages as well. This prevents code or read-only data
1214 from being modified (inadvertently or intentionally) via another
1215 mapping of the same memory page. This additional enhancement can
1216 be turned off at runtime by passing rodata=[off|on] (and turned on
1217 with rodata=full if this option is set to 'n')
1219 This requires the linear region to be mapped down to pages,
1220 which may adversely affect performance in some cases.
1222 config ARM64_SW_TTBR0_PAN
1223 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1225 Enabling this option prevents the kernel from accessing
1226 user-space memory directly by pointing TTBR0_EL1 to a reserved
1227 zeroed area and reserved ASID. The user access routines
1228 restore the valid TTBR0_EL1 temporarily.
1230 config ARM64_TAGGED_ADDR_ABI
1231 bool "Enable the tagged user addresses syscall ABI"
1234 When this option is enabled, user applications can opt in to a
1235 relaxed ABI via prctl() allowing tagged addresses to be passed
1236 to system calls as pointer arguments. For details, see
1237 Documentation/arm64/tagged-address-abi.rst.
1240 bool "Kernel support for 32-bit EL0"
1241 depends on ARM64_4K_PAGES || EXPERT
1242 select COMPAT_BINFMT_ELF if BINFMT_ELF
1244 select OLD_SIGSUSPEND3
1245 select COMPAT_OLD_SIGACTION
1247 This option enables support for a 32-bit EL0 running under a 64-bit
1248 kernel at EL1. AArch32-specific components such as system calls,
1249 the user helper functions, VFP support and the ptrace interface are
1250 handled appropriately by the kernel.
1252 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1253 that you will only be able to execute AArch32 binaries that were compiled
1254 with page size aligned segments.
1256 If you want to execute 32-bit userspace applications, say Y.
1260 config KUSER_HELPERS
1261 bool "Enable kuser helpers page for 32-bit applications"
1264 Warning: disabling this option may break 32-bit user programs.
1266 Provide kuser helpers to compat tasks. The kernel provides
1267 helper code to userspace in read only form at a fixed location
1268 to allow userspace to be independent of the CPU type fitted to
1269 the system. This permits binaries to be run on ARMv4 through
1270 to ARMv8 without modification.
1272 See Documentation/arm/kernel_user_helpers.rst for details.
1274 However, the fixed address nature of these helpers can be used
1275 by ROP (return orientated programming) authors when creating
1278 If all of the binaries and libraries which run on your platform
1279 are built specifically for your platform, and make no use of
1280 these helpers, then you can turn this option off to hinder
1281 such exploits. However, in that case, if a binary or library
1282 relying on those helpers is run, it will not function correctly.
1284 Say N here only if you are absolutely certain that you do not
1285 need these helpers; otherwise, the safe option is to say Y.
1288 bool "Enable vDSO for 32-bit applications"
1289 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1290 select GENERIC_COMPAT_VDSO
1293 Place in the process address space of 32-bit applications an
1294 ELF shared object providing fast implementations of gettimeofday
1297 You must have a 32-bit build of glibc 2.22 or later for programs
1298 to seamlessly take advantage of this.
1300 config THUMB2_COMPAT_VDSO
1301 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1302 depends on COMPAT_VDSO
1305 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1306 otherwise with '-marm'.
1308 menuconfig ARMV8_DEPRECATED
1309 bool "Emulate deprecated/obsolete ARMv8 instructions"
1312 Legacy software support may require certain instructions
1313 that have been deprecated or obsoleted in the architecture.
1315 Enable this config to enable selective emulation of these
1322 config SWP_EMULATION
1323 bool "Emulate SWP/SWPB instructions"
1325 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1326 they are always undefined. Say Y here to enable software
1327 emulation of these instructions for userspace using LDXR/STXR.
1329 In some older versions of glibc [<=2.8] SWP is used during futex
1330 trylock() operations with the assumption that the code will not
1331 be preempted. This invalid assumption may be more likely to fail
1332 with SWP emulation enabled, leading to deadlock of the user
1335 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1336 on an external transaction monitoring block called a global
1337 monitor to maintain update atomicity. If your system does not
1338 implement a global monitor, this option can cause programs that
1339 perform SWP operations to uncached memory to deadlock.
1343 config CP15_BARRIER_EMULATION
1344 bool "Emulate CP15 Barrier instructions"
1346 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1347 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1348 strongly recommended to use the ISB, DSB, and DMB
1349 instructions instead.
1351 Say Y here to enable software emulation of these
1352 instructions for AArch32 userspace code. When this option is
1353 enabled, CP15 barrier usage is traced which can help
1354 identify software that needs updating.
1358 config SETEND_EMULATION
1359 bool "Emulate SETEND instruction"
1361 The SETEND instruction alters the data-endianness of the
1362 AArch32 EL0, and is deprecated in ARMv8.
1364 Say Y here to enable software emulation of the instruction
1365 for AArch32 userspace code.
1367 Note: All the cpus on the system must have mixed endian support at EL0
1368 for this feature to be enabled. If a new CPU - which doesn't support mixed
1369 endian - is hotplugged in after this feature has been enabled, there could
1370 be unexpected results in the applications.
1377 menu "ARMv8.1 architectural features"
1379 config ARM64_HW_AFDBM
1380 bool "Support for hardware updates of the Access and Dirty page flags"
1383 The ARMv8.1 architecture extensions introduce support for
1384 hardware updates of the access and dirty information in page
1385 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1386 capable processors, accesses to pages with PTE_AF cleared will
1387 set this bit instead of raising an access flag fault.
1388 Similarly, writes to read-only pages with the DBM bit set will
1389 clear the read-only bit (AP[2]) instead of raising a
1392 Kernels built with this configuration option enabled continue
1393 to work on pre-ARMv8.1 hardware and the performance impact is
1394 minimal. If unsure, say Y.
1397 bool "Enable support for Privileged Access Never (PAN)"
1400 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1401 prevents the kernel or hypervisor from accessing user-space (EL0)
1404 Choosing this option will cause any unprotected (not using
1405 copy_to_user et al) memory access to fail with a permission fault.
1407 The feature is detected at runtime, and will remain as a 'nop'
1408 instruction if the cpu does not implement the feature.
1410 config ARM64_LSE_ATOMICS
1412 default ARM64_USE_LSE_ATOMICS
1413 depends on $(as-instr,.arch_extension lse)
1415 config ARM64_USE_LSE_ATOMICS
1416 bool "Atomic instructions"
1417 depends on JUMP_LABEL
1420 As part of the Large System Extensions, ARMv8.1 introduces new
1421 atomic instructions that are designed specifically to scale in
1424 Say Y here to make use of these instructions for the in-kernel
1425 atomic routines. This incurs a small overhead on CPUs that do
1426 not support these instructions and requires the kernel to be
1427 built with binutils >= 2.25 in order for the new instructions
1431 bool "Enable support for Virtualization Host Extensions (VHE)"
1434 Virtualization Host Extensions (VHE) allow the kernel to run
1435 directly at EL2 (instead of EL1) on processors that support
1436 it. This leads to better performance for KVM, as they reduce
1437 the cost of the world switch.
1439 Selecting this option allows the VHE feature to be detected
1440 at runtime, and does not affect processors that do not
1441 implement this feature.
1445 menu "ARMv8.2 architectural features"
1448 bool "Enable support for User Access Override (UAO)"
1451 User Access Override (UAO; part of the ARMv8.2 Extensions)
1452 causes the 'unprivileged' variant of the load/store instructions to
1453 be overridden to be privileged.
1455 This option changes get_user() and friends to use the 'unprivileged'
1456 variant of the load/store instructions. This ensures that user-space
1457 really did have access to the supplied memory. When addr_limit is
1458 set to kernel memory the UAO bit will be set, allowing privileged
1459 access to kernel memory.
1461 Choosing this option will cause copy_to_user() et al to use user-space
1464 The feature is detected at runtime, the kernel will use the
1465 regular load/store instructions if the cpu does not implement the
1469 bool "Enable support for persistent memory"
1470 select ARCH_HAS_PMEM_API
1471 select ARCH_HAS_UACCESS_FLUSHCACHE
1473 Say Y to enable support for the persistent memory API based on the
1474 ARMv8.2 DCPoP feature.
1476 The feature is detected at runtime, and the kernel will use DC CVAC
1477 operations if DC CVAP is not supported (following the behaviour of
1478 DC CVAP itself if the system does not define a point of persistence).
1480 config ARM64_RAS_EXTN
1481 bool "Enable support for RAS CPU Extensions"
1484 CPUs that support the Reliability, Availability and Serviceability
1485 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1486 errors, classify them and report them to software.
1488 On CPUs with these extensions system software can use additional
1489 barriers to determine if faults are pending and read the
1490 classification from a new set of registers.
1492 Selecting this feature will allow the kernel to use these barriers
1493 and access the new registers if the system supports the extension.
1494 Platform RAS features may additionally depend on firmware support.
1497 bool "Enable support for Common Not Private (CNP) translations"
1499 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1501 Common Not Private (CNP) allows translation table entries to
1502 be shared between different PEs in the same inner shareable
1503 domain, so the hardware can use this fact to optimise the
1504 caching of such entries in the TLB.
1506 Selecting this option allows the CNP feature to be detected
1507 at runtime, and does not affect PEs that do not implement
1512 menu "ARMv8.3 architectural features"
1514 config ARM64_PTR_AUTH
1515 bool "Enable support for pointer authentication"
1517 depends on !KVM || ARM64_VHE
1518 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1519 # GCC 9.1 and later inserts a .note.gnu.property section note for PAC
1520 # which is only understood by binutils starting with version 2.33.1.
1521 depends on !CC_IS_GCC || GCC_VERSION < 90100 || LD_VERSION >= 233010000
1522 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1523 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1525 Pointer authentication (part of the ARMv8.3 Extensions) provides
1526 instructions for signing and authenticating pointers against secret
1527 keys, which can be used to mitigate Return Oriented Programming (ROP)
1530 This option enables these instructions at EL0 (i.e. for userspace).
1531 Choosing this option will cause the kernel to initialise secret keys
1532 for each process at exec() time, with these keys being
1533 context-switched along with the process.
1535 If the compiler supports the -mbranch-protection or
1536 -msign-return-address flag (e.g. GCC 7 or later), then this option
1537 will also cause the kernel itself to be compiled with return address
1538 protection. In this case, and if the target hardware is known to
1539 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1540 disabled with minimal loss of protection.
1542 The feature is detected at runtime. If the feature is not present in
1543 hardware it will not be advertised to userspace/KVM guest nor will it
1544 be enabled. However, KVM guest also require VHE mode and hence
1545 CONFIG_ARM64_VHE=y option to use this feature.
1547 If the feature is present on the boot CPU but not on a late CPU, then
1548 the late CPU will be parked. Also, if the boot CPU does not have
1549 address auth and the late CPU has then the late CPU will still boot
1550 but with the feature disabled. On such a system, this option should
1553 This feature works with FUNCTION_GRAPH_TRACER option only if
1554 DYNAMIC_FTRACE_WITH_REGS is enabled.
1556 config CC_HAS_BRANCH_PROT_PAC_RET
1557 # GCC 9 or later, clang 8 or later
1558 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1560 config CC_HAS_SIGN_RETURN_ADDRESS
1562 def_bool $(cc-option,-msign-return-address=all)
1565 def_bool $(as-option,-Wa$(comma)-march=armv8.3-a)
1567 config AS_HAS_CFI_NEGATE_RA_STATE
1568 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1572 menu "ARMv8.4 architectural features"
1574 config ARM64_AMU_EXTN
1575 bool "Enable support for the Activity Monitors Unit CPU extension"
1578 The activity monitors extension is an optional extension introduced
1579 by the ARMv8.4 CPU architecture. This enables support for version 1
1580 of the activity monitors architecture, AMUv1.
1582 To enable the use of this extension on CPUs that implement it, say Y.
1584 Note that for architectural reasons, firmware _must_ implement AMU
1585 support when running on CPUs that present the activity monitors
1586 extension. The required support is present in:
1587 * Version 1.5 and later of the ARM Trusted Firmware
1589 For kernels that have this configuration enabled but boot with broken
1590 firmware, you may need to say N here until the firmware is fixed.
1591 Otherwise you may experience firmware panics or lockups when
1592 accessing the counter registers. Even if you are not observing these
1593 symptoms, the values returned by the register reads might not
1594 correctly reflect reality. Most commonly, the value read will be 0,
1595 indicating that the counter is not enabled.
1599 menu "ARMv8.5 architectural features"
1602 bool "Branch Target Identification support"
1605 Branch Target Identification (part of the ARMv8.5 Extensions)
1606 provides a mechanism to limit the set of locations to which computed
1607 branch instructions such as BR or BLR can jump.
1609 To make use of BTI on CPUs that support it, say Y.
1611 BTI is intended to provide complementary protection to other control
1612 flow integrity protection mechanisms, such as the Pointer
1613 authentication mechanism provided as part of the ARMv8.3 Extensions.
1614 For this reason, it does not make sense to enable this option without
1615 also enabling support for pointer authentication. Thus, when
1616 enabling this option you should also select ARM64_PTR_AUTH=y.
1618 Userspace binaries must also be specifically compiled to make use of
1619 this mechanism. If you say N here or the hardware does not support
1620 BTI, such binaries can still run, but you get no additional
1621 enforcement of branch destinations.
1623 config ARM64_BTI_KERNEL
1624 bool "Use Branch Target Identification for kernel"
1626 depends on ARM64_BTI
1627 depends on ARM64_PTR_AUTH
1628 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1629 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1630 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1631 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1632 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1634 Build the kernel with Branch Target Identification annotations
1635 and enable enforcement of this for kernel code. When this option
1636 is enabled and the system supports BTI all kernel code including
1637 modular code must have BTI enabled.
1639 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1640 # GCC 9 or later, clang 8 or later
1641 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1644 bool "Enable support for E0PD"
1647 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1648 that EL0 accesses made via TTBR1 always fault in constant time,
1649 providing similar benefits to KASLR as those provided by KPTI, but
1650 with lower overhead and without disrupting legitimate access to
1651 kernel memory such as SPE.
1653 This option enables E0PD for TTBR1 where available.
1656 bool "Enable support for random number generation"
1659 Random number generation (part of the ARMv8.5 Extensions)
1660 provides a high bandwidth, cryptographically secure
1661 hardware random number generator.
1666 bool "ARM Scalable Vector Extension support"
1668 depends on !KVM || ARM64_VHE
1670 The Scalable Vector Extension (SVE) is an extension to the AArch64
1671 execution state which complements and extends the SIMD functionality
1672 of the base architecture to support much larger vectors and to enable
1673 additional vectorisation opportunities.
1675 To enable use of this extension on CPUs that implement it, say Y.
1677 On CPUs that support the SVE2 extensions, this option will enable
1680 Note that for architectural reasons, firmware _must_ implement SVE
1681 support when running on SVE capable hardware. The required support
1684 * version 1.5 and later of the ARM Trusted Firmware
1685 * the AArch64 boot wrapper since commit 5e1261e08abf
1686 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1688 For other firmware implementations, consult the firmware documentation
1691 If you need the kernel to boot on SVE-capable hardware with broken
1692 firmware, you may need to say N here until you get your firmware
1693 fixed. Otherwise, you may experience firmware panics or lockups when
1694 booting the kernel. If unsure and you are not observing these
1695 symptoms, you should assume that it is safe to say Y.
1697 CPUs that support SVE are architecturally required to support the
1698 Virtualization Host Extensions (VHE), so the kernel makes no
1699 provision for supporting SVE alongside KVM without VHE enabled.
1700 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1701 KVM in the same kernel image.
1703 config ARM64_MODULE_PLTS
1704 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1706 select HAVE_MOD_ARCH_SPECIFIC
1708 Allocate PLTs when loading modules so that jumps and calls whose
1709 targets are too far away for their relative offsets to be encoded
1710 in the instructions themselves can be bounced via veneers in the
1711 module's PLT. This allows modules to be allocated in the generic
1712 vmalloc area after the dedicated module memory area has been
1715 When running with address space randomization (KASLR), the module
1716 region itself may be too far away for ordinary relative jumps and
1717 calls, and so in that case, module PLTs are required and cannot be
1720 Specific errata workaround(s) might also force module PLTs to be
1721 enabled (ARM64_ERRATUM_843419).
1723 config ARM64_PSEUDO_NMI
1724 bool "Support for NMI-like interrupts"
1727 Adds support for mimicking Non-Maskable Interrupts through the use of
1728 GIC interrupt priority. This support requires version 3 or later of
1731 This high priority configuration for interrupts needs to be
1732 explicitly enabled by setting the kernel parameter
1733 "irqchip.gicv3_pseudo_nmi" to 1.
1738 config ARM64_DEBUG_PRIORITY_MASKING
1739 bool "Debug interrupt priority masking"
1741 This adds runtime checks to functions enabling/disabling
1742 interrupts when using priority masking. The additional checks verify
1743 the validity of ICC_PMR_EL1 when calling concerned functions.
1750 select ARCH_HAS_RELR
1752 This builds the kernel as a Position Independent Executable (PIE),
1753 which retains all relocation metadata required to relocate the
1754 kernel binary at runtime to a different virtual address than the
1755 address it was linked at.
1756 Since AArch64 uses the RELA relocation format, this requires a
1757 relocation pass at runtime even if the kernel is loaded at the
1758 same address it was linked at.
1760 config RANDOMIZE_BASE
1761 bool "Randomize the address of the kernel image"
1762 select ARM64_MODULE_PLTS if MODULES
1765 Randomizes the virtual address at which the kernel image is
1766 loaded, as a security feature that deters exploit attempts
1767 relying on knowledge of the location of kernel internals.
1769 It is the bootloader's job to provide entropy, by passing a
1770 random u64 value in /chosen/kaslr-seed at kernel entry.
1772 When booting via the UEFI stub, it will invoke the firmware's
1773 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1774 to the kernel proper. In addition, it will randomise the physical
1775 location of the kernel Image as well.
1779 config RANDOMIZE_MODULE_REGION_FULL
1780 bool "Randomize the module region over a 4 GB range"
1781 depends on RANDOMIZE_BASE
1784 Randomizes the location of the module region inside a 4 GB window
1785 covering the core kernel. This way, it is less likely for modules
1786 to leak information about the location of core kernel data structures
1787 but it does imply that function calls between modules and the core
1788 kernel will need to be resolved via veneers in the module PLT.
1790 When this option is not set, the module region will be randomized over
1791 a limited range that contains the [_stext, _etext] interval of the
1792 core kernel, so branch relocations are always in range.
1794 config CC_HAVE_STACKPROTECTOR_SYSREG
1795 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1797 config STACKPROTECTOR_PER_TASK
1799 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1805 config ARM64_ACPI_PARKING_PROTOCOL
1806 bool "Enable support for the ARM64 ACPI parking protocol"
1809 Enable support for the ARM64 ACPI parking protocol. If disabled
1810 the kernel will not allow booting through the ARM64 ACPI parking
1811 protocol even if the corresponding data is present in the ACPI
1815 string "Default kernel command string"
1818 Provide a set of default command-line options at build time by
1819 entering them here. As a minimum, you should specify the the
1820 root device (e.g. root=/dev/nfs).
1822 config CMDLINE_FORCE
1823 bool "Always use the default kernel command string"
1824 depends on CMDLINE != ""
1826 Always use the default kernel command string, even if the boot
1827 loader passes other arguments to the kernel.
1828 This is useful if you cannot or don't want to change the
1829 command-line options your boot loader passes to the kernel.
1835 bool "UEFI runtime support"
1836 depends on OF && !CPU_BIG_ENDIAN
1837 depends on KERNEL_MODE_NEON
1838 select ARCH_SUPPORTS_ACPI
1841 select EFI_PARAMS_FROM_FDT
1842 select EFI_RUNTIME_WRAPPERS
1847 This option provides support for runtime services provided
1848 by UEFI firmware (such as non-volatile variables, realtime
1849 clock, and platform reset). A UEFI stub is also provided to
1850 allow the kernel to be booted as an EFI application. This
1851 is only useful on systems that have UEFI firmware.
1854 bool "Enable support for SMBIOS (DMI) tables"
1858 This enables SMBIOS/DMI feature for systems.
1860 This option is only useful on systems that have UEFI firmware.
1861 However, even with this option, the resultant kernel should
1862 continue to boot on existing non-UEFI platforms.
1866 config SYSVIPC_COMPAT
1868 depends on COMPAT && SYSVIPC
1870 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1872 depends on HUGETLB_PAGE && MIGRATION
1874 menu "Power management options"
1876 source "kernel/power/Kconfig"
1878 config ARCH_HIBERNATION_POSSIBLE
1882 config ARCH_HIBERNATION_HEADER
1884 depends on HIBERNATION
1886 config ARCH_SUSPEND_POSSIBLE
1891 menu "CPU Power Management"
1893 source "drivers/cpuidle/Kconfig"
1895 source "drivers/cpufreq/Kconfig"
1899 source "drivers/firmware/Kconfig"
1901 source "drivers/acpi/Kconfig"
1903 source "arch/arm64/kvm/Kconfig"
1906 source "arch/arm64/crypto/Kconfig"