1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mm/mmu.c
5 * Copyright (C) 1995-2005 Russell King
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/errno.h>
10 #include <linux/init.h>
11 #include <linux/mman.h>
12 #include <linux/nodemask.h>
13 #include <linux/memblock.h>
15 #include <linux/vmalloc.h>
16 #include <linux/sizes.h>
19 #include <asm/cputype.h>
20 #include <asm/sections.h>
21 #include <asm/cachetype.h>
22 #include <asm/fixmap.h>
23 #include <asm/sections.h>
24 #include <asm/setup.h>
25 #include <asm/smp_plat.h>
27 #include <asm/highmem.h>
28 #include <asm/system_info.h>
29 #include <asm/traps.h>
30 #include <asm/procinfo.h>
31 #include <asm/memory.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/pci.h>
36 #include <asm/fixmap.h>
43 * empty_zero_page is a special page that is used for
44 * zero-initialized data and COW.
46 struct page *empty_zero_page;
47 EXPORT_SYMBOL(empty_zero_page);
50 * The pmd table for the upper-most set of pages.
54 pmdval_t user_pmd_table = _PAGE_USER_TABLE;
56 #define CPOLICY_UNCACHED 0
57 #define CPOLICY_BUFFERED 1
58 #define CPOLICY_WRITETHROUGH 2
59 #define CPOLICY_WRITEBACK 3
60 #define CPOLICY_WRITEALLOC 4
62 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
63 static unsigned int ecc_mask __initdata = 0;
65 pgprot_t pgprot_kernel;
67 EXPORT_SYMBOL(pgprot_user);
68 EXPORT_SYMBOL(pgprot_kernel);
71 const char policy[16];
77 unsigned long kimage_voffset __ro_after_init;
79 static struct cachepolicy cache_policies[] __initdata = {
83 .pmd = PMD_SECT_UNCACHED,
84 .pte = L_PTE_MT_UNCACHED,
88 .pmd = PMD_SECT_BUFFERED,
89 .pte = L_PTE_MT_BUFFERABLE,
91 .policy = "writethrough",
94 .pte = L_PTE_MT_WRITETHROUGH,
96 .policy = "writeback",
99 .pte = L_PTE_MT_WRITEBACK,
101 .policy = "writealloc",
103 .pmd = PMD_SECT_WBWA,
104 .pte = L_PTE_MT_WRITEALLOC,
108 #ifdef CONFIG_CPU_CP15
109 static unsigned long initial_pmd_value __initdata = 0;
112 * Initialise the cache_policy variable with the initial state specified
113 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
114 * the C code sets the page tables up with the same policy as the head
115 * assembly code, which avoids an illegal state where the TLBs can get
116 * confused. See comments in early_cachepolicy() for more information.
118 void __init init_default_cache_policy(unsigned long pmd)
122 initial_pmd_value = pmd;
124 pmd &= PMD_SECT_CACHE_MASK;
126 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
127 if (cache_policies[i].pmd == pmd) {
132 if (i == ARRAY_SIZE(cache_policies))
133 pr_err("ERROR: could not find cache policy\n");
137 * These are useful for identifying cache coherency problems by allowing
138 * the cache or the cache and writebuffer to be turned off. (Note: the
139 * write buffer should not be on and the cache off).
141 static int __init early_cachepolicy(char *p)
143 int i, selected = -1;
145 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
146 int len = strlen(cache_policies[i].policy);
148 if (memcmp(p, cache_policies[i].policy, len) == 0) {
155 pr_err("ERROR: unknown or unsupported cache policy\n");
158 * This restriction is partly to do with the way we boot; it is
159 * unpredictable to have memory mapped using two different sets of
160 * memory attributes (shared, type, and cache attribs). We can not
161 * change these attributes once the initial assembly has setup the
164 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
165 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
166 cache_policies[cachepolicy].policy);
170 if (selected != cachepolicy) {
171 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
172 cachepolicy = selected;
178 early_param("cachepolicy", early_cachepolicy);
180 static int __init early_nocache(char *__unused)
182 char *p = "buffered";
183 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
184 early_cachepolicy(p);
187 early_param("nocache", early_nocache);
189 static int __init early_nowrite(char *__unused)
191 char *p = "uncached";
192 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
193 early_cachepolicy(p);
196 early_param("nowb", early_nowrite);
198 #ifndef CONFIG_ARM_LPAE
199 static int __init early_ecc(char *p)
201 if (memcmp(p, "on", 2) == 0)
202 ecc_mask = PMD_PROTECTION;
203 else if (memcmp(p, "off", 3) == 0)
207 early_param("ecc", early_ecc);
210 #else /* ifdef CONFIG_CPU_CP15 */
212 static int __init early_cachepolicy(char *p)
214 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
216 early_param("cachepolicy", early_cachepolicy);
218 static int __init noalign_setup(char *__unused)
220 pr_warn("noalign kernel parameter not supported without cp15\n");
222 __setup("noalign", noalign_setup);
224 #endif /* ifdef CONFIG_CPU_CP15 / else */
226 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
227 #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
228 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
230 static struct mem_type mem_types[] __ro_after_init = {
231 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
232 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
234 .prot_l1 = PMD_TYPE_TABLE,
235 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
238 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
239 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
240 .prot_l1 = PMD_TYPE_TABLE,
241 .prot_sect = PROT_SECT_DEVICE,
244 [MT_DEVICE_CACHED] = { /* ioremap_cache */
245 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
246 .prot_l1 = PMD_TYPE_TABLE,
247 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
250 [MT_DEVICE_WC] = { /* ioremap_wc */
251 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
252 .prot_l1 = PMD_TYPE_TABLE,
253 .prot_sect = PROT_SECT_DEVICE,
257 .prot_pte = PROT_PTE_DEVICE,
258 .prot_l1 = PMD_TYPE_TABLE,
259 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
263 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
264 .domain = DOMAIN_KERNEL,
266 #ifndef CONFIG_ARM_LPAE
268 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
269 .domain = DOMAIN_KERNEL,
273 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
275 .prot_l1 = PMD_TYPE_TABLE,
276 .domain = DOMAIN_VECTORS,
278 [MT_HIGH_VECTORS] = {
279 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
280 L_PTE_USER | L_PTE_RDONLY,
281 .prot_l1 = PMD_TYPE_TABLE,
282 .domain = DOMAIN_VECTORS,
285 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
286 .prot_l1 = PMD_TYPE_TABLE,
287 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
288 .domain = DOMAIN_KERNEL,
291 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
293 .prot_l1 = PMD_TYPE_TABLE,
294 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
295 .domain = DOMAIN_KERNEL,
298 .prot_sect = PMD_TYPE_SECT,
299 .domain = DOMAIN_KERNEL,
301 [MT_MEMORY_RWX_NONCACHED] = {
302 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
304 .prot_l1 = PMD_TYPE_TABLE,
305 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
306 .domain = DOMAIN_KERNEL,
308 [MT_MEMORY_RW_DTCM] = {
309 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
311 .prot_l1 = PMD_TYPE_TABLE,
312 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
313 .domain = DOMAIN_KERNEL,
315 [MT_MEMORY_RWX_ITCM] = {
316 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
317 .prot_l1 = PMD_TYPE_TABLE,
318 .domain = DOMAIN_KERNEL,
320 [MT_MEMORY_RW_SO] = {
321 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
322 L_PTE_MT_UNCACHED | L_PTE_XN,
323 .prot_l1 = PMD_TYPE_TABLE,
324 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
325 PMD_SECT_UNCACHED | PMD_SECT_XN,
326 .domain = DOMAIN_KERNEL,
328 [MT_MEMORY_DMA_READY] = {
329 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
331 .prot_l1 = PMD_TYPE_TABLE,
332 .domain = DOMAIN_KERNEL,
336 const struct mem_type *get_mem_type(unsigned int type)
338 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
340 EXPORT_SYMBOL(get_mem_type);
342 static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
344 static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
345 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
347 static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
349 return &bm_pte[pte_index(addr)];
352 static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
354 return pte_offset_kernel(dir, addr);
357 static inline pmd_t * __init fixmap_pmd(unsigned long addr)
359 pgd_t *pgd = pgd_offset_k(addr);
360 p4d_t *p4d = p4d_offset(pgd, addr);
361 pud_t *pud = pud_offset(p4d, addr);
362 pmd_t *pmd = pmd_offset(pud, addr);
367 void __init early_fixmap_init(void)
372 * The early fixmap range spans multiple pmds, for which
373 * we are not prepared:
375 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
376 != FIXADDR_TOP >> PMD_SHIFT);
378 pmd = fixmap_pmd(FIXADDR_TOP);
379 pmd_populate_kernel(&init_mm, pmd, bm_pte);
381 pte_offset_fixmap = pte_offset_early_fixmap;
385 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
386 * As a result, this can only be called with preemption disabled, as under
389 void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
391 unsigned long vaddr = __fix_to_virt(idx);
392 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
394 /* Make sure fixmap region does not exceed available allocation. */
395 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
397 BUG_ON(idx >= __end_of_fixed_addresses);
399 /* we only support device mappings until pgprot_kernel has been set */
400 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
401 pgprot_val(pgprot_kernel) == 0))
404 if (pgprot_val(prot))
405 set_pte_at(NULL, vaddr, pte,
406 pfn_pte(phys >> PAGE_SHIFT, prot));
408 pte_clear(NULL, vaddr, pte);
409 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
413 * Adjust the PMD section entries according to the CPU in use.
415 static void __init build_mem_type_table(void)
417 struct cachepolicy *cp;
418 unsigned int cr = get_cr();
419 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
420 int cpu_arch = cpu_architecture();
423 if (cpu_arch < CPU_ARCH_ARMv6) {
424 #if defined(CONFIG_CPU_DCACHE_DISABLE)
425 if (cachepolicy > CPOLICY_BUFFERED)
426 cachepolicy = CPOLICY_BUFFERED;
427 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
428 if (cachepolicy > CPOLICY_WRITETHROUGH)
429 cachepolicy = CPOLICY_WRITETHROUGH;
432 if (cpu_arch < CPU_ARCH_ARMv5) {
433 if (cachepolicy >= CPOLICY_WRITEALLOC)
434 cachepolicy = CPOLICY_WRITEBACK;
439 if (cachepolicy != CPOLICY_WRITEALLOC) {
440 pr_warn("Forcing write-allocate cache policy for SMP\n");
441 cachepolicy = CPOLICY_WRITEALLOC;
443 if (!(initial_pmd_value & PMD_SECT_S)) {
444 pr_warn("Forcing shared mappings for SMP\n");
445 initial_pmd_value |= PMD_SECT_S;
450 * Strip out features not present on earlier architectures.
451 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
452 * without extended page tables don't have the 'Shared' bit.
454 if (cpu_arch < CPU_ARCH_ARMv5)
455 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
456 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
457 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
458 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
459 mem_types[i].prot_sect &= ~PMD_SECT_S;
462 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
463 * "update-able on write" bit on ARM610). However, Xscale and
464 * Xscale3 require this bit to be cleared.
466 if (cpu_is_xscale_family()) {
467 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
468 mem_types[i].prot_sect &= ~PMD_BIT4;
469 mem_types[i].prot_l1 &= ~PMD_BIT4;
471 } else if (cpu_arch < CPU_ARCH_ARMv6) {
472 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
473 if (mem_types[i].prot_l1)
474 mem_types[i].prot_l1 |= PMD_BIT4;
475 if (mem_types[i].prot_sect)
476 mem_types[i].prot_sect |= PMD_BIT4;
481 * Mark the device areas according to the CPU/architecture.
483 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
484 if (!cpu_is_xsc3()) {
486 * Mark device regions on ARMv6+ as execute-never
487 * to prevent speculative instruction fetches.
489 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
490 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
491 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
492 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
494 /* Also setup NX memory mapping */
495 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
497 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
499 * For ARMv7 with TEX remapping,
500 * - shared device is SXCB=1100
501 * - nonshared device is SXCB=0100
502 * - write combine device mem is SXCB=0001
503 * (Uncached Normal memory)
505 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
506 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
507 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
508 } else if (cpu_is_xsc3()) {
511 * - shared device is TEXCB=00101
512 * - nonshared device is TEXCB=01000
513 * - write combine device mem is TEXCB=00100
514 * (Inner/Outer Uncacheable in xsc3 parlance)
516 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
517 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
518 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
521 * For ARMv6 and ARMv7 without TEX remapping,
522 * - shared device is TEXCB=00001
523 * - nonshared device is TEXCB=01000
524 * - write combine device mem is TEXCB=00100
525 * (Uncached Normal in ARMv6 parlance).
527 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
528 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
529 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
533 * On others, write combining is "Uncached/Buffered"
535 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
539 * Now deal with the memory-type mappings
541 cp = &cache_policies[cachepolicy];
542 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
544 #ifndef CONFIG_ARM_LPAE
546 * We don't use domains on ARMv6 (since this causes problems with
547 * v6/v7 kernels), so we must use a separate memory type for user
548 * r/o, kernel r/w to map the vectors page.
550 if (cpu_arch == CPU_ARCH_ARMv6)
551 vecs_pgprot |= L_PTE_MT_VECTORS;
554 * Check is it with support for the PXN bit
555 * in the Short-descriptor translation table format descriptors.
557 if (cpu_arch == CPU_ARCH_ARMv7 &&
558 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
559 user_pmd_table |= PMD_PXNTABLE;
564 * ARMv6 and above have extended page tables.
566 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
567 #ifndef CONFIG_ARM_LPAE
569 * Mark cache clean areas and XIP ROM read only
570 * from SVC mode and no access from userspace.
572 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
573 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
574 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
578 * If the initial page tables were created with the S bit
579 * set, then we need to do the same here for the same
580 * reasons given in early_cachepolicy().
582 if (initial_pmd_value & PMD_SECT_S) {
583 user_pgprot |= L_PTE_SHARED;
584 kern_pgprot |= L_PTE_SHARED;
585 vecs_pgprot |= L_PTE_SHARED;
586 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
587 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
588 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
589 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
590 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
591 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
592 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
593 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
594 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
595 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
596 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
601 * Non-cacheable Normal - intended for memory areas that must
602 * not cause dirty cache line writebacks when used
604 if (cpu_arch >= CPU_ARCH_ARMv6) {
605 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
606 /* Non-cacheable Normal is XCB = 001 */
607 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
610 /* For both ARMv6 and non-TEX-remapping ARMv7 */
611 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
615 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
618 #ifdef CONFIG_ARM_LPAE
620 * Do not generate access flag faults for the kernel mappings.
622 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
623 mem_types[i].prot_pte |= PTE_EXT_AF;
624 if (mem_types[i].prot_sect)
625 mem_types[i].prot_sect |= PMD_SECT_AF;
627 kern_pgprot |= PTE_EXT_AF;
628 vecs_pgprot |= PTE_EXT_AF;
631 * Set PXN for user mappings
633 user_pgprot |= PTE_EXT_PXN;
636 for (i = 0; i < 16; i++) {
637 pteval_t v = pgprot_val(protection_map[i]);
638 protection_map[i] = __pgprot(v | user_pgprot);
641 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
642 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
644 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
645 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
646 L_PTE_DIRTY | kern_pgprot);
648 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
649 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
650 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
651 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
652 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
653 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
654 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
655 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
656 mem_types[MT_ROM].prot_sect |= cp->pmd;
660 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
664 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
667 pr_info("Memory policy: %sData cache %s\n",
668 ecc_mask ? "ECC enabled, " : "", cp->policy);
670 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
671 struct mem_type *t = &mem_types[i];
673 t->prot_l1 |= PMD_DOMAIN(t->domain);
675 t->prot_sect |= PMD_DOMAIN(t->domain);
679 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
680 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
681 unsigned long size, pgprot_t vma_prot)
684 return pgprot_noncached(vma_prot);
685 else if (file->f_flags & O_SYNC)
686 return pgprot_writecombine(vma_prot);
689 EXPORT_SYMBOL(phys_mem_access_prot);
692 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
694 static void __init *early_alloc(unsigned long sz)
696 void *ptr = memblock_alloc(sz, sz);
699 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
705 static void *__init late_alloc(unsigned long sz)
707 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
709 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr)))
714 static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
716 void *(*alloc)(unsigned long sz))
718 if (pmd_none(*pmd)) {
719 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
720 __pmd_populate(pmd, __pa(pte), prot);
722 BUG_ON(pmd_bad(*pmd));
723 return pte_offset_kernel(pmd, addr);
726 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
729 return arm_pte_alloc(pmd, addr, prot, early_alloc);
732 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
733 unsigned long end, unsigned long pfn,
734 const struct mem_type *type,
735 void *(*alloc)(unsigned long sz),
738 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
740 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
741 ng ? PTE_EXT_NG : 0);
743 } while (pte++, addr += PAGE_SIZE, addr != end);
746 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
747 unsigned long end, phys_addr_t phys,
748 const struct mem_type *type, bool ng)
752 #ifndef CONFIG_ARM_LPAE
754 * In classic MMU format, puds and pmds are folded in to
755 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
756 * group of L1 entries making up one logical pointer to
757 * an L2 table (2MB), where as PMDs refer to the individual
758 * L1 entries (1MB). Hence increment to get the correct
759 * offset for odd 1MB sections.
760 * (See arch/arm/include/asm/pgtable-2level.h)
762 if (addr & SECTION_SIZE)
766 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
767 phys += SECTION_SIZE;
768 } while (pmd++, addr += SECTION_SIZE, addr != end);
773 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
774 unsigned long end, phys_addr_t phys,
775 const struct mem_type *type,
776 void *(*alloc)(unsigned long sz), bool ng)
778 pmd_t *pmd = pmd_offset(pud, addr);
783 * With LPAE, we must loop over to map
784 * all the pmds for the given range.
786 next = pmd_addr_end(addr, end);
789 * Try a section mapping - addr, next and phys must all be
790 * aligned to a section boundary.
792 if (type->prot_sect &&
793 ((addr | next | phys) & ~SECTION_MASK) == 0) {
794 __map_init_section(pmd, addr, next, phys, type, ng);
796 alloc_init_pte(pmd, addr, next,
797 __phys_to_pfn(phys), type, alloc, ng);
802 } while (pmd++, addr = next, addr != end);
805 static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr,
806 unsigned long end, phys_addr_t phys,
807 const struct mem_type *type,
808 void *(*alloc)(unsigned long sz), bool ng)
810 pud_t *pud = pud_offset(p4d, addr);
814 next = pud_addr_end(addr, end);
815 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
817 } while (pud++, addr = next, addr != end);
820 static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr,
821 unsigned long end, phys_addr_t phys,
822 const struct mem_type *type,
823 void *(*alloc)(unsigned long sz), bool ng)
825 p4d_t *p4d = p4d_offset(pgd, addr);
829 next = p4d_addr_end(addr, end);
830 alloc_init_pud(p4d, addr, next, phys, type, alloc, ng);
832 } while (p4d++, addr = next, addr != end);
835 #ifndef CONFIG_ARM_LPAE
836 static void __init create_36bit_mapping(struct mm_struct *mm,
838 const struct mem_type *type,
841 unsigned long addr, length, end;
846 phys = __pfn_to_phys(md->pfn);
847 length = PAGE_ALIGN(md->length);
849 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
850 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
851 (long long)__pfn_to_phys((u64)md->pfn), addr);
855 /* N.B. ARMv6 supersections are only defined to work with domain 0.
856 * Since domain assignments can in fact be arbitrary, the
857 * 'domain == 0' check below is required to insure that ARMv6
858 * supersections are only allocated for domain 0 regardless
859 * of the actual domain assignments in use.
862 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
863 (long long)__pfn_to_phys((u64)md->pfn), addr);
867 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
868 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
869 (long long)__pfn_to_phys((u64)md->pfn), addr);
874 * Shift bits [35:32] of address into bits [23:20] of PMD
877 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
879 pgd = pgd_offset(mm, addr);
882 p4d_t *p4d = p4d_offset(pgd, addr);
883 pud_t *pud = pud_offset(p4d, addr);
884 pmd_t *pmd = pmd_offset(pud, addr);
887 for (i = 0; i < 16; i++)
888 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
889 (ng ? PMD_SECT_nG : 0));
891 addr += SUPERSECTION_SIZE;
892 phys += SUPERSECTION_SIZE;
893 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
894 } while (addr != end);
896 #endif /* !CONFIG_ARM_LPAE */
898 static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
899 void *(*alloc)(unsigned long sz),
902 unsigned long addr, length, end;
904 const struct mem_type *type;
907 type = &mem_types[md->type];
909 #ifndef CONFIG_ARM_LPAE
911 * Catch 36-bit addresses
913 if (md->pfn >= 0x100000) {
914 create_36bit_mapping(mm, md, type, ng);
919 addr = md->virtual & PAGE_MASK;
920 phys = __pfn_to_phys(md->pfn);
921 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
923 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
924 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
925 (long long)__pfn_to_phys(md->pfn), addr);
929 pgd = pgd_offset(mm, addr);
932 unsigned long next = pgd_addr_end(addr, end);
934 alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng);
938 } while (pgd++, addr != end);
942 * Create the page directory entries and any necessary
943 * page tables for the mapping specified by `md'. We
944 * are able to cope here with varying sizes and address
945 * offsets, and we take full advantage of sections and
948 static void __init create_mapping(struct map_desc *md)
950 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
951 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
952 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
956 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
957 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
958 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
959 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
960 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
963 __create_mapping(&init_mm, md, early_alloc, false);
966 void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
969 #ifdef CONFIG_ARM_LPAE
973 p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
976 pud = pud_alloc(mm, p4d, md->virtual);
979 pmd_alloc(mm, pud, 0);
981 __create_mapping(mm, md, late_alloc, ng);
985 * Create the architecture specific mappings
987 void __init iotable_init(struct map_desc *io_desc, int nr)
990 struct vm_struct *vm;
991 struct static_vm *svm;
996 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
998 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
999 __func__, sizeof(*svm) * nr, __alignof__(*svm));
1001 for (md = io_desc; nr; md++, nr--) {
1005 vm->addr = (void *)(md->virtual & PAGE_MASK);
1006 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1007 vm->phys_addr = __pfn_to_phys(md->pfn);
1008 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1009 vm->flags |= VM_ARM_MTYPE(md->type);
1010 vm->caller = iotable_init;
1011 add_static_vm_early(svm++);
1015 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1018 struct vm_struct *vm;
1019 struct static_vm *svm;
1021 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
1023 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1024 __func__, sizeof(*svm), __alignof__(*svm));
1027 vm->addr = (void *)addr;
1029 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1030 vm->caller = caller;
1031 add_static_vm_early(svm);
1034 #ifndef CONFIG_ARM_LPAE
1037 * The Linux PMD is made of two consecutive section entries covering 2MB
1038 * (see definition in include/asm/pgtable-2level.h). However a call to
1039 * create_mapping() may optimize static mappings by using individual
1040 * 1MB section mappings. This leaves the actual PMD potentially half
1041 * initialized if the top or bottom section entry isn't used, leaving it
1042 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1043 * the virtual space left free by that unused section entry.
1045 * Let's avoid the issue by inserting dummy vm entries covering the unused
1046 * PMD halves once the static mappings are in place.
1049 static void __init pmd_empty_section_gap(unsigned long addr)
1051 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1054 static void __init fill_pmd_gaps(void)
1056 struct static_vm *svm;
1057 struct vm_struct *vm;
1058 unsigned long addr, next = 0;
1061 list_for_each_entry(svm, &static_vmlist, list) {
1063 addr = (unsigned long)vm->addr;
1068 * Check if this vm starts on an odd section boundary.
1069 * If so and the first section entry for this PMD is free
1070 * then we block the corresponding virtual address.
1072 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1073 pmd = pmd_off_k(addr);
1075 pmd_empty_section_gap(addr & PMD_MASK);
1079 * Then check if this vm ends on an odd section boundary.
1080 * If so and the second section entry for this PMD is empty
1081 * then we block the corresponding virtual address.
1084 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1085 pmd = pmd_off_k(addr) + 1;
1087 pmd_empty_section_gap(addr);
1090 /* no need to look at any vm entry until we hit the next PMD */
1091 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1096 #define fill_pmd_gaps() do { } while (0)
1099 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1100 static void __init pci_reserve_io(void)
1102 struct static_vm *svm;
1104 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1108 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1111 #define pci_reserve_io() do { } while (0)
1114 #ifdef CONFIG_DEBUG_LL
1115 void __init debug_ll_io_init(void)
1117 struct map_desc map;
1119 debug_ll_addr(&map.pfn, &map.virtual);
1120 if (!map.pfn || !map.virtual)
1122 map.pfn = __phys_to_pfn(map.pfn);
1123 map.virtual &= PAGE_MASK;
1124 map.length = PAGE_SIZE;
1125 map.type = MT_DEVICE;
1126 iotable_init(&map, 1);
1130 static void * __initdata vmalloc_min =
1131 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1134 * vmalloc=size forces the vmalloc area to be exactly 'size'
1135 * bytes. This can be used to increase (or decrease) the vmalloc
1136 * area - the default is 240m.
1138 static int __init early_vmalloc(char *arg)
1140 unsigned long vmalloc_reserve = memparse(arg, NULL);
1142 if (vmalloc_reserve < SZ_16M) {
1143 vmalloc_reserve = SZ_16M;
1144 pr_warn("vmalloc area too small, limiting to %luMB\n",
1145 vmalloc_reserve >> 20);
1148 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1149 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1150 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1151 vmalloc_reserve >> 20);
1154 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1157 early_param("vmalloc", early_vmalloc);
1159 phys_addr_t arm_lowmem_limit __initdata = 0;
1161 void __init adjust_lowmem_bounds(void)
1163 phys_addr_t memblock_limit = 0;
1165 struct memblock_region *reg;
1166 phys_addr_t lowmem_limit = 0;
1169 * Let's use our own (unoptimized) equivalent of __pa() that is
1170 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1171 * The result is used as the upper bound on physical memory address
1172 * and may itself be outside the valid range for which phys_addr_t
1173 * and therefore __pa() is defined.
1175 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET;
1178 * The first usable region must be PMD aligned. Mark its start
1179 * as MEMBLOCK_NOMAP if it isn't
1181 for_each_memblock(memory, reg) {
1182 if (!memblock_is_nomap(reg)) {
1183 if (!IS_ALIGNED(reg->base, PMD_SIZE)) {
1186 len = round_up(reg->base, PMD_SIZE) - reg->base;
1187 memblock_mark_nomap(reg->base, len);
1193 for_each_memblock(memory, reg) {
1194 phys_addr_t block_start = reg->base;
1195 phys_addr_t block_end = reg->base + reg->size;
1197 if (memblock_is_nomap(reg))
1200 if (reg->base < vmalloc_limit) {
1201 if (block_end > lowmem_limit)
1203 * Compare as u64 to ensure vmalloc_limit does
1204 * not get truncated. block_end should always
1205 * fit in phys_addr_t so there should be no
1206 * issue with assignment.
1208 lowmem_limit = min_t(u64,
1213 * Find the first non-pmd-aligned page, and point
1214 * memblock_limit at it. This relies on rounding the
1215 * limit down to be pmd-aligned, which happens at the
1216 * end of this function.
1218 * With this algorithm, the start or end of almost any
1219 * bank can be non-pmd-aligned. The only exception is
1220 * that the start of the bank 0 must be section-
1221 * aligned, since otherwise memory would need to be
1222 * allocated when mapping the start of bank 0, which
1223 * occurs before any free memory is mapped.
1225 if (!memblock_limit) {
1226 if (!IS_ALIGNED(block_start, PMD_SIZE))
1227 memblock_limit = block_start;
1228 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1229 memblock_limit = lowmem_limit;
1235 arm_lowmem_limit = lowmem_limit;
1237 high_memory = __va(arm_lowmem_limit - 1) + 1;
1239 if (!memblock_limit)
1240 memblock_limit = arm_lowmem_limit;
1243 * Round the memblock limit down to a pmd size. This
1244 * helps to ensure that we will allocate memory from the
1245 * last full pmd, which should be mapped.
1247 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1249 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1250 if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1251 phys_addr_t end = memblock_end_of_DRAM();
1253 pr_notice("Ignoring RAM at %pa-%pa\n",
1254 &memblock_limit, &end);
1255 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1257 memblock_remove(memblock_limit, end - memblock_limit);
1261 memblock_set_current_limit(memblock_limit);
1264 static inline void prepare_page_table(void)
1270 * Clear out all the mappings below the kernel image.
1272 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1273 pmd_clear(pmd_off_k(addr));
1275 #ifdef CONFIG_XIP_KERNEL
1276 /* The XIP kernel is mapped in the module area -- skip over it */
1277 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1279 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1280 pmd_clear(pmd_off_k(addr));
1283 * Find the end of the first block of lowmem.
1285 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1286 if (end >= arm_lowmem_limit)
1287 end = arm_lowmem_limit;
1290 * Clear out all the kernel space mappings, except for the first
1291 * memory bank, up to the vmalloc region.
1293 for (addr = __phys_to_virt(end);
1294 addr < VMALLOC_START; addr += PMD_SIZE)
1295 pmd_clear(pmd_off_k(addr));
1298 #ifdef CONFIG_ARM_LPAE
1299 /* the first page is reserved for pgd */
1300 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1301 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1303 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1307 * Reserve the special regions of memory
1309 void __init arm_mm_memblock_reserve(void)
1312 * Reserve the page tables. These are already in use,
1313 * and can only be in node 0.
1315 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1317 #ifdef CONFIG_SA1111
1319 * Because of the SA1111 DMA bug, we want to preserve our
1320 * precious DMA-able memory...
1322 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1327 * Set up the device mappings. Since we clear out the page tables for all
1328 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1329 * device mappings. This means earlycon can be used to debug this function
1330 * Any other function or debugging method which may touch any device _will_
1333 static void __init devicemaps_init(const struct machine_desc *mdesc)
1335 struct map_desc map;
1340 * Allocate the vector page early.
1342 vectors = early_alloc(PAGE_SIZE * 2);
1344 early_trap_init(vectors);
1347 * Clear page table except top pmd used by early fixmaps
1349 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1350 pmd_clear(pmd_off_k(addr));
1353 * Map the kernel if it is XIP.
1354 * It is always first in the modulearea.
1356 #ifdef CONFIG_XIP_KERNEL
1357 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1358 map.virtual = MODULES_VADDR;
1359 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1361 create_mapping(&map);
1365 * Map the cache flushing regions.
1368 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1369 map.virtual = FLUSH_BASE;
1371 map.type = MT_CACHECLEAN;
1372 create_mapping(&map);
1374 #ifdef FLUSH_BASE_MINICACHE
1375 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1376 map.virtual = FLUSH_BASE_MINICACHE;
1378 map.type = MT_MINICLEAN;
1379 create_mapping(&map);
1383 * Create a mapping for the machine vectors at the high-vectors
1384 * location (0xffff0000). If we aren't using high-vectors, also
1385 * create a mapping at the low-vectors virtual address.
1387 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1388 map.virtual = 0xffff0000;
1389 map.length = PAGE_SIZE;
1390 #ifdef CONFIG_KUSER_HELPERS
1391 map.type = MT_HIGH_VECTORS;
1393 map.type = MT_LOW_VECTORS;
1395 create_mapping(&map);
1397 if (!vectors_high()) {
1399 map.length = PAGE_SIZE * 2;
1400 map.type = MT_LOW_VECTORS;
1401 create_mapping(&map);
1404 /* Now create a kernel read-only mapping */
1406 map.virtual = 0xffff0000 + PAGE_SIZE;
1407 map.length = PAGE_SIZE;
1408 map.type = MT_LOW_VECTORS;
1409 create_mapping(&map);
1412 * Ask the machine support to map in the statically mapped devices.
1420 /* Reserve fixed i/o space in VMALLOC region */
1424 * Finally flush the caches and tlb to ensure that we're in a
1425 * consistent state wrt the writebuffer. This also ensures that
1426 * any write-allocated cache lines in the vector page are written
1427 * back. After this point, we can start to touch devices again.
1429 local_flush_tlb_all();
1432 /* Enable asynchronous aborts */
1436 static void __init kmap_init(void)
1438 #ifdef CONFIG_HIGHMEM
1439 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1440 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1443 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1444 _PAGE_KERNEL_TABLE);
1447 static void __init map_lowmem(void)
1449 struct memblock_region *reg;
1450 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
1451 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1453 /* Map all the lowmem memory banks. */
1454 for_each_memblock(memory, reg) {
1455 phys_addr_t start = reg->base;
1456 phys_addr_t end = start + reg->size;
1457 struct map_desc map;
1459 if (memblock_is_nomap(reg))
1462 if (end > arm_lowmem_limit)
1463 end = arm_lowmem_limit;
1467 if (end < kernel_x_start) {
1468 map.pfn = __phys_to_pfn(start);
1469 map.virtual = __phys_to_virt(start);
1470 map.length = end - start;
1471 map.type = MT_MEMORY_RWX;
1473 create_mapping(&map);
1474 } else if (start >= kernel_x_end) {
1475 map.pfn = __phys_to_pfn(start);
1476 map.virtual = __phys_to_virt(start);
1477 map.length = end - start;
1478 map.type = MT_MEMORY_RW;
1480 create_mapping(&map);
1482 /* This better cover the entire kernel */
1483 if (start < kernel_x_start) {
1484 map.pfn = __phys_to_pfn(start);
1485 map.virtual = __phys_to_virt(start);
1486 map.length = kernel_x_start - start;
1487 map.type = MT_MEMORY_RW;
1489 create_mapping(&map);
1492 map.pfn = __phys_to_pfn(kernel_x_start);
1493 map.virtual = __phys_to_virt(kernel_x_start);
1494 map.length = kernel_x_end - kernel_x_start;
1495 map.type = MT_MEMORY_RWX;
1497 create_mapping(&map);
1499 if (kernel_x_end < end) {
1500 map.pfn = __phys_to_pfn(kernel_x_end);
1501 map.virtual = __phys_to_virt(kernel_x_end);
1502 map.length = end - kernel_x_end;
1503 map.type = MT_MEMORY_RW;
1505 create_mapping(&map);
1511 #ifdef CONFIG_ARM_PV_FIXUP
1512 extern unsigned long __atags_pointer;
1513 typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
1514 pgtables_remap lpae_pgtables_remap_asm;
1517 * early_paging_init() recreates boot time page table setup, allowing machines
1518 * to switch over to a high (>4G) address space on LPAE systems
1520 static void __init early_paging_init(const struct machine_desc *mdesc)
1522 pgtables_remap *lpae_pgtables_remap;
1523 unsigned long pa_pgd;
1524 unsigned int cr, ttbcr;
1528 if (!mdesc->pv_fixup)
1531 offset = mdesc->pv_fixup();
1536 * Get the address of the remap function in the 1:1 identity
1537 * mapping setup by the early page table assembly code. We
1538 * must get this prior to the pv update. The following barrier
1539 * ensures that this is complete before we fixup any P:V offsets.
1541 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1542 pa_pgd = __pa(swapper_pg_dir);
1543 boot_data = __va(__atags_pointer);
1546 pr_info("Switching physical address space to 0x%08llx\n",
1547 (u64)PHYS_OFFSET + offset);
1549 /* Re-set the phys pfn offset, and the pv offset */
1550 __pv_offset += offset;
1551 __pv_phys_pfn_offset += PFN_DOWN(offset);
1553 /* Run the patch stub to update the constants */
1554 fixup_pv_table(&__pv_table_begin,
1555 (&__pv_table_end - &__pv_table_begin) << 2);
1558 * We changing not only the virtual to physical mapping, but also
1559 * the physical addresses used to access memory. We need to flush
1560 * all levels of cache in the system with caching disabled to
1561 * ensure that all data is written back, and nothing is prefetched
1562 * into the caches. We also need to prevent the TLB walkers
1563 * allocating into the caches too. Note that this is ARMv7 LPAE
1567 set_cr(cr & ~(CR_I | CR_C));
1568 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1569 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1570 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1574 * Fixup the page tables - this must be in the idmap region as
1575 * we need to disable the MMU to do this safely, and hence it
1576 * needs to be assembly. It's fairly simple, as we're using the
1577 * temporary tables setup by the initial assembly code.
1579 lpae_pgtables_remap(offset, pa_pgd, boot_data);
1581 /* Re-enable the caches and cacheable TLB walks */
1582 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1588 static void __init early_paging_init(const struct machine_desc *mdesc)
1592 if (!mdesc->pv_fixup)
1595 offset = mdesc->pv_fixup();
1599 pr_crit("Physical address space modification is only to support Keystone2.\n");
1600 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1601 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1602 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1607 static void __init early_fixmap_shutdown(void)
1610 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1612 pte_offset_fixmap = pte_offset_late_fixmap;
1613 pmd_clear(fixmap_pmd(va));
1614 local_flush_tlb_kernel_page(va);
1616 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1618 struct map_desc map;
1620 map.virtual = fix_to_virt(i);
1621 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1623 /* Only i/o device mappings are supported ATM */
1624 if (pte_none(*pte) ||
1625 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1628 map.pfn = pte_pfn(*pte);
1629 map.type = MT_DEVICE;
1630 map.length = PAGE_SIZE;
1632 create_mapping(&map);
1637 * paging_init() sets up the page tables, initialises the zone memory
1638 * maps, and sets up the zero page, bad page and bad page tables.
1640 void __init paging_init(const struct machine_desc *mdesc)
1644 prepare_page_table();
1646 memblock_set_current_limit(arm_lowmem_limit);
1647 dma_contiguous_remap();
1648 early_fixmap_shutdown();
1649 devicemaps_init(mdesc);
1653 top_pmd = pmd_off_k(0xffff0000);
1655 /* allocate the zero page. */
1656 zero_page = early_alloc(PAGE_SIZE);
1660 empty_zero_page = virt_to_page(zero_page);
1661 __flush_dcache_page(NULL, empty_zero_page);
1663 /* Compute the virt/idmap offset, mostly for the sake of KVM */
1664 kimage_voffset = (unsigned long)&kimage_voffset - virt_to_idmap(&kimage_voffset);
1667 void __init early_mm_init(const struct machine_desc *mdesc)
1669 build_mem_type_table();
1670 early_paging_init(mdesc);
1673 void set_pte_at(struct mm_struct *mm, unsigned long addr,
1674 pte_t *ptep, pte_t pteval)
1676 unsigned long ext = 0;
1678 if (addr < TASK_SIZE && pte_valid_user(pteval)) {
1679 if (!pte_special(pteval))
1680 __sync_icache_dcache(pteval);
1684 set_pte_ext(ptep, pteval, ext);