arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18
  19 #include "omap_hwmod.h"
  20 #include "wd_timer.h"
  21 #include "cm33xx.h"
  22 #include "prm33xx.h"
  23 #include "omap_hwmod_33xx_43xx_common_data.h"
  24 #include "prcm43xx.h"
  25 #include "common.h"
  26
  27 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  28 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  29 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  30 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
  31
  32 /*
  33  * 'l3' class
  34  * instance(s): l3_main, l3_s, l3_instr
  35  */
  36 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  37         .name           = "l3",
  38 };
  39
  40 struct omap_hwmod am33xx_l3_main_hwmod = {
  41         .name           = "l3_main",
  42         .class          = &am33xx_l3_hwmod_class,
  43         .clkdm_name     = "l3_clkdm",
  44         .flags          = HWMOD_INIT_NO_IDLE,
  45         .main_clk       = "l3_gclk",
  46         .prcm           = {
  47                 .omap4  = {
  48                         .modulemode     = MODULEMODE_SWCTRL,
  49                 },
  50         },
  51 };
  52
  53 /* l3_s */
  54 struct omap_hwmod am33xx_l3_s_hwmod = {
  55         .name           = "l3_s",
  56         .class          = &am33xx_l3_hwmod_class,
  57         .clkdm_name     = "l3s_clkdm",
  58 };
  59
  60 /* l3_instr */
  61 struct omap_hwmod am33xx_l3_instr_hwmod = {
  62         .name           = "l3_instr",
  63         .class          = &am33xx_l3_hwmod_class,
  64         .clkdm_name     = "l3_clkdm",
  65         .flags          = HWMOD_INIT_NO_IDLE,
  66         .main_clk       = "l3_gclk",
  67         .prcm           = {
  68                 .omap4  = {
  69                         .modulemode     = MODULEMODE_SWCTRL,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'l4' class
  76  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  77  */
  78 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  79         .name           = "l4",
  80 };
  81
  82 /* l4_ls */
  83 struct omap_hwmod am33xx_l4_ls_hwmod = {
  84         .name           = "l4_ls",
  85         .class          = &am33xx_l4_hwmod_class,
  86         .clkdm_name     = "l4ls_clkdm",
  87         .flags          = HWMOD_INIT_NO_IDLE,
  88         .main_clk       = "l4ls_gclk",
  89         .prcm           = {
  90                 .omap4  = {
  91                         .modulemode     = MODULEMODE_SWCTRL,
  92                 },
  93         },
  94 };
  95
  96 /* l4_wkup */
  97 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  98         .name           = "l4_wkup",
  99         .class          = &am33xx_l4_hwmod_class,
 100         .clkdm_name     = "l4_wkup_clkdm",
 101         .flags          = HWMOD_INIT_NO_IDLE,
 102         .prcm           = {
 103                 .omap4  = {
 104                         .modulemode     = MODULEMODE_SWCTRL,
 105                 },
 106         },
 107 };
 108
 109 /*
 110  * 'mpu' class
 111  */
 112 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 113         .name   = "mpu",
 114 };
 115
 116 struct omap_hwmod am33xx_mpu_hwmod = {
 117         .name           = "mpu",
 118         .class          = &am33xx_mpu_hwmod_class,
 119         .clkdm_name     = "mpu_clkdm",
 120         .flags          = HWMOD_INIT_NO_IDLE,
 121         .main_clk       = "dpll_mpu_m2_ck",
 122         .prcm           = {
 123                 .omap4  = {
 124                         .modulemode     = MODULEMODE_SWCTRL,
 125                 },
 126         },
 127 };
 128
 129 /*
 130  * 'wakeup m3' class
 131  * Wakeup controller sub-system under wakeup domain
 132  */
 133 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 134         .name           = "wkup_m3",
 135 };
 136
 137 /*
 138  * 'pru-icss' class
 139  * Programmable Real-Time Unit and Industrial Communication Subsystem
 140  */
 141 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 142         .name   = "pruss",
 143 };
 144
 145 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 146         { .name = "pruss", .rst_shift = 1 },
 147 };
 148
 149 /* pru-icss */
 150 /* Pseudo hwmod for reset control purpose only */
 151 struct omap_hwmod am33xx_pruss_hwmod = {
 152         .name           = "pruss",
 153         .class          = &am33xx_pruss_hwmod_class,
 154         .clkdm_name     = "pruss_ocp_clkdm",
 155         .main_clk       = "pruss_ocp_gclk",
 156         .prcm           = {
 157                 .omap4  = {
 158                         .modulemode     = MODULEMODE_SWCTRL,
 159                 },
 160         },
 161         .rst_lines      = am33xx_pruss_resets,
 162         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 163 };
 164
 165 /* gfx */
 166 /* Pseudo hwmod for reset control purpose only */
 167 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 168         .name   = "gfx",
 169 };
 170
 171 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 172         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 173 };
 174
 175 struct omap_hwmod am33xx_gfx_hwmod = {
 176         .name           = "gfx",
 177         .class          = &am33xx_gfx_hwmod_class,
 178         .clkdm_name     = "gfx_l3_clkdm",
 179         .main_clk       = "gfx_fck_div_ck",
 180         .prcm           = {
 181                 .omap4  = {
 182                         .modulemode     = MODULEMODE_SWCTRL,
 183                 },
 184         },
 185         .rst_lines      = am33xx_gfx_resets,
 186         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 187 };
 188
 189 /*
 190  * 'prcm' class
 191  * power and reset manager (whole prcm infrastructure)
 192  */
 193 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 194         .name   = "prcm",
 195 };
 196
 197 /* prcm */
 198 struct omap_hwmod am33xx_prcm_hwmod = {
 199         .name           = "prcm",
 200         .class          = &am33xx_prcm_hwmod_class,
 201         .clkdm_name     = "l4_wkup_clkdm",
 202 };
 203
 204 /*
 205  * 'emif' class
 206  * instance(s): emif
 207  */
 208 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 209         .rev_offs       = 0x0000,
 210 };
 211
 212 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 213         .name           = "emif",
 214         .sysc           = &am33xx_emif_sysc,
 215 };
 216
 217 /*
 218  * 'aes0' class
 219  */
 220 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 221         .rev_offs       = 0x80,
 222         .sysc_offs      = 0x84,
 223         .syss_offs      = 0x88,
 224         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 225 };
 226
 227 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 228         .name           = "aes0",
 229         .sysc           = &am33xx_aes0_sysc,
 230 };
 231
 232 struct omap_hwmod am33xx_aes0_hwmod = {
 233         .name           = "aes",
 234         .class          = &am33xx_aes0_hwmod_class,
 235         .clkdm_name     = "l3_clkdm",
 236         .main_clk       = "aes0_fck",
 237         .prcm           = {
 238                 .omap4  = {
 239                         .modulemode     = MODULEMODE_SWCTRL,
 240                 },
 241         },
 242 };
 243
 244 /* sha0 HIB2 (the 'P' (public) device) */
 245 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 246         .rev_offs       = 0x100,
 247         .sysc_offs      = 0x110,
 248         .syss_offs      = 0x114,
 249         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 250 };
 251
 252 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 253         .name           = "sha0",
 254         .sysc           = &am33xx_sha0_sysc,
 255 };
 256
 257 struct omap_hwmod am33xx_sha0_hwmod = {
 258         .name           = "sham",
 259         .class          = &am33xx_sha0_hwmod_class,
 260         .clkdm_name     = "l3_clkdm",
 261         .main_clk       = "l3_gclk",
 262         .prcm           = {
 263                 .omap4  = {
 264                         .modulemode     = MODULEMODE_SWCTRL,
 265                 },
 266         },
 267 };
 268
 269 /* rng */
 270 static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
 271         .rev_offs       = 0x1fe0,
 272         .sysc_offs      = 0x1fe4,
 273         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
 274         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
 275         .sysc_fields    = &omap_hwmod_sysc_type1,
 276 };
 277
 278 static struct omap_hwmod_class am33xx_rng_hwmod_class = {
 279         .name           = "rng",
 280         .sysc           = &am33xx_rng_sysc,
 281 };
 282
 283 struct omap_hwmod am33xx_rng_hwmod = {
 284         .name           = "rng",
 285         .class          = &am33xx_rng_hwmod_class,
 286         .clkdm_name     = "l4ls_clkdm",
 287         .flags          = HWMOD_SWSUP_SIDLE,
 288         .main_clk       = "rng_fck",
 289         .prcm           = {
 290                 .omap4  = {
 291                         .modulemode     = MODULEMODE_SWCTRL,
 292                 },
 293         },
 294 };
 295
 296 /* ocmcram */
 297 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 298         .name = "ocmcram",
 299 };
 300
 301 struct omap_hwmod am33xx_ocmcram_hwmod = {
 302         .name           = "ocmcram",
 303         .class          = &am33xx_ocmcram_hwmod_class,
 304         .clkdm_name     = "l3_clkdm",
 305         .flags          = HWMOD_INIT_NO_IDLE,
 306         .main_clk       = "l3_gclk",
 307         .prcm           = {
 308                 .omap4  = {
 309                         .modulemode     = MODULEMODE_SWCTRL,
 310                 },
 311         },
 312 };
 313
 314 /* 'smartreflex' class */
 315 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 316         .name           = "smartreflex",
 317 };
 318
 319 /* smartreflex0 */
 320 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 321         .name           = "smartreflex0",
 322         .class          = &am33xx_smartreflex_hwmod_class,
 323         .clkdm_name     = "l4_wkup_clkdm",
 324         .main_clk       = "smartreflex0_fck",
 325         .prcm           = {
 326                 .omap4  = {
 327                         .modulemode     = MODULEMODE_SWCTRL,
 328                 },
 329         },
 330 };
 331
 332 /* smartreflex1 */
 333 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 334         .name           = "smartreflex1",
 335         .class          = &am33xx_smartreflex_hwmod_class,
 336         .clkdm_name     = "l4_wkup_clkdm",
 337         .main_clk       = "smartreflex1_fck",
 338         .prcm           = {
 339                 .omap4  = {
 340                         .modulemode     = MODULEMODE_SWCTRL,
 341                 },
 342         },
 343 };
 344
 345 /*
 346  * 'control' module class
 347  */
 348 struct omap_hwmod_class am33xx_control_hwmod_class = {
 349         .name           = "control",
 350 };
 351
 352 /*
 353  * dcan class
 354  */
 355 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 356         .name = "d_can",
 357 };
 358
 359 /* dcan0 */
 360 struct omap_hwmod am33xx_dcan0_hwmod = {
 361         .name           = "d_can0",
 362         .class          = &am33xx_dcan_hwmod_class,
 363         .clkdm_name     = "l4ls_clkdm",
 364         .main_clk       = "dcan0_fck",
 365         .prcm           = {
 366                 .omap4  = {
 367                         .modulemode     = MODULEMODE_SWCTRL,
 368                 },
 369         },
 370 };
 371
 372 /* dcan1 */
 373 struct omap_hwmod am33xx_dcan1_hwmod = {
 374         .name           = "d_can1",
 375         .class          = &am33xx_dcan_hwmod_class,
 376         .clkdm_name     = "l4ls_clkdm",
 377         .main_clk       = "dcan1_fck",
 378         .prcm           = {
 379                 .omap4  = {
 380                         .modulemode     = MODULEMODE_SWCTRL,
 381                 },
 382         },
 383 };
 384
 385 /* elm */
 386 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 387         .rev_offs       = 0x0000,
 388         .sysc_offs      = 0x0010,
 389         .syss_offs      = 0x0014,
 390         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 391                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 392                         SYSS_HAS_RESET_STATUS),
 393         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 394         .sysc_fields    = &omap_hwmod_sysc_type1,
 395 };
 396
 397 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 398         .name           = "elm",
 399         .sysc           = &am33xx_elm_sysc,
 400 };
 401
 402 struct omap_hwmod am33xx_elm_hwmod = {
 403         .name           = "elm",
 404         .class          = &am33xx_elm_hwmod_class,
 405         .clkdm_name     = "l4ls_clkdm",
 406         .main_clk       = "l4ls_gclk",
 407         .prcm           = {
 408                 .omap4  = {
 409                         .modulemode     = MODULEMODE_SWCTRL,
 410                 },
 411         },
 412 };
 413
 414 /* pwmss  */
 415 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 416         .rev_offs       = 0x0,
 417         .sysc_offs      = 0x4,
 418         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 419         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 420                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 421                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 422         .sysc_fields    = &omap_hwmod_sysc_type2,
 423 };
 424
 425 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 426         .name           = "epwmss",
 427         .sysc           = &am33xx_epwmss_sysc,
 428 };
 429
 430 /* epwmss0 */
 431 struct omap_hwmod am33xx_epwmss0_hwmod = {
 432         .name           = "epwmss0",
 433         .class          = &am33xx_epwmss_hwmod_class,
 434         .clkdm_name     = "l4ls_clkdm",
 435         .main_clk       = "l4ls_gclk",
 436         .prcm           = {
 437                 .omap4  = {
 438                         .modulemode     = MODULEMODE_SWCTRL,
 439                 },
 440         },
 441 };
 442
 443 /* epwmss1 */
 444 struct omap_hwmod am33xx_epwmss1_hwmod = {
 445         .name           = "epwmss1",
 446         .class          = &am33xx_epwmss_hwmod_class,
 447         .clkdm_name     = "l4ls_clkdm",
 448         .main_clk       = "l4ls_gclk",
 449         .prcm           = {
 450                 .omap4  = {
 451                         .modulemode     = MODULEMODE_SWCTRL,
 452                 },
 453         },
 454 };
 455
 456 /* epwmss2 */
 457 struct omap_hwmod am33xx_epwmss2_hwmod = {
 458         .name           = "epwmss2",
 459         .class          = &am33xx_epwmss_hwmod_class,
 460         .clkdm_name     = "l4ls_clkdm",
 461         .main_clk       = "l4ls_gclk",
 462         .prcm           = {
 463                 .omap4  = {
 464                         .modulemode     = MODULEMODE_SWCTRL,
 465                 },
 466         },
 467 };
 468
 469 /*
 470  * 'gpio' class: for gpio 0,1,2,3
 471  */
 472 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 473         .rev_offs       = 0x0000,
 474         .sysc_offs      = 0x0010,
 475         .syss_offs      = 0x0114,
 476         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 477                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 478                           SYSS_HAS_RESET_STATUS),
 479         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 480                           SIDLE_SMART_WKUP),
 481         .sysc_fields    = &omap_hwmod_sysc_type1,
 482 };
 483
 484 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 485         .name           = "gpio",
 486         .sysc           = &am33xx_gpio_sysc,
 487 };
 488
 489 /* gpio1 */
 490 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 491         { .role = "dbclk", .clk = "gpio1_dbclk" },
 492 };
 493
 494 static struct omap_hwmod am33xx_gpio1_hwmod = {
 495         .name           = "gpio2",
 496         .class          = &am33xx_gpio_hwmod_class,
 497         .clkdm_name     = "l4ls_clkdm",
 498         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 499         .main_clk       = "l4ls_gclk",
 500         .prcm           = {
 501                 .omap4  = {
 502                         .modulemode     = MODULEMODE_SWCTRL,
 503                 },
 504         },
 505         .opt_clks       = gpio1_opt_clks,
 506         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 507 };
 508
 509 /* gpio2 */
 510 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 511         { .role = "dbclk", .clk = "gpio2_dbclk" },
 512 };
 513
 514 static struct omap_hwmod am33xx_gpio2_hwmod = {
 515         .name           = "gpio3",
 516         .class          = &am33xx_gpio_hwmod_class,
 517         .clkdm_name     = "l4ls_clkdm",
 518         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 519         .main_clk       = "l4ls_gclk",
 520         .prcm           = {
 521                 .omap4  = {
 522                         .modulemode     = MODULEMODE_SWCTRL,
 523                 },
 524         },
 525         .opt_clks       = gpio2_opt_clks,
 526         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 527 };
 528
 529 /* gpio3 */
 530 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 531         { .role = "dbclk", .clk = "gpio3_dbclk" },
 532 };
 533
 534 static struct omap_hwmod am33xx_gpio3_hwmod = {
 535         .name           = "gpio4",
 536         .class          = &am33xx_gpio_hwmod_class,
 537         .clkdm_name     = "l4ls_clkdm",
 538         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 539         .main_clk       = "l4ls_gclk",
 540         .prcm           = {
 541                 .omap4  = {
 542                         .modulemode     = MODULEMODE_SWCTRL,
 543                 },
 544         },
 545         .opt_clks       = gpio3_opt_clks,
 546         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 547 };
 548
 549 /* gpmc */
 550 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 551         .rev_offs       = 0x0,
 552         .sysc_offs      = 0x10,
 553         .syss_offs      = 0x14,
 554         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 555                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 556         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 557         .sysc_fields    = &omap_hwmod_sysc_type1,
 558 };
 559
 560 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 561         .name           = "gpmc",
 562         .sysc           = &gpmc_sysc,
 563 };
 564
 565 struct omap_hwmod am33xx_gpmc_hwmod = {
 566         .name           = "gpmc",
 567         .class          = &am33xx_gpmc_hwmod_class,
 568         .clkdm_name     = "l3s_clkdm",
 569         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 570         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 571         .main_clk       = "l3s_gclk",
 572         .prcm           = {
 573                 .omap4  = {
 574                         .modulemode     = MODULEMODE_SWCTRL,
 575                 },
 576         },
 577 };
 578
 579 /*
 580  * 'mailbox' class
 581  * mailbox module allowing communication between the on-chip processors using a
 582  * queued mailbox-interrupt mechanism.
 583  */
 584 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 585         .rev_offs       = 0x0000,
 586         .sysc_offs      = 0x0010,
 587         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 588                           SYSC_HAS_SOFTRESET),
 589         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 590         .sysc_fields    = &omap_hwmod_sysc_type2,
 591 };
 592
 593 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 594         .name   = "mailbox",
 595         .sysc   = &am33xx_mailbox_sysc,
 596 };
 597
 598 struct omap_hwmod am33xx_mailbox_hwmod = {
 599         .name           = "mailbox",
 600         .class          = &am33xx_mailbox_hwmod_class,
 601         .clkdm_name     = "l4ls_clkdm",
 602         .main_clk       = "l4ls_gclk",
 603         .prcm = {
 604                 .omap4 = {
 605                         .modulemode     = MODULEMODE_SWCTRL,
 606                 },
 607         },
 608 };
 609
 610 /*
 611  * 'mcasp' class
 612  */
 613 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 614         .rev_offs       = 0x0,
 615         .sysc_offs      = 0x4,
 616         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 617         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 618         .sysc_fields    = &omap_hwmod_sysc_type3,
 619 };
 620
 621 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 622         .name           = "mcasp",
 623         .sysc           = &am33xx_mcasp_sysc,
 624 };
 625
 626 /* mcasp0 */
 627 struct omap_hwmod am33xx_mcasp0_hwmod = {
 628         .name           = "mcasp0",
 629         .class          = &am33xx_mcasp_hwmod_class,
 630         .clkdm_name     = "l3s_clkdm",
 631         .main_clk       = "mcasp0_fck",
 632         .prcm           = {
 633                 .omap4  = {
 634                         .modulemode     = MODULEMODE_SWCTRL,
 635                 },
 636         },
 637 };
 638
 639 /* mcasp1 */
 640 struct omap_hwmod am33xx_mcasp1_hwmod = {
 641         .name           = "mcasp1",
 642         .class          = &am33xx_mcasp_hwmod_class,
 643         .clkdm_name     = "l3s_clkdm",
 644         .main_clk       = "mcasp1_fck",
 645         .prcm           = {
 646                 .omap4  = {
 647                         .modulemode     = MODULEMODE_SWCTRL,
 648                 },
 649         },
 650 };
 651
 652 /*
 653  * 'rtc' class
 654  * rtc subsystem
 655  */
 656 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 657         .rev_offs       = 0x0074,
 658         .sysc_offs      = 0x0078,
 659         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 660         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 661                           SIDLE_SMART | SIDLE_SMART_WKUP),
 662         .sysc_fields    = &omap_hwmod_sysc_type3,
 663 };
 664
 665 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 666         .name           = "rtc",
 667         .sysc           = &am33xx_rtc_sysc,
 668         .unlock         = &omap_hwmod_rtc_unlock,
 669         .lock           = &omap_hwmod_rtc_lock,
 670 };
 671
 672 struct omap_hwmod am33xx_rtc_hwmod = {
 673         .name           = "rtc",
 674         .class          = &am33xx_rtc_hwmod_class,
 675         .clkdm_name     = "l4_rtc_clkdm",
 676         .main_clk       = "clk_32768_ck",
 677         .prcm           = {
 678                 .omap4  = {
 679                         .modulemode     = MODULEMODE_SWCTRL,
 680                 },
 681         },
 682 };
 683
 684 /* 'spi' class */
 685 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 686         .rev_offs       = 0x0000,
 687         .sysc_offs      = 0x0110,
 688         .syss_offs      = 0x0114,
 689         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 690                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 691                           SYSS_HAS_RESET_STATUS),
 692         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 693         .sysc_fields    = &omap_hwmod_sysc_type1,
 694 };
 695
 696 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 697         .name           = "mcspi",
 698         .sysc           = &am33xx_mcspi_sysc,
 699 };
 700
 701 /* spi0 */
 702 struct omap_hwmod am33xx_spi0_hwmod = {
 703         .name           = "spi0",
 704         .class          = &am33xx_spi_hwmod_class,
 705         .clkdm_name     = "l4ls_clkdm",
 706         .main_clk       = "dpll_per_m2_div4_ck",
 707         .prcm           = {
 708                 .omap4  = {
 709                         .modulemode     = MODULEMODE_SWCTRL,
 710                 },
 711         },
 712 };
 713
 714 /* spi1 */
 715 struct omap_hwmod am33xx_spi1_hwmod = {
 716         .name           = "spi1",
 717         .class          = &am33xx_spi_hwmod_class,
 718         .clkdm_name     = "l4ls_clkdm",
 719         .main_clk       = "dpll_per_m2_div4_ck",
 720         .prcm           = {
 721                 .omap4  = {
 722                         .modulemode     = MODULEMODE_SWCTRL,
 723                 },
 724         },
 725 };
 726
 727 /*
 728  * 'spinlock' class
 729  * spinlock provides hardware assistance for synchronizing the
 730  * processes running on multiple processors
 731  */
 732
 733 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 734         .rev_offs       = 0x0000,
 735         .sysc_offs      = 0x0010,
 736         .syss_offs      = 0x0014,
 737         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 738                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 739                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 740         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 741         .sysc_fields    = &omap_hwmod_sysc_type1,
 742 };
 743
 744 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 745         .name           = "spinlock",
 746         .sysc           = &am33xx_spinlock_sysc,
 747 };
 748
 749 struct omap_hwmod am33xx_spinlock_hwmod = {
 750         .name           = "spinlock",
 751         .class          = &am33xx_spinlock_hwmod_class,
 752         .clkdm_name     = "l4ls_clkdm",
 753         .main_clk       = "l4ls_gclk",
 754         .prcm           = {
 755                 .omap4  = {
 756                         .modulemode     = MODULEMODE_SWCTRL,
 757                 },
 758         },
 759 };
 760
 761 /* 'timer 2-7' class */
 762 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 763         .rev_offs       = 0x0000,
 764         .sysc_offs      = 0x0010,
 765         .syss_offs      = 0x0014,
 766         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 767                           SYSC_HAS_RESET_STATUS,
 768         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 769                           SIDLE_SMART_WKUP),
 770         .sysc_fields    = &omap_hwmod_sysc_type2,
 771 };
 772
 773 struct omap_hwmod_class am33xx_timer_hwmod_class = {
 774         .name           = "timer",
 775         .sysc           = &am33xx_timer_sysc,
 776 };
 777
 778 /* timer1 1ms */
 779 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 780         .rev_offs       = 0x0000,
 781         .sysc_offs      = 0x0010,
 782         .syss_offs      = 0x0014,
 783         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 784                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 785                         SYSS_HAS_RESET_STATUS),
 786         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 787         .sysc_fields    = &omap_hwmod_sysc_type1,
 788 };
 789
 790 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 791         .name           = "timer",
 792         .sysc           = &am33xx_timer1ms_sysc,
 793 };
 794
 795 struct omap_hwmod am33xx_timer1_hwmod = {
 796         .name           = "timer1",
 797         .class          = &am33xx_timer1ms_hwmod_class,
 798         .clkdm_name     = "l4_wkup_clkdm",
 799         .main_clk       = "timer1_fck",
 800         .prcm           = {
 801                 .omap4  = {
 802                         .modulemode     = MODULEMODE_SWCTRL,
 803                 },
 804         },
 805 };
 806
 807 struct omap_hwmod am33xx_timer2_hwmod = {
 808         .name           = "timer2",
 809         .class          = &am33xx_timer_hwmod_class,
 810         .clkdm_name     = "l4ls_clkdm",
 811         .main_clk       = "timer2_fck",
 812         .prcm           = {
 813                 .omap4  = {
 814                         .modulemode     = MODULEMODE_SWCTRL,
 815                 },
 816         },
 817 };
 818
 819 struct omap_hwmod am33xx_timer3_hwmod = {
 820         .name           = "timer3",
 821         .class          = &am33xx_timer_hwmod_class,
 822         .clkdm_name     = "l4ls_clkdm",
 823         .main_clk       = "timer3_fck",
 824         .prcm           = {
 825                 .omap4  = {
 826                         .modulemode     = MODULEMODE_SWCTRL,
 827                 },
 828         },
 829 };
 830
 831 struct omap_hwmod am33xx_timer4_hwmod = {
 832         .name           = "timer4",
 833         .class          = &am33xx_timer_hwmod_class,
 834         .clkdm_name     = "l4ls_clkdm",
 835         .main_clk       = "timer4_fck",
 836         .prcm           = {
 837                 .omap4  = {
 838                         .modulemode     = MODULEMODE_SWCTRL,
 839                 },
 840         },
 841 };
 842
 843 struct omap_hwmod am33xx_timer5_hwmod = {
 844         .name           = "timer5",
 845         .class          = &am33xx_timer_hwmod_class,
 846         .clkdm_name     = "l4ls_clkdm",
 847         .main_clk       = "timer5_fck",
 848         .prcm           = {
 849                 .omap4  = {
 850                         .modulemode     = MODULEMODE_SWCTRL,
 851                 },
 852         },
 853 };
 854
 855 struct omap_hwmod am33xx_timer6_hwmod = {
 856         .name           = "timer6",
 857         .class          = &am33xx_timer_hwmod_class,
 858         .clkdm_name     = "l4ls_clkdm",
 859         .main_clk       = "timer6_fck",
 860         .prcm           = {
 861                 .omap4  = {
 862                         .modulemode     = MODULEMODE_SWCTRL,
 863                 },
 864         },
 865 };
 866
 867 struct omap_hwmod am33xx_timer7_hwmod = {
 868         .name           = "timer7",
 869         .class          = &am33xx_timer_hwmod_class,
 870         .clkdm_name     = "l4ls_clkdm",
 871         .main_clk       = "timer7_fck",
 872         .prcm           = {
 873                 .omap4  = {
 874                         .modulemode     = MODULEMODE_SWCTRL,
 875                 },
 876         },
 877 };
 878
 879 /* tpcc */
 880 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
 881         .name           = "tpcc",
 882 };
 883
 884 struct omap_hwmod am33xx_tpcc_hwmod = {
 885         .name           = "tpcc",
 886         .class          = &am33xx_tpcc_hwmod_class,
 887         .clkdm_name     = "l3_clkdm",
 888         .main_clk       = "l3_gclk",
 889         .prcm           = {
 890                 .omap4  = {
 891                         .modulemode     = MODULEMODE_SWCTRL,
 892                 },
 893         },
 894 };
 895
 896 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
 897         .rev_offs       = 0x0,
 898         .sysc_offs      = 0x10,
 899         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 900                           SYSC_HAS_MIDLEMODE),
 901         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
 902         .sysc_fields    = &omap_hwmod_sysc_type2,
 903 };
 904
 905 /* 'tptc' class */
 906 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
 907         .name           = "tptc",
 908         .sysc           = &am33xx_tptc_sysc,
 909 };
 910
 911 /* tptc0 */
 912 struct omap_hwmod am33xx_tptc0_hwmod = {
 913         .name           = "tptc0",
 914         .class          = &am33xx_tptc_hwmod_class,
 915         .clkdm_name     = "l3_clkdm",
 916         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 917         .main_clk       = "l3_gclk",
 918         .prcm           = {
 919                 .omap4  = {
 920                         .modulemode     = MODULEMODE_SWCTRL,
 921                 },
 922         },
 923 };
 924
 925 /* tptc1 */
 926 struct omap_hwmod am33xx_tptc1_hwmod = {
 927         .name           = "tptc1",
 928         .class          = &am33xx_tptc_hwmod_class,
 929         .clkdm_name     = "l3_clkdm",
 930         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 931         .main_clk       = "l3_gclk",
 932         .prcm           = {
 933                 .omap4  = {
 934                         .modulemode     = MODULEMODE_SWCTRL,
 935                 },
 936         },
 937 };
 938
 939 /* tptc2 */
 940 struct omap_hwmod am33xx_tptc2_hwmod = {
 941         .name           = "tptc2",
 942         .class          = &am33xx_tptc_hwmod_class,
 943         .clkdm_name     = "l3_clkdm",
 944         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 945         .main_clk       = "l3_gclk",
 946         .prcm           = {
 947                 .omap4  = {
 948                         .modulemode     = MODULEMODE_SWCTRL,
 949                 },
 950         },
 951 };
 952
 953 /* 'wd_timer' class */
 954 static struct omap_hwmod_class_sysconfig wdt_sysc = {
 955         .rev_offs       = 0x0,
 956         .sysc_offs      = 0x10,
 957         .syss_offs      = 0x14,
 958         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
 959                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 960         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 961                         SIDLE_SMART_WKUP),
 962         .sysc_fields    = &omap_hwmod_sysc_type1,
 963 };
 964
 965 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
 966         .name           = "wd_timer",
 967         .sysc           = &wdt_sysc,
 968         .pre_shutdown   = &omap2_wd_timer_disable,
 969 };
 970
 971 /*
 972  * XXX: device.c file uses hardcoded name for watchdog timer
 973  * driver "wd_timer2, so we are also using same name as of now...
 974  */
 975 struct omap_hwmod am33xx_wd_timer1_hwmod = {
 976         .name           = "wd_timer2",
 977         .class          = &am33xx_wd_timer_hwmod_class,
 978         .clkdm_name     = "l4_wkup_clkdm",
 979         .flags          = HWMOD_SWSUP_SIDLE,
 980         .main_clk       = "wdt1_fck",
 981         .prcm           = {
 982                 .omap4  = {
 983                         .modulemode     = MODULEMODE_SWCTRL,
 984                 },
 985         },
 986 };
 987
 988 static void omap_hwmod_am33xx_clkctrl(void)
 989 {
 990         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
 991         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
 992         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
 993         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
 994         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
 995         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
 996         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
 997         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
 998         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
 999         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1000         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1001         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1002         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1003         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1004         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1005         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1006         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1007         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1008         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1009         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1010         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1011         CLKCTRL(am33xx_smartreflex0_hwmod,
1012                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1013         CLKCTRL(am33xx_smartreflex1_hwmod,
1014                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1015         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1016         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1017         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1018         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
1019         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1020         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1021         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1022         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1023         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1024         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1025         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1026         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1027         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1028         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1029         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1030         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1031         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1032         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1033         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1034         CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
1035 }
1036
1037 static void omap_hwmod_am33xx_rst(void)
1038 {
1039         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1040         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1041         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1042 }
1043
1044 void omap_hwmod_am33xx_reg(void)
1045 {
1046         omap_hwmod_am33xx_clkctrl();
1047         omap_hwmod_am33xx_rst();
1048 }
1049
1050 static void omap_hwmod_am43xx_clkctrl(void)
1051 {
1052         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1053         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1054         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1055         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1056         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1057         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1058         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1059         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1060         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1061         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1062         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1063         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1064         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1065         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1066         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1067         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1068         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1069         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1070         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1071         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1072         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1073         CLKCTRL(am33xx_smartreflex0_hwmod,
1074                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1075         CLKCTRL(am33xx_smartreflex1_hwmod,
1076                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1077         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1078         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1079         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1080         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1081         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1082         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1083         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1084         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1085         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1086         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1087         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1088         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1089         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1090         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1091         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1092         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1093         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1094         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1095         CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
1096 }
1097
1098 static void omap_hwmod_am43xx_rst(void)
1099 {
1100         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1101         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1102         RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
1103         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1104 }
1105
1106 void omap_hwmod_am43xx_reg(void)
1107 {
1108         omap_hwmod_am43xx_clkctrl();
1109         omap_hwmod_am43xx_rst();
1110 }