2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/tty.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/time.h>
26 #include <linux/clocksource.h>
27 #include <linux/clockchips.h>
29 #include <linux/export.h>
30 #include <linux/gpio/driver.h>
31 #include <linux/cpu.h>
32 #include <linux/pci.h>
33 #include <linux/sched_clock.h>
34 #include <linux/bitops.h>
36 #include <mach/hardware.h>
38 #include <linux/uaccess.h>
39 #include <asm/pgtable.h>
41 #include <asm/exception.h>
43 #include <asm/system_misc.h>
44 #include <asm/mach/map.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/time.h>
50 #define IXP4XX_TIMER_FREQ 66666000
53 * The timer register doesn't allow to specify the two least significant bits of
54 * the timeout value and assumes them being zero. So make sure IXP4XX_LATCH is
55 * the best value with the two least significant bits unset.
57 #define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, \
58 (IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \
59 (IXP4XX_OST_RELOAD_MASK + 1)
61 static struct irq_domain *ixp4xx_irqdomain;
62 static void __init ixp4xx_clocksource_init(void);
63 static void __init ixp4xx_clockevent_init(void);
64 static struct clock_event_device clockevent_ixp4xx;
66 /*************************************************************************
67 * IXP4xx chipset I/O mapping
68 *************************************************************************/
69 static struct map_desc ixp4xx_io_desc[] __initdata = {
70 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
71 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
72 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
73 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
75 }, { /* Expansion Bus Config Registers */
76 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
77 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
78 .length = IXP4XX_EXP_CFG_REGION_SIZE,
80 }, { /* PCI Registers */
81 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
82 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
83 .length = IXP4XX_PCI_CFG_REGION_SIZE,
85 }, { /* Queue Manager */
86 .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
87 .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
88 .length = IXP4XX_QMGR_REGION_SIZE,
93 void __init ixp4xx_map_io(void)
95 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
102 * The following converted to the real HW bits the gpio_line_config
105 #define IXP4XX_GPIO_OUT 0x1
106 #define IXP4XX_GPIO_IN 0x2
108 /* GPIO signal types */
109 #define IXP4XX_GPIO_LOW 0
110 #define IXP4XX_GPIO_HIGH 1
113 #define IXP4XX_GPIO_CLK_0 14
114 #define IXP4XX_GPIO_CLK_1 15
116 static void gpio_line_config(u8 line, u32 direction)
118 if (direction == IXP4XX_GPIO_IN)
119 *IXP4XX_GPIO_GPOER |= (1 << line);
121 *IXP4XX_GPIO_GPOER &= ~(1 << line);
124 static void gpio_line_get(u8 line, int *value)
126 *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
129 static void gpio_line_set(u8 line, int value)
131 if (value == IXP4XX_GPIO_HIGH)
132 *IXP4XX_GPIO_GPOUTR |= (1 << line);
133 else if (value == IXP4XX_GPIO_LOW)
134 *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
137 /*************************************************************************
138 * IXP4xx chipset IRQ handling
140 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
141 * (be it PCI or something else) configures that GPIO line
143 **************************************************************************/
144 enum ixp4xx_irq_type {
145 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
148 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
149 static unsigned long long ixp4xx_irq_edge = 0;
152 * IRQ -> GPIO mapping table
154 static signed char irq2gpio[32] = {
155 -1, -1, -1, -1, -1, -1, 0, 1,
156 -1, -1, -1, -1, -1, -1, -1, -1,
157 -1, -1, -1, 2, 3, 4, 5, 6,
158 7, 8, 9, 10, 11, 12, -1, -1,
161 static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
165 for (irq = 0; irq < 32; irq++) {
166 if (irq2gpio[irq] == gpio)
172 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
174 int line = irq2gpio[d->hwirq];
176 enum ixp4xx_irq_type irq_type;
177 volatile u32 *int_reg;
181 * all other IRQs are simply active low
187 case IRQ_TYPE_EDGE_BOTH:
188 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
189 irq_type = IXP4XX_IRQ_EDGE;
191 case IRQ_TYPE_EDGE_RISING:
192 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
193 irq_type = IXP4XX_IRQ_EDGE;
195 case IRQ_TYPE_EDGE_FALLING:
196 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
197 irq_type = IXP4XX_IRQ_EDGE;
199 case IRQ_TYPE_LEVEL_HIGH:
200 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
201 irq_type = IXP4XX_IRQ_LEVEL;
203 case IRQ_TYPE_LEVEL_LOW:
204 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
205 irq_type = IXP4XX_IRQ_LEVEL;
211 if (irq_type == IXP4XX_IRQ_EDGE)
212 ixp4xx_irq_edge |= (1 << d->hwirq);
214 ixp4xx_irq_edge &= ~(1 << d->hwirq);
216 if (line >= 8) { /* pins 8-15 */
218 int_reg = IXP4XX_GPIO_GPIT2R;
219 } else { /* pins 0-7 */
220 int_reg = IXP4XX_GPIO_GPIT1R;
223 /* Clear the style for the appropriate pin */
224 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
225 (line * IXP4XX_GPIO_STYLE_SIZE));
227 *IXP4XX_GPIO_GPISR = (1 << line);
229 /* Set the new style */
230 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
232 /* Configure the line as an input */
233 gpio_line_config(irq2gpio[d->hwirq], IXP4XX_GPIO_IN);
238 static void ixp4xx_irq_mask(struct irq_data *d)
240 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->hwirq >= 32)
241 *IXP4XX_ICMR2 &= ~(1 << (d->hwirq - 32));
243 *IXP4XX_ICMR &= ~(1 << d->hwirq);
246 static void ixp4xx_irq_ack(struct irq_data *d)
248 int line = (d->hwirq < 32) ? irq2gpio[d->hwirq] : -1;
251 *IXP4XX_GPIO_GPISR = (1 << line);
255 * Level triggered interrupts on GPIO lines can only be cleared when the
256 * interrupt condition disappears.
258 static void ixp4xx_irq_unmask(struct irq_data *d)
260 if (!(ixp4xx_irq_edge & (1 << d->hwirq)))
263 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->hwirq >= 32)
264 *IXP4XX_ICMR2 |= (1 << (d->hwirq - 32));
266 *IXP4XX_ICMR |= (1 << d->hwirq);
269 static struct irq_chip ixp4xx_irq_chip = {
271 .irq_ack = ixp4xx_irq_ack,
272 .irq_mask = ixp4xx_irq_mask,
273 .irq_unmask = ixp4xx_irq_unmask,
274 .irq_set_type = ixp4xx_set_irq_type,
277 asmlinkage void __exception_irq_entry ixp4xx_handle_irq(struct pt_regs *regs)
279 unsigned long status;
282 status = *IXP4XX_ICIP;
284 for_each_set_bit(i, &status, 32)
285 handle_domain_irq(ixp4xx_irqdomain, i, regs);
288 * IXP465/IXP435 has an upper IRQ status register
290 if ((cpu_is_ixp46x() || cpu_is_ixp43x())) {
291 status = *IXP4XX_ICIP2;
292 for_each_set_bit(i, &status, 32)
293 handle_domain_irq(ixp4xx_irqdomain, i + 32, regs);
297 static int ixp4xx_irqdomain_map(struct irq_domain *d, unsigned int irq,
298 irq_hw_number_t hwirq)
300 irq_set_chip_data(irq, &ixp4xx_irq_chip);
301 irq_set_chip_and_handler(irq, &ixp4xx_irq_chip, handle_level_irq);
307 static void ixp4xx_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
309 irq_set_chip_and_handler(irq, NULL, NULL);
310 irq_set_chip_data(irq, NULL);
313 static const struct irq_domain_ops ixp4xx_irqdomain_ops = {
314 .map = ixp4xx_irqdomain_map,
315 .unmap = ixp4xx_irqdomain_unmap,
318 void __init ixp4xx_init_irq(void)
323 * ixp4xx does not implement the XScale PWRMODE register
324 * so it must not call cpu_do_idle().
326 cpu_idle_poll_ctrl(true);
328 /* Route all sources to IRQ instead of FIQ */
331 /* Disable all interrupt */
334 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
335 /* Route upper 32 sources to IRQ instead of FIQ */
336 *IXP4XX_ICLR2 = 0x00;
338 /* Disable upper 32 interrupts */
339 *IXP4XX_ICMR2 = 0x00;
346 ixp4xx_irqdomain = irq_domain_add_simple(NULL, nr_irqs, IRQ_IXP4XX_BASE,
347 &ixp4xx_irqdomain_ops,
349 if (!ixp4xx_irqdomain) {
350 pr_crit("can not add primary irqdomain\n");
354 set_handle_irq(ixp4xx_handle_irq);
358 /*************************************************************************
360 * We use OS timer1 on the CPU for the timer tick and the timestamp
361 * counter as a source of real clock ticks to account for missed jiffies.
362 *************************************************************************/
364 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
366 struct clock_event_device *evt = dev_id;
368 /* Clear Pending Interrupt by writing '1' to it */
369 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
371 evt->event_handler(evt);
376 void __init ixp4xx_timer_init(void)
378 /* Reset/disable counter */
381 /* Clear Pending Interrupt by writing '1' to it */
382 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
384 /* Reset time-stamp counter */
387 ixp4xx_clocksource_init();
388 ixp4xx_clockevent_init();
391 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
393 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
395 memcpy(&ixp4xx_udc_info, info, sizeof *info);
398 static struct resource ixp4xx_udc_resources[] = {
402 .flags = IORESOURCE_MEM,
405 .start = IRQ_IXP4XX_USB,
406 .end = IRQ_IXP4XX_USB,
407 .flags = IORESOURCE_IRQ,
412 * USB device controller. The IXP4xx uses the same controller as PXA25X,
413 * so we just use the same device.
415 static struct platform_device ixp4xx_udc_device = {
416 .name = "pxa25x-udc",
419 .resource = ixp4xx_udc_resources,
421 .platform_data = &ixp4xx_udc_info,
425 static struct platform_device *ixp4xx_devices[] __initdata = {
429 static struct resource ixp46x_i2c_resources[] = {
433 .flags = IORESOURCE_MEM,
436 .start = IRQ_IXP4XX_I2C,
437 .end = IRQ_IXP4XX_I2C,
438 .flags = IORESOURCE_IRQ
443 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
444 * we just use the same device name.
446 static struct platform_device ixp46x_i2c_controller = {
447 .name = "IOP3xx-I2C",
450 .resource = ixp46x_i2c_resources
453 static struct platform_device *ixp46x_devices[] __initdata = {
454 &ixp46x_i2c_controller
457 unsigned long ixp4xx_exp_bus_size;
458 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
460 static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
462 gpio_line_config(gpio, IXP4XX_GPIO_IN);
467 static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
470 gpio_line_set(gpio, level);
471 gpio_line_config(gpio, IXP4XX_GPIO_OUT);
476 static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
480 gpio_line_get(gpio, &value);
485 static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
488 gpio_line_set(gpio, value);
491 static struct gpio_chip ixp4xx_gpio_chip = {
492 .label = "IXP4XX_GPIO_CHIP",
493 .direction_input = ixp4xx_gpio_direction_input,
494 .direction_output = ixp4xx_gpio_direction_output,
495 .get = ixp4xx_gpio_get_value,
496 .set = ixp4xx_gpio_set_value,
497 .to_irq = ixp4xx_gpio_to_irq,
502 void __init ixp4xx_sys_init(void)
504 ixp4xx_exp_bus_size = SZ_16M;
506 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
508 gpiochip_add_data(&ixp4xx_gpio_chip, NULL);
510 if (cpu_is_ixp46x()) {
513 platform_add_devices(ixp46x_devices,
514 ARRAY_SIZE(ixp46x_devices));
516 for (region = 0; region < 7; region++) {
517 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
518 ixp4xx_exp_bus_size = SZ_32M;
524 printk("IXP4xx: Using %luMiB expansion bus window size\n",
525 ixp4xx_exp_bus_size >> 20);
531 static u64 notrace ixp4xx_read_sched_clock(void)
540 static u64 ixp4xx_clocksource_read(struct clocksource *c)
545 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
546 EXPORT_SYMBOL(ixp4xx_timer_freq);
547 static void __init ixp4xx_clocksource_init(void)
549 sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
551 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
552 ixp4xx_clocksource_read);
558 static int ixp4xx_set_next_event(unsigned long evt,
559 struct clock_event_device *unused)
561 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
563 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
568 static int ixp4xx_shutdown(struct clock_event_device *evt)
570 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
571 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
573 opts &= ~IXP4XX_OST_ENABLE;
574 *IXP4XX_OSRT1 = osrt | opts;
578 static int ixp4xx_set_oneshot(struct clock_event_device *evt)
580 unsigned long opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
581 unsigned long osrt = 0;
583 /* period set by 'set next_event' */
584 *IXP4XX_OSRT1 = osrt | opts;
588 static int ixp4xx_set_periodic(struct clock_event_device *evt)
590 unsigned long opts = IXP4XX_OST_ENABLE;
591 unsigned long osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
593 *IXP4XX_OSRT1 = osrt | opts;
597 static int ixp4xx_resume(struct clock_event_device *evt)
599 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
600 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
602 opts |= IXP4XX_OST_ENABLE;
603 *IXP4XX_OSRT1 = osrt | opts;
607 static struct clock_event_device clockevent_ixp4xx = {
608 .name = "ixp4xx timer1",
609 .features = CLOCK_EVT_FEAT_PERIODIC |
610 CLOCK_EVT_FEAT_ONESHOT,
612 .set_state_shutdown = ixp4xx_shutdown,
613 .set_state_periodic = ixp4xx_set_periodic,
614 .set_state_oneshot = ixp4xx_set_oneshot,
615 .tick_resume = ixp4xx_resume,
616 .set_next_event = ixp4xx_set_next_event,
619 static void __init ixp4xx_clockevent_init(void)
623 clockevent_ixp4xx.cpumask = cpumask_of(0);
624 clockevent_ixp4xx.irq = IRQ_IXP4XX_TIMER1;
625 ret = request_irq(IRQ_IXP4XX_TIMER1, ixp4xx_timer_interrupt,
626 IRQF_TIMER, "IXP4XX-TIMER1", &clockevent_ixp4xx);
628 pr_crit("no timer IRQ\n");
631 clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
635 void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
637 if (mode == REBOOT_SOFT) {
638 /* Jump into ROM at address 0 */
641 /* Use on-chip reset capability */
643 /* set the "key" register to enable access to
644 * "timer" and "enable" registers
646 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
648 /* write 0 to the timer register for an immediate reset */
651 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
656 static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
658 return (dma_addr + size) > SZ_64M;
661 static int ixp4xx_platform_notify_remove(struct device *dev)
664 dmabounce_unregister_dev(dev);
671 * Setup DMA mask to 64MB on PCI devices and 4 GB on all other things.
673 static int ixp4xx_platform_notify(struct device *dev)
675 dev->dma_mask = &dev->coherent_dma_mask;
678 if (dev_is_pci(dev)) {
679 dev->coherent_dma_mask = DMA_BIT_MASK(28); /* 64 MB */
680 dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
685 dev->coherent_dma_mask = DMA_BIT_MASK(32);
689 int dma_set_coherent_mask(struct device *dev, u64 mask)
692 mask &= DMA_BIT_MASK(28); /* 64 MB */
694 if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) {
695 dev->coherent_dma_mask = mask;
699 return -EIO; /* device wanted sub-64MB mask */
701 EXPORT_SYMBOL(dma_set_coherent_mask);
703 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
705 * In the case of using indirect PCI, we simply return the actual PCI
706 * address and our read/write implementation use that to drive the
707 * access registers. If something outside of PCI is ioremap'd, we
708 * fallback to the default.
711 static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
712 unsigned int mtype, void *caller)
714 if (!is_pci_memory(addr))
715 return __arm_ioremap_caller(addr, size, mtype, caller);
717 return (void __iomem *)addr;
720 static void ixp4xx_iounmap(volatile void __iomem *addr)
722 if (!is_pci_memory((__force u32)addr))
727 void __init ixp4xx_init_early(void)
729 platform_notify = ixp4xx_platform_notify;
731 platform_notify_remove = ixp4xx_platform_notify_remove;
733 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
734 arch_ioremap_caller = ixp4xx_ioremap_caller;
735 arch_iounmap = ixp4xx_iounmap;