2 * linux/arch/arm/mach-at91/gpio.c
4 * Copyright (C) 2005 HP Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/device.h>
15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/debugfs.h>
19 #include <linux/seq_file.h>
20 #include <linux/kernel.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
28 #include <mach/hardware.h>
29 #include <mach/at91_pio.h>
33 struct at91_gpio_chip {
34 struct gpio_chip chip;
35 struct at91_gpio_chip *next; /* Bank sharing same clock */
36 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
37 int pioc_idx; /* PIO bank index */
38 void __iomem *regbase; /* PIO bank virtual address */
39 struct clk *clock; /* associated clock */
40 struct irq_domain *domain; /* associated irq domain */
43 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
45 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
46 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
47 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
48 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
49 unsigned offset, int val);
50 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
52 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
54 #define AT91_GPIO_CHIP(name, nr_gpio) \
58 .direction_input = at91_gpiolib_direction_input, \
59 .direction_output = at91_gpiolib_direction_output, \
60 .get = at91_gpiolib_get, \
61 .set = at91_gpiolib_set, \
62 .dbg_show = at91_gpiolib_dbg_show, \
63 .to_irq = at91_gpiolib_to_irq, \
68 static struct at91_gpio_chip gpio_chip[] = {
69 AT91_GPIO_CHIP("pioA", 32),
70 AT91_GPIO_CHIP("pioB", 32),
71 AT91_GPIO_CHIP("pioC", 32),
72 AT91_GPIO_CHIP("pioD", 32),
73 AT91_GPIO_CHIP("pioE", 32),
76 static int gpio_banks;
78 static inline void __iomem *pin_to_controller(unsigned pin)
81 if (likely(pin < gpio_banks))
82 return gpio_chip[pin].regbase;
87 static inline unsigned pin_to_mask(unsigned pin)
89 return 1 << (pin % 32);
93 /*--------------------------------------------------------------------------*/
95 /* Not all hardware capabilities are exposed through these calls; they
96 * only encapsulate the most common features and modes. (So if you
97 * want to change signals in groups, do it directly.)
99 * Bootloaders will usually handle some of the pin multiplexing setup.
100 * The intent is certainly that by the time Linux is fully booted, all
101 * pins should have been fully initialized. These setup calls should
102 * only be used by board setup routines, or possibly in driver probe().
104 * For bootloaders doing all that setup, these calls could be inlined
105 * as NOPs so Linux won't duplicate any setup code
110 * mux the pin to the "GPIO" peripheral role.
112 int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
114 void __iomem *pio = pin_to_controller(pin);
115 unsigned mask = pin_to_mask(pin);
119 __raw_writel(mask, pio + PIO_IDR);
120 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
121 __raw_writel(mask, pio + PIO_PER);
124 EXPORT_SYMBOL(at91_set_GPIO_periph);
128 * mux the pin to the "A" internal peripheral role.
130 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
132 void __iomem *pio = pin_to_controller(pin);
133 unsigned mask = pin_to_mask(pin);
138 __raw_writel(mask, pio + PIO_IDR);
139 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
140 __raw_writel(mask, pio + PIO_ASR);
141 __raw_writel(mask, pio + PIO_PDR);
144 EXPORT_SYMBOL(at91_set_A_periph);
148 * mux the pin to the "B" internal peripheral role.
150 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
152 void __iomem *pio = pin_to_controller(pin);
153 unsigned mask = pin_to_mask(pin);
158 __raw_writel(mask, pio + PIO_IDR);
159 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
160 __raw_writel(mask, pio + PIO_BSR);
161 __raw_writel(mask, pio + PIO_PDR);
164 EXPORT_SYMBOL(at91_set_B_periph);
168 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
169 * configure it for an input.
171 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
173 void __iomem *pio = pin_to_controller(pin);
174 unsigned mask = pin_to_mask(pin);
179 __raw_writel(mask, pio + PIO_IDR);
180 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
181 __raw_writel(mask, pio + PIO_ODR);
182 __raw_writel(mask, pio + PIO_PER);
185 EXPORT_SYMBOL(at91_set_gpio_input);
189 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
190 * and configure it for an output.
192 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
194 void __iomem *pio = pin_to_controller(pin);
195 unsigned mask = pin_to_mask(pin);
200 __raw_writel(mask, pio + PIO_IDR);
201 __raw_writel(mask, pio + PIO_PUDR);
202 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
203 __raw_writel(mask, pio + PIO_OER);
204 __raw_writel(mask, pio + PIO_PER);
207 EXPORT_SYMBOL(at91_set_gpio_output);
211 * enable/disable the glitch filter; mostly used with IRQ handling.
213 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
215 void __iomem *pio = pin_to_controller(pin);
216 unsigned mask = pin_to_mask(pin);
220 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
223 EXPORT_SYMBOL(at91_set_deglitch);
226 * enable/disable the multi-driver; This is only valid for output and
227 * allows the output pin to run as an open collector output.
229 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
231 void __iomem *pio = pin_to_controller(pin);
232 unsigned mask = pin_to_mask(pin);
237 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
240 EXPORT_SYMBOL(at91_set_multi_drive);
243 * assuming the pin is muxed as a gpio output, set its value.
245 int at91_set_gpio_value(unsigned pin, int value)
247 void __iomem *pio = pin_to_controller(pin);
248 unsigned mask = pin_to_mask(pin);
252 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
255 EXPORT_SYMBOL(at91_set_gpio_value);
259 * read the pin's value (works even if it's not muxed as a gpio).
261 int at91_get_gpio_value(unsigned pin)
263 void __iomem *pio = pin_to_controller(pin);
264 unsigned mask = pin_to_mask(pin);
269 pdsr = __raw_readl(pio + PIO_PDSR);
270 return (pdsr & mask) != 0;
272 EXPORT_SYMBOL(at91_get_gpio_value);
274 /*--------------------------------------------------------------------------*/
278 static u32 wakeups[MAX_GPIO_BANKS];
279 static u32 backups[MAX_GPIO_BANKS];
281 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
283 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
284 unsigned mask = 1 << d->hwirq;
285 unsigned bank = at91_gpio->pioc_idx;
287 if (unlikely(bank >= MAX_GPIO_BANKS))
291 wakeups[bank] |= mask;
293 wakeups[bank] &= ~mask;
295 irq_set_irq_wake(gpio_chip[bank].pioc_hwirq, state);
300 void at91_gpio_suspend(void)
304 for (i = 0; i < gpio_banks; i++) {
305 void __iomem *pio = gpio_chip[i].regbase;
307 backups[i] = __raw_readl(pio + PIO_IMR);
308 __raw_writel(backups[i], pio + PIO_IDR);
309 __raw_writel(wakeups[i], pio + PIO_IER);
312 clk_unprepare(gpio_chip[i].clock);
313 clk_disable(gpio_chip[i].clock);
315 #ifdef CONFIG_PM_DEBUG
316 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
322 void at91_gpio_resume(void)
326 for (i = 0; i < gpio_banks; i++) {
327 void __iomem *pio = gpio_chip[i].regbase;
330 if (clk_prepare(gpio_chip[i].clock) == 0)
331 clk_enable(gpio_chip[i].clock);
334 __raw_writel(wakeups[i], pio + PIO_IDR);
335 __raw_writel(backups[i], pio + PIO_IER);
340 #define gpio_irq_set_wake NULL
344 /* Several AIC controller irqs are dispatched through this GPIO handler.
345 * To use any AT91_PIN_* as an externally triggered IRQ, first call
346 * at91_set_gpio_input() then maybe enable its glitch filter.
347 * Then just request_irq() with the pin ID; it works like any ARM IRQ
348 * handler, though it always triggers on rising and falling edges.
350 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
351 * configuring them with at91_set_a_periph() or at91_set_b_periph().
352 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
355 static void gpio_irq_mask(struct irq_data *d)
357 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
358 void __iomem *pio = at91_gpio->regbase;
359 unsigned mask = 1 << d->hwirq;
362 __raw_writel(mask, pio + PIO_IDR);
365 static void gpio_irq_unmask(struct irq_data *d)
367 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
368 void __iomem *pio = at91_gpio->regbase;
369 unsigned mask = 1 << d->hwirq;
372 __raw_writel(mask, pio + PIO_IER);
375 static int gpio_irq_type(struct irq_data *d, unsigned type)
379 case IRQ_TYPE_EDGE_BOTH:
386 static struct irq_chip gpio_irqchip = {
388 .irq_disable = gpio_irq_mask,
389 .irq_mask = gpio_irq_mask,
390 .irq_unmask = gpio_irq_unmask,
391 .irq_set_type = gpio_irq_type,
392 .irq_set_wake = gpio_irq_set_wake,
395 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
398 struct irq_data *idata = irq_desc_get_irq_data(desc);
399 struct irq_chip *chip = irq_data_get_irq_chip(idata);
400 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
401 void __iomem *pio = at91_gpio->regbase;
404 /* temporarily mask (level sensitive) parent IRQ */
405 chip->irq_ack(idata);
407 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
408 * When there none are pending, we're finished unless we need
409 * to process multiple banks (like ID_PIOCDE on sam9263).
411 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
413 if (!at91_gpio->next)
415 at91_gpio = at91_gpio->next;
416 pio = at91_gpio->regbase;
420 virq = gpio_to_irq(at91_gpio->chip.base);
424 generic_handle_irq(virq);
429 chip->irq_unmask(idata);
430 /* now it may re-trigger */
433 /*--------------------------------------------------------------------------*/
435 #ifdef CONFIG_DEBUG_FS
437 static int at91_gpio_show(struct seq_file *s, void *unused)
442 seq_printf(s, "Pin\t");
443 for (bank = 0; bank < gpio_banks; bank++) {
444 seq_printf(s, "PIO%c\t", 'A' + bank);
446 seq_printf(s, "\n\n");
448 /* print pin status */
449 for (j = 0; j < 32; j++) {
450 seq_printf(s, "%i:\t", j);
452 for (bank = 0; bank < gpio_banks; bank++) {
453 unsigned pin = (32 * bank) + j;
454 void __iomem *pio = pin_to_controller(pin);
455 unsigned mask = pin_to_mask(pin);
457 if (__raw_readl(pio + PIO_PSR) & mask)
458 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
460 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
471 static int at91_gpio_open(struct inode *inode, struct file *file)
473 return single_open(file, at91_gpio_show, NULL);
476 static const struct file_operations at91_gpio_operations = {
477 .open = at91_gpio_open,
480 .release = single_release,
483 static int __init at91_gpio_debugfs_init(void)
485 /* /sys/kernel/debug/at91_gpio */
486 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
489 postcore_initcall(at91_gpio_debugfs_init);
493 /*--------------------------------------------------------------------------*/
496 * irqdomain initialization: pile up irqdomains on top of AIC range
498 static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
501 #if defined(CONFIG_OF)
502 struct device_node *of_node = at91_gpio->chip.of_node;
504 struct device_node *of_node = NULL;
507 irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
509 panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
510 at91_gpio->pioc_idx, irq_base);
511 at91_gpio->domain = irq_domain_add_legacy(of_node,
512 at91_gpio->chip.ngpio,
514 &irq_domain_simple_ops, NULL);
515 if (!at91_gpio->domain)
516 panic("at91_gpio.%d: couldn't allocate irq domain.\n",
517 at91_gpio->pioc_idx);
521 * This lock class tells lockdep that GPIO irqs are in a different
522 * category than their parents, so it won't report false recursion.
524 static struct lock_class_key gpio_lock_class;
527 * Called from the processor-specific init to enable GPIO interrupt support.
529 void __init at91_gpio_irq_setup(void)
533 struct at91_gpio_chip *this, *prev;
535 for (pioc = 0, this = gpio_chip, prev = NULL;
537 prev = this, this++) {
538 unsigned pioc_hwirq = this->pioc_hwirq;
541 __raw_writel(~0, this->regbase + PIO_IDR);
543 /* setup irq domain for this GPIO controller */
544 at91_gpio_irqdomain(this);
546 for (offset = 0; offset < this->chip.ngpio; offset++) {
547 unsigned int virq = irq_find_mapping(this->domain, offset);
548 irq_set_lockdep_class(virq, &gpio_lock_class);
551 * Can use the "simple" and not "edge" handler since it's
552 * shorter, and the AIC handles interrupts sanely.
554 irq_set_chip_and_handler(virq, &gpio_irqchip,
556 set_irq_flags(virq, IRQF_VALID);
557 irq_set_chip_data(virq, this);
562 /* The toplevel handler handles one bank of GPIOs, except
563 * on some SoC it can handles up to three...
564 * We only set up the handler for the first of the list.
566 if (prev && prev->next == this)
569 irq_set_chip_data(pioc_hwirq, this);
570 irq_set_chained_handler(pioc_hwirq, gpio_irq_handler);
572 pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
575 /* gpiolib support */
576 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
579 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
580 void __iomem *pio = at91_gpio->regbase;
581 unsigned mask = 1 << offset;
583 __raw_writel(mask, pio + PIO_ODR);
587 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
588 unsigned offset, int val)
590 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
591 void __iomem *pio = at91_gpio->regbase;
592 unsigned mask = 1 << offset;
594 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
595 __raw_writel(mask, pio + PIO_OER);
599 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
601 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
602 void __iomem *pio = at91_gpio->regbase;
603 unsigned mask = 1 << offset;
606 pdsr = __raw_readl(pio + PIO_PDSR);
607 return (pdsr & mask) != 0;
610 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
612 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
613 void __iomem *pio = at91_gpio->regbase;
614 unsigned mask = 1 << offset;
616 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
619 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
623 for (i = 0; i < chip->ngpio; i++) {
624 unsigned pin = chip->base + i;
625 void __iomem *pio = pin_to_controller(pin);
626 unsigned mask = pin_to_mask(pin);
627 const char *gpio_label;
629 gpio_label = gpiochip_is_requested(chip, i);
631 seq_printf(s, "[%s] GPIO%s%d: ",
632 gpio_label, chip->label, i);
633 if (__raw_readl(pio + PIO_PSR) & mask)
634 seq_printf(s, "[gpio] %s\n",
635 at91_get_gpio_value(pin) ?
638 seq_printf(s, "[periph %s]\n",
639 __raw_readl(pio + PIO_ABSR) &
645 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
647 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
648 int virq = irq_find_mapping(at91_gpio->domain, offset);
650 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
651 chip->label, offset + chip->base, virq);
655 static int __init at91_gpio_setup_clk(int idx)
657 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
659 /* retreive PIO controller's clock */
660 at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
661 if (IS_ERR(at91_gpio->clock)) {
662 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
666 if (clk_prepare(at91_gpio->clock))
669 /* enable PIO controller's clock */
670 if (clk_enable(at91_gpio->clock)) {
671 pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
678 clk_unprepare(at91_gpio->clock);
680 clk_put(at91_gpio->clock);
685 #ifdef CONFIG_OF_GPIO
686 static void __init of_at91_gpio_init_one(struct device_node *np)
689 struct at91_gpio_chip *at91_gpio;
694 alias_idx = of_alias_get_id(np, "gpio");
695 if (alias_idx >= MAX_GPIO_BANKS) {
696 pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
697 alias_idx, MAX_GPIO_BANKS);
701 at91_gpio = &gpio_chip[alias_idx];
702 at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
704 at91_gpio->regbase = of_iomap(np, 0);
705 if (!at91_gpio->regbase) {
706 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
711 /* Get the interrupts property */
712 if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
713 pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
719 if (at91_gpio_setup_clk(alias_idx))
722 at91_gpio->chip.of_node = np;
723 gpio_banks = max(gpio_banks, alias_idx + 1);
724 at91_gpio->pioc_idx = alias_idx;
728 iounmap(at91_gpio->regbase);
731 static int __init of_at91_gpio_init(void)
733 struct device_node *np = NULL;
736 * This isn't ideal, but it gets things hooked up until this
737 * driver is converted into a platform_device
739 for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
740 of_at91_gpio_init_one(np);
742 return gpio_banks > 0 ? 0 : -EINVAL;
745 static int __init of_at91_gpio_init(void)
751 static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
753 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
755 at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
756 at91_gpio->pioc_hwirq = pioc_hwirq;
757 at91_gpio->pioc_idx = idx;
759 at91_gpio->regbase = ioremap(regbase, 512);
760 if (!at91_gpio->regbase) {
761 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
765 if (at91_gpio_setup_clk(idx))
768 gpio_banks = max(gpio_banks, idx + 1);
772 iounmap(at91_gpio->regbase);
776 * Called from the processor-specific init to enable GPIO pin support.
778 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
781 struct at91_gpio_chip *at91_gpio, *last = NULL;
783 BUG_ON(nr_banks > MAX_GPIO_BANKS);
785 if (of_at91_gpio_init() < 0) {
786 /* No GPIO controller found in device tree */
787 for (i = 0; i < nr_banks; i++)
788 at91_gpio_init_one(i, data[i].regbase, data[i].id);
791 for (i = 0; i < gpio_banks; i++) {
792 at91_gpio = &gpio_chip[i];
795 * GPIO controller are grouped on some SoC:
796 * PIOC, PIOD and PIOE can share the same IRQ line
798 if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
799 last->next = at91_gpio;
802 gpiochip_add(&at91_gpio->chip);