arch/arm/boot/dts/r8a7779.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7779
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Simon Horman
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7779-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a7779-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a7779";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <0>;
  31                         clock-frequency = <1000000000>;
  32                 };
  33                 cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         reg = <1>;
  37                         clock-frequency = <1000000000>;
  38                         power-domains = <&sysc R8A7779_PD_ARM1>;
  39                 };
  40                 cpu@2 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         reg = <2>;
  44                         clock-frequency = <1000000000>;
  45                         power-domains = <&sysc R8A7779_PD_ARM2>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         reg = <3>;
  51                         clock-frequency = <1000000000>;
  52                         power-domains = <&sysc R8A7779_PD_ARM3>;
  53                 };
  54         };
  55
  56         aliases {
  57                 spi0 = &hspi0;
  58                 spi1 = &hspi1;
  59                 spi2 = &hspi2;
  60         };
  61
  62         gic: interrupt-controller@f0001000 {
  63                 compatible = "arm,cortex-a9-gic";
  64                 #interrupt-cells = <3>;
  65                 interrupt-controller;
  66                 reg = <0xf0001000 0x1000>,
  67                       <0xf0000100 0x100>;
  68         };
  69
  70         timer@f0000600 {
  71                 compatible = "arm,cortex-a9-twd-timer";
  72                 reg = <0xf0000600 0x20>;
  73                 interrupts = <GIC_PPI 13
  74                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
  75                 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
  76         };
  77
  78         gpio0: gpio@ffc40000 {
  79                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  80                 reg = <0xffc40000 0x2c>;
  81                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
  82                 #gpio-cells = <2>;
  83                 gpio-controller;
  84                 gpio-ranges = <&pfc 0 0 32>;
  85                 #interrupt-cells = <2>;
  86                 interrupt-controller;
  87         };
  88
  89         gpio1: gpio@ffc41000 {
  90                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  91                 reg = <0xffc41000 0x2c>;
  92                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
  93                 #gpio-cells = <2>;
  94                 gpio-controller;
  95                 gpio-ranges = <&pfc 0 32 32>;
  96                 #interrupt-cells = <2>;
  97                 interrupt-controller;
  98         };
  99
 100         gpio2: gpio@ffc42000 {
 101                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 102                 reg = <0xffc42000 0x2c>;
 103                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 104                 #gpio-cells = <2>;
 105                 gpio-controller;
 106                 gpio-ranges = <&pfc 0 64 32>;
 107                 #interrupt-cells = <2>;
 108                 interrupt-controller;
 109         };
 110
 111         gpio3: gpio@ffc43000 {
 112                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 113                 reg = <0xffc43000 0x2c>;
 114                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 115                 #gpio-cells = <2>;
 116                 gpio-controller;
 117                 gpio-ranges = <&pfc 0 96 32>;
 118                 #interrupt-cells = <2>;
 119                 interrupt-controller;
 120         };
 121
 122         gpio4: gpio@ffc44000 {
 123                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 124                 reg = <0xffc44000 0x2c>;
 125                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 126                 #gpio-cells = <2>;
 127                 gpio-controller;
 128                 gpio-ranges = <&pfc 0 128 32>;
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131         };
 132
 133         gpio5: gpio@ffc45000 {
 134                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 135                 reg = <0xffc45000 0x2c>;
 136                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 137                 #gpio-cells = <2>;
 138                 gpio-controller;
 139                 gpio-ranges = <&pfc 0 160 32>;
 140                 #interrupt-cells = <2>;
 141                 interrupt-controller;
 142         };
 143
 144         gpio6: gpio@ffc46000 {
 145                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 146                 reg = <0xffc46000 0x2c>;
 147                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 148                 #gpio-cells = <2>;
 149                 gpio-controller;
 150                 gpio-ranges = <&pfc 0 192 9>;
 151                 #interrupt-cells = <2>;
 152                 interrupt-controller;
 153         };
 154
 155         irqpin0: interrupt-controller@fe78001c {
 156                 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
 157                 #interrupt-cells = <2>;
 158                 status = "disabled";
 159                 interrupt-controller;
 160                 reg = <0xfe78001c 4>,
 161                         <0xfe780010 4>,
 162                         <0xfe780024 4>,
 163                         <0xfe780044 4>,
 164                         <0xfe780064 4>,
 165                         <0xfe780000 4>;
 166                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
 167                               GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
 168                               GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
 169                               GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 170                 sense-bitfield-width = <2>;
 171         };
 172
 173         i2c0: i2c@ffc70000 {
 174                 #address-cells = <1>;
 175                 #size-cells = <0>;
 176                 compatible = "renesas,i2c-r8a7779";
 177                 reg = <0xffc70000 0x1000>;
 178                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 180                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 181                 status = "disabled";
 182         };
 183
 184         i2c1: i2c@ffc71000 {
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187                 compatible = "renesas,i2c-r8a7779";
 188                 reg = <0xffc71000 0x1000>;
 189                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 190                 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 191                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 192                 status = "disabled";
 193         };
 194
 195         i2c2: i2c@ffc72000 {
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 compatible = "renesas,i2c-r8a7779";
 199                 reg = <0xffc72000 0x1000>;
 200                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 202                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 203                 status = "disabled";
 204         };
 205
 206         i2c3: i2c@ffc73000 {
 207                 #address-cells = <1>;
 208                 #size-cells = <0>;
 209                 compatible = "renesas,i2c-r8a7779";
 210                 reg = <0xffc73000 0x1000>;
 211                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 213                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 214                 status = "disabled";
 215         };
 216
 217         scif0: serial@ffe40000 {
 218                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 219                              "renesas,scif";
 220                 reg = <0xffe40000 0x100>;
 221                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
 223                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 224                 clock-names = "fck", "brg_int", "scif_clk";
 225                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 226                 status = "disabled";
 227         };
 228
 229         scif1: serial@ffe41000 {
 230                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 231                              "renesas,scif";
 232                 reg = <0xffe41000 0x100>;
 233                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
 235                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 236                 clock-names = "fck", "brg_int", "scif_clk";
 237                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 238                 status = "disabled";
 239         };
 240
 241         scif2: serial@ffe42000 {
 242                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 243                              "renesas,scif";
 244                 reg = <0xffe42000 0x100>;
 245                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
 247                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 248                 clock-names = "fck", "brg_int", "scif_clk";
 249                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 250                 status = "disabled";
 251         };
 252
 253         scif3: serial@ffe43000 {
 254                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 255                              "renesas,scif";
 256                 reg = <0xffe43000 0x100>;
 257                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
 259                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 260                 clock-names = "fck", "brg_int", "scif_clk";
 261                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 262                 status = "disabled";
 263         };
 264
 265         scif4: serial@ffe44000 {
 266                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 267                              "renesas,scif";
 268                 reg = <0xffe44000 0x100>;
 269                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
 271                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 272                 clock-names = "fck", "brg_int", "scif_clk";
 273                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 274                 status = "disabled";
 275         };
 276
 277         scif5: serial@ffe45000 {
 278                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 279                              "renesas,scif";
 280                 reg = <0xffe45000 0x100>;
 281                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
 283                          <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
 284                 clock-names = "fck", "brg_int", "scif_clk";
 285                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 286                 status = "disabled";
 287         };
 288
 289         pfc: pfc@fffc0000 {
 290                 compatible = "renesas,pfc-r8a7779";
 291                 reg = <0xfffc0000 0x23c>;
 292         };
 293
 294         thermal@ffc48000 {
 295                 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
 296                 reg = <0xffc48000 0x38>;
 297         };
 298
 299         tmu0: timer@ffd80000 {
 300                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 301                 reg = <0xffd80000 0x30>;
 302                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 305                 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
 306                 clock-names = "fck";
 307                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 308
 309                 #renesas,channels = <3>;
 310
 311                 status = "disabled";
 312         };
 313
 314         tmu1: timer@ffd81000 {
 315                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 316                 reg = <0xffd81000 0x30>;
 317                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
 321                 clock-names = "fck";
 322                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 323
 324                 #renesas,channels = <3>;
 325
 326                 status = "disabled";
 327         };
 328
 329         tmu2: timer@ffd82000 {
 330                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 331                 reg = <0xffd82000 0x30>;
 332                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 333                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 335                 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
 336                 clock-names = "fck";
 337                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 338
 339                 #renesas,channels = <3>;
 340
 341                 status = "disabled";
 342         };
 343
 344         sata: sata@fc600000 {
 345                 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
 346                 reg = <0xfc600000 0x2000>;
 347                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 349                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 350         };
 351
 352         sdhi0: sd@ffe4c000 {
 353                 compatible = "renesas,sdhi-r8a7779";
 354                 reg = <0xffe4c000 0x100>;
 355                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 357                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 358                 status = "disabled";
 359         };
 360
 361         sdhi1: sd@ffe4d000 {
 362                 compatible = "renesas,sdhi-r8a7779";
 363                 reg = <0xffe4d000 0x100>;
 364                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 365                 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 366                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 367                 status = "disabled";
 368         };
 369
 370         sdhi2: sd@ffe4e000 {
 371                 compatible = "renesas,sdhi-r8a7779";
 372                 reg = <0xffe4e000 0x100>;
 373                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 375                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 376                 status = "disabled";
 377         };
 378
 379         sdhi3: sd@ffe4f000 {
 380                 compatible = "renesas,sdhi-r8a7779";
 381                 reg = <0xffe4f000 0x100>;
 382                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 384                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 385                 status = "disabled";
 386         };
 387
 388         hspi0: spi@fffc7000 {
 389                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 390                 reg = <0xfffc7000 0x18>;
 391                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 395                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 396                 status = "disabled";
 397         };
 398
 399         hspi1: spi@fffc8000 {
 400                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 401                 reg = <0xfffc8000 0x18>;
 402                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 406                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 407                 status = "disabled";
 408         };
 409
 410         hspi2: spi@fffc6000 {
 411                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 412                 reg = <0xfffc6000 0x18>;
 413                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 417                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 418                 status = "disabled";
 419         };
 420
 421         du: display@fff80000 {
 422                 compatible = "renesas,du-r8a7779";
 423                 reg = <0xfff80000 0x40000>;
 424                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 425                 clocks = <&mstp1_clks R8A7779_CLK_DU>;
 426                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
 427                 status = "disabled";
 428
 429                 ports {
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432
 433                         port@0 {
 434                                 reg = <0>;
 435                                 du_out_rgb0: endpoint {
 436                                 };
 437                         };
 438                         port@1 {
 439                                 reg = <1>;
 440                                 du_out_rgb1: endpoint {
 441                                 };
 442                         };
 443                 };
 444         };
 445
 446         clocks {
 447                 #address-cells = <1>;
 448                 #size-cells = <1>;
 449                 ranges;
 450
 451                 /* External root clock */
 452                 extal_clk: extal {
 453                         compatible = "fixed-clock";
 454                         #clock-cells = <0>;
 455                         /* This value must be overriden by the board. */
 456                         clock-frequency = <0>;
 457                 };
 458
 459                 /* External SCIF clock */
 460                 scif_clk: scif {
 461                         compatible = "fixed-clock";
 462                         #clock-cells = <0>;
 463                         /* This value must be overridden by the board. */
 464                         clock-frequency = <0>;
 465                 };
 466
 467                 /* Special CPG clocks */
 468                 cpg_clocks: clocks@ffc80000 {
 469                         compatible = "renesas,r8a7779-cpg-clocks";
 470                         reg = <0xffc80000 0x30>;
 471                         clocks = <&extal_clk>;
 472                         #clock-cells = <1>;
 473                         clock-output-names = "plla", "z", "zs", "s",
 474                                              "s1", "p", "b", "out";
 475                         #power-domain-cells = <0>;
 476                 };
 477
 478                 /* Fixed factor clocks */
 479                 i_clk: i {
 480                         compatible = "fixed-factor-clock";
 481                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 482                         #clock-cells = <0>;
 483                         clock-div = <2>;
 484                         clock-mult = <1>;
 485                 };
 486                 s3_clk: s3 {
 487                         compatible = "fixed-factor-clock";
 488                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 489                         #clock-cells = <0>;
 490                         clock-div = <8>;
 491                         clock-mult = <1>;
 492                 };
 493                 s4_clk: s4 {
 494                         compatible = "fixed-factor-clock";
 495                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 496                         #clock-cells = <0>;
 497                         clock-div = <16>;
 498                         clock-mult = <1>;
 499                 };
 500                 g_clk: g {
 501                         compatible = "fixed-factor-clock";
 502                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 503                         #clock-cells = <0>;
 504                         clock-div = <24>;
 505                         clock-mult = <1>;
 506                 };
 507
 508                 /* Gate clocks */
 509                 mstp0_clks: clocks@ffc80030 {
 510                         compatible = "renesas,r8a7779-mstp-clocks",
 511                                      "renesas,cpg-mstp-clocks";
 512                         reg = <0xffc80030 4>;
 513                         clocks = <&cpg_clocks R8A7779_CLK_S>,
 514                                  <&cpg_clocks R8A7779_CLK_P>,
 515                                  <&cpg_clocks R8A7779_CLK_P>,
 516                                  <&cpg_clocks R8A7779_CLK_P>,
 517                                  <&cpg_clocks R8A7779_CLK_S>,
 518                                  <&cpg_clocks R8A7779_CLK_S>,
 519                                  <&cpg_clocks R8A7779_CLK_P>,
 520                                  <&cpg_clocks R8A7779_CLK_P>,
 521                                  <&cpg_clocks R8A7779_CLK_P>,
 522                                  <&cpg_clocks R8A7779_CLK_P>,
 523                                  <&cpg_clocks R8A7779_CLK_P>,
 524                                  <&cpg_clocks R8A7779_CLK_P>,
 525                                  <&cpg_clocks R8A7779_CLK_P>,
 526                                  <&cpg_clocks R8A7779_CLK_P>,
 527                                  <&cpg_clocks R8A7779_CLK_P>,
 528                                  <&cpg_clocks R8A7779_CLK_P>;
 529                         #clock-cells = <1>;
 530                         clock-indices = <
 531                                 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
 532                                 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
 533                                 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
 534                                 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
 535                                 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
 536                                 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
 537                                 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
 538                                 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
 539                         >;
 540                         clock-output-names =
 541                                 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
 542                                 "hscif0", "scif5", "scif4", "scif3", "scif2",
 543                                 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
 544                                 "i2c0";
 545                 };
 546                 mstp1_clks: clocks@ffc80034 {
 547                         compatible = "renesas,r8a7779-mstp-clocks",
 548                                      "renesas,cpg-mstp-clocks";
 549                         reg = <0xffc80034 4>, <0xffc80044 4>;
 550                         clocks = <&cpg_clocks R8A7779_CLK_P>,
 551                                  <&cpg_clocks R8A7779_CLK_P>,
 552                                  <&cpg_clocks R8A7779_CLK_S>,
 553                                  <&cpg_clocks R8A7779_CLK_S>,
 554                                  <&cpg_clocks R8A7779_CLK_S>,
 555                                  <&cpg_clocks R8A7779_CLK_S>,
 556                                  <&cpg_clocks R8A7779_CLK_P>,
 557                                  <&cpg_clocks R8A7779_CLK_P>,
 558                                  <&cpg_clocks R8A7779_CLK_P>,
 559                                  <&cpg_clocks R8A7779_CLK_S>;
 560                         #clock-cells = <1>;
 561                         clock-indices = <
 562                                 R8A7779_CLK_USB01 R8A7779_CLK_USB2
 563                                 R8A7779_CLK_DU R8A7779_CLK_VIN2
 564                                 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
 565                                 R8A7779_CLK_ETHER R8A7779_CLK_SATA
 566                                 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
 567                         >;
 568                         clock-output-names =
 569                                 "usb01", "usb2",
 570                                 "du", "vin2",
 571                                 "vin1", "vin0",
 572                                 "ether", "sata",
 573                                 "pcie", "vin3";
 574                 };
 575                 mstp3_clks: clocks@ffc8003c {
 576                         compatible = "renesas,r8a7779-mstp-clocks",
 577                                      "renesas,cpg-mstp-clocks";
 578                         reg = <0xffc8003c 4>;
 579                         clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
 580                                  <&s4_clk>, <&s4_clk>;
 581                         #clock-cells = <1>;
 582                         clock-indices = <
 583                                 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
 584                                 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
 585                                 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
 586                         >;
 587                         clock-output-names =
 588                                 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
 589                                 "mmc1", "mmc0";
 590                 };
 591         };
 592
 593         prr: chipid@ff000044 {
 594                 compatible = "renesas,prr";
 595                 reg = <0xff000044 4>;
 596         };
 597
 598         rst: reset-controller@ffcc0000 {
 599                 compatible = "renesas,r8a7779-reset-wdt";
 600                 reg = <0xffcc0000 0x48>;
 601         };
 602
 603         sysc: system-controller@ffd85000 {
 604                 compatible = "renesas,r8a7779-sysc";
 605                 reg = <0xffd85000 0x0200>;
 606                 #power-domain-cells = <1>;
 607         };
 608 };