arch/arm/boot/dts/qcom/qcom-msm8974.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interconnect/qcom,msm8974.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         interrupt-parent = <&intc>;
  16
  17         clocks {
  18                 xo_board: xo_board {
  19                         compatible = "fixed-clock";
  20                         #clock-cells = <0>;
  21                         clock-frequency = <19200000>;
  22                 };
  23
  24                 sleep_clk: sleep_clk {
  25                         compatible = "fixed-clock";
  26                         #clock-cells = <0>;
  27                         clock-frequency = <32768>;
  28                 };
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34                 interrupts = <GIC_PPI 9 0xf04>;
  35
  36                 CPU0: cpu@0 {
  37                         compatible = "qcom,krait";
  38                         enable-method = "qcom,kpss-acc-v2";
  39                         device_type = "cpu";
  40                         reg = <0>;
  41                         next-level-cache = <&L2>;
  42                         qcom,acc = <&acc0>;
  43                         qcom,saw = <&saw0>;
  44                         cpu-idle-states = <&CPU_SPC>;
  45                 };
  46
  47                 CPU1: cpu@1 {
  48                         compatible = "qcom,krait";
  49                         enable-method = "qcom,kpss-acc-v2";
  50                         device_type = "cpu";
  51                         reg = <1>;
  52                         next-level-cache = <&L2>;
  53                         qcom,acc = <&acc1>;
  54                         qcom,saw = <&saw1>;
  55                         cpu-idle-states = <&CPU_SPC>;
  56                 };
  57
  58                 CPU2: cpu@2 {
  59                         compatible = "qcom,krait";
  60                         enable-method = "qcom,kpss-acc-v2";
  61                         device_type = "cpu";
  62                         reg = <2>;
  63                         next-level-cache = <&L2>;
  64                         qcom,acc = <&acc2>;
  65                         qcom,saw = <&saw2>;
  66                         cpu-idle-states = <&CPU_SPC>;
  67                 };
  68
  69                 CPU3: cpu@3 {
  70                         compatible = "qcom,krait";
  71                         enable-method = "qcom,kpss-acc-v2";
  72                         device_type = "cpu";
  73                         reg = <3>;
  74                         next-level-cache = <&L2>;
  75                         qcom,acc = <&acc3>;
  76                         qcom,saw = <&saw3>;
  77                         cpu-idle-states = <&CPU_SPC>;
  78                 };
  79
  80                 L2: l2-cache {
  81                         compatible = "cache";
  82                         cache-level = <2>;
  83                         cache-unified;
  84                         qcom,saw = <&saw_l2>;
  85                 };
  86
  87                 idle-states {
  88                         CPU_SPC: spc {
  89                                 compatible = "qcom,idle-state-spc",
  90                                                 "arm,idle-state";
  91                                 entry-latency-us = <150>;
  92                                 exit-latency-us = <200>;
  93                                 min-residency-us = <2000>;
  94                         };
  95                 };
  96         };
  97
  98         firmware {
  99                 scm {
 100                         compatible = "qcom,scm-msm8974", "qcom,scm";
 101                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 102                         clock-names = "core", "bus", "iface";
 103                 };
 104         };
 105
 106         memory {
 107                 device_type = "memory";
 108                 reg = <0x0 0x0>;
 109         };
 110
 111         pmu {
 112                 compatible = "qcom,krait-pmu";
 113                 interrupts = <GIC_PPI 7 0xf04>;
 114         };
 115
 116         reserved-memory {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 ranges;
 120
 121                 mpss_region: mpss@8000000 {
 122                         reg = <0x08000000 0x5100000>;
 123                         no-map;
 124                 };
 125
 126                 mba_region: mba@d100000 {
 127                         reg = <0x0d100000 0x100000>;
 128                         no-map;
 129                 };
 130
 131                 wcnss_region: wcnss@d200000 {
 132                         reg = <0x0d200000 0xa00000>;
 133                         no-map;
 134                 };
 135
 136                 adsp_region: adsp@dc00000 {
 137                         reg = <0x0dc00000 0x1900000>;
 138                         no-map;
 139                 };
 140
 141                 venus_region: memory@f500000 {
 142                         reg = <0x0f500000 0x500000>;
 143                         no-map;
 144                 };
 145
 146                 smem_region: smem@fa00000 {
 147                         reg = <0xfa00000 0x200000>;
 148                         no-map;
 149                 };
 150
 151                 tz_region: memory@fc00000 {
 152                         reg = <0x0fc00000 0x160000>;
 153                         no-map;
 154                 };
 155
 156                 rfsa_mem: memory@fd60000 {
 157                         reg = <0x0fd60000 0x20000>;
 158                         no-map;
 159                 };
 160
 161                 rmtfs@fd80000 {
 162                         compatible = "qcom,rmtfs-mem";
 163                         reg = <0x0fd80000 0x180000>;
 164                         no-map;
 165
 166                         qcom,client-id = <1>;
 167                 };
 168         };
 169
 170         smem {
 171                 compatible = "qcom,smem";
 172
 173                 memory-region = <&smem_region>;
 174                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 175
 176                 hwlocks = <&tcsr_mutex 3>;
 177         };
 178
 179         smp2p-adsp {
 180                 compatible = "qcom,smp2p";
 181                 qcom,smem = <443>, <429>;
 182
 183                 interrupt-parent = <&intc>;
 184                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 185
 186                 qcom,ipc = <&apcs 8 10>;
 187
 188                 qcom,local-pid = <0>;
 189                 qcom,remote-pid = <2>;
 190
 191                 adsp_smp2p_out: master-kernel {
 192                         qcom,entry-name = "master-kernel";
 193                         #qcom,smem-state-cells = <1>;
 194                 };
 195
 196                 adsp_smp2p_in: slave-kernel {
 197                         qcom,entry-name = "slave-kernel";
 198
 199                         interrupt-controller;
 200                         #interrupt-cells = <2>;
 201                 };
 202         };
 203
 204         smp2p-modem {
 205                 compatible = "qcom,smp2p";
 206                 qcom,smem = <435>, <428>;
 207
 208                 interrupt-parent = <&intc>;
 209                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 210
 211                 qcom,ipc = <&apcs 8 14>;
 212
 213                 qcom,local-pid = <0>;
 214                 qcom,remote-pid = <1>;
 215
 216                 modem_smp2p_out: master-kernel {
 217                         qcom,entry-name = "master-kernel";
 218                         #qcom,smem-state-cells = <1>;
 219                 };
 220
 221                 modem_smp2p_in: slave-kernel {
 222                         qcom,entry-name = "slave-kernel";
 223
 224                         interrupt-controller;
 225                         #interrupt-cells = <2>;
 226                 };
 227         };
 228
 229         smp2p-wcnss {
 230                 compatible = "qcom,smp2p";
 231                 qcom,smem = <451>, <431>;
 232
 233                 interrupt-parent = <&intc>;
 234                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 235
 236                 qcom,ipc = <&apcs 8 18>;
 237
 238                 qcom,local-pid = <0>;
 239                 qcom,remote-pid = <4>;
 240
 241                 wcnss_smp2p_out: master-kernel {
 242                         qcom,entry-name = "master-kernel";
 243
 244                         #qcom,smem-state-cells = <1>;
 245                 };
 246
 247                 wcnss_smp2p_in: slave-kernel {
 248                         qcom,entry-name = "slave-kernel";
 249
 250                         interrupt-controller;
 251                         #interrupt-cells = <2>;
 252                 };
 253         };
 254
 255         smsm {
 256                 compatible = "qcom,smsm";
 257
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260
 261                 qcom,ipc-1 = <&apcs 8 13>;
 262                 qcom,ipc-2 = <&apcs 8 9>;
 263                 qcom,ipc-3 = <&apcs 8 19>;
 264
 265                 apps_smsm: apps@0 {
 266                         reg = <0>;
 267
 268                         #qcom,smem-state-cells = <1>;
 269                 };
 270
 271                 modem_smsm: modem@1 {
 272                         reg = <1>;
 273                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 274
 275                         interrupt-controller;
 276                         #interrupt-cells = <2>;
 277                 };
 278
 279                 adsp_smsm: adsp@2 {
 280                         reg = <2>;
 281                         interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
 282
 283                         interrupt-controller;
 284                         #interrupt-cells = <2>;
 285                 };
 286
 287                 wcnss_smsm: wcnss@7 {
 288                         reg = <7>;
 289                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 290
 291                         interrupt-controller;
 292                         #interrupt-cells = <2>;
 293                 };
 294         };
 295
 296         smd {
 297                 compatible = "qcom,smd";
 298
 299                 rpm {
 300                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 301                         qcom,ipc = <&apcs 8 0>;
 302                         qcom,smd-edge = <15>;
 303
 304                         rpm_requests: rpm-requests {
 305                                 compatible = "qcom,rpm-msm8974";
 306                                 qcom,smd-channels = "rpm_requests";
 307
 308                                 rpmcc: clock-controller {
 309                                         compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
 310                                         #clock-cells = <1>;
 311                                         clocks = <&xo_board>;
 312                                         clock-names = "xo";
 313                                 };
 314                         };
 315                 };
 316         };
 317
 318         soc: soc {
 319                 #address-cells = <1>;
 320                 #size-cells = <1>;
 321                 ranges;
 322                 compatible = "simple-bus";
 323
 324                 intc: interrupt-controller@f9000000 {
 325                         compatible = "qcom,msm-qgic2";
 326                         interrupt-controller;
 327                         #interrupt-cells = <3>;
 328                         reg = <0xf9000000 0x1000>,
 329                               <0xf9002000 0x1000>;
 330                 };
 331
 332                 apcs: syscon@f9011000 {
 333                         compatible = "syscon";
 334                         reg = <0xf9011000 0x1000>;
 335                 };
 336
 337                 timer@f9020000 {
 338                         #address-cells = <1>;
 339                         #size-cells = <1>;
 340                         ranges;
 341                         compatible = "arm,armv7-timer-mem";
 342                         reg = <0xf9020000 0x1000>;
 343                         clock-frequency = <19200000>;
 344
 345                         frame@f9021000 {
 346                                 frame-number = <0>;
 347                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 348                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 349                                 reg = <0xf9021000 0x1000>,
 350                                       <0xf9022000 0x1000>;
 351                         };
 352
 353                         frame@f9023000 {
 354                                 frame-number = <1>;
 355                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 356                                 reg = <0xf9023000 0x1000>;
 357                                 status = "disabled";
 358                         };
 359
 360                         frame@f9024000 {
 361                                 frame-number = <2>;
 362                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 363                                 reg = <0xf9024000 0x1000>;
 364                                 status = "disabled";
 365                         };
 366
 367                         frame@f9025000 {
 368                                 frame-number = <3>;
 369                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 370                                 reg = <0xf9025000 0x1000>;
 371                                 status = "disabled";
 372                         };
 373
 374                         frame@f9026000 {
 375                                 frame-number = <4>;
 376                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 377                                 reg = <0xf9026000 0x1000>;
 378                                 status = "disabled";
 379                         };
 380
 381                         frame@f9027000 {
 382                                 frame-number = <5>;
 383                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 384                                 reg = <0xf9027000 0x1000>;
 385                                 status = "disabled";
 386                         };
 387
 388                         frame@f9028000 {
 389                                 frame-number = <6>;
 390                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 391                                 reg = <0xf9028000 0x1000>;
 392                                 status = "disabled";
 393                         };
 394                 };
 395
 396                 saw0: power-controller@f9089000 {
 397                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 398                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 399                 };
 400
 401                 saw1: power-controller@f9099000 {
 402                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 403                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 404                 };
 405
 406                 saw2: power-controller@f90a9000 {
 407                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 408                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 409                 };
 410
 411                 saw3: power-controller@f90b9000 {
 412                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
 413                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 414                 };
 415
 416                 saw_l2: power-controller@f9012000 {
 417                         compatible = "qcom,saw2";
 418                         reg = <0xf9012000 0x1000>;
 419                         regulator;
 420                 };
 421
 422                 acc0: power-manager@f9088000 {
 423                         compatible = "qcom,kpss-acc-v2";
 424                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 425                 };
 426
 427                 acc1: power-manager@f9098000 {
 428                         compatible = "qcom,kpss-acc-v2";
 429                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 430                 };
 431
 432                 acc2: power-manager@f90a8000 {
 433                         compatible = "qcom,kpss-acc-v2";
 434                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 435                 };
 436
 437                 acc3: power-manager@f90b8000 {
 438                         compatible = "qcom,kpss-acc-v2";
 439                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 440                 };
 441
 442                 sdhc_1: mmc@f9824900 {
 443                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 444                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 445                         reg-names = "hc", "core";
 446                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 447                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 448                         interrupt-names = "hc_irq", "pwr_irq";
 449                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 450                                  <&gcc GCC_SDCC1_APPS_CLK>,
 451                                  <&xo_board>;
 452                         clock-names = "iface", "core", "xo";
 453                         bus-width = <8>;
 454                         non-removable;
 455
 456                         status = "disabled";
 457                 };
 458
 459                 sdhc_3: mmc@f9864900 {
 460                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 461                         reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
 462                         reg-names = "hc", "core";
 463                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 464                                      <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 465                         interrupt-names = "hc_irq", "pwr_irq";
 466                         clocks = <&gcc GCC_SDCC3_AHB_CLK>,
 467                                  <&gcc GCC_SDCC3_APPS_CLK>,
 468                                  <&xo_board>;
 469                         clock-names = "iface", "core", "xo";
 470                         bus-width = <4>;
 471
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474
 475                         status = "disabled";
 476                 };
 477
 478                 sdhc_2: mmc@f98a4900 {
 479                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 480                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 481                         reg-names = "hc", "core";
 482                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 483                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 484                         interrupt-names = "hc_irq", "pwr_irq";
 485                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 486                                  <&gcc GCC_SDCC2_APPS_CLK>,
 487                                  <&xo_board>;
 488                         clock-names = "iface", "core", "xo";
 489                         bus-width = <4>;
 490
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493
 494                         status = "disabled";
 495                 };
 496
 497                 blsp1_uart1: serial@f991d000 {
 498                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 499                         reg = <0xf991d000 0x1000>;
 500                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 502                         clock-names = "core", "iface";
 503                         status = "disabled";
 504                 };
 505
 506                 blsp1_uart2: serial@f991e000 {
 507                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 508                         reg = <0xf991e000 0x1000>;
 509                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 511                         clock-names = "core", "iface";
 512                         pinctrl-names = "default";
 513                         pinctrl-0 = <&blsp1_uart2_default>;
 514                         status = "disabled";
 515                 };
 516
 517                 blsp1_i2c1: i2c@f9923000 {
 518                         status = "disabled";
 519                         compatible = "qcom,i2c-qup-v2.1.1";
 520                         reg = <0xf9923000 0x1000>;
 521                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 522                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 523                         clock-names = "core", "iface";
 524                         pinctrl-names = "default", "sleep";
 525                         pinctrl-0 = <&blsp1_i2c1_default>;
 526                         pinctrl-1 = <&blsp1_i2c1_sleep>;
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                 };
 530
 531                 blsp1_i2c2: i2c@f9924000 {
 532                         status = "disabled";
 533                         compatible = "qcom,i2c-qup-v2.1.1";
 534                         reg = <0xf9924000 0x1000>;
 535                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 536                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 537                         clock-names = "core", "iface";
 538                         pinctrl-names = "default", "sleep";
 539                         pinctrl-0 = <&blsp1_i2c2_default>;
 540                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                 };
 544
 545                 blsp1_i2c3: i2c@f9925000 {
 546                         status = "disabled";
 547                         compatible = "qcom,i2c-qup-v2.1.1";
 548                         reg = <0xf9925000 0x1000>;
 549                         interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 550                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 551                         clock-names = "core", "iface";
 552                         pinctrl-names = "default", "sleep";
 553                         pinctrl-0 = <&blsp1_i2c3_default>;
 554                         pinctrl-1 = <&blsp1_i2c3_sleep>;
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                 };
 558
 559                 blsp1_i2c6: i2c@f9928000 {
 560                         status = "disabled";
 561                         compatible = "qcom,i2c-qup-v2.1.1";
 562                         reg = <0xf9928000 0x1000>;
 563                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 565                         clock-names = "core", "iface";
 566                         pinctrl-names = "default", "sleep";
 567                         pinctrl-0 = <&blsp1_i2c6_default>;
 568                         pinctrl-1 = <&blsp1_i2c6_sleep>;
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                 };
 572
 573                 blsp2_dma: dma-controller@f9944000 {
 574                         compatible = "qcom,bam-v1.4.0";
 575                         reg = <0xf9944000 0x19000>;
 576                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 577                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 578                         clock-names = "bam_clk";
 579                         #dma-cells = <1>;
 580                         qcom,ee = <0>;
 581                 };
 582
 583                 blsp2_uart1: serial@f995d000 {
 584                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 585                         reg = <0xf995d000 0x1000>;
 586                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 587                         clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 588                         clock-names = "core", "iface";
 589                         pinctrl-names = "default", "sleep";
 590                         pinctrl-0 = <&blsp2_uart1_default>;
 591                         pinctrl-1 = <&blsp2_uart1_sleep>;
 592                         status = "disabled";
 593                 };
 594
 595                 blsp2_uart2: serial@f995e000 {
 596                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 597                         reg = <0xf995e000 0x1000>;
 598                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 600                         clock-names = "core", "iface";
 601                         status = "disabled";
 602                 };
 603
 604                 blsp2_uart4: serial@f9960000 {
 605                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 606                         reg = <0xf9960000 0x1000>;
 607                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 608                         clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 609                         clock-names = "core", "iface";
 610                         pinctrl-names = "default";
 611                         pinctrl-0 = <&blsp2_uart4_default>;
 612                         status = "disabled";
 613                 };
 614
 615                 blsp2_i2c2: i2c@f9964000 {
 616                         status = "disabled";
 617                         compatible = "qcom,i2c-qup-v2.1.1";
 618                         reg = <0xf9964000 0x1000>;
 619                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 620                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 621                         clock-names = "core", "iface";
 622                         pinctrl-names = "default", "sleep";
 623                         pinctrl-0 = <&blsp2_i2c2_default>;
 624                         pinctrl-1 = <&blsp2_i2c2_sleep>;
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                 };
 628
 629                 blsp2_i2c5: i2c@f9967000 {
 630                         status = "disabled";
 631                         compatible = "qcom,i2c-qup-v2.1.1";
 632                         reg = <0xf9967000 0x1000>;
 633                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 634                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 635                         clock-names = "core", "iface";
 636                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 637                         dma-names = "tx", "rx";
 638                         pinctrl-names = "default", "sleep";
 639                         pinctrl-0 = <&blsp2_i2c5_default>;
 640                         pinctrl-1 = <&blsp2_i2c5_sleep>;
 641                         #address-cells = <1>;
 642                         #size-cells = <0>;
 643                 };
 644
 645                 blsp2_i2c6: i2c@f9968000 {
 646                         status = "disabled";
 647                         compatible = "qcom,i2c-qup-v2.1.1";
 648                         reg = <0xf9968000 0x1000>;
 649                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 650                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 651                         clock-names = "core", "iface";
 652                         pinctrl-names = "default", "sleep";
 653                         pinctrl-0 = <&blsp2_i2c6_default>;
 654                         pinctrl-1 = <&blsp2_i2c6_sleep>;
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                 };
 658
 659                 usb: usb@f9a55000 {
 660                         compatible = "qcom,ci-hdrc";
 661                         reg = <0xf9a55000 0x200>,
 662                               <0xf9a55200 0x200>;
 663                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 664                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 665                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 666                         clock-names = "iface", "core";
 667                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 668                         assigned-clock-rates = <75000000>;
 669                         resets = <&gcc GCC_USB_HS_BCR>;
 670                         reset-names = "core";
 671                         phy_type = "ulpi";
 672                         dr_mode = "otg";
 673                         ahb-burst-config = <0>;
 674                         phy-names = "usb-phy";
 675                         status = "disabled";
 676                         #reset-cells = <1>;
 677
 678                         ulpi {
 679                                 usb_hs1_phy: phy-0 {
 680                                         compatible = "qcom,usb-hs-phy-msm8974",
 681                                                      "qcom,usb-hs-phy";
 682                                         #phy-cells = <0>;
 683                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 684                                         clock-names = "ref", "sleep";
 685                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
 686                                         reset-names = "phy", "por";
 687                                         status = "disabled";
 688                                 };
 689
 690                                 usb_hs2_phy: phy-1 {
 691                                         compatible = "qcom,usb-hs-phy-msm8974",
 692                                                      "qcom,usb-hs-phy";
 693                                         #phy-cells = <0>;
 694                                         clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
 695                                         clock-names = "ref", "sleep";
 696                                         resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>;
 697                                         reset-names = "phy", "por";
 698                                         status = "disabled";
 699                                 };
 700                         };
 701                 };
 702
 703                 rng@f9bff000 {
 704                         compatible = "qcom,prng";
 705                         reg = <0xf9bff000 0x200>;
 706                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 707                         clock-names = "core";
 708                 };
 709
 710                 pronto: remoteproc@fb204000 {
 711                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
 712                         reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
 713                         reg-names = "ccu", "dxe", "pmu";
 714
 715                         memory-region = <&wcnss_region>;
 716
 717                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
 718                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 719                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 720                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 721                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 722                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 723
 724                         qcom,smem-states = <&wcnss_smp2p_out 0>;
 725                         qcom,smem-state-names = "stop";
 726
 727                         status = "disabled";
 728
 729                         iris {
 730                                 compatible = "qcom,wcn3680";
 731
 732                                 clocks = <&rpmcc RPM_SMD_CXO_A2>;
 733                                 clock-names = "xo";
 734                         };
 735
 736                         smd-edge {
 737                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
 738
 739                                 qcom,ipc = <&apcs 8 17>;
 740                                 qcom,smd-edge = <6>;
 741
 742                                 wcnss {
 743                                         compatible = "qcom,wcnss";
 744                                         qcom,smd-channels = "WCNSS_CTRL";
 745                                         status = "disabled";
 746
 747                                         qcom,mmio = <&pronto>;
 748
 749                                         bluetooth {
 750                                                 compatible = "qcom,wcnss-bt";
 751                                         };
 752
 753                                         wifi {
 754                                                 compatible = "qcom,wcnss-wlan";
 755
 756                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
 757                                                              <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
 758                                                 interrupt-names = "tx", "rx";
 759
 760                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
 761                                                 qcom,smem-state-names = "tx-enable",
 762                                                                         "tx-rings-empty";
 763                                         };
 764                                 };
 765                         };
 766                 };
 767
 768                 sram@fc190000 {
 769                         compatible = "qcom,msm8974-rpm-stats";
 770                         reg = <0xfc190000 0x10000>;
 771                 };
 772
 773                 etf@fc307000 {
 774                         compatible = "arm,coresight-tmc", "arm,primecell";
 775                         reg = <0xfc307000 0x1000>;
 776
 777                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 778                         clock-names = "apb_pclk", "atclk";
 779
 780                         out-ports {
 781                                 port {
 782                                         etf_out: endpoint {
 783                                                 remote-endpoint = <&replicator_in>;
 784                                         };
 785                                 };
 786                         };
 787
 788                         in-ports {
 789                                 port {
 790                                         etf_in: endpoint {
 791                                                 remote-endpoint = <&merger_out>;
 792                                         };
 793                                 };
 794                         };
 795                 };
 796
 797                 tpiu@fc318000 {
 798                         compatible = "arm,coresight-tpiu", "arm,primecell";
 799                         reg = <0xfc318000 0x1000>;
 800
 801                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 802                         clock-names = "apb_pclk", "atclk";
 803
 804                         in-ports {
 805                                 port {
 806                                         tpiu_in: endpoint {
 807                                                 remote-endpoint = <&replicator_out1>;
 808                                         };
 809                                  };
 810                         };
 811                 };
 812
 813                 funnel@fc31a000 {
 814                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 815                         reg = <0xfc31a000 0x1000>;
 816
 817                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 818                         clock-names = "apb_pclk", "atclk";
 819
 820                         in-ports {
 821                                 #address-cells = <1>;
 822                                 #size-cells = <0>;
 823
 824                                 /*
 825                                  * Not described input ports:
 826                                  * 0 - not-connected
 827                                  * 1 - connected trought funnel to Multimedia CPU
 828                                  * 2 - connected to Wireless CPU
 829                                  * 3 - not-connected
 830                                  * 4 - not-connected
 831                                  * 6 - not-connected
 832                                  * 7 - connected to STM
 833                                  */
 834                                 port@5 {
 835                                         reg = <5>;
 836                                         funnel1_in5: endpoint {
 837                                                 remote-endpoint = <&kpss_out>;
 838                                         };
 839                                 };
 840                         };
 841
 842                         out-ports {
 843                                 port {
 844                                         funnel1_out: endpoint {
 845                                                 remote-endpoint = <&merger_in1>;
 846                                         };
 847                                 };
 848                         };
 849                 };
 850
 851                 funnel@fc31b000 {
 852                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 853                         reg = <0xfc31b000 0x1000>;
 854
 855                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 856                         clock-names = "apb_pclk", "atclk";
 857
 858                         in-ports {
 859                                 #address-cells = <1>;
 860                                 #size-cells = <0>;
 861
 862                                 /*
 863                                  * Not described input ports:
 864                                  * 0 - connected trought funnel to Audio, Modem and
 865                                  *     Resource and Power Manager CPU's
 866                                  * 2...7 - not-connected
 867                                  */
 868                                 port@1 {
 869                                         reg = <1>;
 870                                         merger_in1: endpoint {
 871                                                 remote-endpoint = <&funnel1_out>;
 872                                         };
 873                                 };
 874                         };
 875
 876                         out-ports {
 877                                 port {
 878                                         merger_out: endpoint {
 879                                                 remote-endpoint = <&etf_in>;
 880                                         };
 881                                 };
 882                         };
 883                 };
 884
 885                 replicator@fc31c000 {
 886                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 887                         reg = <0xfc31c000 0x1000>;
 888
 889                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 890                         clock-names = "apb_pclk", "atclk";
 891
 892                         out-ports {
 893                                 #address-cells = <1>;
 894                                 #size-cells = <0>;
 895
 896                                 port@0 {
 897                                         reg = <0>;
 898                                         replicator_out0: endpoint {
 899                                                 remote-endpoint = <&etr_in>;
 900                                         };
 901                                 };
 902                                 port@1 {
 903                                         reg = <1>;
 904                                         replicator_out1: endpoint {
 905                                                 remote-endpoint = <&tpiu_in>;
 906                                         };
 907                                 };
 908                         };
 909
 910                         in-ports {
 911                                 port {
 912                                         replicator_in: endpoint {
 913                                                 remote-endpoint = <&etf_out>;
 914                                         };
 915                                 };
 916                         };
 917                 };
 918
 919                 etr@fc322000 {
 920                         compatible = "arm,coresight-tmc", "arm,primecell";
 921                         reg = <0xfc322000 0x1000>;
 922
 923                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 924                         clock-names = "apb_pclk", "atclk";
 925
 926                         in-ports {
 927                                 port {
 928                                         etr_in: endpoint {
 929                                                 remote-endpoint = <&replicator_out0>;
 930                                         };
 931                                 };
 932                         };
 933                 };
 934
 935                 etm@fc33c000 {
 936                         compatible = "arm,coresight-etm4x", "arm,primecell";
 937                         reg = <0xfc33c000 0x1000>;
 938
 939                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 940                         clock-names = "apb_pclk", "atclk";
 941
 942                         cpu = <&CPU0>;
 943
 944                         out-ports {
 945                                 port {
 946                                         etm0_out: endpoint {
 947                                                 remote-endpoint = <&kpss_in0>;
 948                                         };
 949                                 };
 950                         };
 951                 };
 952
 953                 etm@fc33d000 {
 954                         compatible = "arm,coresight-etm4x", "arm,primecell";
 955                         reg = <0xfc33d000 0x1000>;
 956
 957                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 958                         clock-names = "apb_pclk", "atclk";
 959
 960                         cpu = <&CPU1>;
 961
 962                         out-ports {
 963                                 port {
 964                                         etm1_out: endpoint {
 965                                                 remote-endpoint = <&kpss_in1>;
 966                                         };
 967                                 };
 968                         };
 969                 };
 970
 971                 etm@fc33e000 {
 972                         compatible = "arm,coresight-etm4x", "arm,primecell";
 973                         reg = <0xfc33e000 0x1000>;
 974
 975                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 976                         clock-names = "apb_pclk", "atclk";
 977
 978                         cpu = <&CPU2>;
 979
 980                         out-ports {
 981                                 port {
 982                                         etm2_out: endpoint {
 983                                                 remote-endpoint = <&kpss_in2>;
 984                                         };
 985                                 };
 986                         };
 987                 };
 988
 989                 etm@fc33f000 {
 990                         compatible = "arm,coresight-etm4x", "arm,primecell";
 991                         reg = <0xfc33f000 0x1000>;
 992
 993                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 994                         clock-names = "apb_pclk", "atclk";
 995
 996                         cpu = <&CPU3>;
 997
 998                         out-ports {
 999                                 port {
1000                                         etm3_out: endpoint {
1001                                                 remote-endpoint = <&kpss_in3>;
1002                                         };
1003                                 };
1004                         };
1005                 };
1006
1007                 /* KPSS funnel, only 4 inputs are used */
1008                 funnel@fc345000 {
1009                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1010                         reg = <0xfc345000 0x1000>;
1011
1012                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1013                         clock-names = "apb_pclk", "atclk";
1014
1015                         in-ports {
1016                                 #address-cells = <1>;
1017                                 #size-cells = <0>;
1018
1019                                 port@0 {
1020                                         reg = <0>;
1021                                         kpss_in0: endpoint {
1022                                                 remote-endpoint = <&etm0_out>;
1023                                         };
1024                                 };
1025                                 port@1 {
1026                                         reg = <1>;
1027                                         kpss_in1: endpoint {
1028                                                 remote-endpoint = <&etm1_out>;
1029                                         };
1030                                 };
1031                                 port@2 {
1032                                         reg = <2>;
1033                                         kpss_in2: endpoint {
1034                                                 remote-endpoint = <&etm2_out>;
1035                                         };
1036                                 };
1037                                 port@3 {
1038                                         reg = <3>;
1039                                         kpss_in3: endpoint {
1040                                                 remote-endpoint = <&etm3_out>;
1041                                         };
1042                                 };
1043                         };
1044
1045                         out-ports {
1046                                 port {
1047                                         kpss_out: endpoint {
1048                                                 remote-endpoint = <&funnel1_in5>;
1049                                         };
1050                                 };
1051                         };
1052                 };
1053
1054                 gcc: clock-controller@fc400000 {
1055                         compatible = "qcom,gcc-msm8974";
1056                         #clock-cells = <1>;
1057                         #reset-cells = <1>;
1058                         #power-domain-cells = <1>;
1059                         reg = <0xfc400000 0x4000>;
1060
1061                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1062                                  <&sleep_clk>;
1063                         clock-names = "xo",
1064                                       "sleep_clk";
1065                 };
1066
1067                 rpm_msg_ram: sram@fc428000 {
1068                         compatible = "qcom,rpm-msg-ram";
1069                         reg = <0xfc428000 0x4000>;
1070                 };
1071
1072                 bimc: interconnect@fc380000 {
1073                         reg = <0xfc380000 0x6a000>;
1074                         compatible = "qcom,msm8974-bimc";
1075                         #interconnect-cells = <1>;
1076                         clock-names = "bus", "bus_a";
1077                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1078                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
1079                 };
1080
1081                 snoc: interconnect@fc460000 {
1082                         reg = <0xfc460000 0x4000>;
1083                         compatible = "qcom,msm8974-snoc";
1084                         #interconnect-cells = <1>;
1085                         clock-names = "bus", "bus_a";
1086                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1087                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
1088                 };
1089
1090                 pnoc: interconnect@fc468000 {
1091                         reg = <0xfc468000 0x4000>;
1092                         compatible = "qcom,msm8974-pnoc";
1093                         #interconnect-cells = <1>;
1094                         clock-names = "bus", "bus_a";
1095                         clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1096                                  <&rpmcc RPM_SMD_PNOC_A_CLK>;
1097                 };
1098
1099                 ocmemnoc: interconnect@fc470000 {
1100                         reg = <0xfc470000 0x4000>;
1101                         compatible = "qcom,msm8974-ocmemnoc";
1102                         #interconnect-cells = <1>;
1103                         clock-names = "bus", "bus_a";
1104                         clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1105                                  <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1106                 };
1107
1108                 mmssnoc: interconnect@fc478000 {
1109                         reg = <0xfc478000 0x4000>;
1110                         compatible = "qcom,msm8974-mmssnoc";
1111                         #interconnect-cells = <1>;
1112                         clock-names = "bus", "bus_a";
1113                         clocks = <&mmcc MMSS_S0_AXI_CLK>,
1114                                  <&mmcc MMSS_S0_AXI_CLK>;
1115                 };
1116
1117                 cnoc: interconnect@fc480000 {
1118                         reg = <0xfc480000 0x4000>;
1119                         compatible = "qcom,msm8974-cnoc";
1120                         #interconnect-cells = <1>;
1121                         clock-names = "bus", "bus_a";
1122                         clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1123                                  <&rpmcc RPM_SMD_CNOC_A_CLK>;
1124                 };
1125
1126                 tsens: thermal-sensor@fc4a9000 {
1127                         compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
1128                         reg = <0xfc4a9000 0x1000>, /* TM */
1129                               <0xfc4a8000 0x1000>; /* SROT */
1130                         nvmem-cells = <&tsens_mode>,
1131                                       <&tsens_base1>, <&tsens_base2>,
1132                                       <&tsens_use_backup>,
1133                                       <&tsens_mode_backup>,
1134                                       <&tsens_base1_backup>, <&tsens_base2_backup>,
1135                                       <&tsens_s0_p1>, <&tsens_s0_p2>,
1136                                       <&tsens_s1_p1>, <&tsens_s1_p2>,
1137                                       <&tsens_s2_p1>, <&tsens_s2_p2>,
1138                                       <&tsens_s3_p1>, <&tsens_s3_p2>,
1139                                       <&tsens_s4_p1>, <&tsens_s4_p2>,
1140                                       <&tsens_s5_p1>, <&tsens_s5_p2>,
1141                                       <&tsens_s6_p1>, <&tsens_s6_p2>,
1142                                       <&tsens_s7_p1>, <&tsens_s7_p2>,
1143                                       <&tsens_s8_p1>, <&tsens_s8_p2>,
1144                                       <&tsens_s9_p1>, <&tsens_s9_p2>,
1145                                       <&tsens_s10_p1>, <&tsens_s10_p2>,
1146                                       <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
1147                                       <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
1148                                       <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
1149                                       <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
1150                                       <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
1151                                       <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
1152                                       <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
1153                                       <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
1154                                       <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
1155                                       <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
1156                                       <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
1157                         nvmem-cell-names = "mode",
1158                                            "base1", "base2",
1159                                            "use_backup",
1160                                            "mode_backup",
1161                                            "base1_backup", "base2_backup",
1162                                            "s0_p1", "s0_p2",
1163                                            "s1_p1", "s1_p2",
1164                                            "s2_p1", "s2_p2",
1165                                            "s3_p1", "s3_p2",
1166                                            "s4_p1", "s4_p2",
1167                                            "s5_p1", "s5_p2",
1168                                            "s6_p1", "s6_p2",
1169                                            "s7_p1", "s7_p2",
1170                                            "s8_p1", "s8_p2",
1171                                            "s9_p1", "s9_p2",
1172                                            "s10_p1", "s10_p2",
1173                                            "s0_p1_backup", "s0_p2_backup",
1174                                            "s1_p1_backup", "s1_p2_backup",
1175                                            "s2_p1_backup", "s2_p2_backup",
1176                                            "s3_p1_backup", "s3_p2_backup",
1177                                            "s4_p1_backup", "s4_p2_backup",
1178                                            "s5_p1_backup", "s5_p2_backup",
1179                                            "s6_p1_backup", "s6_p2_backup",
1180                                            "s7_p1_backup", "s7_p2_backup",
1181                                            "s8_p1_backup", "s8_p2_backup",
1182                                            "s9_p1_backup", "s9_p2_backup",
1183                                            "s10_p1_backup", "s10_p2_backup";
1184                         #qcom,sensors = <11>;
1185                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1186                         interrupt-names = "uplow";
1187                         #thermal-sensor-cells = <1>;
1188                 };
1189
1190                 restart@fc4ab000 {
1191                         compatible = "qcom,pshold";
1192                         reg = <0xfc4ab000 0x4>;
1193                 };
1194
1195                 qfprom: qfprom@fc4bc000 {
1196                         compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1197                         reg = <0xfc4bc000 0x1000>;
1198                         #address-cells = <1>;
1199                         #size-cells = <1>;
1200
1201                         tsens_base1: base1@d0 {
1202                                 reg = <0xd0 0x1>;
1203                                 bits = <0 8>;
1204                         };
1205
1206                         tsens_s0_p1: s0-p1@d1 {
1207                                 reg = <0xd1 0x1>;
1208                                 bits = <0 6>;
1209                         };
1210
1211                         tsens_s1_p1: s1-p1@d2 {
1212                                 reg = <0xd1 0x2>;
1213                                 bits = <6 6>;
1214                         };
1215
1216                         tsens_s2_p1: s2-p1@d2 {
1217                                 reg = <0xd2 0x2>;
1218                                 bits = <4 6>;
1219                         };
1220
1221                         tsens_s3_p1: s3-p1@d3 {
1222                                 reg = <0xd3 0x1>;
1223                                 bits = <2 6>;
1224                         };
1225
1226                         tsens_s4_p1: s4-p1@d4 {
1227                                 reg = <0xd4 0x1>;
1228                                 bits = <0 6>;
1229                         };
1230
1231                         tsens_s5_p1: s5-p1@d4 {
1232                                 reg = <0xd4 0x2>;
1233                                 bits = <6 6>;
1234                         };
1235
1236                         tsens_s6_p1: s6-p1@d5 {
1237                                 reg = <0xd5 0x2>;
1238                                 bits = <4 6>;
1239                         };
1240
1241                         tsens_s7_p1: s7-p1@d6 {
1242                                 reg = <0xd6 0x1>;
1243                                 bits = <2 6>;
1244                         };
1245
1246                         tsens_s8_p1: s8-p1@d7 {
1247                                 reg = <0xd7 0x1>;
1248                                 bits = <0 6>;
1249                         };
1250
1251                         tsens_mode: mode@d7 {
1252                                 reg = <0xd7 0x1>;
1253                                 bits = <6 2>;
1254                         };
1255
1256                         tsens_s9_p1: s9-p1@d8 {
1257                                 reg = <0xd8 0x1>;
1258                                 bits = <0 6>;
1259                         };
1260
1261                         tsens_s10_p1: s10_p1@d8 {
1262                                 reg = <0xd8 0x2>;
1263                                 bits = <6 6>;
1264                         };
1265
1266                         tsens_base2: base2@d9 {
1267                                 reg = <0xd9 0x2>;
1268                                 bits = <4 8>;
1269                         };
1270
1271                         tsens_s0_p2: s0-p2@da {
1272                                 reg = <0xda 0x2>;
1273                                 bits = <4 6>;
1274                         };
1275
1276                         tsens_s1_p2: s1-p2@db {
1277                                 reg = <0xdb 0x1>;
1278                                 bits = <2 6>;
1279                         };
1280
1281                         tsens_s2_p2: s2-p2@dc {
1282                                 reg = <0xdc 0x1>;
1283                                 bits = <0 6>;
1284                         };
1285
1286                         tsens_s3_p2: s3-p2@dc {
1287                                 reg = <0xdc 0x2>;
1288                                 bits = <6 6>;
1289                         };
1290
1291                         tsens_s4_p2: s4-p2@dd {
1292                                 reg = <0xdd 0x2>;
1293                                 bits = <4 6>;
1294                         };
1295
1296                         tsens_s5_p2: s5-p2@de {
1297                                 reg = <0xde 0x2>;
1298                                 bits = <2 6>;
1299                         };
1300
1301                         tsens_s6_p2: s6-p2@df {
1302                                 reg = <0xdf 0x1>;
1303                                 bits = <0 6>;
1304                         };
1305
1306                         tsens_s7_p2: s7-p2@e0 {
1307                                 reg = <0xe0 0x1>;
1308                                 bits = <0 6>;
1309                         };
1310
1311                         tsens_s8_p2: s8-p2@e0 {
1312                                 reg = <0xe0 0x2>;
1313                                 bits = <6 6>;
1314                         };
1315
1316                         tsens_s9_p2: s9-p2@e1 {
1317                                 reg = <0xe1 0x2>;
1318                                 bits = <4 6>;
1319                         };
1320
1321                         tsens_s10_p2: s10_p2@e2 {
1322                                 reg = <0xe2 0x2>;
1323                                 bits = <2 6>;
1324                         };
1325
1326                         tsens_s5_p2_backup: s5-p2_backup@e3 {
1327                                 reg = <0xe3 0x2>;
1328                                 bits = <0 6>;
1329                         };
1330
1331                         tsens_mode_backup: mode_backup@e3 {
1332                                 reg = <0xe3 0x1>;
1333                                 bits = <6 2>;
1334                         };
1335
1336                         tsens_s6_p2_backup: s6-p2_backup@e4 {
1337                                 reg = <0xe4 0x1>;
1338                                 bits = <0 6>;
1339                         };
1340
1341                         tsens_s7_p2_backup: s7-p2_backup@e4 {
1342                                 reg = <0xe4 0x2>;
1343                                 bits = <6 6>;
1344                         };
1345
1346                         tsens_s8_p2_backup: s8-p2_backup@e5 {
1347                                 reg = <0xe5 0x2>;
1348                                 bits = <4 6>;
1349                         };
1350
1351                         tsens_s9_p2_backup: s9-p2_backup@e6 {
1352                                 reg = <0xe6 0x2>;
1353                                 bits = <2 6>;
1354                         };
1355
1356                         tsens_s10_p2_backup: s10_p2_backup@e7 {
1357                                 reg = <0xe7 0x1>;
1358                                 bits = <0 6>;
1359                         };
1360
1361                         tsens_base1_backup: base1_backup@440 {
1362                                 reg = <0x440 0x1>;
1363                                 bits = <0 8>;
1364                         };
1365
1366                         tsens_s0_p1_backup: s0-p1_backup@441 {
1367                                 reg = <0x441 0x1>;
1368                                 bits = <0 6>;
1369                         };
1370
1371                         tsens_s1_p1_backup: s1-p1_backup@442 {
1372                                 reg = <0x441 0x2>;
1373                                 bits = <6 6>;
1374                         };
1375
1376                         tsens_s2_p1_backup: s2-p1_backup@442 {
1377                                 reg = <0x442 0x2>;
1378                                 bits = <4 6>;
1379                         };
1380
1381                         tsens_s3_p1_backup: s3-p1_backup@443 {
1382                                 reg = <0x443 0x1>;
1383                                 bits = <2 6>;
1384                         };
1385
1386                         tsens_s4_p1_backup: s4-p1_backup@444 {
1387                                 reg = <0x444 0x1>;
1388                                 bits = <0 6>;
1389                         };
1390
1391                         tsens_s5_p1_backup: s5-p1_backup@444 {
1392                                 reg = <0x444 0x2>;
1393                                 bits = <6 6>;
1394                         };
1395
1396                         tsens_s6_p1_backup: s6-p1_backup@445 {
1397                                 reg = <0x445 0x2>;
1398                                 bits = <4 6>;
1399                         };
1400
1401                         tsens_s7_p1_backup: s7-p1_backup@446 {
1402                                 reg = <0x446 0x1>;
1403                                 bits = <2 6>;
1404                         };
1405
1406                         tsens_use_backup: use_backup@447 {
1407                                 reg = <0x447 0x1>;
1408                                 bits = <5 3>;
1409                         };
1410
1411                         tsens_s8_p1_backup: s8-p1_backup@448 {
1412                                 reg = <0x448 0x1>;
1413                                 bits = <0 6>;
1414                         };
1415
1416                         tsens_s9_p1_backup: s9-p1_backup@448 {
1417                                 reg = <0x448 0x2>;
1418                                 bits = <6 6>;
1419                         };
1420
1421                         tsens_s10_p1_backup: s10_p1_backup@449 {
1422                                 reg = <0x449 0x2>;
1423                                 bits = <4 6>;
1424                         };
1425
1426                         tsens_base2_backup: base2_backup@44a {
1427                                 reg = <0x44a 0x2>;
1428                                 bits = <2 8>;
1429                         };
1430
1431                         tsens_s0_p2_backup: s0-p2_backup@44b {
1432                                 reg = <0x44b 0x3>;
1433                                 bits = <2 6>;
1434                         };
1435
1436                         tsens_s1_p2_backup: s1-p2_backup@44c {
1437                                 reg = <0x44c 0x1>;
1438                                 bits = <0 6>;
1439                         };
1440
1441                         tsens_s2_p2_backup: s2-p2_backup@44c {
1442                                 reg = <0x44c 0x2>;
1443                                 bits = <6 6>;
1444                         };
1445
1446                         tsens_s3_p2_backup: s3-p2_backup@44d {
1447                                 reg = <0x44d 0x2>;
1448                                 bits = <4 6>;
1449                         };
1450
1451                         tsens_s4_p2_backup: s4-p2_backup@44e {
1452                                 reg = <0x44e 0x1>;
1453                                 bits = <2 6>;
1454                         };
1455                 };
1456
1457                 spmi_bus: spmi@fc4cf000 {
1458                         compatible = "qcom,spmi-pmic-arb";
1459                         reg-names = "core", "intr", "cnfg";
1460                         reg = <0xfc4cf000 0x1000>,
1461                               <0xfc4cb000 0x1000>,
1462                               <0xfc4ca000 0x1000>;
1463                         interrupt-names = "periph_irq";
1464                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1465                         qcom,ee = <0>;
1466                         qcom,channel = <0>;
1467                         #address-cells = <2>;
1468                         #size-cells = <0>;
1469                         interrupt-controller;
1470                         #interrupt-cells = <4>;
1471                 };
1472
1473                 bam_dmux_dma: dma-controller@fc834000 {
1474                         compatible = "qcom,bam-v1.4.0";
1475                         reg = <0xfc834000 0x7000>;
1476                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1477                         #dma-cells = <1>;
1478                         qcom,ee = <0>;
1479
1480                         num-channels = <6>;
1481                         qcom,num-ees = <1>;
1482                         qcom,powered-remotely;
1483                 };
1484
1485                 remoteproc_mss: remoteproc@fc880000 {
1486                         compatible = "qcom,msm8974-mss-pil";
1487                         reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1488                         reg-names = "qdsp6", "rmb";
1489
1490                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1491                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1492                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1493                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1494                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1495                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1496
1497                         clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1498                                  <&gcc GCC_MSS_CFG_AHB_CLK>,
1499                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1500                                  <&xo_board>;
1501                         clock-names = "iface", "bus", "mem", "xo";
1502
1503                         resets = <&gcc GCC_MSS_RESTART>;
1504                         reset-names = "mss_restart";
1505
1506                         qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1507
1508                         qcom,smem-states = <&modem_smp2p_out 0>;
1509                         qcom,smem-state-names = "stop";
1510
1511                         status = "disabled";
1512
1513                         mba {
1514                                 memory-region = <&mba_region>;
1515                         };
1516
1517                         mpss {
1518                                 memory-region = <&mpss_region>;
1519                         };
1520
1521                         bam_dmux: bam-dmux {
1522                                 compatible = "qcom,bam-dmux";
1523
1524                                 interrupt-parent = <&modem_smsm>;
1525                                 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1526                                 interrupt-names = "pc", "pc-ack";
1527
1528                                 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1529                                 qcom,smem-state-names = "pc", "pc-ack";
1530
1531                                 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1532                                 dma-names = "tx", "rx";
1533                         };
1534
1535                         smd-edge {
1536                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1537
1538                                 qcom,ipc = <&apcs 8 12>;
1539                                 qcom,smd-edge = <0>;
1540
1541                                 label = "modem";
1542                         };
1543                 };
1544
1545                 tcsr_mutex: hwlock@fd484000 {
1546                         compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
1547                         reg = <0xfd484000 0x2000>;
1548                         #hwlock-cells = <1>;
1549                 };
1550
1551                 tcsr: syscon@fd4a0000 {
1552                         compatible = "qcom,tcsr-msm8974", "syscon";
1553                         reg = <0xfd4a0000 0x10000>;
1554                 };
1555
1556                 tlmm: pinctrl@fd510000 {
1557                         compatible = "qcom,msm8974-pinctrl";
1558                         reg = <0xfd510000 0x4000>;
1559                         gpio-controller;
1560                         gpio-ranges = <&tlmm 0 0 146>;
1561                         #gpio-cells = <2>;
1562                         interrupt-controller;
1563                         #interrupt-cells = <2>;
1564                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1565
1566                         sdc1_off: sdc1-off-state {
1567                                 clk-pins {
1568                                         pins = "sdc1_clk";
1569                                         bias-disable;
1570                                         drive-strength = <2>;
1571                                 };
1572
1573                                 cmd-pins {
1574                                         pins = "sdc1_cmd";
1575                                         bias-pull-up;
1576                                         drive-strength = <2>;
1577                                 };
1578
1579                                 data-pins {
1580                                         pins = "sdc1_data";
1581                                         bias-pull-up;
1582                                         drive-strength = <2>;
1583                                 };
1584                         };
1585
1586                         sdc2_off: sdc2-off-state {
1587                                 clk-pins {
1588                                         pins = "sdc2_clk";
1589                                         bias-disable;
1590                                         drive-strength = <2>;
1591                                 };
1592
1593                                 cmd-pins {
1594                                         pins = "sdc2_cmd";
1595                                         bias-pull-up;
1596                                         drive-strength = <2>;
1597                                 };
1598
1599                                 data-pins {
1600                                         pins = "sdc2_data";
1601                                         bias-pull-up;
1602                                         drive-strength = <2>;
1603                                 };
1604
1605                                 cd-pins {
1606                                         pins = "gpio54";
1607                                         function = "gpio";
1608                                         bias-disable;
1609                                         drive-strength = <2>;
1610                                 };
1611                         };
1612
1613                         blsp1_uart2_default: blsp1-uart2-default-state {
1614                                 rx-pins {
1615                                         pins = "gpio5";
1616                                         function = "blsp_uart2";
1617                                         drive-strength = <2>;
1618                                         bias-pull-up;
1619                                 };
1620
1621                                 tx-pins {
1622                                         pins = "gpio4";
1623                                         function = "blsp_uart2";
1624                                         drive-strength = <4>;
1625                                         bias-disable;
1626                                 };
1627                         };
1628
1629                         blsp2_uart1_default: blsp2-uart1-default-state {
1630                                 tx-rts-pins {
1631                                         pins = "gpio41", "gpio44";
1632                                         function = "blsp_uart7";
1633                                         drive-strength = <2>;
1634                                         bias-disable;
1635                                 };
1636
1637                                 rx-cts-pins {
1638                                         pins = "gpio42", "gpio43";
1639                                         function = "blsp_uart7";
1640                                         drive-strength = <2>;
1641                                         bias-pull-up;
1642                                 };
1643                         };
1644
1645                         blsp2_uart1_sleep: blsp2-uart1-sleep-state {
1646                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1647                                 function = "gpio";
1648                                 drive-strength = <2>;
1649                                 bias-pull-down;
1650                         };
1651
1652                         blsp2_uart4_default: blsp2-uart4-default-state {
1653                                 tx-rts-pins {
1654                                         pins = "gpio53", "gpio56";
1655                                         function = "blsp_uart10";
1656                                         drive-strength = <2>;
1657                                         bias-disable;
1658                                 };
1659
1660                                 rx-cts-pins {
1661                                         pins = "gpio54", "gpio55";
1662                                         function = "blsp_uart10";
1663                                         drive-strength = <2>;
1664                                         bias-pull-up;
1665                                 };
1666                         };
1667
1668                         blsp1_i2c1_default: blsp1-i2c1-default-state {
1669                                 pins = "gpio2", "gpio3";
1670                                 function = "blsp_i2c1";
1671                                 drive-strength = <2>;
1672                                 bias-disable;
1673                         };
1674
1675                         blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
1676                                 pins = "gpio2", "gpio3";
1677                                 function = "blsp_i2c1";
1678                                 drive-strength = <2>;
1679                                 bias-pull-up;
1680                         };
1681
1682                         blsp1_i2c2_default: blsp1-i2c2-default-state {
1683                                 pins = "gpio6", "gpio7";
1684                                 function = "blsp_i2c2";
1685                                 drive-strength = <2>;
1686                                 bias-disable;
1687                         };
1688
1689                         blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
1690                                 pins = "gpio6", "gpio7";
1691                                 function = "blsp_i2c2";
1692                                 drive-strength = <2>;
1693                                 bias-pull-up;
1694                         };
1695
1696                         blsp1_i2c3_default: blsp1-i2c3-default-state {
1697                                 pins = "gpio10", "gpio11";
1698                                 function = "blsp_i2c3";
1699                                 drive-strength = <2>;
1700                                 bias-disable;
1701                         };
1702
1703                         blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1704                                 pins = "gpio10", "gpio11";
1705                                 function = "blsp_i2c3";
1706                                 drive-strength = <2>;
1707                                 bias-pull-up;
1708                         };
1709
1710                         /* BLSP1_I2C4 info is missing */
1711
1712                         /* BLSP1_I2C5 info is missing */
1713
1714                         blsp1_i2c6_default: blsp1-i2c6-default-state {
1715                                 pins = "gpio29", "gpio30";
1716                                 function = "blsp_i2c6";
1717                                 drive-strength = <2>;
1718                                 bias-disable;
1719                         };
1720
1721                         blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1722                                 pins = "gpio29", "gpio30";
1723                                 function = "blsp_i2c6";
1724                                 drive-strength = <2>;
1725                                 bias-pull-up;
1726                         };
1727                         /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1728
1729                         /* BLSP2_I2C1 info is missing */
1730
1731                         blsp2_i2c2_default: blsp2-i2c2-default-state {
1732                                 pins = "gpio47", "gpio48";
1733                                 function = "blsp_i2c8";
1734                                 drive-strength = <2>;
1735                                 bias-disable;
1736                         };
1737
1738                         blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1739                                 pins = "gpio47", "gpio48";
1740                                 function = "blsp_i2c8";
1741                                 drive-strength = <2>;
1742                                 bias-pull-up;
1743                         };
1744
1745                         /* BLSP2_I2C3 info is missing */
1746
1747                         /* BLSP2_I2C4 info is missing */
1748
1749                         blsp2_i2c5_default: blsp2-i2c5-default-state {
1750                                 pins = "gpio83", "gpio84";
1751                                 function = "blsp_i2c11";
1752                                 drive-strength = <2>;
1753                                 bias-disable;
1754                         };
1755
1756                         blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1757                                 pins = "gpio83", "gpio84";
1758                                 function = "blsp_i2c11";
1759                                 drive-strength = <2>;
1760                                 bias-pull-up;
1761                         };
1762
1763                         blsp2_i2c6_default: blsp2-i2c6-default-state {
1764                                 pins = "gpio87", "gpio88";
1765                                 function = "blsp_i2c12";
1766                                 drive-strength = <2>;
1767                                 bias-disable;
1768                         };
1769
1770                         blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1771                                 pins = "gpio87", "gpio88";
1772                                 function = "blsp_i2c12";
1773                                 drive-strength = <2>;
1774                                 bias-pull-up;
1775                         };
1776
1777                         cci_default: cci-default-state {
1778                                 cci_i2c0_default: cci-i2c0-default-pins {
1779                                         pins = "gpio19", "gpio20";
1780                                         function = "cci_i2c0";
1781                                         drive-strength = <2>;
1782                                         bias-disable;
1783                                 };
1784
1785                                 cci_i2c1_default: cci-i2c1-default-pins {
1786                                         pins = "gpio21", "gpio22";
1787                                         function = "cci_i2c1";
1788                                         drive-strength = <2>;
1789                                         bias-disable;
1790                                 };
1791                         };
1792
1793                         cci_sleep: cci-sleep-state {
1794                                 cci_i2c0_sleep: cci-i2c0-sleep-pins {
1795                                         pins = "gpio19", "gpio20";
1796                                         function = "gpio";
1797                                         drive-strength = <2>;
1798                                         bias-disable;
1799                                 };
1800
1801                                 cci_i2c1_sleep: cci-i2c1-sleep-pins {
1802                                         pins = "gpio21", "gpio22";
1803                                         function = "gpio";
1804                                         drive-strength = <2>;
1805                                         bias-disable;
1806                                 };
1807                         };
1808
1809                         spi8_default: spi8_default-state {
1810                                 mosi-pins {
1811                                         pins = "gpio45";
1812                                         function = "blsp_spi8";
1813                                 };
1814                                 miso-pins {
1815                                         pins = "gpio46";
1816                                         function = "blsp_spi8";
1817                                 };
1818                                 cs-pins {
1819                                         pins = "gpio47";
1820                                         function = "blsp_spi8";
1821                                 };
1822                                 clk-pins {
1823                                         pins = "gpio48";
1824                                         function = "blsp_spi8";
1825                                 };
1826                         };
1827                 };
1828
1829                 mmcc: clock-controller@fd8c0000 {
1830                         compatible = "qcom,mmcc-msm8974";
1831                         #clock-cells = <1>;
1832                         #reset-cells = <1>;
1833                         #power-domain-cells = <1>;
1834                         reg = <0xfd8c0000 0x6000>;
1835                         clocks = <&xo_board>,
1836                                  <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
1837                                  <&gcc GPLL0_VOTE>,
1838                                  <&gcc GPLL1_VOTE>,
1839                                  <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1840                                  <&mdss_dsi0_phy 1>,
1841                                  <&mdss_dsi0_phy 0>,
1842                                  <&mdss_dsi1_phy 1>,
1843                                  <&mdss_dsi1_phy 0>,
1844                                  <0>,
1845                                  <0>,
1846                                  <0>;
1847                         clock-names = "xo",
1848                                       "mmss_gpll0_vote",
1849                                       "gpll0_vote",
1850                                       "gpll1_vote",
1851                                       "gfx3d_clk_src",
1852                                       "dsi0pll",
1853                                       "dsi0pllbyte",
1854                                       "dsi1pll",
1855                                       "dsi1pllbyte",
1856                                       "hdmipll",
1857                                       "edp_link_clk",
1858                                       "edp_vco_div";
1859                 };
1860
1861                 mdss: display-subsystem@fd900000 {
1862                         compatible = "qcom,mdss";
1863                         reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1864                         reg-names = "mdss_phys", "vbif_phys";
1865
1866                         power-domains = <&mmcc MDSS_GDSC>;
1867
1868                         clocks = <&mmcc MDSS_AHB_CLK>,
1869                                  <&mmcc MDSS_AXI_CLK>,
1870                                  <&mmcc MDSS_VSYNC_CLK>;
1871                         clock-names = "iface", "bus", "vsync";
1872
1873                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1874
1875                         interrupt-controller;
1876                         #interrupt-cells = <1>;
1877
1878                         status = "disabled";
1879
1880                         #address-cells = <1>;
1881                         #size-cells = <1>;
1882                         ranges;
1883
1884                         mdp: display-controller@fd900000 {
1885                                 compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
1886                                 reg = <0xfd900100 0x22000>;
1887                                 reg-names = "mdp_phys";
1888
1889                                 interrupt-parent = <&mdss>;
1890                                 interrupts = <0>;
1891
1892                                 clocks = <&mmcc MDSS_AHB_CLK>,
1893                                          <&mmcc MDSS_AXI_CLK>,
1894                                          <&mmcc MDSS_MDP_CLK>,
1895                                          <&mmcc MDSS_VSYNC_CLK>;
1896                                 clock-names = "iface", "bus", "core", "vsync";
1897
1898                                 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1899                                 interconnect-names = "mdp0-mem";
1900
1901                                 ports {
1902                                         #address-cells = <1>;
1903                                         #size-cells = <0>;
1904
1905                                         port@0 {
1906                                                 reg = <0>;
1907                                                 mdp5_intf1_out: endpoint {
1908                                                         remote-endpoint = <&mdss_dsi0_in>;
1909                                                 };
1910                                         };
1911
1912                                         port@1 {
1913                                                 reg = <1>;
1914                                                 mdp5_intf2_out: endpoint {
1915                                                         remote-endpoint = <&mdss_dsi1_in>;
1916                                                 };
1917                                         };
1918                                 };
1919                         };
1920
1921                         mdss_dsi0: dsi@fd922800 {
1922                                 compatible = "qcom,msm8974-dsi-ctrl",
1923                                              "qcom,mdss-dsi-ctrl";
1924                                 reg = <0xfd922800 0x1f8>;
1925                                 reg-names = "dsi_ctrl";
1926
1927                                 interrupt-parent = <&mdss>;
1928                                 interrupts = <4>;
1929
1930                                 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1931                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1932
1933                                 clocks = <&mmcc MDSS_MDP_CLK>,
1934                                          <&mmcc MDSS_AHB_CLK>,
1935                                          <&mmcc MDSS_AXI_CLK>,
1936                                          <&mmcc MDSS_BYTE0_CLK>,
1937                                          <&mmcc MDSS_PCLK0_CLK>,
1938                                          <&mmcc MDSS_ESC0_CLK>,
1939                                          <&mmcc MMSS_MISC_AHB_CLK>;
1940                                 clock-names = "mdp_core",
1941                                               "iface",
1942                                               "bus",
1943                                               "byte",
1944                                               "pixel",
1945                                               "core",
1946                                               "core_mmss";
1947
1948                                 phys = <&mdss_dsi0_phy>;
1949
1950                                 status = "disabled";
1951
1952                                 #address-cells = <1>;
1953                                 #size-cells = <0>;
1954
1955                                 ports {
1956                                         #address-cells = <1>;
1957                                         #size-cells = <0>;
1958
1959                                         port@0 {
1960                                                 reg = <0>;
1961                                                 mdss_dsi0_in: endpoint {
1962                                                         remote-endpoint = <&mdp5_intf1_out>;
1963                                                 };
1964                                         };
1965
1966                                         port@1 {
1967                                                 reg = <1>;
1968                                                 mdss_dsi0_out: endpoint {
1969                                                 };
1970                                         };
1971                                 };
1972                         };
1973
1974                         mdss_dsi0_phy: phy@fd922a00 {
1975                                 compatible = "qcom,dsi-phy-28nm-hpm";
1976                                 reg = <0xfd922a00 0xd4>,
1977                                       <0xfd922b00 0x280>,
1978                                       <0xfd922d80 0x30>;
1979                                 reg-names = "dsi_pll",
1980                                             "dsi_phy",
1981                                             "dsi_phy_regulator";
1982
1983                                 #clock-cells = <1>;
1984                                 #phy-cells = <0>;
1985
1986                                 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1987                                 clock-names = "iface", "ref";
1988
1989                                 status = "disabled";
1990                         };
1991
1992                         mdss_dsi1: dsi@fd922e00 {
1993                                 compatible = "qcom,msm8974-dsi-ctrl",
1994                                              "qcom,mdss-dsi-ctrl";
1995                                 reg = <0xfd922e00 0x1f8>;
1996                                 reg-names = "dsi_ctrl";
1997
1998                                 interrupt-parent = <&mdss>;
1999                                 interrupts = <4>;
2000
2001                                 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2002                                 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2003
2004                                 clocks = <&mmcc MDSS_MDP_CLK>,
2005                                          <&mmcc MDSS_AHB_CLK>,
2006                                          <&mmcc MDSS_AXI_CLK>,
2007                                          <&mmcc MDSS_BYTE1_CLK>,
2008                                          <&mmcc MDSS_PCLK1_CLK>,
2009                                          <&mmcc MDSS_ESC1_CLK>,
2010                                          <&mmcc MMSS_MISC_AHB_CLK>;
2011                                 clock-names = "mdp_core",
2012                                               "iface",
2013                                               "bus",
2014                                               "byte",
2015                                               "pixel",
2016                                               "core",
2017                                               "core_mmss";
2018
2019                                 phys = <&mdss_dsi1_phy>;
2020
2021                                 status = "disabled";
2022
2023                                 #address-cells = <1>;
2024                                 #size-cells = <0>;
2025
2026                                 ports {
2027                                         #address-cells = <1>;
2028                                         #size-cells = <0>;
2029
2030                                         port@0 {
2031                                                 reg = <0>;
2032                                                 mdss_dsi1_in: endpoint {
2033                                                         remote-endpoint = <&mdp5_intf2_out>;
2034                                                 };
2035                                         };
2036
2037                                         port@1 {
2038                                                 reg = <1>;
2039                                                 mdss_dsi1_out: endpoint {
2040                                                 };
2041                                         };
2042                                 };
2043                         };
2044
2045                         mdss_dsi1_phy: phy@fd923000 {
2046                                 compatible = "qcom,dsi-phy-28nm-hpm";
2047                                 reg = <0xfd923000 0xd4>,
2048                                       <0xfd923100 0x280>,
2049                                       <0xfd923380 0x30>;
2050                                 reg-names = "dsi_pll",
2051                                             "dsi_phy",
2052                                             "dsi_phy_regulator";
2053
2054                                 #clock-cells = <1>;
2055                                 #phy-cells = <0>;
2056
2057                                 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2058                                 clock-names = "iface", "ref";
2059
2060                                 status = "disabled";
2061                         };
2062                 };
2063
2064                 cci: cci@fda0c000 {
2065                         compatible = "qcom,msm8974-cci";
2066                         #address-cells = <1>;
2067                         #size-cells = <0>;
2068                         reg = <0xfda0c000 0x1000>;
2069                         interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
2070                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2071                                  <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
2072                                  <&mmcc CAMSS_CCI_CCI_CLK>;
2073                         clock-names = "camss_top_ahb",
2074                                       "cci_ahb",
2075                                       "cci";
2076
2077                         pinctrl-names = "default", "sleep";
2078                         pinctrl-0 = <&cci_default>;
2079                         pinctrl-1 = <&cci_sleep>;
2080
2081                         status = "disabled";
2082
2083                         cci_i2c0: i2c-bus@0 {
2084                                 reg = <0>;
2085                                 clock-frequency = <100000>;
2086                                 #address-cells = <1>;
2087                                 #size-cells = <0>;
2088                         };
2089
2090                         cci_i2c1: i2c-bus@1 {
2091                                 reg = <1>;
2092                                 clock-frequency = <100000>;
2093                                 #address-cells = <1>;
2094                                 #size-cells = <0>;
2095                         };
2096                 };
2097
2098                 gpu: adreno@fdb00000 {
2099                         compatible = "qcom,adreno-330.1", "qcom,adreno";
2100                         reg = <0xfdb00000 0x10000>;
2101                         reg-names = "kgsl_3d0_reg_memory";
2102
2103                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2104                         interrupt-names = "kgsl_3d0_irq";
2105
2106                         clocks = <&mmcc OXILI_GFX3D_CLK>,
2107                                  <&mmcc OXILICX_AHB_CLK>,
2108                                  <&mmcc OXILICX_AXI_CLK>;
2109                         clock-names = "core", "iface", "mem_iface";
2110
2111                         sram = <&gmu_sram>;
2112                         power-domains = <&mmcc OXILICX_GDSC>;
2113                         operating-points-v2 = <&gpu_opp_table>;
2114
2115                         interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
2116                                         <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
2117                         interconnect-names = "gfx-mem", "ocmem";
2118
2119                         // iommus = <&gpu_iommu 0>;
2120
2121                         status = "disabled";
2122
2123                         gpu_opp_table: opp-table {
2124                                 compatible = "operating-points-v2";
2125
2126                                 opp-320000000 {
2127                                         opp-hz = /bits/ 64 <320000000>;
2128                                 };
2129
2130                                 opp-200000000 {
2131                                         opp-hz = /bits/ 64 <200000000>;
2132                                 };
2133
2134                                 opp-27000000 {
2135                                         opp-hz = /bits/ 64 <27000000>;
2136                                 };
2137                         };
2138                 };
2139
2140                 sram@fdd00000 {
2141                         compatible = "qcom,msm8974-ocmem";
2142                         reg = <0xfdd00000 0x2000>,
2143                               <0xfec00000 0x180000>;
2144                         reg-names = "ctrl", "mem";
2145                         ranges = <0 0xfec00000 0x180000>;
2146                         clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
2147                                  <&mmcc OCMEMCX_OCMEMNOC_CLK>;
2148                         clock-names = "core", "iface";
2149
2150                         #address-cells = <1>;
2151                         #size-cells = <1>;
2152
2153                         gmu_sram: gmu-sram@0 {
2154                                 reg = <0x0 0x100000>;
2155                         };
2156                 };
2157
2158                 remoteproc_adsp: remoteproc@fe200000 {
2159                         compatible = "qcom,msm8974-adsp-pil";
2160                         reg = <0xfe200000 0x100>;
2161
2162                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2163                                                <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2164                                                <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2165                                                <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2166                                                <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2167                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2168
2169                         clocks = <&xo_board>;
2170                         clock-names = "xo";
2171
2172                         memory-region = <&adsp_region>;
2173
2174                         qcom,smem-states = <&adsp_smp2p_out 0>;
2175                         qcom,smem-state-names = "stop";
2176
2177                         status = "disabled";
2178
2179                         smd-edge {
2180                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2181
2182                                 qcom,ipc = <&apcs 8 8>;
2183                                 qcom,smd-edge = <1>;
2184                                 label = "lpass";
2185                         };
2186                 };
2187
2188                 imem: sram@fe805000 {
2189                         compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
2190                         reg = <0xfe805000 0x1000>;
2191
2192                         reboot-mode {
2193                                 compatible = "syscon-reboot-mode";
2194                                 offset = <0x65c>;
2195                         };
2196                 };
2197         };
2198
2199         thermal-zones {
2200                 cpu0-thermal {
2201                         polling-delay-passive = <250>;
2202                         polling-delay = <1000>;
2203
2204                         thermal-sensors = <&tsens 5>;
2205
2206                         trips {
2207                                 cpu_alert0: trip0 {
2208                                         temperature = <75000>;
2209                                         hysteresis = <2000>;
2210                                         type = "passive";
2211                                 };
2212                                 cpu_crit0: trip1 {
2213                                         temperature = <110000>;
2214                                         hysteresis = <2000>;
2215                                         type = "critical";
2216                                 };
2217                         };
2218                 };
2219
2220                 cpu1-thermal {
2221                         polling-delay-passive = <250>;
2222                         polling-delay = <1000>;
2223
2224                         thermal-sensors = <&tsens 6>;
2225
2226                         trips {
2227                                 cpu_alert1: trip0 {
2228                                         temperature = <75000>;
2229                                         hysteresis = <2000>;
2230                                         type = "passive";
2231                                 };
2232                                 cpu_crit1: trip1 {
2233                                         temperature = <110000>;
2234                                         hysteresis = <2000>;
2235                                         type = "critical";
2236                                 };
2237                         };
2238                 };
2239
2240                 cpu2-thermal {
2241                         polling-delay-passive = <250>;
2242                         polling-delay = <1000>;
2243
2244                         thermal-sensors = <&tsens 7>;
2245
2246                         trips {
2247                                 cpu_alert2: trip0 {
2248                                         temperature = <75000>;
2249                                         hysteresis = <2000>;
2250                                         type = "passive";
2251                                 };
2252                                 cpu_crit2: trip1 {
2253                                         temperature = <110000>;
2254                                         hysteresis = <2000>;
2255                                         type = "critical";
2256                                 };
2257                         };
2258                 };
2259
2260                 cpu3-thermal {
2261                         polling-delay-passive = <250>;
2262                         polling-delay = <1000>;
2263
2264                         thermal-sensors = <&tsens 8>;
2265
2266                         trips {
2267                                 cpu_alert3: trip0 {
2268                                         temperature = <75000>;
2269                                         hysteresis = <2000>;
2270                                         type = "passive";
2271                                 };
2272                                 cpu_crit3: trip1 {
2273                                         temperature = <110000>;
2274                                         hysteresis = <2000>;
2275                                         type = "critical";
2276                                 };
2277                         };
2278                 };
2279
2280                 q6-dsp-thermal {
2281                         polling-delay-passive = <250>;
2282                         polling-delay = <1000>;
2283
2284                         thermal-sensors = <&tsens 1>;
2285
2286                         trips {
2287                                 q6_dsp_alert0: trip-point0 {
2288                                         temperature = <90000>;
2289                                         hysteresis = <2000>;
2290                                         type = "hot";
2291                                 };
2292                         };
2293                 };
2294
2295                 modemtx-thermal {
2296                         polling-delay-passive = <250>;
2297                         polling-delay = <1000>;
2298
2299                         thermal-sensors = <&tsens 2>;
2300
2301                         trips {
2302                                 modemtx_alert0: trip-point0 {
2303                                         temperature = <90000>;
2304                                         hysteresis = <2000>;
2305                                         type = "hot";
2306                                 };
2307                         };
2308                 };
2309
2310                 video-thermal {
2311                         polling-delay-passive = <250>;
2312                         polling-delay = <1000>;
2313
2314                         thermal-sensors = <&tsens 3>;
2315
2316                         trips {
2317                                 video_alert0: trip-point0 {
2318                                         temperature = <95000>;
2319                                         hysteresis = <2000>;
2320                                         type = "hot";
2321                                 };
2322                         };
2323                 };
2324
2325                 wlan-thermal {
2326                         polling-delay-passive = <250>;
2327                         polling-delay = <1000>;
2328
2329                         thermal-sensors = <&tsens 4>;
2330
2331                         trips {
2332                                 wlan_alert0: trip-point0 {
2333                                         temperature = <105000>;
2334                                         hysteresis = <2000>;
2335                                         type = "hot";
2336                                 };
2337                         };
2338                 };
2339
2340                 gpu-top-thermal {
2341                         polling-delay-passive = <250>;
2342                         polling-delay = <1000>;
2343
2344                         thermal-sensors = <&tsens 9>;
2345
2346                         trips {
2347                                 gpu1_alert0: trip-point0 {
2348                                         temperature = <90000>;
2349                                         hysteresis = <2000>;
2350                                         type = "hot";
2351                                 };
2352                         };
2353                 };
2354
2355                 gpu-bottom-thermal {
2356                         polling-delay-passive = <250>;
2357                         polling-delay = <1000>;
2358
2359                         thermal-sensors = <&tsens 10>;
2360
2361                         trips {
2362                                 gpu2_alert0: trip-point0 {
2363                                         temperature = <90000>;
2364                                         hysteresis = <2000>;
2365                                         type = "hot";
2366                                 };
2367                         };
2368                 };
2369         };
2370
2371         timer {
2372                 compatible = "arm,armv7-timer";
2373                 interrupts = <GIC_PPI 2 0xf08>,
2374                              <GIC_PPI 3 0xf08>,
2375                              <GIC_PPI 4 0xf08>,
2376                              <GIC_PPI 1 0xf08>;
2377                 clock-frequency = <19200000>;
2378         };
2379
2380         vreg_boost: vreg-boost {
2381                 compatible = "regulator-fixed";
2382
2383                 regulator-name = "vreg-boost";
2384                 regulator-min-microvolt = <3150000>;
2385                 regulator-max-microvolt = <3150000>;
2386
2387                 regulator-always-on;
2388                 regulator-boot-on;
2389
2390                 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
2391                 enable-active-high;
2392
2393                 pinctrl-names = "default";
2394                 pinctrl-0 = <&boost_bypass_n_pin>;
2395         };
2396
2397         vreg_vph_pwr: vreg-vph-pwr {
2398                 compatible = "regulator-fixed";
2399                 regulator-name = "vph-pwr";
2400
2401                 regulator-min-microvolt = <3600000>;
2402                 regulator-max-microvolt = <3600000>;
2403
2404                 regulator-always-on;
2405         };
2406 };