arch/arm/boot/dts/qcom/qcom-apq8084.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11         model = "Qualcomm APQ 8084";
  12         compatible = "qcom,apq8084";
  13         interrupt-parent = <&intc>;
  14
  15         reserved-memory {
  16                 #address-cells = <1>;
  17                 #size-cells = <1>;
  18                 ranges;
  19
  20                 smem_mem: smem_region@fa00000 {
  21                         reg = <0xfa00000 0x200000>;
  22                         no-map;
  23                 };
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "qcom,krait";
  33                         reg = <0>;
  34                         enable-method = "qcom,kpss-acc-v2";
  35                         next-level-cache = <&L2>;
  36                         qcom,acc = <&acc0>;
  37                         qcom,saw = <&saw0>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "qcom,krait";
  44                         reg = <1>;
  45                         enable-method = "qcom,kpss-acc-v2";
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc1>;
  48                         qcom,saw = <&saw1>;
  49                         cpu-idle-states = <&CPU_SPC>;
  50                 };
  51
  52                 cpu@2 {
  53                         device_type = "cpu";
  54                         compatible = "qcom,krait";
  55                         reg = <2>;
  56                         enable-method = "qcom,kpss-acc-v2";
  57                         next-level-cache = <&L2>;
  58                         qcom,acc = <&acc2>;
  59                         qcom,saw = <&saw2>;
  60                         cpu-idle-states = <&CPU_SPC>;
  61                 };
  62
  63                 cpu@3 {
  64                         device_type = "cpu";
  65                         compatible = "qcom,krait";
  66                         reg = <3>;
  67                         enable-method = "qcom,kpss-acc-v2";
  68                         next-level-cache = <&L2>;
  69                         qcom,acc = <&acc3>;
  70                         qcom,saw = <&saw3>;
  71                         cpu-idle-states = <&CPU_SPC>;
  72                 };
  73
  74                 L2: l2-cache {
  75                         compatible = "cache";
  76                         cache-level = <2>;
  77                         cache-unified;
  78                         qcom,saw = <&saw_l2>;
  79                 };
  80
  81                 idle-states {
  82                         CPU_SPC: spc {
  83                                 compatible = "qcom,idle-state-spc",
  84                                                 "arm,idle-state";
  85                                 entry-latency-us = <150>;
  86                                 exit-latency-us = <200>;
  87                                 min-residency-us = <2000>;
  88                         };
  89                 };
  90         };
  91
  92         memory {
  93                 device_type = "memory";
  94                 reg = <0x0 0x0>;
  95         };
  96
  97         firmware {
  98                 scm {
  99                         compatible = "qcom,scm-apq8084", "qcom,scm";
 100                         clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
 101                         clock-names = "core", "bus", "iface";
 102                 };
 103         };
 104
 105         thermal-zones {
 106                 cpu0-thermal {
 107                         polling-delay-passive = <250>;
 108                         polling-delay = <1000>;
 109
 110                         thermal-sensors = <&tsens 5>;
 111
 112                         trips {
 113                                 cpu_alert0: trip0 {
 114                                         temperature = <75000>;
 115                                         hysteresis = <2000>;
 116                                         type = "passive";
 117                                 };
 118                                 cpu_crit0: trip1 {
 119                                         temperature = <110000>;
 120                                         hysteresis = <2000>;
 121                                         type = "critical";
 122                                 };
 123                         };
 124                 };
 125
 126                 cpu1-thermal {
 127                         polling-delay-passive = <250>;
 128                         polling-delay = <1000>;
 129
 130                         thermal-sensors = <&tsens 6>;
 131
 132                         trips {
 133                                 cpu_alert1: trip0 {
 134                                         temperature = <75000>;
 135                                         hysteresis = <2000>;
 136                                         type = "passive";
 137                                 };
 138                                 cpu_crit1: trip1 {
 139                                         temperature = <110000>;
 140                                         hysteresis = <2000>;
 141                                         type = "critical";
 142                                 };
 143                         };
 144                 };
 145
 146                 cpu2-thermal {
 147                         polling-delay-passive = <250>;
 148                         polling-delay = <1000>;
 149
 150                         thermal-sensors = <&tsens 7>;
 151
 152                         trips {
 153                                 cpu_alert2: trip0 {
 154                                         temperature = <75000>;
 155                                         hysteresis = <2000>;
 156                                         type = "passive";
 157                                 };
 158                                 cpu_crit2: trip1 {
 159                                         temperature = <110000>;
 160                                         hysteresis = <2000>;
 161                                         type = "critical";
 162                                 };
 163                         };
 164                 };
 165
 166                 cpu3-thermal {
 167                         polling-delay-passive = <250>;
 168                         polling-delay = <1000>;
 169
 170                         thermal-sensors = <&tsens 8>;
 171
 172                         trips {
 173                                 cpu_alert3: trip0 {
 174                                         temperature = <75000>;
 175                                         hysteresis = <2000>;
 176                                         type = "passive";
 177                                 };
 178                                 cpu_crit3: trip1 {
 179                                         temperature = <110000>;
 180                                         hysteresis = <2000>;
 181                                         type = "critical";
 182                                 };
 183                         };
 184                 };
 185         };
 186
 187         cpu-pmu {
 188                 compatible = "qcom,krait-pmu";
 189                 interrupts = <GIC_PPI 7 0xf04>;
 190         };
 191
 192         clocks {
 193                 xo_board: xo_board {
 194                         compatible = "fixed-clock";
 195                         #clock-cells = <0>;
 196                         clock-frequency = <19200000>;
 197                 };
 198
 199                 sleep_clk: sleep_clk {
 200                         compatible = "fixed-clock";
 201                         #clock-cells = <0>;
 202                         clock-frequency = <32768>;
 203                 };
 204         };
 205
 206         timer {
 207                 compatible = "arm,armv7-timer";
 208                 interrupts = <GIC_PPI 2 0xf08>,
 209                              <GIC_PPI 3 0xf08>,
 210                              <GIC_PPI 4 0xf08>,
 211                              <GIC_PPI 1 0xf08>;
 212                 clock-frequency = <19200000>;
 213         };
 214
 215         smem {
 216                 compatible = "qcom,smem";
 217
 218                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 219                 memory-region = <&smem_mem>;
 220
 221                 hwlocks = <&tcsr_mutex 3>;
 222         };
 223
 224         soc: soc {
 225                 #address-cells = <1>;
 226                 #size-cells = <1>;
 227                 ranges;
 228                 compatible = "simple-bus";
 229
 230                 intc: interrupt-controller@f9000000 {
 231                         compatible = "qcom,msm-qgic2";
 232                         interrupt-controller;
 233                         #interrupt-cells = <3>;
 234                         reg = <0xf9000000 0x1000>,
 235                               <0xf9002000 0x1000>;
 236                 };
 237
 238                 apcs: syscon@f9011000 {
 239                         compatible = "syscon";
 240                         reg = <0xf9011000 0x1000>;
 241                 };
 242
 243                 sram@fc190000 {
 244                         compatible = "qcom,apq8084-rpm-stats";
 245                         reg = <0xfc190000 0x10000>;
 246                 };
 247
 248                 qfprom: qfprom@fc4bc000 {
 249                         compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
 250                         reg = <0xfc4bc000 0x1000>;
 251                         #address-cells = <1>;
 252                         #size-cells = <1>;
 253
 254                         tsens_base1: base1@d0 {
 255                                 reg = <0xd0 0x1>;
 256                                 bits = <0 8>;
 257                         };
 258
 259                         tsens_s0_p1: s0-p1@d1 {
 260                                 reg = <0xd1 0x1>;
 261                                 bits = <0 6>;
 262                         };
 263
 264                         tsens_s1_p1: s1-p1@d2 {
 265                                 reg = <0xd1 0x2>;
 266                                 bits = <6 6>;
 267                         };
 268
 269                         tsens_s2_p1: s2-p1@d2 {
 270                                 reg = <0xd2 0x2>;
 271                                 bits = <4 6>;
 272                         };
 273
 274                         tsens_s3_p1: s3-p1@d3 {
 275                                 reg = <0xd3 0x1>;
 276                                 bits = <2 6>;
 277                         };
 278
 279                         tsens_s4_p1: s4-p1@d4 {
 280                                 reg = <0xd4 0x1>;
 281                                 bits = <0 6>;
 282                         };
 283
 284                         tsens_s5_p1: s5-p1@d4 {
 285                                 reg = <0xd4 0x2>;
 286                                 bits = <6 6>;
 287                         };
 288
 289                         tsens_s6_p1: s6-p1@d5 {
 290                                 reg = <0xd5 0x2>;
 291                                 bits = <4 6>;
 292                         };
 293
 294                         tsens_s7_p1: s7-p1@d6 {
 295                                 reg = <0xd6 0x1>;
 296                                 bits = <2 6>;
 297                         };
 298
 299                         tsens_s8_p1: s8-p1@d7 {
 300                                 reg = <0xd7 0x1>;
 301                                 bits = <0 6>;
 302                         };
 303
 304                         tsens_mode: mode@d7 {
 305                                 reg = <0xd7 0x1>;
 306                                 bits = <6 2>;
 307                         };
 308
 309                         tsens_s9_p1: s9-p1@d8 {
 310                                 reg = <0xd8 0x1>;
 311                                 bits = <0 6>;
 312                         };
 313
 314                         tsens_s10_p1: s10_p1@d8 {
 315                                 reg = <0xd8 0x2>;
 316                                 bits = <6 6>;
 317                         };
 318
 319                         tsens_base2: base2@d9 {
 320                                 reg = <0xd9 0x2>;
 321                                 bits = <4 8>;
 322                         };
 323
 324                         tsens_s0_p2: s0-p2@da {
 325                                 reg = <0xda 0x2>;
 326                                 bits = <4 6>;
 327                         };
 328
 329                         tsens_s1_p2: s1-p2@db {
 330                                 reg = <0xdb 0x1>;
 331                                 bits = <2 6>;
 332                         };
 333
 334                         tsens_s2_p2: s2-p2@dc {
 335                                 reg = <0xdc 0x1>;
 336                                 bits = <0 6>;
 337                         };
 338
 339                         tsens_s3_p2: s3-p2@dc {
 340                                 reg = <0xdc 0x2>;
 341                                 bits = <6 6>;
 342                         };
 343
 344                         tsens_s4_p2: s4-p2@dd {
 345                                 reg = <0xdd 0x2>;
 346                                 bits = <4 6>;
 347                         };
 348
 349                         tsens_s5_p2: s5-p2@de {
 350                                 reg = <0xde 0x2>;
 351                                 bits = <2 6>;
 352                         };
 353
 354                         tsens_s6_p2: s6-p2@df {
 355                                 reg = <0xdf 0x1>;
 356                                 bits = <0 6>;
 357                         };
 358
 359                         tsens_s7_p2: s7-p2@e0 {
 360                                 reg = <0xe0 0x1>;
 361                                 bits = <0 6>;
 362                         };
 363
 364                         tsens_s8_p2: s8-p2@e0 {
 365                                 reg = <0xe0 0x2>;
 366                                 bits = <6 6>;
 367                         };
 368
 369                         tsens_s9_p2: s9-p2@e1 {
 370                                 reg = <0xe1 0x2>;
 371                                 bits = <4 6>;
 372                         };
 373
 374                         tsens_s10_p2: s10_p2@e2 {
 375                                 reg = <0xe2 0x2>;
 376                                 bits = <2 6>;
 377                         };
 378
 379                         tsens_s5_p2_backup: s5-p2_backup@e3 {
 380                                 reg = <0xe3 0x2>;
 381                                 bits = <0 6>;
 382                         };
 383
 384                         tsens_mode_backup: mode_backup@e3 {
 385                                 reg = <0xe3 0x1>;
 386                                 bits = <6 2>;
 387                         };
 388
 389                         tsens_s6_p2_backup: s6-p2_backup@e4 {
 390                                 reg = <0xe4 0x1>;
 391                                 bits = <0 6>;
 392                         };
 393
 394                         tsens_s7_p2_backup: s7-p2_backup@e4 {
 395                                 reg = <0xe4 0x2>;
 396                                 bits = <6 6>;
 397                         };
 398
 399                         tsens_s8_p2_backup: s8-p2_backup@e5 {
 400                                 reg = <0xe5 0x2>;
 401                                 bits = <4 6>;
 402                         };
 403
 404                         tsens_s9_p2_backup: s9-p2_backup@e6 {
 405                                 reg = <0xe6 0x2>;
 406                                 bits = <2 6>;
 407                         };
 408
 409                         tsens_s10_p2_backup: s10_p2_backup@e7 {
 410                                 reg = <0xe7 0x1>;
 411                                 bits = <0 6>;
 412                         };
 413
 414                         tsens_base1_backup: base1_backup@440 {
 415                                 reg = <0x440 0x1>;
 416                                 bits = <0 8>;
 417                         };
 418
 419                         tsens_s0_p1_backup: s0-p1_backup@441 {
 420                                 reg = <0x441 0x1>;
 421                                 bits = <0 6>;
 422                         };
 423
 424                         tsens_s1_p1_backup: s1-p1_backup@442 {
 425                                 reg = <0x441 0x2>;
 426                                 bits = <6 6>;
 427                         };
 428
 429                         tsens_s2_p1_backup: s2-p1_backup@442 {
 430                                 reg = <0x442 0x2>;
 431                                 bits = <4 6>;
 432                         };
 433
 434                         tsens_s3_p1_backup: s3-p1_backup@443 {
 435                                 reg = <0x443 0x1>;
 436                                 bits = <2 6>;
 437                         };
 438
 439                         tsens_s4_p1_backup: s4-p1_backup@444 {
 440                                 reg = <0x444 0x1>;
 441                                 bits = <0 6>;
 442                         };
 443
 444                         tsens_s5_p1_backup: s5-p1_backup@444 {
 445                                 reg = <0x444 0x2>;
 446                                 bits = <6 6>;
 447                         };
 448
 449                         tsens_s6_p1_backup: s6-p1_backup@445 {
 450                                 reg = <0x445 0x2>;
 451                                 bits = <4 6>;
 452                         };
 453
 454                         tsens_s7_p1_backup: s7-p1_backup@446 {
 455                                 reg = <0x446 0x1>;
 456                                 bits = <2 6>;
 457                         };
 458
 459                         tsens_use_backup: use_backup@447 {
 460                                 reg = <0x447 0x1>;
 461                                 bits = <5 3>;
 462                         };
 463
 464                         tsens_s8_p1_backup: s8-p1_backup@448 {
 465                                 reg = <0x448 0x1>;
 466                                 bits = <0 6>;
 467                         };
 468
 469                         tsens_s9_p1_backup: s9-p1_backup@448 {
 470                                 reg = <0x448 0x2>;
 471                                 bits = <6 6>;
 472                         };
 473
 474                         tsens_s10_p1_backup: s10_p1_backup@449 {
 475                                 reg = <0x449 0x2>;
 476                                 bits = <4 6>;
 477                         };
 478
 479                         tsens_base2_backup: base2_backup@44a {
 480                                 reg = <0x44a 0x2>;
 481                                 bits = <2 8>;
 482                         };
 483
 484                         tsens_s0_p2_backup: s0-p2_backup@44b {
 485                                 reg = <0x44b 0x3>;
 486                                 bits = <2 6>;
 487                         };
 488
 489                         tsens_s1_p2_backup: s1-p2_backup@44c {
 490                                 reg = <0x44c 0x1>;
 491                                 bits = <0 6>;
 492                         };
 493
 494                         tsens_s2_p2_backup: s2-p2_backup@44c {
 495                                 reg = <0x44c 0x2>;
 496                                 bits = <6 6>;
 497                         };
 498
 499                         tsens_s3_p2_backup: s3-p2_backup@44d {
 500                                 reg = <0x44d 0x2>;
 501                                 bits = <4 6>;
 502                         };
 503
 504                         tsens_s4_p2_backup: s4-p2_backup@44e {
 505                                 reg = <0x44e 0x1>;
 506                                 bits = <2 6>;
 507                         };
 508                 };
 509
 510                 tsens: thermal-sensor@fc4a9000 {
 511                         compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
 512                         reg = <0xfc4a9000 0x1000>, /* TM */
 513                               <0xfc4a8000 0x1000>; /* SROT */
 514                         nvmem-cells = <&tsens_mode>,
 515                                       <&tsens_base1>, <&tsens_base2>,
 516                                       <&tsens_use_backup>,
 517                                       <&tsens_mode_backup>,
 518                                       <&tsens_base1_backup>, <&tsens_base2_backup>,
 519                                       <&tsens_s0_p1>, <&tsens_s0_p2>,
 520                                       <&tsens_s1_p1>, <&tsens_s1_p2>,
 521                                       <&tsens_s2_p1>, <&tsens_s2_p2>,
 522                                       <&tsens_s3_p1>, <&tsens_s3_p2>,
 523                                       <&tsens_s4_p1>, <&tsens_s4_p2>,
 524                                       <&tsens_s5_p1>, <&tsens_s5_p2>,
 525                                       <&tsens_s6_p1>, <&tsens_s6_p2>,
 526                                       <&tsens_s7_p1>, <&tsens_s7_p2>,
 527                                       <&tsens_s8_p1>, <&tsens_s8_p2>,
 528                                       <&tsens_s9_p1>, <&tsens_s9_p2>,
 529                                       <&tsens_s10_p1>, <&tsens_s10_p2>,
 530                                       <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
 531                                       <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
 532                                       <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
 533                                       <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
 534                                       <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
 535                                       <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
 536                                       <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
 537                                       <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
 538                                       <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
 539                                       <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
 540                                       <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
 541                         nvmem-cell-names = "mode",
 542                                            "base1", "base2",
 543                                            "use_backup",
 544                                            "mode_backup",
 545                                            "base1_backup", "base2_backup",
 546                                            "s0_p1", "s0_p2",
 547                                            "s1_p1", "s1_p2",
 548                                            "s2_p1", "s2_p2",
 549                                            "s3_p1", "s3_p2",
 550                                            "s4_p1", "s4_p2",
 551                                            "s5_p1", "s5_p2",
 552                                            "s6_p1", "s6_p2",
 553                                            "s7_p1", "s7_p2",
 554                                            "s8_p1", "s8_p2",
 555                                            "s9_p1", "s9_p2",
 556                                            "s10_p1", "s10_p2",
 557                                            "s0_p1_backup", "s0_p2_backup",
 558                                            "s1_p1_backup", "s1_p2_backup",
 559                                            "s2_p1_backup", "s2_p2_backup",
 560                                            "s3_p1_backup", "s3_p2_backup",
 561                                            "s4_p1_backup", "s4_p2_backup",
 562                                            "s5_p1_backup", "s5_p2_backup",
 563                                            "s6_p1_backup", "s6_p2_backup",
 564                                            "s7_p1_backup", "s7_p2_backup",
 565                                            "s8_p1_backup", "s8_p2_backup",
 566                                            "s9_p1_backup", "s9_p2_backup",
 567                                            "s10_p1_backup", "s10_p2_backup";
 568                         #qcom,sensors = <11>;
 569                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 570                         interrupt-names = "uplow";
 571                         #thermal-sensor-cells = <1>;
 572                 };
 573                 timer@f9020000 {
 574                         #address-cells = <1>;
 575                         #size-cells = <1>;
 576                         ranges;
 577                         compatible = "arm,armv7-timer-mem";
 578                         reg = <0xf9020000 0x1000>;
 579                         clock-frequency = <19200000>;
 580
 581                         frame@f9021000 {
 582                                 frame-number = <0>;
 583                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 584                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 585                                 reg = <0xf9021000 0x1000>,
 586                                       <0xf9022000 0x1000>;
 587                         };
 588
 589                         frame@f9023000 {
 590                                 frame-number = <1>;
 591                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 592                                 reg = <0xf9023000 0x1000>;
 593                                 status = "disabled";
 594                         };
 595
 596                         frame@f9024000 {
 597                                 frame-number = <2>;
 598                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 599                                 reg = <0xf9024000 0x1000>;
 600                                 status = "disabled";
 601                         };
 602
 603                         frame@f9025000 {
 604                                 frame-number = <3>;
 605                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 606                                 reg = <0xf9025000 0x1000>;
 607                                 status = "disabled";
 608                         };
 609
 610                         frame@f9026000 {
 611                                 frame-number = <4>;
 612                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 613                                 reg = <0xf9026000 0x1000>;
 614                                 status = "disabled";
 615                         };
 616
 617                         frame@f9027000 {
 618                                 frame-number = <5>;
 619                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 620                                 reg = <0xf9027000 0x1000>;
 621                                 status = "disabled";
 622                         };
 623
 624                         frame@f9028000 {
 625                                 frame-number = <6>;
 626                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 627                                 reg = <0xf9028000 0x1000>;
 628                                 status = "disabled";
 629                         };
 630                 };
 631
 632                 saw0: power-controller@f9089000 {
 633                         compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
 634                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
 635                 };
 636
 637                 saw1: power-controller@f9099000 {
 638                         compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
 639                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
 640                 };
 641
 642                 saw2: power-controller@f90a9000 {
 643                         compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
 644                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
 645                 };
 646
 647                 saw3: power-controller@f90b9000 {
 648                         compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
 649                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
 650                 };
 651
 652                 saw_l2: power-controller@f9012000 {
 653                         compatible = "qcom,saw2";
 654                         reg = <0xf9012000 0x1000>;
 655                         regulator;
 656                 };
 657
 658                 acc0: power-manager@f9088000 {
 659                         compatible = "qcom,kpss-acc-v2";
 660                         reg = <0xf9088000 0x1000>,
 661                               <0xf9008000 0x1000>;
 662                 };
 663
 664                 acc1: power-manager@f9098000 {
 665                         compatible = "qcom,kpss-acc-v2";
 666                         reg = <0xf9098000 0x1000>,
 667                               <0xf9008000 0x1000>;
 668                 };
 669
 670                 acc2: power-manager@f90a8000 {
 671                         compatible = "qcom,kpss-acc-v2";
 672                         reg = <0xf90a8000 0x1000>,
 673                               <0xf9008000 0x1000>;
 674                 };
 675
 676                 acc3: power-manager@f90b8000 {
 677                         compatible = "qcom,kpss-acc-v2";
 678                         reg = <0xf90b8000 0x1000>,
 679                               <0xf9008000 0x1000>;
 680                 };
 681
 682                 restart@fc4ab000 {
 683                         compatible = "qcom,pshold";
 684                         reg = <0xfc4ab000 0x4>;
 685                 };
 686
 687                 gcc: clock-controller@fc400000 {
 688                         compatible = "qcom,gcc-apq8084";
 689                         #clock-cells = <1>;
 690                         #reset-cells = <1>;
 691                         #power-domain-cells = <1>;
 692                         reg = <0xfc400000 0x4000>;
 693                         clocks = <&xo_board>,
 694                                  <&sleep_clk>,
 695                                  <0>, /* ufs */
 696                                  <0>,
 697                                  <0>,
 698                                  <0>,
 699                                  <0>, /* sata */
 700                                  <0>,
 701                                  <0>; /* pcie */
 702                         clock-names = "xo",
 703                                       "sleep_clk",
 704                                       "ufs_rx_symbol_0_clk_src",
 705                                       "ufs_rx_symbol_1_clk_src",
 706                                       "ufs_tx_symbol_0_clk_src",
 707                                       "ufs_tx_symbol_1_clk_src",
 708                                       "sata_asic0_clk",
 709                                       "sata_rx_clk",
 710                                       "pcie_pipe";
 711                 };
 712
 713                 tcsr_mutex: hwlock@fd484000 {
 714                         compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
 715                         reg = <0xfd484000 0x1000>;
 716                         #hwlock-cells = <1>;
 717                 };
 718
 719                 rpm_msg_ram: sram@fc428000 {
 720                         compatible = "qcom,rpm-msg-ram";
 721                         reg = <0xfc428000 0x4000>;
 722                 };
 723
 724                 tlmm: pinctrl@fd510000 {
 725                         compatible = "qcom,apq8084-pinctrl";
 726                         reg = <0xfd510000 0x4000>;
 727                         gpio-controller;
 728                         gpio-ranges = <&tlmm 0 0 147>;
 729                         #gpio-cells = <2>;
 730                         interrupt-controller;
 731                         #interrupt-cells = <2>;
 732                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 733                 };
 734
 735                 blsp2_uart2: serial@f995e000 {
 736                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 737                         reg = <0xf995e000 0x1000>;
 738                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 739                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 740                         clock-names = "core", "iface";
 741                         status = "disabled";
 742                 };
 743
 744                 sdhc_1: mmc@f9824900 {
 745                         compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
 746                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 747                         reg-names = "hc", "core";
 748                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 749                         interrupt-names = "hc_irq", "pwr_irq";
 750                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 751                                  <&gcc GCC_SDCC1_APPS_CLK>,
 752                                  <&xo_board>;
 753                         clock-names = "iface", "core", "xo";
 754                         status = "disabled";
 755                 };
 756
 757                 sdhc_2: mmc@f98a4900 {
 758                         compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
 759                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 760                         reg-names = "hc", "core";
 761                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 762                         interrupt-names = "hc_irq", "pwr_irq";
 763                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 764                                  <&gcc GCC_SDCC2_APPS_CLK>,
 765                                  <&xo_board>;
 766                         clock-names = "iface", "core", "xo";
 767                         status = "disabled";
 768                 };
 769
 770                 spmi_bus: spmi@fc4cf000 {
 771                         compatible = "qcom,spmi-pmic-arb";
 772                         reg-names = "core", "intr", "cnfg";
 773                         reg = <0xfc4cf000 0x1000>,
 774                               <0xfc4cb000 0x1000>,
 775                               <0xfc4ca000 0x1000>;
 776                         interrupt-names = "periph_irq";
 777                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 778                         qcom,ee = <0>;
 779                         qcom,channel = <0>;
 780                         #address-cells = <2>;
 781                         #size-cells = <0>;
 782                         interrupt-controller;
 783                         #interrupt-cells = <4>;
 784                 };
 785         };
 786
 787         smd {
 788                 compatible = "qcom,smd";
 789
 790                 rpm {
 791                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 792                         qcom,ipc = <&apcs 8 0>;
 793                         qcom,smd-edge = <15>;
 794
 795                         rpm-requests {
 796                                 compatible = "qcom,rpm-apq8084";
 797                                 qcom,smd-channels = "rpm_requests";
 798
 799                                 regulators-0 {
 800                                         compatible = "qcom,rpm-pma8084-regulators";
 801
 802                                         pma8084_s1: s1 {};
 803                                         pma8084_s2: s2 {};
 804                                         pma8084_s3: s3 {};
 805                                         pma8084_s4: s4 {};
 806                                         pma8084_s5: s5 {};
 807                                         pma8084_s6: s6 {};
 808                                         pma8084_s7: s7 {};
 809                                         pma8084_s8: s8 {};
 810                                         pma8084_s9: s9 {};
 811                                         pma8084_s10: s10 {};
 812                                         pma8084_s11: s11 {};
 813                                         pma8084_s12: s12 {};
 814
 815                                         pma8084_l1: l1 {};
 816                                         pma8084_l2: l2 {};
 817                                         pma8084_l3: l3 {};
 818                                         pma8084_l4: l4 {};
 819                                         pma8084_l5: l5 {};
 820                                         pma8084_l6: l6 {};
 821                                         pma8084_l7: l7 {};
 822                                         pma8084_l8: l8 {};
 823                                         pma8084_l9: l9 {};
 824                                         pma8084_l10: l10 {};
 825                                         pma8084_l11: l11 {};
 826                                         pma8084_l12: l12 {};
 827                                         pma8084_l13: l13 {};
 828                                         pma8084_l14: l14 {};
 829                                         pma8084_l15: l15 {};
 830                                         pma8084_l16: l16 {};
 831                                         pma8084_l17: l17 {};
 832                                         pma8084_l18: l18 {};
 833                                         pma8084_l19: l19 {};
 834                                         pma8084_l20: l20 {};
 835                                         pma8084_l21: l21 {};
 836                                         pma8084_l22: l22 {};
 837                                         pma8084_l23: l23 {};
 838                                         pma8084_l24: l24 {};
 839                                         pma8084_l25: l25 {};
 840                                         pma8084_l26: l26 {};
 841                                         pma8084_l27: l27 {};
 842
 843                                         pma8084_lvs1: lvs1 {};
 844                                         pma8084_lvs2: lvs2 {};
 845                                         pma8084_lvs3: lvs3 {};
 846                                         pma8084_lvs4: lvs4 {};
 847
 848                                         pma8084_5vs1: 5vs1 {};
 849                                 };
 850                         };
 851                 };
 852         };
 853 };