arch/arm/boot/dts/imx7d-sdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
   4
   5 /dts-v1/;
   6
   7 #include "imx7d.dtsi"
   8
   9 / {
  10         model = "Freescale i.MX7 SabreSD Board";
  11         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  12
  13         chosen {
  14                 stdout-path = &uart1;
  15         };
  16
  17         memory@80000000 {
  18                 device_type = "memory";
  19                 reg = <0x80000000 0x80000000>;
  20         };
  21
  22         gpio-keys {
  23                 compatible = "gpio-keys";
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&pinctrl_gpio_keys>;
  26
  27                 volume-up {
  28                         label = "Volume Up";
  29                         gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
  30                         linux,code = <KEY_VOLUMEUP>;
  31                         wakeup-source;
  32                 };
  33
  34                 volume-down {
  35                         label = "Volume Down";
  36                         gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_VOLUMEDOWN>;
  38                         wakeup-source;
  39                 };
  40         };
  41
  42         spi4 {
  43                 compatible = "spi-gpio";
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_spi4>;
  46                 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  47                 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  48                 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  49                 num-chipselects = <1>;
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 extended_io: gpio-expander@0 {
  54                         compatible = "fairchild,74hc595";
  55                         gpio-controller;
  56                         #gpio-cells = <2>;
  57                         reg = <0>;
  58                         registers-number = <1>;
  59                         spi-max-frequency = <100000>;
  60                 };
  61         };
  62
  63         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "usb_otg1_vbus";
  66                 regulator-min-microvolt = <5000000>;
  67                 regulator-max-microvolt = <5000000>;
  68                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  69                 enable-active-high;
  70         };
  71
  72         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "usb_otg2_vbus";
  75                 pinctrl-names = "default";
  76                 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
  77                 regulator-min-microvolt = <5000000>;
  78                 regulator-max-microvolt = <5000000>;
  79                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  80                 enable-active-high;
  81         };
  82
  83         reg_vref_1v8: regulator-vref-1v8 {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "vref-1v8";
  86                 regulator-min-microvolt = <1800000>;
  87                 regulator-max-microvolt = <1800000>;
  88         };
  89
  90         reg_brcm: regulator-brcm {
  91                 compatible = "regulator-fixed";
  92                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  93                 enable-active-high;
  94                 regulator-name = "brcm_reg";
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_brcm_reg>;
  97                 regulator-min-microvolt = <3300000>;
  98                 regulator-max-microvolt = <3300000>;
  99                 startup-delay-us = <200000>;
 100         };
 101
 102         reg_lcd_3v3: regulator-lcd-3v3 {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "lcd-3v3";
 105                 regulator-min-microvolt = <3300000>;
 106                 regulator-max-microvolt = <3300000>;
 107                 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
 108         };
 109
 110         reg_can2_3v3: regulator-can2-3v3 {
 111                 compatible = "regulator-fixed";
 112                 regulator-name = "can2-3v3";
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-max-microvolt = <3300000>;
 117                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
 118         };
 119
 120         reg_fec2_3v3: regulator-fec2-3v3 {
 121                 compatible = "regulator-fixed";
 122                 regulator-name = "fec2-3v3";
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&pinctrl_enet2_reg>;
 125                 regulator-min-microvolt = <3300000>;
 126                 regulator-max-microvolt = <3300000>;
 127                 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
 128         };
 129
 130         backlight: backlight {
 131                 compatible = "pwm-backlight";
 132                 pwms = <&pwm1 0 5000000 0>;
 133                 brightness-levels = <0 4 8 16 32 64 128 255>;
 134                 default-brightness-level = <6>;
 135                 status = "okay";
 136         };
 137
 138         panel {
 139                 compatible = "innolux,at043tn24";
 140                 backlight = <&backlight>;
 141                 power-supply = <&reg_lcd_3v3>;
 142
 143                 port {
 144                         panel_in: endpoint {
 145                                 remote-endpoint = <&display_out>;
 146                         };
 147                 };
 148         };
 149 };
 150
 151 &adc1 {
 152         vref-supply = <&reg_vref_1v8>;
 153         status = "okay";
 154 };
 155
 156 &adc2 {
 157         vref-supply = <&reg_vref_1v8>;
 158         status = "okay";
 159 };
 160
 161 &cpu0 {
 162         cpu-supply = <&sw1a_reg>;
 163 };
 164
 165 &cpu1 {
 166         cpu-supply = <&sw1a_reg>;
 167 };
 168
 169 &ecspi3 {
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&pinctrl_ecspi3>;
 172         cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
 173         status = "okay";
 174
 175         tsc2046@0 {
 176                 compatible = "ti,tsc2046";
 177                 reg = <0>;
 178                 spi-max-frequency = <1000000>;
 179                 pinctrl-names ="default";
 180                 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 181                 interrupt-parent = <&gpio2>;
 182                 interrupts = <29 0>;
 183                 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 184                 ti,x-min = /bits/ 16 <0>;
 185                 ti,x-max = /bits/ 16 <0>;
 186                 ti,y-min = /bits/ 16 <0>;
 187                 ti,y-max = /bits/ 16 <0>;
 188                 ti,pressure-max = /bits/ 16 <0>;
 189                 ti,x-plate-ohms = /bits/ 16 <400>;
 190                 wakeup-source;
 191         };
 192 };
 193
 194 &fec1 {
 195         pinctrl-names = "default";
 196         pinctrl-0 = <&pinctrl_enet1>;
 197         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 198                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 199         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 200         assigned-clock-rates = <0>, <100000000>;
 201         phy-mode = "rgmii";
 202         phy-handle = <&ethphy0>;
 203         fsl,magic-packet;
 204         phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
 205         status = "okay";
 206
 207         mdio {
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210
 211                 ethphy0: ethernet-phy@0 {
 212                         reg = <0>;
 213                 };
 214
 215                 ethphy1: ethernet-phy@1 {
 216                         reg = <1>;
 217                 };
 218         };
 219 };
 220
 221 &fec2 {
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_enet2>;
 224         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 225                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 226         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 227         assigned-clock-rates = <0>, <100000000>;
 228         phy-mode = "rgmii";
 229         phy-handle = <&ethphy1>;
 230         phy-supply = <&reg_fec2_3v3>;
 231         fsl,magic-packet;
 232         status = "okay";
 233 };
 234
 235 &flexcan2 {
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&pinctrl_flexcan2>;
 238         xceiver-supply = <&reg_can2_3v3>;
 239         status = "okay";
 240 };
 241
 242 &i2c1 {
 243         pinctrl-names = "default";
 244         pinctrl-0 = <&pinctrl_i2c1>;
 245         status = "okay";
 246
 247         pmic: pfuze3000@8 {
 248                 compatible = "fsl,pfuze3000";
 249                 reg = <0x08>;
 250
 251                 regulators {
 252                         sw1a_reg: sw1a {
 253                                 regulator-min-microvolt = <700000>;
 254                                 regulator-max-microvolt = <1475000>;
 255                                 regulator-boot-on;
 256                                 regulator-always-on;
 257                                 regulator-ramp-delay = <6250>;
 258                         };
 259
 260                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 261                         sw1c_reg: sw1b {
 262                                 regulator-min-microvolt = <700000>;
 263                                 regulator-max-microvolt = <1475000>;
 264                                 regulator-boot-on;
 265                                 regulator-always-on;
 266                                 regulator-ramp-delay = <6250>;
 267                         };
 268
 269                         sw2_reg: sw2 {
 270                                 regulator-min-microvolt = <1800000>;
 271                                 regulator-max-microvolt = <1800000>;
 272                                 regulator-boot-on;
 273                                 regulator-always-on;
 274                         };
 275
 276                         sw3a_reg: sw3 {
 277                                 regulator-min-microvolt = <900000>;
 278                                 regulator-max-microvolt = <1650000>;
 279                                 regulator-boot-on;
 280                                 regulator-always-on;
 281                         };
 282
 283                         swbst_reg: swbst {
 284                                 regulator-min-microvolt = <5000000>;
 285                                 regulator-max-microvolt = <5150000>;
 286                         };
 287
 288                         snvs_reg: vsnvs {
 289                                 regulator-min-microvolt = <1000000>;
 290                                 regulator-max-microvolt = <3000000>;
 291                                 regulator-boot-on;
 292                                 regulator-always-on;
 293                         };
 294
 295                         vref_reg: vrefddr {
 296                                 regulator-boot-on;
 297                                 regulator-always-on;
 298                         };
 299
 300                         vgen1_reg: vldo1 {
 301                                 regulator-min-microvolt = <1800000>;
 302                                 regulator-max-microvolt = <3300000>;
 303                                 regulator-always-on;
 304                         };
 305
 306                         vgen2_reg: vldo2 {
 307                                 regulator-min-microvolt = <800000>;
 308                                 regulator-max-microvolt = <1550000>;
 309                         };
 310
 311                         vgen3_reg: vccsd {
 312                                 regulator-min-microvolt = <2850000>;
 313                                 regulator-max-microvolt = <3300000>;
 314                                 regulator-always-on;
 315                         };
 316
 317                         vgen4_reg: v33 {
 318                                 regulator-min-microvolt = <2850000>;
 319                                 regulator-max-microvolt = <3300000>;
 320                                 regulator-always-on;
 321                         };
 322
 323                         vgen5_reg: vldo3 {
 324                                 regulator-min-microvolt = <1800000>;
 325                                 regulator-max-microvolt = <3300000>;
 326                                 regulator-always-on;
 327                         };
 328
 329                         vgen6_reg: vldo4 {
 330                                 regulator-min-microvolt = <2800000>;
 331                                 regulator-max-microvolt = <2800000>;
 332                                 regulator-always-on;
 333                         };
 334                 };
 335         };
 336 };
 337
 338 &i2c2 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_i2c2>;
 341         status = "okay";
 342
 343         mpl3115@60 {
 344                 compatible = "fsl,mpl3115";
 345                 reg = <0x60>;
 346         };
 347 };
 348
 349 &i2c3 {
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&pinctrl_i2c3>;
 352         status = "okay";
 353 };
 354
 355 &i2c4 {
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&pinctrl_i2c4>;
 358         status = "okay";
 359
 360         codec: wm8960@1a {
 361                 compatible = "wlf,wm8960";
 362                 reg = <0x1a>;
 363                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 364                 clock-names = "mclk";
 365                 wlf,shared-lrclk;
 366         };
 367 };
 368
 369 &lcdif {
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&pinctrl_lcdif>;
 372         status = "okay";
 373
 374         port {
 375                 display_out: endpoint {
 376                         remote-endpoint = <&panel_in>;
 377                 };
 378         };
 379 };
 380
 381 &pcie {
 382         reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
 383         status = "okay";
 384 };
 385
 386 &reg_1p0d {
 387         vin-supply = <&sw2_reg>;
 388 };
 389
 390 &reg_1p2 {
 391         vin-supply = <&sw2_reg>;
 392 };
 393
 394 &snvs_pwrkey {
 395         status = "okay";
 396 };
 397
 398 &uart1 {
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&pinctrl_uart1>;
 401         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 402         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 403         status = "okay";
 404 };
 405
 406 &uart6 {
 407         pinctrl-names = "default";
 408         pinctrl-0 = <&pinctrl_uart6>;
 409         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 410         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 411         uart-has-rtscts;
 412         status = "okay";
 413 };
 414
 415 &usbotg1 {
 416         vbus-supply = <&reg_usb_otg1_vbus>;
 417         status = "okay";
 418 };
 419
 420 &usbotg2 {
 421         vbus-supply = <&reg_usb_otg2_vbus>;
 422         dr_mode = "host";
 423         status = "okay";
 424 };
 425
 426 &usdhc1 {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_usdhc1>;
 429         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 430         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 431         wakeup-source;
 432         keep-power-in-suspend;
 433         status = "okay";
 434 };
 435
 436 &usdhc2 {
 437         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 438         pinctrl-0 = <&pinctrl_usdhc2>;
 439         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 440         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 441         wakeup-source;
 442         keep-power-in-suspend;
 443         non-removable;
 444         vmmc-supply = <&reg_brcm>;
 445         fsl,tuning-step = <2>;
 446         status = "okay";
 447 };
 448
 449 &usdhc3 {
 450         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 451         pinctrl-0 = <&pinctrl_usdhc3>;
 452         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 453         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 454         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 455         assigned-clock-rates = <400000000>;
 456         bus-width = <8>;
 457         fsl,tuning-step = <2>;
 458         non-removable;
 459         status = "okay";
 460 };
 461
 462 &wdog1 {
 463         pinctrl-names = "default";
 464         pinctrl-0 = <&pinctrl_wdog>;
 465         fsl,ext-reset-output;
 466 };
 467
 468 &iomuxc {
 469         pinctrl-names = "default";
 470         pinctrl-0 = <&pinctrl_hog>;
 471
 472         imx7d-sdb {
 473                 pinctrl_brcm_reg: brcmreggrp {
 474                         fsl,pins = <
 475                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x14
 476                         >;
 477                 };
 478
 479                 pinctrl_ecspi3: ecspi3grp {
 480                         fsl,pins = <
 481                                 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
 482                                 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
 483                                 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
 484                                 MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
 485                         >;
 486                 };
 487
 488                 pinctrl_enet1: enet1grp {
 489                         fsl,pins = <
 490                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 491                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 492                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 493                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 494                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 495                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 496                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 497                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 498                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 499                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 500                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 501                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 502                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 503                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 504                         >;
 505                 };
 506
 507                 pinctrl_enet2: enet2grp {
 508                         fsl,pins = <
 509                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 510                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 511                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 512                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 513                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 514                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 515                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 516                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 517                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 518                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 519                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 520                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 521                         >;
 522                 };
 523
 524                 pinctrl_enet2_reg: enet2reggrp {
 525                         fsl,pins = <
 526                                 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4     0x14
 527                         >;
 528                 };
 529
 530                 pinctrl_flexcan2: flexcan2grp {
 531                         fsl,pins = <
 532                                 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
 533                                 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
 534                         >;
 535                 };
 536
 537                 pinctrl_flexcan2_reg: flexcan2reggrp {
 538                         fsl,pins = <
 539                                 MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x59    /* CAN_STBY */
 540                         >;
 541                 };
 542
 543                 pinctrl_gpio_keys: gpio_keysgrp {
 544                         fsl,pins = <
 545                                 MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x59
 546                                 MX7D_PAD_SD2_WP__GPIO5_IO10             0x59
 547                         >;
 548                 };
 549
 550                 pinctrl_hog: hoggrp {
 551                         fsl,pins = <
 552                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 553                         >;
 554                 };
 555
 556                 pinctrl_i2c1: i2c1grp {
 557                         fsl,pins = <
 558                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 559                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 560                         >;
 561                 };
 562
 563                 pinctrl_i2c2: i2c2grp {
 564                         fsl,pins = <
 565                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 566                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 567                         >;
 568                 };
 569
 570                 pinctrl_i2c3: i2c3grp {
 571                         fsl,pins = <
 572                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 573                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 574                         >;
 575                 };
 576
 577                 pinctrl_i2c4: i2c4grp {
 578                         fsl,pins = <
 579                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 580                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 581                         >;
 582                 };
 583
 584                 pinctrl_lcdif: lcdifgrp {
 585                         fsl,pins = <
 586                                 MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 587                                 MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 588                                 MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 589                                 MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 590                                 MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 591                                 MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 592                                 MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 593                                 MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 594                                 MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 595                                 MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 596                                 MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 597                                 MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 598                                 MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 599                                 MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 600                                 MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 601                                 MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 602                                 MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 603                                 MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 604                                 MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 605                                 MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 606                                 MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 607                                 MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 608                                 MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 609                                 MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 610                                 MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 611                                 MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 612                                 MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 613                                 MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 614                                 MX7D_PAD_LCD_RESET__LCD_RESET           0x79
 615                         >;
 616                 };
 617
 618                 pinctrl_spi4: spi4grp {
 619                         fsl,pins = <
 620                                 MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
 621                                 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
 622                                 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
 623                         >;
 624                 };
 625
 626                 pinctrl_tsc2046_pendown: tsc2046_pendown {
 627                         fsl,pins = <
 628                                 MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
 629                         >;
 630                 };
 631
 632                 pinctrl_uart1: uart1grp {
 633                         fsl,pins = <
 634                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 635                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 636                         >;
 637                 };
 638
 639                 pinctrl_uart5: uart5grp {
 640                         fsl,pins = <
 641                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 642                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 643                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 644                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 645                         >;
 646                 };
 647
 648                 pinctrl_uart6: uart6grp {
 649                         fsl,pins = <
 650                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 651                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 652                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 653                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 654                         >;
 655                 };
 656
 657                 pinctrl_usdhc1: usdhc1grp {
 658                         fsl,pins = <
 659                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 660                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 661                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 662                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 663                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 664                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 665                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 666                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 667                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 668                         >;
 669                 };
 670
 671                 pinctrl_usdhc2: usdhc2grp {
 672                         fsl,pins = <
 673                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 674                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 675                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 676                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 677                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 678                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 679                         >;
 680                 };
 681
 682                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 683                         fsl,pins = <
 684                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 685                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 686                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 687                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 688                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 689                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 690                         >;
 691                 };
 692
 693                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 694                         fsl,pins = <
 695                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 696                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 697                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 698                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 699                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 700                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 701                         >;
 702                 };
 703
 704
 705                 pinctrl_usdhc3: usdhc3grp {
 706                         fsl,pins = <
 707                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 708                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 709                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 710                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 711                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 712                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 713                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 714                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 715                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 716                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 717                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 718                         >;
 719                 };
 720
 721                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 722                         fsl,pins = <
 723                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 724                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 725                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 726                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 727                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 728                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 729                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 730                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 731                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 732                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 733                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 734                         >;
 735                 };
 736
 737                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 738                         fsl,pins = <
 739                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 740                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 741                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 742                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 743                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 744                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 745                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 746                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 747                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 748                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 749                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 750                         >;
 751                 };
 752         };
 753 };
 754
 755 &pwm1 {
 756         pinctrl-names = "default";
 757         pinctrl-0 = <&pinctrl_pwm1>;
 758         status = "okay";
 759 };
 760
 761 &iomuxc_lpsr {
 762         pinctrl_wdog: wdoggrp {
 763                 fsl,pins = <
 764                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B          0x74
 765                 >;
 766         };
 767
 768         pinctrl_pwm1: pwm1grp {
 769                 fsl,pins = <
 770                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT              0x30
 771                 >;
 772         };
 773
 774         pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
 775                 fsl,pins = <
 776                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7       0x14
 777                 >;
 778         };
 779 };