drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c

   1 /*
   2  * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
   3  *
   4  * Samsung MFC (Multi Function Codec - FIMV) driver
   5  * This file contains hw related functions.
   6  *
   7  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   8  *              http://www.samsung.com/
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #undef DEBUG
  16
  17 #include <linux/delay.h>
  18 #include <linux/mm.h>
  19 #include <linux/io.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/firmware.h>
  22 #include <linux/err.h>
  23 #include <linux/sched.h>
  24 #include <linux/dma-mapping.h>
  25
  26 #include <asm/cacheflush.h>
  27
  28 #include "s5p_mfc_common.h"
  29 #include "s5p_mfc_cmd.h"
  30 #include "s5p_mfc_intr.h"
  31 #include "s5p_mfc_pm.h"
  32 #include "s5p_mfc_debug.h"
  33 #include "s5p_mfc_opr.h"
  34 #include "s5p_mfc_opr_v6.h"
  35
  36 /* #define S5P_MFC_DEBUG_REGWRITE  */
  37 #ifdef S5P_MFC_DEBUG_REGWRITE
  38 #undef writel
  39 #define writel(v, r)                                                    \
  40         do {                                                            \
  41                 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v);     \
  42         __raw_writel(v, r);                                             \
  43         } while (0)
  44 #endif /* S5P_MFC_DEBUG_REGWRITE */
  45
  46 #define READL(reg) \
  47         (WARN_ON_ONCE(!(reg)) ? 0 : readl(reg))
  48 #define WRITEL(data, reg) \
  49         (WARN_ON_ONCE(!(reg)) ? 0 : writel((data), (reg)))
  50
  51 #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
  52
  53 /* Allocate temporary buffers for decoding */
  54 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
  55 {
  56         /* NOP */
  57
  58         return 0;
  59 }
  60
  61 /* Release temproary buffers for decoding */
  62 static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
  63 {
  64         /* NOP */
  65 }
  66
  67 /* Allocate codec buffers */
  68 static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
  69 {
  70         struct s5p_mfc_dev *dev = ctx->dev;
  71         unsigned int mb_width, mb_height;
  72         int ret;
  73
  74         mb_width = MB_WIDTH(ctx->img_width);
  75         mb_height = MB_HEIGHT(ctx->img_height);
  76
  77         if (ctx->type == MFCINST_DECODER) {
  78                 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
  79                           ctx->luma_size, ctx->chroma_size, ctx->mv_size);
  80                 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
  81         } else if (ctx->type == MFCINST_ENCODER) {
  82                 if (IS_MFCV8(dev))
  83                         ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  84                         ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
  85                         S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  86                 else
  87                         ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
  88                         ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
  89                         S5P_FIMV_TMV_BUFFER_ALIGN_V6);
  90
  91                 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
  92                                 S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
  93                                 S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
  94                 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
  95                                 S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
  96                                 S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
  97                 if (IS_MFCV8(dev))
  98                         ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
  99                                                 ctx->img_width, ctx->img_height,
 100                                                 mb_width, mb_height),
 101                                                 S5P_FIMV_ME_BUFFER_ALIGN_V6);
 102                 else
 103                         ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
 104                                                 ctx->img_width, ctx->img_height,
 105                                                 mb_width, mb_height),
 106                                                 S5P_FIMV_ME_BUFFER_ALIGN_V6);
 107
 108                 mfc_debug(2, "recon luma size: %d chroma size: %d\n",
 109                           ctx->luma_dpb_size, ctx->chroma_dpb_size);
 110         } else {
 111                 return -EINVAL;
 112         }
 113
 114         /* Codecs have different memory requirements */
 115         switch (ctx->codec_mode) {
 116         case S5P_MFC_CODEC_H264_DEC:
 117         case S5P_MFC_CODEC_H264_MVC_DEC:
 118                 if (IS_MFCV8(dev))
 119                         ctx->scratch_buf_size =
 120                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(
 121                                         mb_width,
 122                                         mb_height);
 123                 else
 124                         ctx->scratch_buf_size =
 125                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
 126                                         mb_width,
 127                                         mb_height);
 128                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 129                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 130                 ctx->bank1.size =
 131                         ctx->scratch_buf_size +
 132                         (ctx->mv_count * ctx->mv_size);
 133                 break;
 134         case S5P_MFC_CODEC_MPEG4_DEC:
 135                 if (IS_MFCV7_PLUS(dev)) {
 136                         ctx->scratch_buf_size =
 137                                 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
 138                                                 mb_width,
 139                                                 mb_height);
 140                 } else {
 141                         ctx->scratch_buf_size =
 142                                 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
 143                                                 mb_width,
 144                                                 mb_height);
 145                 }
 146
 147                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 148                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 149                 ctx->bank1.size = ctx->scratch_buf_size;
 150                 break;
 151         case S5P_MFC_CODEC_VC1RCV_DEC:
 152         case S5P_MFC_CODEC_VC1_DEC:
 153                 ctx->scratch_buf_size =
 154                         S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
 155                                         mb_width,
 156                                         mb_height);
 157                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 158                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 159                 ctx->bank1.size = ctx->scratch_buf_size;
 160                 break;
 161         case S5P_MFC_CODEC_MPEG2_DEC:
 162                 ctx->bank1.size = 0;
 163                 ctx->bank2.size = 0;
 164                 break;
 165         case S5P_MFC_CODEC_H263_DEC:
 166                 ctx->scratch_buf_size =
 167                         S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
 168                                         mb_width,
 169                                         mb_height);
 170                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 171                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 172                 ctx->bank1.size = ctx->scratch_buf_size;
 173                 break;
 174         case S5P_MFC_CODEC_VP8_DEC:
 175                 if (IS_MFCV8(dev))
 176                         ctx->scratch_buf_size =
 177                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(
 178                                                 mb_width,
 179                                                 mb_height);
 180                 else
 181                         ctx->scratch_buf_size =
 182                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
 183                                                 mb_width,
 184                                                 mb_height);
 185                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 186                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 187                 ctx->bank1.size = ctx->scratch_buf_size;
 188                 break;
 189         case S5P_MFC_CODEC_H264_ENC:
 190                 if (IS_MFCV8(dev))
 191                         ctx->scratch_buf_size =
 192                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
 193                                         mb_width,
 194                                         mb_height);
 195                 else
 196                         ctx->scratch_buf_size =
 197                                 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
 198                                                 mb_width,
 199                                                 mb_height);
 200                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 201                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 202                 ctx->bank1.size =
 203                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 204                         (ctx->pb_count * (ctx->luma_dpb_size +
 205                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 206                 ctx->bank2.size = 0;
 207                 break;
 208         case S5P_MFC_CODEC_MPEG4_ENC:
 209         case S5P_MFC_CODEC_H263_ENC:
 210                 ctx->scratch_buf_size =
 211                         S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
 212                                         mb_width,
 213                                         mb_height);
 214                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 215                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 216                 ctx->bank1.size =
 217                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 218                         (ctx->pb_count * (ctx->luma_dpb_size +
 219                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 220                 ctx->bank2.size = 0;
 221                 break;
 222         case S5P_MFC_CODEC_VP8_ENC:
 223                 if (IS_MFCV8(dev))
 224                         ctx->scratch_buf_size =
 225                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
 226                                         mb_width,
 227                                         mb_height);
 228                 else
 229                         ctx->scratch_buf_size =
 230                                 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(
 231                                                 mb_width,
 232                                                 mb_height);
 233                 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 234                                 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 235                 ctx->bank1.size =
 236                         ctx->scratch_buf_size + ctx->tmv_buffer_size +
 237                         (ctx->pb_count * (ctx->luma_dpb_size +
 238                         ctx->chroma_dpb_size + ctx->me_buffer_size));
 239                 ctx->bank2.size = 0;
 240                 break;
 241         default:
 242                 break;
 243         }
 244
 245         /* Allocate only if memory from bank 1 is necessary */
 246         if (ctx->bank1.size > 0) {
 247                 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1);
 248                 if (ret) {
 249                         mfc_err("Failed to allocate Bank1 memory\n");
 250                         return ret;
 251                 }
 252                 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
 253         }
 254         return 0;
 255 }
 256
 257 /* Release buffers allocated for codec */
 258 static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 259 {
 260         s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
 261 }
 262
 263 /* Allocate memory for instance data buffer */
 264 static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 265 {
 266         struct s5p_mfc_dev *dev = ctx->dev;
 267         struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 268         int ret;
 269
 270         mfc_debug_enter();
 271
 272         switch (ctx->codec_mode) {
 273         case S5P_MFC_CODEC_H264_DEC:
 274         case S5P_MFC_CODEC_H264_MVC_DEC:
 275                 ctx->ctx.size = buf_size->h264_dec_ctx;
 276                 break;
 277         case S5P_MFC_CODEC_MPEG4_DEC:
 278         case S5P_MFC_CODEC_H263_DEC:
 279         case S5P_MFC_CODEC_VC1RCV_DEC:
 280         case S5P_MFC_CODEC_VC1_DEC:
 281         case S5P_MFC_CODEC_MPEG2_DEC:
 282         case S5P_MFC_CODEC_VP8_DEC:
 283                 ctx->ctx.size = buf_size->other_dec_ctx;
 284                 break;
 285         case S5P_MFC_CODEC_H264_ENC:
 286                 ctx->ctx.size = buf_size->h264_enc_ctx;
 287                 break;
 288         case S5P_MFC_CODEC_MPEG4_ENC:
 289         case S5P_MFC_CODEC_H263_ENC:
 290         case S5P_MFC_CODEC_VP8_ENC:
 291                 ctx->ctx.size = buf_size->other_enc_ctx;
 292                 break;
 293         default:
 294                 ctx->ctx.size = 0;
 295                 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
 296                 break;
 297         }
 298
 299         ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx);
 300         if (ret) {
 301                 mfc_err("Failed to allocate instance buffer\n");
 302                 return ret;
 303         }
 304
 305         memset(ctx->ctx.virt, 0, ctx->ctx.size);
 306         wmb();
 307
 308         mfc_debug_leave();
 309
 310         return 0;
 311 }
 312
 313 /* Release instance buffer */
 314 static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 315 {
 316         s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx);
 317 }
 318
 319 /* Allocate context buffers for SYS_INIT */
 320 static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 321 {
 322         struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
 323         int ret;
 324
 325         mfc_debug_enter();
 326
 327         dev->ctx_buf.size = buf_size->dev_ctx;
 328         ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
 329         if (ret) {
 330                 mfc_err("Failed to allocate device context buffer\n");
 331                 return ret;
 332         }
 333
 334         memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
 335         wmb();
 336
 337         mfc_debug_leave();
 338
 339         return 0;
 340 }
 341
 342 /* Release context buffers for SYS_INIT */
 343 static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
 344 {
 345         s5p_mfc_release_priv_buf(dev->mem_dev_l, &dev->ctx_buf);
 346 }
 347
 348 static int calc_plane(int width, int height)
 349 {
 350         int mbX, mbY;
 351
 352         mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 353         mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
 354
 355         if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
 356                 mbY = (mbY + 1) / 2 * 2;
 357
 358         return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
 359                 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
 360 }
 361
 362 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 363 {
 364         ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
 365         ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
 366         mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
 367                         "buffer dimensions: %dx%d\n", ctx->img_width,
 368                         ctx->img_height, ctx->buf_width, ctx->buf_height);
 369
 370         ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
 371         ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
 372         if (IS_MFCV8(ctx->dev)) {
 373                 /* MFCv8 needs additional 64 bytes for luma,chroma dpb*/
 374                 ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 375                 ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 376         }
 377
 378         if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 379                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
 380                 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
 381                                 ctx->img_height);
 382                 ctx->mv_size = ALIGN(ctx->mv_size, 16);
 383         } else {
 384                 ctx->mv_size = 0;
 385         }
 386 }
 387
 388 static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
 389 {
 390         unsigned int mb_width, mb_height;
 391
 392         mb_width = MB_WIDTH(ctx->img_width);
 393         mb_height = MB_HEIGHT(ctx->img_height);
 394
 395         ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
 396         ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
 397         ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
 398
 399         /* MFCv7 needs pad bytes for Luma and Chroma */
 400         if (IS_MFCV7_PLUS(ctx->dev)) {
 401                 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
 402                 ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7;
 403         }
 404 }
 405
 406 /* Set registers for decoding stream buffer */
 407 static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 408                         int buf_addr, unsigned int start_num_byte,
 409                         unsigned int strm_size)
 410 {
 411         struct s5p_mfc_dev *dev = ctx->dev;
 412         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 413         struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
 414
 415         mfc_debug_enter();
 416         mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
 417                 "buf_size: 0x%08x (%d)\n",
 418                 ctx->inst_no, buf_addr, strm_size, strm_size);
 419         WRITEL(strm_size, mfc_regs->d_stream_data_size);
 420         WRITEL(buf_addr, mfc_regs->d_cpb_buffer_addr);
 421         WRITEL(buf_size->cpb, mfc_regs->d_cpb_buffer_size);
 422         WRITEL(start_num_byte, mfc_regs->d_cpb_buffer_offset);
 423
 424         mfc_debug_leave();
 425         return 0;
 426 }
 427
 428 /* Set decoding frame buffer */
 429 static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
 430 {
 431         unsigned int frame_size, i;
 432         unsigned int frame_size_ch, frame_size_mv;
 433         struct s5p_mfc_dev *dev = ctx->dev;
 434         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 435         size_t buf_addr1;
 436         int buf_size1;
 437         int align_gap;
 438
 439         buf_addr1 = ctx->bank1.dma;
 440         buf_size1 = ctx->bank1.size;
 441
 442         mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 443         mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
 444         mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
 445
 446         WRITEL(ctx->total_dpb_count, mfc_regs->d_num_dpb);
 447         WRITEL(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
 448         WRITEL(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
 449
 450         WRITEL(buf_addr1, mfc_regs->d_scratch_buffer_addr);
 451         WRITEL(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
 452
 453         if (IS_MFCV8(dev)) {
 454                 WRITEL(ctx->img_width,
 455                         mfc_regs->d_first_plane_dpb_stride_size);
 456                 WRITEL(ctx->img_width,
 457                         mfc_regs->d_second_plane_dpb_stride_size);
 458         }
 459
 460         buf_addr1 += ctx->scratch_buf_size;
 461         buf_size1 -= ctx->scratch_buf_size;
 462
 463         if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
 464                         ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
 465                 WRITEL(ctx->mv_size, mfc_regs->d_mv_buffer_size);
 466                 WRITEL(ctx->mv_count, mfc_regs->d_num_mv);
 467         }
 468
 469         frame_size = ctx->luma_size;
 470         frame_size_ch = ctx->chroma_size;
 471         frame_size_mv = ctx->mv_size;
 472         mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
 473                         frame_size, frame_size_ch, frame_size_mv);
 474
 475         for (i = 0; i < ctx->total_dpb_count; i++) {
 476                 /* Bank2 */
 477                 mfc_debug(2, "Luma %d: %x\n", i,
 478                                         ctx->dst_bufs[i].cookie.raw.luma);
 479                 WRITEL(ctx->dst_bufs[i].cookie.raw.luma,
 480                                 mfc_regs->d_first_plane_dpb + i * 4);
 481                 mfc_debug(2, "\tChroma %d: %x\n", i,
 482                                         ctx->dst_bufs[i].cookie.raw.chroma);
 483                 WRITEL(ctx->dst_bufs[i].cookie.raw.chroma,
 484                                 mfc_regs->d_second_plane_dpb + i * 4);
 485         }
 486         if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 487                         ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
 488                 for (i = 0; i < ctx->mv_count; i++) {
 489                         /* To test alignment */
 490                         align_gap = buf_addr1;
 491                         buf_addr1 = ALIGN(buf_addr1, 16);
 492                         align_gap = buf_addr1 - align_gap;
 493                         buf_size1 -= align_gap;
 494
 495                         mfc_debug(2, "\tBuf1: %x, size: %d\n",
 496                                         buf_addr1, buf_size1);
 497                         WRITEL(buf_addr1, mfc_regs->d_mv_buffer + i * 4);
 498                         buf_addr1 += frame_size_mv;
 499                         buf_size1 -= frame_size_mv;
 500                 }
 501         }
 502
 503         mfc_debug(2, "Buf1: %u, buf_size1: %d (frames %d)\n",
 504                         buf_addr1, buf_size1, ctx->total_dpb_count);
 505         if (buf_size1 < 0) {
 506                 mfc_debug(2, "Not enough memory has been allocated.\n");
 507                 return -ENOMEM;
 508         }
 509
 510         WRITEL(ctx->inst_no, mfc_regs->instance_id);
 511         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
 512                         S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 513
 514         mfc_debug(2, "After setting buffers.\n");
 515         return 0;
 516 }
 517
 518 /* Set registers for encoding stream buffer */
 519 static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
 520                 unsigned long addr, unsigned int size)
 521 {
 522         struct s5p_mfc_dev *dev = ctx->dev;
 523         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 524
 525         WRITEL(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */
 526         WRITEL(size, mfc_regs->e_stream_buffer_size);
 527
 528         mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n",
 529                   addr, size);
 530
 531         return 0;
 532 }
 533
 534 static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 535                 unsigned long y_addr, unsigned long c_addr)
 536 {
 537         struct s5p_mfc_dev *dev = ctx->dev;
 538         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 539
 540         WRITEL(y_addr, mfc_regs->e_source_first_plane_addr);
 541         WRITEL(c_addr, mfc_regs->e_source_second_plane_addr);
 542
 543         mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
 544         mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
 545 }
 546
 547 static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
 548                 unsigned long *y_addr, unsigned long *c_addr)
 549 {
 550         struct s5p_mfc_dev *dev = ctx->dev;
 551         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 552         unsigned long enc_recon_y_addr, enc_recon_c_addr;
 553
 554         *y_addr = READL(mfc_regs->e_encoded_source_first_plane_addr);
 555         *c_addr = READL(mfc_regs->e_encoded_source_second_plane_addr);
 556
 557         enc_recon_y_addr = READL(mfc_regs->e_recon_luma_dpb_addr);
 558         enc_recon_c_addr = READL(mfc_regs->e_recon_chroma_dpb_addr);
 559
 560         mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr);
 561         mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
 562 }
 563
 564 /* Set encoding ref & codec buffer */
 565 static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
 566 {
 567         struct s5p_mfc_dev *dev = ctx->dev;
 568         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 569         size_t buf_addr1;
 570         int i, buf_size1;
 571
 572         mfc_debug_enter();
 573
 574         buf_addr1 = ctx->bank1.dma;
 575         buf_size1 = ctx->bank1.size;
 576
 577         mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 578
 579         for (i = 0; i < ctx->pb_count; i++) {
 580                 WRITEL(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
 581                 buf_addr1 += ctx->luma_dpb_size;
 582                 WRITEL(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
 583                 buf_addr1 += ctx->chroma_dpb_size;
 584                 WRITEL(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
 585                 buf_addr1 += ctx->me_buffer_size;
 586                 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
 587                         ctx->me_buffer_size);
 588         }
 589
 590         WRITEL(buf_addr1, mfc_regs->e_scratch_buffer_addr);
 591         WRITEL(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
 592         buf_addr1 += ctx->scratch_buf_size;
 593         buf_size1 -= ctx->scratch_buf_size;
 594
 595         WRITEL(buf_addr1, mfc_regs->e_tmv_buffer0);
 596         buf_addr1 += ctx->tmv_buffer_size >> 1;
 597         WRITEL(buf_addr1, mfc_regs->e_tmv_buffer1);
 598         buf_addr1 += ctx->tmv_buffer_size >> 1;
 599         buf_size1 -= ctx->tmv_buffer_size;
 600
 601         mfc_debug(2, "Buf1: %u, buf_size1: %d (ref frames %d)\n",
 602                         buf_addr1, buf_size1, ctx->pb_count);
 603         if (buf_size1 < 0) {
 604                 mfc_debug(2, "Not enough memory has been allocated.\n");
 605                 return -ENOMEM;
 606         }
 607
 608         WRITEL(ctx->inst_no, mfc_regs->instance_id);
 609         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
 610                         S5P_FIMV_CH_INIT_BUFS_V6, NULL);
 611
 612         mfc_debug_leave();
 613
 614         return 0;
 615 }
 616
 617 static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
 618 {
 619         struct s5p_mfc_dev *dev = ctx->dev;
 620         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 621
 622         /* multi-slice control */
 623         /* multi-slice MB number or bit size */
 624         WRITEL(ctx->slice_mode, mfc_regs->e_mslice_mode);
 625         if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
 626                 WRITEL(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
 627         } else if (ctx->slice_mode ==
 628                         V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
 629                 WRITEL(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
 630         } else {
 631                 WRITEL(0x0, mfc_regs->e_mslice_size_mb);
 632                 WRITEL(0x0, mfc_regs->e_mslice_size_bits);
 633         }
 634
 635         return 0;
 636 }
 637
 638 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
 639 {
 640         struct s5p_mfc_dev *dev = ctx->dev;
 641         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 642         struct s5p_mfc_enc_params *p = &ctx->enc_params;
 643         unsigned int reg = 0;
 644
 645         mfc_debug_enter();
 646
 647         /* width */
 648         WRITEL(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
 649         /* height */
 650         WRITEL(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
 651
 652         /* cropped width */
 653         WRITEL(ctx->img_width, mfc_regs->e_cropped_frame_width);
 654         /* cropped height */
 655         WRITEL(ctx->img_height, mfc_regs->e_cropped_frame_height);
 656         /* cropped offset */
 657         WRITEL(0x0, mfc_regs->e_frame_crop_offset);
 658
 659         /* pictype : IDR period */
 660         reg = 0;
 661         reg |= p->gop_size & 0xFFFF;
 662         WRITEL(reg, mfc_regs->e_gop_config);
 663
 664         /* multi-slice control */
 665         /* multi-slice MB number or bit size */
 666         ctx->slice_mode = p->slice_mode;
 667         reg = 0;
 668         if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
 669                 reg |= (0x1 << 3);
 670                 WRITEL(reg, mfc_regs->e_enc_options);
 671                 ctx->slice_size.mb = p->slice_mb;
 672         } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
 673                 reg |= (0x1 << 3);
 674                 WRITEL(reg, mfc_regs->e_enc_options);
 675                 ctx->slice_size.bits = p->slice_bit;
 676         } else {
 677                 reg &= ~(0x1 << 3);
 678                 WRITEL(reg, mfc_regs->e_enc_options);
 679         }
 680
 681         s5p_mfc_set_slice_mode(ctx);
 682
 683         /* cyclic intra refresh */
 684         WRITEL(p->intra_refresh_mb, mfc_regs->e_ir_size);
 685         reg = READL(mfc_regs->e_enc_options);
 686         if (p->intra_refresh_mb == 0)
 687                 reg &= ~(0x1 << 4);
 688         else
 689                 reg |= (0x1 << 4);
 690         WRITEL(reg, mfc_regs->e_enc_options);
 691
 692         /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
 693         reg = READL(mfc_regs->e_enc_options);
 694         reg &= ~(0x1 << 9);
 695         WRITEL(reg, mfc_regs->e_enc_options);
 696
 697         /* memory structure cur. frame */
 698         if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
 699                 /* 0: Linear, 1: 2D tiled*/
 700                 reg = READL(mfc_regs->e_enc_options);
 701                 reg &= ~(0x1 << 7);
 702                 WRITEL(reg, mfc_regs->e_enc_options);
 703                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 704                 WRITEL(0x0, mfc_regs->pixel_format);
 705         } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
 706                 /* 0: Linear, 1: 2D tiled*/
 707                 reg = READL(mfc_regs->e_enc_options);
 708                 reg &= ~(0x1 << 7);
 709                 WRITEL(reg, mfc_regs->e_enc_options);
 710                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 711                 WRITEL(0x1, mfc_regs->pixel_format);
 712         } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
 713                 /* 0: Linear, 1: 2D tiled*/
 714                 reg = READL(mfc_regs->e_enc_options);
 715                 reg |= (0x1 << 7);
 716                 WRITEL(reg, mfc_regs->e_enc_options);
 717                 /* 0: NV12(CbCr), 1: NV21(CrCb) */
 718                 WRITEL(0x0, mfc_regs->pixel_format);
 719         }
 720
 721         /* memory structure recon. frame */
 722         /* 0: Linear, 1: 2D tiled */
 723         reg = READL(mfc_regs->e_enc_options);
 724         reg |= (0x1 << 8);
 725         WRITEL(reg, mfc_regs->e_enc_options);
 726
 727         /* padding control & value */
 728         WRITEL(0x0, mfc_regs->e_padding_ctrl);
 729         if (p->pad) {
 730                 reg = 0;
 731                 /** enable */
 732                 reg |= (1 << 31);
 733                 /** cr value */
 734                 reg |= ((p->pad_cr & 0xFF) << 16);
 735                 /** cb value */
 736                 reg |= ((p->pad_cb & 0xFF) << 8);
 737                 /** y value */
 738                 reg |= p->pad_luma & 0xFF;
 739                 WRITEL(reg, mfc_regs->e_padding_ctrl);
 740         }
 741
 742         /* rate control config. */
 743         reg = 0;
 744         /* frame-level rate control */
 745         reg |= ((p->rc_frame & 0x1) << 9);
 746         WRITEL(reg, mfc_regs->e_rc_config);
 747
 748         /* bit rate */
 749         if (p->rc_frame)
 750                 WRITEL(p->rc_bitrate,
 751                         mfc_regs->e_rc_bit_rate);
 752         else
 753                 WRITEL(1, mfc_regs->e_rc_bit_rate);
 754
 755         /* reaction coefficient */
 756         if (p->rc_frame) {
 757                 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
 758                         WRITEL(1, mfc_regs->e_rc_mode);
 759                 else                                      /* loose CBR */
 760                         WRITEL(2, mfc_regs->e_rc_mode);
 761         }
 762
 763         /* seq header ctrl */
 764         reg = READL(mfc_regs->e_enc_options);
 765         reg &= ~(0x1 << 2);
 766         reg |= ((p->seq_hdr_mode & 0x1) << 2);
 767
 768         /* frame skip mode */
 769         reg &= ~(0x3);
 770         reg |= (p->frame_skip_mode & 0x3);
 771         WRITEL(reg, mfc_regs->e_enc_options);
 772
 773         /* 'DROP_CONTROL_ENABLE', disable */
 774         reg = READL(mfc_regs->e_rc_config);
 775         reg &= ~(0x1 << 10);
 776         WRITEL(reg, mfc_regs->e_rc_config);
 777
 778         /* setting for MV range [16, 256] */
 779         reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
 780         WRITEL(reg, mfc_regs->e_mv_hor_range);
 781
 782         reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
 783         WRITEL(reg, mfc_regs->e_mv_ver_range);
 784
 785         WRITEL(0x0, mfc_regs->e_frame_insertion);
 786         WRITEL(0x0, mfc_regs->e_roi_buffer_addr);
 787         WRITEL(0x0, mfc_regs->e_param_change);
 788         WRITEL(0x0, mfc_regs->e_rc_roi_ctrl);
 789         WRITEL(0x0, mfc_regs->e_picture_tag);
 790
 791         WRITEL(0x0, mfc_regs->e_bit_count_enable);
 792         WRITEL(0x0, mfc_regs->e_max_bit_count);
 793         WRITEL(0x0, mfc_regs->e_min_bit_count);
 794
 795         WRITEL(0x0, mfc_regs->e_metadata_buffer_addr);
 796         WRITEL(0x0, mfc_regs->e_metadata_buffer_size);
 797
 798         mfc_debug_leave();
 799
 800         return 0;
 801 }
 802
 803 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
 804 {
 805         struct s5p_mfc_dev *dev = ctx->dev;
 806         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
 807         struct s5p_mfc_enc_params *p = &ctx->enc_params;
 808         struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
 809         unsigned int reg = 0;
 810         int i;
 811
 812         mfc_debug_enter();
 813
 814         s5p_mfc_set_enc_params(ctx);
 815
 816         /* pictype : number of B */
 817         reg = READL(mfc_regs->e_gop_config);
 818         reg &= ~(0x3 << 16);
 819         reg |= ((p->num_b_frame & 0x3) << 16);
 820         WRITEL(reg, mfc_regs->e_gop_config);
 821
 822         /* profile & level */
 823         reg = 0;
 824         /** level */
 825         reg |= ((p_h264->level & 0xFF) << 8);
 826         /** profile - 0 ~ 3 */
 827         reg |= p_h264->profile & 0x3F;
 828         WRITEL(reg, mfc_regs->e_picture_profile);
 829
 830         /* rate control config. */
 831         reg = READL(mfc_regs->e_rc_config);
 832         /** macroblock level rate control */
 833         reg &= ~(0x1 << 8);
 834         reg |= ((p->rc_mb & 0x1) << 8);
 835         WRITEL(reg, mfc_regs->e_rc_config);
 836
 837         /** frame QP */
 838         reg &= ~(0x3F);
 839         reg |= p_h264->rc_frame_qp & 0x3F;
 840         WRITEL(reg, mfc_regs->e_rc_config);
 841
 842         /* max & min value of QP */
 843         reg = 0;
 844         /** max QP */
 845         reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
 846         /** min QP */
 847         reg |= p_h264->rc_min_qp & 0x3F;
 848         WRITEL(reg, mfc_regs->e_rc_qp_bound);
 849
 850         /* other QPs */
 851         WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
 852         if (!p->rc_frame && !p->rc_mb) {
 853                 reg = 0;
 854                 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
 855                 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
 856                 reg |= p_h264->rc_frame_qp & 0x3F;
 857                 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
 858         }
 859
 860         /* frame rate */
 861         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
 862                 reg = 0;
 863                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
 864                 reg |= p->rc_framerate_denom & 0xFFFF;
 865                 WRITEL(reg, mfc_regs->e_rc_frame_rate);
 866         }
 867
 868         /* vbv buffer size */
 869         if (p->frame_skip_mode ==
 870                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
 871                 WRITEL(p_h264->cpb_size & 0xFFFF,
 872                                 mfc_regs->e_vbv_buffer_size);
 873
 874                 if (p->rc_frame)
 875                         WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
 876         }
 877
 878         /* interlace */
 879         reg = 0;
 880         reg |= ((p_h264->interlace & 0x1) << 3);
 881         WRITEL(reg, mfc_regs->e_h264_options);
 882
 883         /* height */
 884         if (p_h264->interlace) {
 885                 WRITEL(ctx->img_height >> 1,
 886                                 mfc_regs->e_frame_height); /* 32 align */
 887                 /* cropped height */
 888                 WRITEL(ctx->img_height >> 1,
 889                                 mfc_regs->e_cropped_frame_height);
 890         }
 891
 892         /* loop filter ctrl */
 893         reg = READL(mfc_regs->e_h264_options);
 894         reg &= ~(0x3 << 1);
 895         reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
 896         WRITEL(reg, mfc_regs->e_h264_options);
 897
 898         /* loopfilter alpha offset */
 899         if (p_h264->loop_filter_alpha < 0) {
 900                 reg = 0x10;
 901                 reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
 902         } else {
 903                 reg = 0x00;
 904                 reg |= (p_h264->loop_filter_alpha & 0xF);
 905         }
 906         WRITEL(reg, mfc_regs->e_h264_lf_alpha_offset);
 907
 908         /* loopfilter beta offset */
 909         if (p_h264->loop_filter_beta < 0) {
 910                 reg = 0x10;
 911                 reg |= (0xFF - p_h264->loop_filter_beta) + 1;
 912         } else {
 913                 reg = 0x00;
 914                 reg |= (p_h264->loop_filter_beta & 0xF);
 915         }
 916         WRITEL(reg, mfc_regs->e_h264_lf_beta_offset);
 917
 918         /* entropy coding mode */
 919         reg = READL(mfc_regs->e_h264_options);
 920         reg &= ~(0x1);
 921         reg |= p_h264->entropy_mode & 0x1;
 922         WRITEL(reg, mfc_regs->e_h264_options);
 923
 924         /* number of ref. picture */
 925         reg = READL(mfc_regs->e_h264_options);
 926         reg &= ~(0x1 << 7);
 927         reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
 928         WRITEL(reg, mfc_regs->e_h264_options);
 929
 930         /* 8x8 transform enable */
 931         reg = READL(mfc_regs->e_h264_options);
 932         reg &= ~(0x3 << 12);
 933         reg |= ((p_h264->_8x8_transform & 0x3) << 12);
 934         WRITEL(reg, mfc_regs->e_h264_options);
 935
 936         /* macroblock adaptive scaling features */
 937         WRITEL(0x0, mfc_regs->e_mb_rc_config);
 938         if (p->rc_mb) {
 939                 reg = 0;
 940                 /** dark region */
 941                 reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
 942                 /** smooth region */
 943                 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
 944                 /** static region */
 945                 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
 946                 /** high activity region */
 947                 reg |= p_h264->rc_mb_activity & 0x1;
 948                 WRITEL(reg, mfc_regs->e_mb_rc_config);
 949         }
 950
 951         /* aspect ratio VUI */
 952         READL(mfc_regs->e_h264_options);
 953         reg &= ~(0x1 << 5);
 954         reg |= ((p_h264->vui_sar & 0x1) << 5);
 955         WRITEL(reg, mfc_regs->e_h264_options);
 956
 957         WRITEL(0x0, mfc_regs->e_aspect_ratio);
 958         WRITEL(0x0, mfc_regs->e_extended_sar);
 959         if (p_h264->vui_sar) {
 960                 /* aspect ration IDC */
 961                 reg = 0;
 962                 reg |= p_h264->vui_sar_idc & 0xFF;
 963                 WRITEL(reg, mfc_regs->e_aspect_ratio);
 964                 if (p_h264->vui_sar_idc == 0xFF) {
 965                         /* extended SAR */
 966                         reg = 0;
 967                         reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
 968                         reg |= p_h264->vui_ext_sar_height & 0xFFFF;
 969                         WRITEL(reg, mfc_regs->e_extended_sar);
 970                 }
 971         }
 972
 973         /* intra picture period for H.264 open GOP */
 974         /* control */
 975         READL(mfc_regs->e_h264_options);
 976         reg &= ~(0x1 << 4);
 977         reg |= ((p_h264->open_gop & 0x1) << 4);
 978         WRITEL(reg, mfc_regs->e_h264_options);
 979
 980         /* value */
 981         WRITEL(0x0, mfc_regs->e_h264_i_period);
 982         if (p_h264->open_gop) {
 983                 reg = 0;
 984                 reg |= p_h264->open_gop_size & 0xFFFF;
 985                 WRITEL(reg, mfc_regs->e_h264_i_period);
 986         }
 987
 988         /* 'WEIGHTED_BI_PREDICTION' for B is disable */
 989         READL(mfc_regs->e_h264_options);
 990         reg &= ~(0x3 << 9);
 991         WRITEL(reg, mfc_regs->e_h264_options);
 992
 993         /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
 994         READL(mfc_regs->e_h264_options);
 995         reg &= ~(0x1 << 14);
 996         WRITEL(reg, mfc_regs->e_h264_options);
 997
 998         /* ASO */
 999         READL(mfc_regs->e_h264_options);
1000         reg &= ~(0x1 << 6);
1001         reg |= ((p_h264->aso & 0x1) << 6);
1002         WRITEL(reg, mfc_regs->e_h264_options);
1003
1004         /* hier qp enable */
1005         READL(mfc_regs->e_h264_options);
1006         reg &= ~(0x1 << 8);
1007         reg |= ((p_h264->open_gop & 0x1) << 8);
1008         WRITEL(reg, mfc_regs->e_h264_options);
1009         reg = 0;
1010         if (p_h264->hier_qp && p_h264->hier_qp_layer) {
1011                 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
1012                 reg |= p_h264->hier_qp_layer & 0x7;
1013                 WRITEL(reg, mfc_regs->e_h264_num_t_layer);
1014                 /* QP value for each layer */
1015                 for (i = 0; i < p_h264->hier_qp_layer &&
1016                                 i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) {
1017                         WRITEL(p_h264->hier_qp_layer_qp[i],
1018                                 mfc_regs->e_h264_hierarchical_qp_layer0
1019                                 + i * 4);
1020                 }
1021         }
1022         /* number of coding layer should be zero when hierarchical is disable */
1023         WRITEL(reg, mfc_regs->e_h264_num_t_layer);
1024
1025         /* frame packing SEI generation */
1026         READL(mfc_regs->e_h264_options);
1027         reg &= ~(0x1 << 25);
1028         reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
1029         WRITEL(reg, mfc_regs->e_h264_options);
1030         if (p_h264->sei_frame_packing) {
1031                 reg = 0;
1032                 /** current frame0 flag */
1033                 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
1034                 /** arrangement type */
1035                 reg |= p_h264->sei_fp_arrangement_type & 0x3;
1036                 WRITEL(reg, mfc_regs->e_h264_frame_packing_sei_info);
1037         }
1038
1039         if (p_h264->fmo) {
1040                 switch (p_h264->fmo_map_type) {
1041                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
1042                         if (p_h264->fmo_slice_grp > 4)
1043                                 p_h264->fmo_slice_grp = 4;
1044                         for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
1045                                 WRITEL(p_h264->fmo_run_len[i] - 1,
1046                                         mfc_regs->e_h264_fmo_run_length_minus1_0
1047                                         + i * 4);
1048                         break;
1049                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
1050                         if (p_h264->fmo_slice_grp > 4)
1051                                 p_h264->fmo_slice_grp = 4;
1052                         break;
1053                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
1054                 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
1055                         if (p_h264->fmo_slice_grp > 2)
1056                                 p_h264->fmo_slice_grp = 2;
1057                         WRITEL(p_h264->fmo_chg_dir & 0x1,
1058                                 mfc_regs->e_h264_fmo_slice_grp_change_dir);
1059                         /* the valid range is 0 ~ number of macroblocks -1 */
1060                         WRITEL(p_h264->fmo_chg_rate,
1061                         mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1);
1062                         break;
1063                 default:
1064                         mfc_err("Unsupported map type for FMO: %d\n",
1065                                         p_h264->fmo_map_type);
1066                         p_h264->fmo_map_type = 0;
1067                         p_h264->fmo_slice_grp = 1;
1068                         break;
1069                 }
1070
1071                 WRITEL(p_h264->fmo_map_type,
1072                                 mfc_regs->e_h264_fmo_slice_grp_map_type);
1073                 WRITEL(p_h264->fmo_slice_grp - 1,
1074                                 mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1075         } else {
1076                 WRITEL(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1077         }
1078
1079         mfc_debug_leave();
1080
1081         return 0;
1082 }
1083
1084 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1085 {
1086         struct s5p_mfc_dev *dev = ctx->dev;
1087         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1088         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1089         struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1090         unsigned int reg = 0;
1091
1092         mfc_debug_enter();
1093
1094         s5p_mfc_set_enc_params(ctx);
1095
1096         /* pictype : number of B */
1097         reg = READL(mfc_regs->e_gop_config);
1098         reg &= ~(0x3 << 16);
1099         reg |= ((p->num_b_frame & 0x3) << 16);
1100         WRITEL(reg, mfc_regs->e_gop_config);
1101
1102         /* profile & level */
1103         reg = 0;
1104         /** level */
1105         reg |= ((p_mpeg4->level & 0xFF) << 8);
1106         /** profile - 0 ~ 1 */
1107         reg |= p_mpeg4->profile & 0x3F;
1108         WRITEL(reg, mfc_regs->e_picture_profile);
1109
1110         /* rate control config. */
1111         reg = READL(mfc_regs->e_rc_config);
1112         /** macroblock level rate control */
1113         reg &= ~(0x1 << 8);
1114         reg |= ((p->rc_mb & 0x1) << 8);
1115         WRITEL(reg, mfc_regs->e_rc_config);
1116
1117         /** frame QP */
1118         reg &= ~(0x3F);
1119         reg |= p_mpeg4->rc_frame_qp & 0x3F;
1120         WRITEL(reg, mfc_regs->e_rc_config);
1121
1122         /* max & min value of QP */
1123         reg = 0;
1124         /** max QP */
1125         reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1126         /** min QP */
1127         reg |= p_mpeg4->rc_min_qp & 0x3F;
1128         WRITEL(reg, mfc_regs->e_rc_qp_bound);
1129
1130         /* other QPs */
1131         WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
1132         if (!p->rc_frame && !p->rc_mb) {
1133                 reg = 0;
1134                 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1135                 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1136                 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1137                 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
1138         }
1139
1140         /* frame rate */
1141         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1142                 reg = 0;
1143                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1144                 reg |= p->rc_framerate_denom & 0xFFFF;
1145                 WRITEL(reg, mfc_regs->e_rc_frame_rate);
1146         }
1147
1148         /* vbv buffer size */
1149         if (p->frame_skip_mode ==
1150                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1151                 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1152
1153                 if (p->rc_frame)
1154                         WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1155         }
1156
1157         /* Disable HEC */
1158         WRITEL(0x0, mfc_regs->e_mpeg4_options);
1159         WRITEL(0x0, mfc_regs->e_mpeg4_hec_period);
1160
1161         mfc_debug_leave();
1162
1163         return 0;
1164 }
1165
1166 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1167 {
1168         struct s5p_mfc_dev *dev = ctx->dev;
1169         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1170         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1171         struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1172         unsigned int reg = 0;
1173
1174         mfc_debug_enter();
1175
1176         s5p_mfc_set_enc_params(ctx);
1177
1178         /* profile & level */
1179         reg = 0;
1180         /** profile */
1181         reg |= (0x1 << 4);
1182         WRITEL(reg, mfc_regs->e_picture_profile);
1183
1184         /* rate control config. */
1185         reg = READL(mfc_regs->e_rc_config);
1186         /** macroblock level rate control */
1187         reg &= ~(0x1 << 8);
1188         reg |= ((p->rc_mb & 0x1) << 8);
1189         WRITEL(reg, mfc_regs->e_rc_config);
1190
1191         /** frame QP */
1192         reg &= ~(0x3F);
1193         reg |= p_h263->rc_frame_qp & 0x3F;
1194         WRITEL(reg, mfc_regs->e_rc_config);
1195
1196         /* max & min value of QP */
1197         reg = 0;
1198         /** max QP */
1199         reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1200         /** min QP */
1201         reg |= p_h263->rc_min_qp & 0x3F;
1202         WRITEL(reg, mfc_regs->e_rc_qp_bound);
1203
1204         /* other QPs */
1205         WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
1206         if (!p->rc_frame && !p->rc_mb) {
1207                 reg = 0;
1208                 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1209                 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1210                 reg |= p_h263->rc_frame_qp & 0x3F;
1211                 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
1212         }
1213
1214         /* frame rate */
1215         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1216                 reg = 0;
1217                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1218                 reg |= p->rc_framerate_denom & 0xFFFF;
1219                 WRITEL(reg, mfc_regs->e_rc_frame_rate);
1220         }
1221
1222         /* vbv buffer size */
1223         if (p->frame_skip_mode ==
1224                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1225                 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1226
1227                 if (p->rc_frame)
1228                         WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1229         }
1230
1231         mfc_debug_leave();
1232
1233         return 0;
1234 }
1235
1236 static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1237 {
1238         struct s5p_mfc_dev *dev = ctx->dev;
1239         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1240         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1241         struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;
1242         unsigned int reg = 0;
1243         unsigned int val = 0;
1244
1245         mfc_debug_enter();
1246
1247         s5p_mfc_set_enc_params(ctx);
1248
1249         /* pictype : number of B */
1250         reg = READL(mfc_regs->e_gop_config);
1251         reg &= ~(0x3 << 16);
1252         reg |= ((p->num_b_frame & 0x3) << 16);
1253         WRITEL(reg, mfc_regs->e_gop_config);
1254
1255         /* profile - 0 ~ 3 */
1256         reg = p_vp8->profile & 0x3;
1257         WRITEL(reg, mfc_regs->e_picture_profile);
1258
1259         /* rate control config. */
1260         reg = READL(mfc_regs->e_rc_config);
1261         /** macroblock level rate control */
1262         reg &= ~(0x1 << 8);
1263         reg |= ((p->rc_mb & 0x1) << 8);
1264         WRITEL(reg, mfc_regs->e_rc_config);
1265
1266         /* frame rate */
1267         if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1268                 reg = 0;
1269                 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1270                 reg |= p->rc_framerate_denom & 0xFFFF;
1271                 WRITEL(reg, mfc_regs->e_rc_frame_rate);
1272         }
1273
1274         /* frame QP */
1275         reg &= ~(0x7F);
1276         reg |= p_vp8->rc_frame_qp & 0x7F;
1277         WRITEL(reg, mfc_regs->e_rc_config);
1278
1279         /* other QPs */
1280         WRITEL(0x0, mfc_regs->e_fixed_picture_qp);
1281         if (!p->rc_frame && !p->rc_mb) {
1282                 reg = 0;
1283                 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);
1284                 reg |= p_vp8->rc_frame_qp & 0x7F;
1285                 WRITEL(reg, mfc_regs->e_fixed_picture_qp);
1286         }
1287
1288         /* max QP */
1289         reg = ((p_vp8->rc_max_qp & 0x7F) << 8);
1290         /* min QP */
1291         reg |= p_vp8->rc_min_qp & 0x7F;
1292         WRITEL(reg, mfc_regs->e_rc_qp_bound);
1293
1294         /* vbv buffer size */
1295         if (p->frame_skip_mode ==
1296                         V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1297                 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1298
1299                 if (p->rc_frame)
1300                         WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1301         }
1302
1303         /* VP8 specific params */
1304         reg = 0;
1305         reg |= (p_vp8->imd_4x4 & 0x1) << 10;
1306         switch (p_vp8->num_partitions) {
1307         case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION:
1308                 val = 0;
1309                 break;
1310         case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS:
1311                 val = 2;
1312                 break;
1313         case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS:
1314                 val = 4;
1315                 break;
1316         case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS:
1317                 val = 8;
1318                 break;
1319         }
1320         reg |= (val & 0xF) << 3;
1321         reg |= (p_vp8->num_ref & 0x2);
1322         WRITEL(reg, mfc_regs->e_vp8_options);
1323
1324         mfc_debug_leave();
1325
1326         return 0;
1327 }
1328
1329 /* Initialize decoding */
1330 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1331 {
1332         struct s5p_mfc_dev *dev = ctx->dev;
1333         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1334         unsigned int reg = 0;
1335         int fmo_aso_ctrl = 0;
1336
1337         mfc_debug_enter();
1338         mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1339                         S5P_FIMV_CH_SEQ_HEADER_V6);
1340         mfc_debug(2, "BUFs: %08x %08x %08x\n",
1341                   READL(mfc_regs->d_cpb_buffer_addr),
1342                   READL(mfc_regs->d_cpb_buffer_addr),
1343                   READL(mfc_regs->d_cpb_buffer_addr));
1344
1345         /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1346         reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1347
1348         /* When user sets desplay_delay to 0,
1349          * It works as "display_delay enable" and delay set to 0.
1350          * If user wants display_delay disable, It should be
1351          * set to negative value. */
1352         if (ctx->display_delay >= 0) {
1353                 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1354                 WRITEL(ctx->display_delay, mfc_regs->d_display_delay);
1355         }
1356
1357         if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) {
1358                 WRITEL(reg, mfc_regs->d_dec_options);
1359                 reg = 0;
1360         }
1361
1362         /* Setup loop filter, for decoding this is only valid for MPEG4 */
1363         if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1364                 mfc_debug(2, "Set loop filter to: %d\n",
1365                                 ctx->loop_filter_mpeg4);
1366                 reg |= (ctx->loop_filter_mpeg4 <<
1367                                 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1368         }
1369         if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1370                 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1371
1372         if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev))
1373                 WRITEL(reg, mfc_regs->d_init_buffer_options);
1374         else
1375                 WRITEL(reg, mfc_regs->d_dec_options);
1376
1377         /* 0: NV12(CbCr), 1: NV21(CrCb) */
1378         if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1379                 WRITEL(0x1, mfc_regs->pixel_format);
1380         else
1381                 WRITEL(0x0, mfc_regs->pixel_format);
1382
1383
1384         /* sei parse */
1385         WRITEL(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
1386
1387         WRITEL(ctx->inst_no, mfc_regs->instance_id);
1388         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1389                         S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1390
1391         mfc_debug_leave();
1392         return 0;
1393 }
1394
1395 static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1396 {
1397         struct s5p_mfc_dev *dev = ctx->dev;
1398         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1399
1400         if (flush) {
1401                 dev->curr_ctx = ctx->num;
1402                 s5p_mfc_clean_ctx_int_flags(ctx);
1403                 WRITEL(ctx->inst_no, mfc_regs->instance_id);
1404                 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1405                                 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1406         }
1407 }
1408
1409 /* Decode a single frame */
1410 static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1411                         enum s5p_mfc_decode_arg last_frame)
1412 {
1413         struct s5p_mfc_dev *dev = ctx->dev;
1414         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1415
1416         WRITEL(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
1417         WRITEL(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
1418
1419         WRITEL(ctx->inst_no, mfc_regs->instance_id);
1420         /* Issue different commands to instance basing on whether it
1421          * is the last frame or not. */
1422         switch (last_frame) {
1423         case 0:
1424                 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1425                                 S5P_FIMV_CH_FRAME_START_V6, NULL);
1426                 break;
1427         case 1:
1428                 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1429                                 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1430                 break;
1431         default:
1432                 mfc_err("Unsupported last frame arg.\n");
1433                 return -EINVAL;
1434         }
1435
1436         mfc_debug(2, "Decoding a usual frame.\n");
1437         return 0;
1438 }
1439
1440 static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1441 {
1442         struct s5p_mfc_dev *dev = ctx->dev;
1443         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1444
1445         if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1446                 s5p_mfc_set_enc_params_h264(ctx);
1447         else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1448                 s5p_mfc_set_enc_params_mpeg4(ctx);
1449         else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1450                 s5p_mfc_set_enc_params_h263(ctx);
1451         else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
1452                 s5p_mfc_set_enc_params_vp8(ctx);
1453         else {
1454                 mfc_err("Unknown codec for encoding (%x).\n",
1455                         ctx->codec_mode);
1456                 return -EINVAL;
1457         }
1458
1459         /* Set stride lengths for v7 & above */
1460         if (IS_MFCV7_PLUS(dev)) {
1461                 WRITEL(ctx->img_width, mfc_regs->e_source_first_plane_stride);
1462                 WRITEL(ctx->img_width, mfc_regs->e_source_second_plane_stride);
1463         }
1464
1465         WRITEL(ctx->inst_no, mfc_regs->instance_id);
1466         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1467                         S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1468
1469         return 0;
1470 }
1471
1472 static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1473 {
1474         struct s5p_mfc_dev *dev = ctx->dev;
1475         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1476         struct s5p_mfc_enc_params *p = &ctx->enc_params;
1477         struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1478         int i;
1479
1480         if (p_h264->aso) {
1481                 for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) {
1482                         WRITEL(p_h264->aso_slice_order[i],
1483                                 mfc_regs->e_h264_aso_slice_order_0 + i * 4);
1484                 }
1485         }
1486         return 0;
1487 }
1488
1489 /* Encode a single frame */
1490 static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1491 {
1492         struct s5p_mfc_dev *dev = ctx->dev;
1493         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1494
1495         mfc_debug(2, "++\n");
1496
1497         /* memory structure cur. frame */
1498
1499         if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1500                 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1501
1502         s5p_mfc_set_slice_mode(ctx);
1503
1504         WRITEL(ctx->inst_no, mfc_regs->instance_id);
1505         s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1506                         S5P_FIMV_CH_FRAME_START_V6, NULL);
1507
1508         mfc_debug(2, "--\n");
1509
1510         return 0;
1511 }
1512
1513 static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
1514 {
1515         unsigned long flags;
1516         int new_ctx;
1517         int cnt;
1518
1519         spin_lock_irqsave(&dev->condlock, flags);
1520         mfc_debug(2, "Previous context: %d (bits %08lx)\n", dev->curr_ctx,
1521                                                         dev->ctx_work_bits);
1522         new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
1523         cnt = 0;
1524         while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
1525                 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
1526                 cnt++;
1527                 if (cnt > MFC_NUM_CONTEXTS) {
1528                         /* No contexts to run */
1529                         spin_unlock_irqrestore(&dev->condlock, flags);
1530                         return -EAGAIN;
1531                 }
1532         }
1533         spin_unlock_irqrestore(&dev->condlock, flags);
1534         return new_ctx;
1535 }
1536
1537 static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1538 {
1539         struct s5p_mfc_dev *dev = ctx->dev;
1540         struct s5p_mfc_buf *temp_vb;
1541         unsigned long flags;
1542
1543         spin_lock_irqsave(&dev->irqlock, flags);
1544
1545         /* Frames are being decoded */
1546         if (list_empty(&ctx->src_queue)) {
1547                 mfc_debug(2, "No src buffers.\n");
1548                 spin_unlock_irqrestore(&dev->irqlock, flags);
1549                 return;
1550         }
1551         /* Get the next source buffer */
1552         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1553         temp_vb->flags |= MFC_BUF_FLAG_USED;
1554         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1555                         vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, 0);
1556         spin_unlock_irqrestore(&dev->irqlock, flags);
1557
1558         dev->curr_ctx = ctx->num;
1559         s5p_mfc_clean_ctx_int_flags(ctx);
1560         s5p_mfc_decode_one_frame_v6(ctx, 1);
1561 }
1562
1563 static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1564 {
1565         struct s5p_mfc_dev *dev = ctx->dev;
1566         struct s5p_mfc_buf *temp_vb;
1567         unsigned long flags;
1568         int last_frame = 0;
1569
1570         if (ctx->state == MFCINST_FINISHING) {
1571                 last_frame = MFC_DEC_LAST_FRAME;
1572                 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1573                 dev->curr_ctx = ctx->num;
1574                 s5p_mfc_clean_ctx_int_flags(ctx);
1575                 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1576                 return 0;
1577         }
1578
1579         spin_lock_irqsave(&dev->irqlock, flags);
1580         /* Frames are being decoded */
1581         if (list_empty(&ctx->src_queue)) {
1582                 mfc_debug(2, "No src buffers.\n");
1583                 spin_unlock_irqrestore(&dev->irqlock, flags);
1584                 return -EAGAIN;
1585         }
1586         /* Get the next source buffer */
1587         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1588         temp_vb->flags |= MFC_BUF_FLAG_USED;
1589         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1590                 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0),
1591                         ctx->consumed_stream,
1592                         temp_vb->b->v4l2_planes[0].bytesused);
1593         spin_unlock_irqrestore(&dev->irqlock, flags);
1594
1595         dev->curr_ctx = ctx->num;
1596         s5p_mfc_clean_ctx_int_flags(ctx);
1597         if (temp_vb->b->v4l2_planes[0].bytesused == 0) {
1598                 last_frame = 1;
1599                 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1600                 ctx->state = MFCINST_FINISHING;
1601         }
1602         s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1603
1604         return 0;
1605 }
1606
1607 static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1608 {
1609         struct s5p_mfc_dev *dev = ctx->dev;
1610         unsigned long flags;
1611         struct s5p_mfc_buf *dst_mb;
1612         struct s5p_mfc_buf *src_mb;
1613         unsigned long src_y_addr, src_c_addr, dst_addr;
1614         /*
1615         unsigned int src_y_size, src_c_size;
1616         */
1617         unsigned int dst_size;
1618
1619         spin_lock_irqsave(&dev->irqlock, flags);
1620
1621         if (list_empty(&ctx->src_queue)) {
1622                 mfc_debug(2, "no src buffers.\n");
1623                 spin_unlock_irqrestore(&dev->irqlock, flags);
1624                 return -EAGAIN;
1625         }
1626
1627         if (list_empty(&ctx->dst_queue)) {
1628                 mfc_debug(2, "no dst buffers.\n");
1629                 spin_unlock_irqrestore(&dev->irqlock, flags);
1630                 return -EAGAIN;
1631         }
1632
1633         src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1634         src_mb->flags |= MFC_BUF_FLAG_USED;
1635         src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
1636         src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
1637
1638         mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
1639         mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
1640
1641         s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
1642
1643         dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1644         dst_mb->flags |= MFC_BUF_FLAG_USED;
1645         dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1646         dst_size = vb2_plane_size(dst_mb->b, 0);
1647
1648         s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1649
1650         spin_unlock_irqrestore(&dev->irqlock, flags);
1651
1652         dev->curr_ctx = ctx->num;
1653         s5p_mfc_clean_ctx_int_flags(ctx);
1654         s5p_mfc_encode_one_frame_v6(ctx);
1655
1656         return 0;
1657 }
1658
1659 static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1660 {
1661         struct s5p_mfc_dev *dev = ctx->dev;
1662         unsigned long flags;
1663         struct s5p_mfc_buf *temp_vb;
1664
1665         /* Initializing decoding - parsing header */
1666         spin_lock_irqsave(&dev->irqlock, flags);
1667         mfc_debug(2, "Preparing to init decoding.\n");
1668         temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1669         mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused);
1670         s5p_mfc_set_dec_stream_buffer_v6(ctx,
1671                 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0,
1672                         temp_vb->b->v4l2_planes[0].bytesused);
1673         spin_unlock_irqrestore(&dev->irqlock, flags);
1674         dev->curr_ctx = ctx->num;
1675         s5p_mfc_clean_ctx_int_flags(ctx);
1676         s5p_mfc_init_decode_v6(ctx);
1677 }
1678
1679 static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1680 {
1681         struct s5p_mfc_dev *dev = ctx->dev;
1682         unsigned long flags;
1683         struct s5p_mfc_buf *dst_mb;
1684         unsigned long dst_addr;
1685         unsigned int dst_size;
1686
1687         spin_lock_irqsave(&dev->irqlock, flags);
1688
1689         dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1690         dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1691         dst_size = vb2_plane_size(dst_mb->b, 0);
1692         s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1693         spin_unlock_irqrestore(&dev->irqlock, flags);
1694         dev->curr_ctx = ctx->num;
1695         s5p_mfc_clean_ctx_int_flags(ctx);
1696         s5p_mfc_init_encode_v6(ctx);
1697 }
1698
1699 static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1700 {
1701         struct s5p_mfc_dev *dev = ctx->dev;
1702         int ret;
1703         /* Header was parsed now start processing
1704          * First set the output frame buffers
1705          * s5p_mfc_alloc_dec_buffers(ctx); */
1706
1707         if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1708                 mfc_err("It seems that not all destionation buffers were\n"
1709                         "mmaped.MFC requires that all destination are mmaped\n"
1710                         "before starting processing.\n");
1711                 return -EAGAIN;
1712         }
1713
1714         dev->curr_ctx = ctx->num;
1715         s5p_mfc_clean_ctx_int_flags(ctx);
1716         ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
1717         if (ret) {
1718                 mfc_err("Failed to alloc frame mem.\n");
1719                 ctx->state = MFCINST_ERROR;
1720         }
1721         return ret;
1722 }
1723
1724 static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
1725 {
1726         struct s5p_mfc_dev *dev = ctx->dev;
1727         int ret;
1728
1729         dev->curr_ctx = ctx->num;
1730         s5p_mfc_clean_ctx_int_flags(ctx);
1731         ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
1732         if (ret) {
1733                 mfc_err("Failed to alloc frame mem.\n");
1734                 ctx->state = MFCINST_ERROR;
1735         }
1736         return ret;
1737 }
1738
1739 /* Try running an operation on hardware */
1740 static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
1741 {
1742         struct s5p_mfc_ctx *ctx;
1743         int new_ctx;
1744         unsigned int ret = 0;
1745
1746         mfc_debug(1, "Try run dev: %p\n", dev);
1747
1748         /* Check whether hardware is not running */
1749         if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1750                 /* This is perfectly ok, the scheduled ctx should wait */
1751                 mfc_debug(1, "Couldn't lock HW.\n");
1752                 return;
1753         }
1754
1755         /* Choose the context to run */
1756         new_ctx = s5p_mfc_get_new_ctx(dev);
1757         if (new_ctx < 0) {
1758                 /* No contexts to run */
1759                 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1760                         mfc_err("Failed to unlock hardware.\n");
1761                         return;
1762                 }
1763
1764                 mfc_debug(1, "No ctx is scheduled to be run.\n");
1765                 return;
1766         }
1767
1768         mfc_debug(1, "New context: %d\n", new_ctx);
1769         ctx = dev->ctx[new_ctx];
1770         mfc_debug(1, "Seting new context to %p\n", ctx);
1771         /* Got context to run in ctx */
1772         mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
1773                 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
1774         mfc_debug(1, "ctx->state=%d\n", ctx->state);
1775         /* Last frame has already been sent to MFC
1776          * Now obtaining frames from MFC buffer */
1777
1778         s5p_mfc_clock_on();
1779         if (ctx->type == MFCINST_DECODER) {
1780                 switch (ctx->state) {
1781                 case MFCINST_FINISHING:
1782                         s5p_mfc_run_dec_last_frames(ctx);
1783                         break;
1784                 case MFCINST_RUNNING:
1785                         ret = s5p_mfc_run_dec_frame(ctx);
1786                         break;
1787                 case MFCINST_INIT:
1788                         s5p_mfc_clean_ctx_int_flags(ctx);
1789                         ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1790                                         ctx);
1791                         break;
1792                 case MFCINST_RETURN_INST:
1793                         s5p_mfc_clean_ctx_int_flags(ctx);
1794                         ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1795                                         ctx);
1796                         break;
1797                 case MFCINST_GOT_INST:
1798                         s5p_mfc_run_init_dec(ctx);
1799                         break;
1800                 case MFCINST_HEAD_PARSED:
1801                         ret = s5p_mfc_run_init_dec_buffers(ctx);
1802                         break;
1803                 case MFCINST_FLUSH:
1804                         s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1805                         break;
1806                 case MFCINST_RES_CHANGE_INIT:
1807                         s5p_mfc_run_dec_last_frames(ctx);
1808                         break;
1809                 case MFCINST_RES_CHANGE_FLUSH:
1810                         s5p_mfc_run_dec_last_frames(ctx);
1811                         break;
1812                 case MFCINST_RES_CHANGE_END:
1813                         mfc_debug(2, "Finished remaining frames after resolution change.\n");
1814                         ctx->capture_state = QUEUE_FREE;
1815                         mfc_debug(2, "Will re-init the codec`.\n");
1816                         s5p_mfc_run_init_dec(ctx);
1817                         break;
1818                 default:
1819                         ret = -EAGAIN;
1820                 }
1821         } else if (ctx->type == MFCINST_ENCODER) {
1822                 switch (ctx->state) {
1823                 case MFCINST_FINISHING:
1824                 case MFCINST_RUNNING:
1825                         ret = s5p_mfc_run_enc_frame(ctx);
1826                         break;
1827                 case MFCINST_INIT:
1828                         ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1829                                         ctx);
1830                         break;
1831                 case MFCINST_RETURN_INST:
1832                         ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1833                                         ctx);
1834                         break;
1835                 case MFCINST_GOT_INST:
1836                         s5p_mfc_run_init_enc(ctx);
1837                         break;
1838                 case MFCINST_HEAD_PRODUCED:
1839                         ret = s5p_mfc_run_init_enc_buffers(ctx);
1840                         break;
1841                 default:
1842                         ret = -EAGAIN;
1843                 }
1844         } else {
1845                 mfc_err("invalid context type: %d\n", ctx->type);
1846                 ret = -EAGAIN;
1847         }
1848
1849         if (ret) {
1850                 /* Free hardware lock */
1851                 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
1852                         mfc_err("Failed to unlock hardware.\n");
1853
1854                 /* This is in deed imporant, as no operation has been
1855                  * scheduled, reduce the clock count as no one will
1856                  * ever do this, because no interrupt related to this try_run
1857                  * will ever come from hardware. */
1858                 s5p_mfc_clock_off();
1859         }
1860 }
1861
1862
1863 static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq)
1864 {
1865         struct s5p_mfc_buf *b;
1866         int i;
1867
1868         while (!list_empty(lh)) {
1869                 b = list_entry(lh->next, struct s5p_mfc_buf, list);
1870                 for (i = 0; i < b->b->num_planes; i++)
1871                         vb2_set_plane_payload(b->b, i, 0);
1872                 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR);
1873                 list_del(&b->list);
1874         }
1875 }
1876
1877 static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
1878 {
1879         const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1880         WRITEL(0, mfc_regs->risc2host_command);
1881         WRITEL(0, mfc_regs->risc2host_int);
1882 }
1883
1884 static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data,
1885                 unsigned int ofs)
1886 {
1887         s5p_mfc_clock_on();
1888         WRITEL(data, (void *)ofs);
1889         s5p_mfc_clock_off();
1890 }
1891
1892 static unsigned int
1893 s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
1894 {
1895         int ret;
1896
1897         s5p_mfc_clock_on();
1898         ret = READL((void *)ofs);
1899         s5p_mfc_clock_off();
1900
1901         return ret;
1902 }
1903
1904 static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
1905 {
1906         return READL(dev->mfc_regs->d_display_first_plane_addr);
1907 }
1908
1909 static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
1910 {
1911         return READL(dev->mfc_regs->d_decoded_first_plane_addr);
1912 }
1913
1914 static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
1915 {
1916         return READL(dev->mfc_regs->d_display_status);
1917 }
1918
1919 static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
1920 {
1921         return READL(dev->mfc_regs->d_decoded_status);
1922 }
1923
1924 static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
1925 {
1926         return READL(dev->mfc_regs->d_decoded_frame_type) &
1927                 S5P_FIMV_DECODE_FRAME_MASK_V6;
1928 }
1929
1930 static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
1931 {
1932         struct s5p_mfc_dev *dev = ctx->dev;
1933         return READL(dev->mfc_regs->d_display_frame_type) &
1934                 S5P_FIMV_DECODE_FRAME_MASK_V6;
1935 }
1936
1937 static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
1938 {
1939         return READL(dev->mfc_regs->d_decoded_nal_size);
1940 }
1941
1942 static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
1943 {
1944         return READL(dev->mfc_regs->risc2host_command) &
1945                 S5P_FIMV_RISC2HOST_CMD_MASK;
1946 }
1947
1948 static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
1949 {
1950         return READL(dev->mfc_regs->error_code);
1951 }
1952
1953 static int s5p_mfc_err_dec_v6(unsigned int err)
1954 {
1955         return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
1956 }
1957
1958 static int s5p_mfc_err_dspl_v6(unsigned int err)
1959 {
1960         return (err & S5P_FIMV_ERR_DSPL_MASK_V6) >> S5P_FIMV_ERR_DSPL_SHIFT_V6;
1961 }
1962
1963 static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
1964 {
1965         return READL(dev->mfc_regs->d_display_frame_width);
1966 }
1967
1968 static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
1969 {
1970         return READL(dev->mfc_regs->d_display_frame_height);
1971 }
1972
1973 static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
1974 {
1975         return READL(dev->mfc_regs->d_min_num_dpb);
1976 }
1977
1978 static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
1979 {
1980         return READL(dev->mfc_regs->d_min_num_mv);
1981 }
1982
1983 static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
1984 {
1985         return READL(dev->mfc_regs->ret_instance_id);
1986 }
1987
1988 static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
1989 {
1990         return READL(dev->mfc_regs->e_num_dpb);
1991 }
1992
1993 static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
1994 {
1995         return READL(dev->mfc_regs->e_stream_size);
1996 }
1997
1998 static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
1999 {
2000         return READL(dev->mfc_regs->e_slice_type);
2001 }
2002
2003 static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev)
2004 {
2005         return READL(dev->mfc_regs->e_picture_count);
2006 }
2007
2008 static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx)
2009 {
2010         struct s5p_mfc_dev *dev = ctx->dev;
2011         return READL(dev->mfc_regs->d_frame_pack_sei_avail);
2012 }
2013
2014 static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev)
2015 {
2016         return READL(dev->mfc_regs->d_mvc_num_views);
2017 }
2018
2019 static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev)
2020 {
2021         return READL(dev->mfc_regs->d_mvc_view_id);
2022 }
2023
2024 static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
2025 {
2026         return s5p_mfc_read_info_v6(ctx,
2027                 (unsigned int) ctx->dev->mfc_regs->d_ret_picture_tag_top);
2028 }
2029
2030 static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
2031 {
2032         return s5p_mfc_read_info_v6(ctx,
2033                 (unsigned int) ctx->dev->mfc_regs->d_ret_picture_tag_bot);
2034 }
2035
2036 static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
2037 {
2038         return s5p_mfc_read_info_v6(ctx,
2039                 (unsigned int) ctx->dev->mfc_regs->d_display_crop_info1);
2040 }
2041
2042 static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
2043 {
2044         return s5p_mfc_read_info_v6(ctx,
2045                 (unsigned int) ctx->dev->mfc_regs->d_display_crop_info2);
2046 }
2047
2048 static struct s5p_mfc_regs mfc_regs;
2049
2050 /* Initialize registers for MFC v6 onwards */
2051 const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
2052 {
2053         memset(&mfc_regs, 0, sizeof(mfc_regs));
2054
2055 #define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg))
2056 #define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r)
2057         /* codec common registers */
2058         R(risc_on, S5P_FIMV_RISC_ON_V6);
2059         R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6);
2060         R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6);
2061         R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6);
2062         R(mfc_reset, S5P_FIMV_MFC_RESET_V6);
2063         R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6);
2064         R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6);
2065         R(firmware_version, S5P_FIMV_FW_VERSION_V6);
2066         R(instance_id, S5P_FIMV_INSTANCE_ID_V6);
2067         R(codec_type, S5P_FIMV_CODEC_TYPE_V6);
2068         R(context_mem_addr, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
2069         R(context_mem_size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
2070         R(pixel_format, S5P_FIMV_PIXEL_FORMAT_V6);
2071         R(ret_instance_id, S5P_FIMV_RET_INSTANCE_ID_V6);
2072         R(error_code, S5P_FIMV_ERROR_CODE_V6);
2073
2074         /* decoder registers */
2075         R(d_crc_ctrl, S5P_FIMV_D_CRC_CTRL_V6);
2076         R(d_dec_options, S5P_FIMV_D_DEC_OPTIONS_V6);
2077         R(d_display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
2078         R(d_sei_enable, S5P_FIMV_D_SEI_ENABLE_V6);
2079         R(d_min_num_dpb, S5P_FIMV_D_MIN_NUM_DPB_V6);
2080         R(d_min_num_mv, S5P_FIMV_D_MIN_NUM_MV_V6);
2081         R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
2082         R(d_num_dpb, S5P_FIMV_D_NUM_DPB_V6);
2083         R(d_num_mv, S5P_FIMV_D_NUM_MV_V6);
2084         R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6);
2085         R(d_first_plane_dpb_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
2086         R(d_second_plane_dpb_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
2087         R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
2088         R(d_first_plane_dpb, S5P_FIMV_D_LUMA_DPB_V6);
2089         R(d_second_plane_dpb, S5P_FIMV_D_CHROMA_DPB_V6);
2090         R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V6);
2091         R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
2092         R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
2093         R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
2094         R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
2095         R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
2096         R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
2097         R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
2098         R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
2099         R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
2100         R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
2101         R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V6);
2102         R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
2103         R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6);
2104         R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6);
2105         R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V6);
2106         R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V6);
2107         R(d_display_aspect_ratio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6);
2108         R(d_display_extended_ar, S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6);
2109         R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V6);
2110         R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
2111         R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_CHROMA_ADDR_V6);
2112         R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V6);
2113         R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
2114         R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6);
2115         R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6);
2116         R(d_h264_info, S5P_FIMV_D_H264_INFO_V6);
2117         R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V6);
2118         R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
2119
2120         /* encoder registers */
2121         R(e_frame_width, S5P_FIMV_E_FRAME_WIDTH_V6);
2122         R(e_frame_height, S5P_FIMV_E_FRAME_HEIGHT_V6);
2123         R(e_cropped_frame_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
2124         R(e_cropped_frame_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
2125         R(e_frame_crop_offset, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
2126         R(e_enc_options, S5P_FIMV_E_ENC_OPTIONS_V6);
2127         R(e_picture_profile, S5P_FIMV_E_PICTURE_PROFILE_V6);
2128         R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
2129         R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
2130         R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
2131         R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V6);
2132         R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V6);
2133         R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V6);
2134         R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V6);
2135         R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V6);
2136         R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V6);
2137         R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V6);
2138         R(e_num_dpb, S5P_FIMV_E_NUM_DPB_V6);
2139         R(e_luma_dpb, S5P_FIMV_E_LUMA_DPB_V6);
2140         R(e_chroma_dpb, S5P_FIMV_E_CHROMA_DPB_V6);
2141         R(e_me_buffer, S5P_FIMV_E_ME_BUFFER_V6);
2142         R(e_scratch_buffer_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
2143         R(e_scratch_buffer_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
2144         R(e_tmv_buffer0, S5P_FIMV_E_TMV_BUFFER0_V6);
2145         R(e_tmv_buffer1, S5P_FIMV_E_TMV_BUFFER1_V6);
2146         R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
2147         R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
2148         R(e_stream_buffer_addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6);
2149         R(e_stream_buffer_size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
2150         R(e_roi_buffer_addr, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
2151         R(e_param_change, S5P_FIMV_E_PARAM_CHANGE_V6);
2152         R(e_ir_size, S5P_FIMV_E_IR_SIZE_V6);
2153         R(e_gop_config, S5P_FIMV_E_GOP_CONFIG_V6);
2154         R(e_mslice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
2155         R(e_mslice_size_mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
2156         R(e_mslice_size_bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
2157         R(e_frame_insertion, S5P_FIMV_E_FRAME_INSERTION_V6);
2158         R(e_rc_frame_rate, S5P_FIMV_E_RC_FRAME_RATE_V6);
2159         R(e_rc_bit_rate, S5P_FIMV_E_RC_BIT_RATE_V6);
2160         R(e_rc_roi_ctrl, S5P_FIMV_E_RC_ROI_CTRL_V6);
2161         R(e_picture_tag, S5P_FIMV_E_PICTURE_TAG_V6);
2162         R(e_bit_count_enable, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
2163         R(e_max_bit_count, S5P_FIMV_E_MAX_BIT_COUNT_V6);
2164         R(e_min_bit_count, S5P_FIMV_E_MIN_BIT_COUNT_V6);
2165         R(e_metadata_buffer_addr, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
2166         R(e_metadata_buffer_size, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
2167         R(e_encoded_source_first_plane_addr,
2168                         S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
2169         R(e_encoded_source_second_plane_addr,
2170                         S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
2171         R(e_stream_size, S5P_FIMV_E_STREAM_SIZE_V6);
2172         R(e_slice_type, S5P_FIMV_E_SLICE_TYPE_V6);
2173         R(e_picture_count, S5P_FIMV_E_PICTURE_COUNT_V6);
2174         R(e_ret_picture_tag, S5P_FIMV_E_RET_PICTURE_TAG_V6);
2175         R(e_recon_luma_dpb_addr, S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
2176         R(e_recon_chroma_dpb_addr, S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
2177         R(e_mpeg4_options, S5P_FIMV_E_MPEG4_OPTIONS_V6);
2178         R(e_mpeg4_hec_period, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
2179         R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V6);
2180         R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V6);
2181         R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V6);
2182         R(e_h264_lf_alpha_offset, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
2183         R(e_h264_lf_beta_offset, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
2184         R(e_h264_i_period, S5P_FIMV_E_H264_I_PERIOD_V6);
2185         R(e_h264_fmo_slice_grp_map_type,
2186                         S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
2187         R(e_h264_fmo_num_slice_grp_minus1,
2188                         S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
2189         R(e_h264_fmo_slice_grp_change_dir,
2190                         S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
2191         R(e_h264_fmo_slice_grp_change_rate_minus1,
2192                         S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
2193         R(e_h264_fmo_run_length_minus1_0,
2194                         S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6);
2195         R(e_h264_aso_slice_order_0, S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6);
2196         R(e_h264_num_t_layer, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
2197         R(e_h264_hierarchical_qp_layer0,
2198                         S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6);
2199         R(e_h264_frame_packing_sei_info,
2200                         S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
2201
2202         if (!IS_MFCV7_PLUS(dev))
2203                 goto done;
2204
2205         /* Initialize registers used in MFC v7+ */
2206         R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);
2207         R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
2208         R(e_source_third_plane_addr, S5P_FIMV_E_SOURCE_THIRD_ADDR_V7);
2209         R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);
2210         R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);
2211         R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7);
2212         R(e_encoded_source_first_plane_addr,
2213                         S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
2214         R(e_encoded_source_second_plane_addr,
2215                         S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
2216         R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);
2217
2218         if (!IS_MFCV8(dev))
2219                 goto done;
2220
2221         /* Initialize registers used in MFC v8 only.
2222          * Also, over-write the registers which have
2223          * a different offset for MFC v8. */
2224         R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V8);
2225         R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V8);
2226         R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V8);
2227         R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8);
2228         R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8);
2229         R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8);
2230         R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8);
2231         R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8);
2232         R(d_first_plane_dpb_stride_size,
2233                         S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);
2234         R(d_second_plane_dpb_stride_size,
2235                         S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);
2236         R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8);
2237         R(d_num_mv, S5P_FIMV_D_NUM_MV_V8);
2238         R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8);
2239         R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8);
2240         R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8);
2241         R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8);
2242         R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8);
2243         R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V8);
2244         R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8);
2245         R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8);
2246         R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8);
2247         R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8);
2248         R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V8);
2249         R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V8);
2250         R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V8);
2251         R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8);
2252         R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V8);
2253         R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8);
2254         R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8);
2255         R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8);
2256         R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V8);
2257         R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V8);
2258         R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8);
2259         R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8);
2260         R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8);
2261         R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8);
2262
2263         /* encoder registers */
2264         R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8);
2265         R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V8);
2266         R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V8);
2267         R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V8);
2268         R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V8);
2269         R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V8);
2270         R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V8);
2271         R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V8);
2272         R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V8);
2273         R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V8);
2274         R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8);
2275         R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8);
2276         R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
2277
2278 done:
2279         return &mfc_regs;
2280 #undef S5P_MFC_REG_ADDR
2281 #undef R
2282 }
2283
2284 /* Initialize opr function pointers for MFC v6 */
2285 static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
2286         .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
2287         .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
2288         .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
2289         .release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
2290         .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
2291         .release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
2292         .alloc_dev_context_buffer =
2293                 s5p_mfc_alloc_dev_context_buffer_v6,
2294         .release_dev_context_buffer =
2295                 s5p_mfc_release_dev_context_buffer_v6,
2296         .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
2297         .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
2298         .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v6,
2299         .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v6,
2300         .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
2301         .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
2302         .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
2303         .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v6,
2304         .init_decode = s5p_mfc_init_decode_v6,
2305         .init_encode = s5p_mfc_init_encode_v6,
2306         .encode_one_frame = s5p_mfc_encode_one_frame_v6,
2307         .try_run = s5p_mfc_try_run_v6,
2308         .cleanup_queue = s5p_mfc_cleanup_queue_v6,
2309         .clear_int_flags = s5p_mfc_clear_int_flags_v6,
2310         .write_info = s5p_mfc_write_info_v6,
2311         .read_info = s5p_mfc_read_info_v6,
2312         .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
2313         .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
2314         .get_dspl_status = s5p_mfc_get_dspl_status_v6,
2315         .get_dec_status = s5p_mfc_get_dec_status_v6,
2316         .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
2317         .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
2318         .get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
2319         .get_int_reason = s5p_mfc_get_int_reason_v6,
2320         .get_int_err = s5p_mfc_get_int_err_v6,
2321         .err_dec = s5p_mfc_err_dec_v6,
2322         .err_dspl = s5p_mfc_err_dspl_v6,
2323         .get_img_width = s5p_mfc_get_img_width_v6,
2324         .get_img_height = s5p_mfc_get_img_height_v6,
2325         .get_dpb_count = s5p_mfc_get_dpb_count_v6,
2326         .get_mv_count = s5p_mfc_get_mv_count_v6,
2327         .get_inst_no = s5p_mfc_get_inst_no_v6,
2328         .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
2329         .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
2330         .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
2331         .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v6,
2332         .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v6,
2333         .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v6,
2334         .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v6,
2335         .get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
2336         .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
2337         .get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
2338         .get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
2339 };
2340
2341 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
2342 {
2343         return &s5p_mfc_ops_v6;
2344 }