1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.
4 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <linux/delay.h>
9 #include <linux/firmware.h>
10 #include <linux/interrupt.h>
12 #include <linux/iommu.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/remoteproc.h>
24 #include <linux/reset.h>
25 #include <linux/soc/qcom/mdt_loader.h>
26 #include <linux/soc/qcom/smem.h>
27 #include <linux/soc/qcom/smem_state.h>
29 #include "qcom_common.h"
30 #include "qcom_pil_info.h"
31 #include "qcom_q6v5.h"
32 #include "remoteproc_internal.h"
35 #define ACK_TIMEOUT 1000
36 #define ACK_TIMEOUT_US 1000000
37 #define BOOT_FSM_TIMEOUT 10000
39 #define EVB_MASK GENMASK(27, 4)
40 /*QDSP6SS register offsets*/
41 #define RST_EVB_REG 0x10
42 #define CORE_START_REG 0x400
43 #define BOOT_CMD_REG 0x404
44 #define BOOT_STATUS_REG 0x408
45 #define RET_CFG_REG 0x1C
46 /*TCSR register offsets*/
47 #define LPASS_MASTER_IDLE_REG 0x8
48 #define LPASS_HALTACK_REG 0x4
49 #define LPASS_PWR_ON_REG 0x10
50 #define LPASS_HALTREQ_REG 0x0
52 #define SID_MASK_DEFAULT 0xF
54 #define QDSP6SS_XO_CBCR 0x38
55 #define QDSP6SS_CORE_CBCR 0x20
56 #define QDSP6SS_SLEEP_CBCR 0x3c
58 #define LPASS_BOOT_CORE_START BIT(0)
59 #define LPASS_BOOT_CMD_START BIT(0)
60 #define LPASS_EFUSE_Q6SS_EVB_SEL 0x0
62 struct adsp_pil_data {
63 int crash_reason_smem;
64 const char *firmware_name;
67 const char *sysmon_name;
75 const char **pd_names;
77 const char *load_state;
84 struct qcom_q6v5 q6v5;
89 struct clk_bulk_data *clks;
91 void __iomem *qdsp6ss_base;
92 void __iomem *lpass_efuse;
94 struct reset_control *pdc_sync_reset;
95 struct reset_control *restart;
97 struct regmap *halt_map;
98 unsigned int halt_lpass;
100 int crash_reason_smem;
101 const char *info_name;
103 struct completion start_done;
104 struct completion stop_done;
106 phys_addr_t mem_phys;
107 phys_addr_t mem_reloc;
112 struct dev_pm_domain_list *pd_list;
114 struct qcom_rproc_glink glink_subdev;
115 struct qcom_rproc_ssr ssr_subdev;
116 struct qcom_sysmon *sysmon;
118 int (*shutdown)(struct qcom_adsp *adsp);
121 static int qcom_rproc_pds_attach(struct qcom_adsp *adsp, const char **pd_names,
122 unsigned int num_pds)
124 struct device *dev = adsp->dev;
125 struct dev_pm_domain_attach_data pd_data = {
126 .pd_names = pd_names,
127 .num_pd_names = num_pds,
131 /* Handle single power domain */
138 ret = dev_pm_domain_attach_list(dev, &pd_data, &adsp->pd_list);
143 pm_runtime_enable(dev);
147 static void qcom_rproc_pds_detach(struct qcom_adsp *adsp)
149 struct device *dev = adsp->dev;
150 struct dev_pm_domain_list *pds = adsp->pd_list;
152 dev_pm_domain_detach_list(pds);
154 if (dev->pm_domain || pds)
155 pm_runtime_disable(adsp->dev);
158 static int qcom_rproc_pds_enable(struct qcom_adsp *adsp)
160 struct device *dev = adsp->dev;
161 struct dev_pm_domain_list *pds = adsp->pd_list;
164 if (!dev->pm_domain && !pds)
168 dev_pm_genpd_set_performance_state(dev, INT_MAX);
170 while (pds && i < pds->num_pds) {
171 dev_pm_genpd_set_performance_state(pds->pd_devs[i], INT_MAX);
175 ret = pm_runtime_resume_and_get(dev);
177 while (pds && i > 0) {
179 dev_pm_genpd_set_performance_state(pds->pd_devs[i], 0);
183 dev_pm_genpd_set_performance_state(dev, 0);
189 static void qcom_rproc_pds_disable(struct qcom_adsp *adsp)
191 struct device *dev = adsp->dev;
192 struct dev_pm_domain_list *pds = adsp->pd_list;
195 if (!dev->pm_domain && !pds)
199 dev_pm_genpd_set_performance_state(dev, 0);
201 while (pds && i < pds->num_pds) {
202 dev_pm_genpd_set_performance_state(pds->pd_devs[i], 0);
209 static int qcom_wpss_shutdown(struct qcom_adsp *adsp)
213 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
215 /* Wait for halt ACK from QDSP6 */
216 regmap_read_poll_timeout(adsp->halt_map,
217 adsp->halt_lpass + LPASS_HALTACK_REG, val,
218 val, 1000, ACK_TIMEOUT_US);
220 /* Assert the WPSS PDC Reset */
221 reset_control_assert(adsp->pdc_sync_reset);
223 /* Place the WPSS processor into reset */
224 reset_control_assert(adsp->restart);
226 /* wait after asserting subsystem restart from AOSS */
227 usleep_range(200, 205);
229 /* Remove the WPSS reset */
230 reset_control_deassert(adsp->restart);
232 /* De-assert the WPSS PDC Reset */
233 reset_control_deassert(adsp->pdc_sync_reset);
235 usleep_range(100, 105);
237 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
239 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
241 /* Wait for halt ACK from QDSP6 */
242 regmap_read_poll_timeout(adsp->halt_map,
243 adsp->halt_lpass + LPASS_HALTACK_REG, val,
244 !val, 1000, ACK_TIMEOUT_US);
249 static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
251 unsigned long timeout;
255 /* Reset the retention logic */
256 val = readl(adsp->qdsp6ss_base + RET_CFG_REG);
258 writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
260 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
262 /* QDSP6 master port needs to be explicitly halted */
263 ret = regmap_read(adsp->halt_map,
264 adsp->halt_lpass + LPASS_PWR_ON_REG, &val);
268 ret = regmap_read(adsp->halt_map,
269 adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
274 regmap_write(adsp->halt_map,
275 adsp->halt_lpass + LPASS_HALTREQ_REG, 1);
277 /* Wait for halt ACK from QDSP6 */
278 timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
280 ret = regmap_read(adsp->halt_map,
281 adsp->halt_lpass + LPASS_HALTACK_REG, &val);
282 if (ret || val || time_after(jiffies, timeout))
285 usleep_range(1000, 1100);
288 ret = regmap_read(adsp->halt_map,
289 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);
291 dev_err(adsp->dev, "port failed halt\n");
294 /* Assert the LPASS PDC Reset */
295 reset_control_assert(adsp->pdc_sync_reset);
296 /* Place the LPASS processor into reset */
297 reset_control_assert(adsp->restart);
298 /* wait after asserting subsystem restart from AOSS */
299 usleep_range(200, 300);
301 /* Clear the halt request for the AXIM and AHBM for Q6 */
302 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);
304 /* De-assert the LPASS PDC Reset */
305 reset_control_deassert(adsp->pdc_sync_reset);
306 /* Remove the LPASS reset */
307 reset_control_deassert(adsp->restart);
308 /* wait after de-asserting subsystem restart from AOSS */
309 usleep_range(200, 300);
314 static int adsp_load(struct rproc *rproc, const struct firmware *fw)
316 struct qcom_adsp *adsp = rproc->priv;
319 ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
320 adsp->mem_region, adsp->mem_phys,
321 adsp->mem_size, &adsp->mem_reloc);
325 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
330 static void adsp_unmap_carveout(struct rproc *rproc)
332 struct qcom_adsp *adsp = rproc->priv;
335 iommu_unmap(rproc->domain, adsp->mem_phys, adsp->mem_size);
338 static int adsp_map_carveout(struct rproc *rproc)
340 struct qcom_adsp *adsp = rproc->priv;
341 struct of_phandle_args args;
346 if (!adsp->has_iommu)
352 ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args);
356 sid = args.args[0] & SID_MASK_DEFAULT;
358 /* Add SID configuration for ADSP Firmware to SMMU */
359 iova = adsp->mem_phys | (sid << 32);
361 ret = iommu_map(rproc->domain, iova, adsp->mem_phys,
362 adsp->mem_size, IOMMU_READ | IOMMU_WRITE,
365 dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n");
372 static int adsp_start(struct rproc *rproc)
374 struct qcom_adsp *adsp = rproc->priv;
378 ret = qcom_q6v5_prepare(&adsp->q6v5);
382 ret = adsp_map_carveout(rproc);
384 dev_err(adsp->dev, "ADSP smmu mapping failed\n");
388 ret = clk_prepare_enable(adsp->xo);
390 goto adsp_smmu_unmap;
392 ret = qcom_rproc_pds_enable(adsp);
396 ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);
398 dev_err(adsp->dev, "adsp clk_enable failed\n");
399 goto disable_power_domain;
402 /* Enable the XO clock */
403 writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
405 /* Enable the QDSP6SS sleep clock */
406 writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
408 /* Enable the QDSP6 core clock */
409 writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
411 /* Program boot address */
412 writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
414 if (adsp->lpass_efuse)
415 writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse);
417 /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
418 writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG);
420 /* Trigger boot FSM to start QDSP6 */
421 writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG);
423 /* Wait for core to come out of reset */
424 ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
425 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
427 dev_err(adsp->dev, "failed to bootup adsp\n");
428 goto disable_adsp_clks;
431 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ));
432 if (ret == -ETIMEDOUT) {
433 dev_err(adsp->dev, "start timed out\n");
434 goto disable_adsp_clks;
440 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);
441 disable_power_domain:
442 qcom_rproc_pds_disable(adsp);
444 clk_disable_unprepare(adsp->xo);
446 adsp_unmap_carveout(rproc);
448 qcom_q6v5_unprepare(&adsp->q6v5);
453 static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5)
455 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
457 clk_disable_unprepare(adsp->xo);
458 qcom_rproc_pds_disable(adsp);
461 static int adsp_stop(struct rproc *rproc)
463 struct qcom_adsp *adsp = rproc->priv;
467 ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon);
468 if (ret == -ETIMEDOUT)
469 dev_err(adsp->dev, "timed out on wait\n");
471 ret = adsp->shutdown(adsp);
473 dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
475 adsp_unmap_carveout(rproc);
477 handover = qcom_q6v5_unprepare(&adsp->q6v5);
479 qcom_adsp_pil_handover(&adsp->q6v5);
484 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
486 struct qcom_adsp *adsp = rproc->priv;
489 offset = da - adsp->mem_reloc;
490 if (offset < 0 || offset + len > adsp->mem_size)
493 return adsp->mem_region + offset;
496 static int adsp_parse_firmware(struct rproc *rproc, const struct firmware *fw)
498 struct qcom_adsp *adsp = rproc->priv;
501 ret = qcom_register_dump_segments(rproc, fw);
503 dev_err(&rproc->dev, "Error in registering dump segments\n");
507 if (adsp->has_iommu) {
508 ret = rproc_elf_load_rsc_table(rproc, fw);
510 dev_err(&rproc->dev, "Error in loading resource table\n");
517 static unsigned long adsp_panic(struct rproc *rproc)
519 struct qcom_adsp *adsp = rproc->priv;
521 return qcom_q6v5_panic(&adsp->q6v5);
524 static const struct rproc_ops adsp_ops = {
527 .da_to_va = adsp_da_to_va,
528 .parse_fw = adsp_parse_firmware,
533 static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)
538 adsp->xo = devm_clk_get(adsp->dev, "xo");
539 if (IS_ERR(adsp->xo)) {
540 ret = PTR_ERR(adsp->xo);
541 if (ret != -EPROBE_DEFER)
542 dev_err(adsp->dev, "failed to get xo clock");
546 for (i = 0; clk_ids[i]; i++)
549 adsp->num_clks = num_clks;
550 adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,
551 sizeof(*adsp->clks), GFP_KERNEL);
555 for (i = 0; i < adsp->num_clks; i++)
556 adsp->clks[i].id = clk_ids[i];
558 return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);
561 static int adsp_init_reset(struct qcom_adsp *adsp)
563 adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,
565 if (IS_ERR(adsp->pdc_sync_reset)) {
566 dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
567 return PTR_ERR(adsp->pdc_sync_reset);
570 adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");
572 /* Fall back to the old "cc_lpass" if "restart" is absent */
574 adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass");
576 if (IS_ERR(adsp->restart)) {
577 dev_err(adsp->dev, "failed to acquire restart\n");
578 return PTR_ERR(adsp->restart);
584 static int adsp_init_mmio(struct qcom_adsp *adsp,
585 struct platform_device *pdev)
587 struct resource *efuse_region;
588 struct device_node *syscon;
591 adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0);
592 if (IS_ERR(adsp->qdsp6ss_base)) {
593 dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
594 return PTR_ERR(adsp->qdsp6ss_base);
597 efuse_region = platform_get_resource(pdev, IORESOURCE_MEM, 1);
599 adsp->lpass_efuse = NULL;
600 dev_dbg(adsp->dev, "failed to get efuse memory region\n");
602 adsp->lpass_efuse = devm_ioremap_resource(&pdev->dev, efuse_region);
603 if (IS_ERR(adsp->lpass_efuse)) {
604 dev_err(adsp->dev, "failed to map efuse registers\n");
605 return PTR_ERR(adsp->lpass_efuse);
608 syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
610 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
614 adsp->halt_map = syscon_node_to_regmap(syscon);
616 if (IS_ERR(adsp->halt_map))
617 return PTR_ERR(adsp->halt_map);
619 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
620 1, &adsp->halt_lpass);
622 dev_err(&pdev->dev, "no offset in syscon\n");
629 static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
631 struct reserved_mem *rmem = NULL;
632 struct device_node *node;
634 node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
636 rmem = of_reserved_mem_lookup(node);
640 dev_err(adsp->dev, "unable to resolve memory-region\n");
644 adsp->mem_phys = adsp->mem_reloc = rmem->base;
645 adsp->mem_size = rmem->size;
646 adsp->mem_region = devm_ioremap_wc(adsp->dev,
647 adsp->mem_phys, adsp->mem_size);
648 if (!adsp->mem_region) {
649 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
650 &rmem->base, adsp->mem_size);
657 static int adsp_probe(struct platform_device *pdev)
659 const struct adsp_pil_data *desc;
660 const char *firmware_name;
661 struct qcom_adsp *adsp;
665 desc = of_device_get_match_data(&pdev->dev);
669 firmware_name = desc->firmware_name;
670 ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
672 if (ret < 0 && ret != -EINVAL) {
673 dev_err(&pdev->dev, "unable to read firmware-name\n");
677 rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
678 firmware_name, sizeof(*adsp));
680 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
684 rproc->auto_boot = desc->auto_boot;
685 rproc->has_iommu = desc->has_iommu;
686 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
689 adsp->dev = &pdev->dev;
691 adsp->info_name = desc->sysmon_name;
692 adsp->has_iommu = desc->has_iommu;
694 platform_set_drvdata(pdev, adsp);
697 adsp->shutdown = qcom_wpss_shutdown;
699 adsp->shutdown = qcom_adsp_shutdown;
701 ret = adsp_alloc_memory_region(adsp);
705 ret = adsp_init_clock(adsp, desc->clk_ids);
709 ret = qcom_rproc_pds_attach(adsp, desc->pd_names, desc->num_pds);
711 dev_err(&pdev->dev, "Failed to attach proxy power domains\n");
715 ret = adsp_init_reset(adsp);
719 ret = adsp_init_mmio(adsp, pdev);
723 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
724 desc->load_state, qcom_adsp_pil_handover);
728 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
729 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
730 adsp->sysmon = qcom_add_sysmon_subdev(rproc,
733 if (IS_ERR(adsp->sysmon)) {
734 ret = PTR_ERR(adsp->sysmon);
738 ret = rproc_add(rproc);
745 qcom_rproc_pds_detach(adsp);
753 static void adsp_remove(struct platform_device *pdev)
755 struct qcom_adsp *adsp = platform_get_drvdata(pdev);
757 rproc_del(adsp->rproc);
759 qcom_q6v5_deinit(&adsp->q6v5);
760 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
761 qcom_remove_sysmon_subdev(adsp->sysmon);
762 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
763 qcom_rproc_pds_detach(adsp);
764 rproc_free(adsp->rproc);
767 static const struct adsp_pil_data adsp_resource_init = {
768 .crash_reason_smem = 423,
769 .firmware_name = "adsp.mdt",
771 .sysmon_name = "adsp",
775 .clk_ids = (const char*[]) {
776 "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",
777 "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
780 .pd_names = (const char*[]) { "cx" },
784 static const struct adsp_pil_data adsp_sc7280_resource_init = {
785 .crash_reason_smem = 423,
786 .firmware_name = "adsp.pbn",
787 .load_state = "adsp",
789 .sysmon_name = "adsp",
793 .clk_ids = (const char*[]) {
794 "gcc_cfg_noc_lpass", NULL
799 static const struct adsp_pil_data cdsp_resource_init = {
800 .crash_reason_smem = 601,
801 .firmware_name = "cdsp.mdt",
803 .sysmon_name = "cdsp",
807 .clk_ids = (const char*[]) {
808 "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",
812 .pd_names = (const char*[]) { "cx" },
816 static const struct adsp_pil_data wpss_resource_init = {
817 .crash_reason_smem = 626,
818 .firmware_name = "wpss.mdt",
820 .sysmon_name = "wpss",
824 .load_state = "wpss",
825 .clk_ids = (const char*[]) {
826 "ahb_bdg", "ahb", "rscp", NULL
829 .pd_names = (const char*[]) { "cx", "mx" },
833 static const struct of_device_id adsp_of_match[] = {
834 { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
835 { .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init },
836 { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init },
837 { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
840 MODULE_DEVICE_TABLE(of, adsp_of_match);
842 static struct platform_driver adsp_pil_driver = {
844 .remove_new = adsp_remove,
846 .name = "qcom_q6v5_adsp",
847 .of_match_table = adsp_of_match,
851 module_platform_driver(adsp_pil_driver);
852 MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");
853 MODULE_LICENSE("GPL v2");