drivers/dma/fsl-edma-main.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * drivers/dma/fsl-edma.c
   4  *
   5  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   6  *
   7  * Driver for the Freescale eDMA engine with flexible channel multiplexing
   8  * capability for DMA request sources. The eDMA block can be found on some
   9  * Vybrid and Layerscape SoCs.
  10  */
  11
  12 #include <dt-bindings/dma/fsl-edma.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/module.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/clk.h>
  17 #include <linux/of.h>
  18 #include <linux/of_dma.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/property.h>
  23
  24 #include "fsl-edma-common.h"
  25
  26 static void fsl_edma_synchronize(struct dma_chan *chan)
  27 {
  28         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
  29
  30         vchan_synchronize(&fsl_chan->vchan);
  31 }
  32
  33 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
  34 {
  35         struct fsl_edma_engine *fsl_edma = dev_id;
  36         unsigned int intr, ch;
  37         struct edma_regs *regs = &fsl_edma->regs;
  38
  39         intr = edma_readl(fsl_edma, regs->intl);
  40         if (!intr)
  41                 return IRQ_NONE;
  42
  43         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
  44                 if (intr & (0x1 << ch)) {
  45                         edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
  46                         fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]);
  47                 }
  48         }
  49         return IRQ_HANDLED;
  50 }
  51
  52 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id)
  53 {
  54         struct fsl_edma_chan *fsl_chan = dev_id;
  55         unsigned int intr;
  56
  57         intr = edma_readl_chreg(fsl_chan, ch_int);
  58         if (!intr)
  59                 return IRQ_HANDLED;
  60
  61         edma_writel_chreg(fsl_chan, 1, ch_int);
  62
  63         fsl_edma_tx_chan_handler(fsl_chan);
  64
  65         return IRQ_HANDLED;
  66 }
  67
  68 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
  69 {
  70         struct fsl_edma_engine *fsl_edma = dev_id;
  71         unsigned int err, ch;
  72         struct edma_regs *regs = &fsl_edma->regs;
  73
  74         err = edma_readl(fsl_edma, regs->errl);
  75         if (!err)
  76                 return IRQ_NONE;
  77
  78         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
  79                 if (err & (0x1 << ch)) {
  80                         fsl_edma_disable_request(&fsl_edma->chans[ch]);
  81                         edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
  82                         fsl_edma_err_chan_handler(&fsl_edma->chans[ch]);
  83                 }
  84         }
  85         return IRQ_HANDLED;
  86 }
  87
  88 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
  89 {
  90         if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
  91                 return IRQ_HANDLED;
  92
  93         return fsl_edma_err_handler(irq, dev_id);
  94 }
  95
  96 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
  97                 struct of_dma *ofdma)
  98 {
  99         struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
 100         struct dma_chan *chan, *_chan;
 101         struct fsl_edma_chan *fsl_chan;
 102         u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
 103         unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
 104
 105         if (dma_spec->args_count != 2)
 106                 return NULL;
 107
 108         mutex_lock(&fsl_edma->fsl_edma_mutex);
 109         list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
 110                 if (chan->client_count)
 111                         continue;
 112                 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
 113                         chan = dma_get_slave_channel(chan);
 114                         if (chan) {
 115                                 chan->device->privatecnt++;
 116                                 fsl_chan = to_fsl_edma_chan(chan);
 117                                 fsl_chan->slave_id = dma_spec->args[1];
 118                                 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
 119                                                 true);
 120                                 mutex_unlock(&fsl_edma->fsl_edma_mutex);
 121                                 return chan;
 122                         }
 123                 }
 124         }
 125         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 126         return NULL;
 127 }
 128
 129 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
 130                                         struct of_dma *ofdma)
 131 {
 132         struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
 133         struct dma_chan *chan, *_chan;
 134         struct fsl_edma_chan *fsl_chan;
 135         bool b_chmux;
 136         int i;
 137
 138         if (dma_spec->args_count != 3)
 139                 return NULL;
 140
 141         b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX);
 142
 143         mutex_lock(&fsl_edma->fsl_edma_mutex);
 144         list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
 145                                         device_node) {
 146
 147                 if (chan->client_count)
 148                         continue;
 149
 150                 fsl_chan = to_fsl_edma_chan(chan);
 151                 i = fsl_chan - fsl_edma->chans;
 152
 153                 fsl_chan->priority = dma_spec->args[1];
 154                 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX;
 155                 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE;
 156                 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO;
 157
 158                 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1))
 159                         continue;
 160
 161                 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1))
 162                         continue;
 163
 164                 if (!b_chmux && i == dma_spec->args[0]) {
 165                         chan = dma_get_slave_channel(chan);
 166                         chan->device->privatecnt++;
 167                         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 168                         return chan;
 169                 } else if (b_chmux && !fsl_chan->srcid) {
 170                         /* if controller support channel mux, choose a free channel */
 171                         chan = dma_get_slave_channel(chan);
 172                         chan->device->privatecnt++;
 173                         fsl_chan->srcid = dma_spec->args[0];
 174                         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 175                         return chan;
 176                 }
 177         }
 178         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 179         return NULL;
 180 }
 181
 182 static int
 183 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 184 {
 185         int ret;
 186
 187         edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
 188
 189         fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
 190         if (fsl_edma->txirq < 0)
 191                 return fsl_edma->txirq;
 192
 193         fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
 194         if (fsl_edma->errirq < 0)
 195                 return fsl_edma->errirq;
 196
 197         if (fsl_edma->txirq == fsl_edma->errirq) {
 198                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 199                                 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
 200                 if (ret) {
 201                         dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
 202                         return ret;
 203                 }
 204         } else {
 205                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 206                                 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
 207                 if (ret) {
 208                         dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
 209                         return ret;
 210                 }
 211
 212                 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
 213                                 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
 214                 if (ret) {
 215                         dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
 216                         return ret;
 217                 }
 218         }
 219
 220         return 0;
 221 }
 222
 223 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 224 {
 225         int ret;
 226         int i;
 227
 228         for (i = 0; i < fsl_edma->n_chans; i++) {
 229
 230                 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
 231
 232                 if (fsl_edma->chan_masked & BIT(i))
 233                         continue;
 234
 235                 /* request channel irq */
 236                 fsl_chan->txirq = platform_get_irq(pdev, i);
 237                 if (fsl_chan->txirq < 0)
 238                         return  -EINVAL;
 239
 240                 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
 241                         fsl_edma3_tx_handler, IRQF_SHARED,
 242                         fsl_chan->chan_name, fsl_chan);
 243                 if (ret) {
 244                         dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i);
 245                         return -EINVAL;
 246                 }
 247         }
 248
 249         return 0;
 250 }
 251
 252 static int
 253 fsl_edma2_irq_init(struct platform_device *pdev,
 254                    struct fsl_edma_engine *fsl_edma)
 255 {
 256         int i, ret, irq;
 257         int count;
 258
 259         edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
 260
 261         count = platform_irq_count(pdev);
 262         dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
 263         if (count <= 2) {
 264                 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
 265                 return -EINVAL;
 266         }
 267         /*
 268          * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
 269          * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
 270          * For now, just simply request irq without IRQF_SHARED flag, since 16
 271          * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
 272          */
 273         for (i = 0; i < count; i++) {
 274                 irq = platform_get_irq(pdev, i);
 275                 if (irq < 0)
 276                         return -ENXIO;
 277
 278                 /* The last IRQ is for eDMA err */
 279                 if (i == count - 1)
 280                         ret = devm_request_irq(&pdev->dev, irq,
 281                                                 fsl_edma_err_handler,
 282                                                 0, "eDMA2-ERR", fsl_edma);
 283                 else
 284                         ret = devm_request_irq(&pdev->dev, irq,
 285                                                 fsl_edma_tx_handler, 0,
 286                                                 fsl_edma->chans[i].chan_name,
 287                                                 fsl_edma);
 288                 if (ret)
 289                         return ret;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static void fsl_edma_irq_exit(
 296                 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 297 {
 298         if (fsl_edma->txirq == fsl_edma->errirq) {
 299                 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
 300         } else {
 301                 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
 302                 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
 303         }
 304 }
 305
 306 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
 307 {
 308         int i;
 309
 310         for (i = 0; i < nr_clocks; i++)
 311                 clk_disable_unprepare(fsl_edma->muxclk[i]);
 312 }
 313
 314 static struct fsl_edma_drvdata vf610_data = {
 315         .dmamuxs = DMAMUX_NR,
 316         .flags = FSL_EDMA_DRV_WRAP_IO,
 317         .chreg_off = EDMA_TCD,
 318         .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
 319         .setup_irq = fsl_edma_irq_init,
 320 };
 321
 322 static struct fsl_edma_drvdata ls1028a_data = {
 323         .dmamuxs = DMAMUX_NR,
 324         .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
 325         .chreg_off = EDMA_TCD,
 326         .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
 327         .setup_irq = fsl_edma_irq_init,
 328 };
 329
 330 static struct fsl_edma_drvdata imx7ulp_data = {
 331         .dmamuxs = 1,
 332         .chreg_off = EDMA_TCD,
 333         .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
 334         .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
 335         .setup_irq = fsl_edma2_irq_init,
 336 };
 337
 338 static struct fsl_edma_drvdata imx8qm_data = {
 339         .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
 340         .chreg_space_sz = 0x10000,
 341         .chreg_off = 0x10000,
 342         .setup_irq = fsl_edma3_irq_init,
 343 };
 344
 345 static struct fsl_edma_drvdata imx8qm_audio_data = {
 346         .flags = FSL_EDMA_DRV_QUIRK_SWAPPED | FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
 347         .chreg_space_sz = 0x10000,
 348         .chreg_off = 0x10000,
 349         .setup_irq = fsl_edma3_irq_init,
 350 };
 351
 352 static struct fsl_edma_drvdata imx93_data3 = {
 353         .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
 354         .chreg_space_sz = 0x10000,
 355         .chreg_off = 0x10000,
 356         .setup_irq = fsl_edma3_irq_init,
 357 };
 358
 359 static struct fsl_edma_drvdata imx93_data4 = {
 360         .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4,
 361         .chreg_space_sz = 0x8000,
 362         .chreg_off = 0x10000,
 363         .setup_irq = fsl_edma3_irq_init,
 364 };
 365
 366 static const struct of_device_id fsl_edma_dt_ids[] = {
 367         { .compatible = "fsl,vf610-edma", .data = &vf610_data},
 368         { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
 369         { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
 370         { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
 371         { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data},
 372         { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
 373         { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
 374         { /* sentinel */ }
 375 };
 376 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
 377
 378 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 379 {
 380         struct fsl_edma_chan *fsl_chan;
 381         struct device_link *link;
 382         struct device *pd_chan;
 383         struct device *dev;
 384         int i;
 385
 386         dev = &pdev->dev;
 387
 388         for (i = 0; i < fsl_edma->n_chans; i++) {
 389                 if (fsl_edma->chan_masked & BIT(i))
 390                         continue;
 391
 392                 fsl_chan = &fsl_edma->chans[i];
 393
 394                 pd_chan = dev_pm_domain_attach_by_id(dev, i);
 395                 if (IS_ERR_OR_NULL(pd_chan)) {
 396                         dev_err(dev, "Failed attach pd %d\n", i);
 397                         return -EINVAL;
 398                 }
 399
 400                 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
 401                                              DL_FLAG_PM_RUNTIME |
 402                                              DL_FLAG_RPM_ACTIVE);
 403                 if (!link) {
 404                         dev_err(dev, "Failed to add device_link to %d\n", i);
 405                         return -EINVAL;
 406                 }
 407
 408                 fsl_chan->pd_dev = pd_chan;
 409
 410                 pm_runtime_use_autosuspend(fsl_chan->pd_dev);
 411                 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200);
 412                 pm_runtime_set_active(fsl_chan->pd_dev);
 413         }
 414
 415         return 0;
 416 }
 417
 418 static int fsl_edma_probe(struct platform_device *pdev)
 419 {
 420         struct device_node *np = pdev->dev.of_node;
 421         struct fsl_edma_engine *fsl_edma;
 422         const struct fsl_edma_drvdata *drvdata = NULL;
 423         u32 chan_mask[2] = {0, 0};
 424         struct edma_regs *regs;
 425         int chans;
 426         int ret, i;
 427
 428         drvdata = device_get_match_data(&pdev->dev);
 429         if (!drvdata) {
 430                 dev_err(&pdev->dev, "unable to find driver data\n");
 431                 return -EINVAL;
 432         }
 433
 434         ret = of_property_read_u32(np, "dma-channels", &chans);
 435         if (ret) {
 436                 dev_err(&pdev->dev, "Can't get dma-channels.\n");
 437                 return ret;
 438         }
 439
 440         fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans),
 441                                 GFP_KERNEL);
 442         if (!fsl_edma)
 443                 return -ENOMEM;
 444
 445         fsl_edma->drvdata = drvdata;
 446         fsl_edma->n_chans = chans;
 447         mutex_init(&fsl_edma->fsl_edma_mutex);
 448
 449         fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0);
 450         if (IS_ERR(fsl_edma->membase))
 451                 return PTR_ERR(fsl_edma->membase);
 452
 453         if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) {
 454                 fsl_edma_setup_regs(fsl_edma);
 455                 regs = &fsl_edma->regs;
 456         }
 457
 458         if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
 459                 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
 460                 if (IS_ERR(fsl_edma->dmaclk)) {
 461                         dev_err(&pdev->dev, "Missing DMA block clock.\n");
 462                         return PTR_ERR(fsl_edma->dmaclk);
 463                 }
 464         }
 465
 466         if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
 467                 fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp");
 468                 if (IS_ERR(fsl_edma->chclk)) {
 469                         dev_err(&pdev->dev, "Missing MP block clock.\n");
 470                         return PTR_ERR(fsl_edma->chclk);
 471                 }
 472         }
 473
 474         ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2);
 475
 476         if (ret > 0) {
 477                 fsl_edma->chan_masked = chan_mask[1];
 478                 fsl_edma->chan_masked <<= 32;
 479                 fsl_edma->chan_masked |= chan_mask[0];
 480         }
 481
 482         for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
 483                 char clkname[32];
 484
 485                 /* eDMAv3 mux register move to TCD area if ch_mux exist */
 486                 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)
 487                         break;
 488
 489                 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev,
 490                                                                       1 + i);
 491                 if (IS_ERR(fsl_edma->muxbase[i])) {
 492                         /* on error: disable all previously enabled clks */
 493                         fsl_disable_clocks(fsl_edma, i);
 494                         return PTR_ERR(fsl_edma->muxbase[i]);
 495                 }
 496
 497                 sprintf(clkname, "dmamux%d", i);
 498                 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname);
 499                 if (IS_ERR(fsl_edma->muxclk[i])) {
 500                         dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
 501                         /* on error: disable all previously enabled clks */
 502                         return PTR_ERR(fsl_edma->muxclk[i]);
 503                 }
 504         }
 505
 506         fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
 507
 508         if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) {
 509                 ret = fsl_edma3_attach_pd(pdev, fsl_edma);
 510                 if (ret)
 511                         return ret;
 512         }
 513
 514         INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
 515         for (i = 0; i < fsl_edma->n_chans; i++) {
 516                 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
 517                 int len;
 518
 519                 if (fsl_edma->chan_masked & BIT(i))
 520                         continue;
 521
 522                 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d",
 523                                                            dev_name(&pdev->dev), i);
 524
 525                 fsl_chan->edma = fsl_edma;
 526                 fsl_chan->pm_state = RUNNING;
 527                 fsl_chan->slave_id = 0;
 528                 fsl_chan->idle = true;
 529                 fsl_chan->dma_dir = DMA_NONE;
 530                 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
 531
 532                 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ?
 533                                 offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
 534                 fsl_chan->tcd = fsl_edma->membase
 535                                 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
 536
 537                 fsl_chan->pdev = pdev;
 538                 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
 539
 540                 edma_write_tcdreg(fsl_chan, 0, csr);
 541                 fsl_edma_chan_mux(fsl_chan, 0, false);
 542         }
 543
 544         ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
 545         if (ret)
 546                 return ret;
 547
 548         dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
 549         dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
 550         dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
 551         dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask);
 552
 553         fsl_edma->dma_dev.dev = &pdev->dev;
 554         fsl_edma->dma_dev.device_alloc_chan_resources
 555                 = fsl_edma_alloc_chan_resources;
 556         fsl_edma->dma_dev.device_free_chan_resources
 557                 = fsl_edma_free_chan_resources;
 558         fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
 559         fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
 560         fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
 561         fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy;
 562         fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
 563         fsl_edma->dma_dev.device_pause = fsl_edma_pause;
 564         fsl_edma->dma_dev.device_resume = fsl_edma_resume;
 565         fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
 566         fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
 567         fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
 568
 569         fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
 570         fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
 571
 572         if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) {
 573                 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
 574                 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
 575         }
 576
 577         fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 578         if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV)
 579                 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV);
 580
 581         fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ?
 582                                         DMAENGINE_ALIGN_64_BYTES :
 583                                         DMAENGINE_ALIGN_32_BYTES;
 584
 585         /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
 586         dma_set_max_seg_size(fsl_edma->dma_dev.dev,
 587                              FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK));
 588
 589         fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
 590
 591         platform_set_drvdata(pdev, fsl_edma);
 592
 593         ret = dma_async_device_register(&fsl_edma->dma_dev);
 594         if (ret) {
 595                 dev_err(&pdev->dev,
 596                         "Can't register Freescale eDMA engine. (%d)\n", ret);
 597                 return ret;
 598         }
 599
 600         ret = of_dma_controller_register(np,
 601                         drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate,
 602                         fsl_edma);
 603         if (ret) {
 604                 dev_err(&pdev->dev,
 605                         "Can't register Freescale eDMA of_dma. (%d)\n", ret);
 606                 dma_async_device_unregister(&fsl_edma->dma_dev);
 607                 return ret;
 608         }
 609
 610         /* enable round robin arbitration */
 611         if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
 612                 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
 613
 614         return 0;
 615 }
 616
 617 static void fsl_edma_remove(struct platform_device *pdev)
 618 {
 619         struct device_node *np = pdev->dev.of_node;
 620         struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
 621
 622         fsl_edma_irq_exit(pdev, fsl_edma);
 623         fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
 624         of_dma_controller_free(np);
 625         dma_async_device_unregister(&fsl_edma->dma_dev);
 626         fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
 627 }
 628
 629 static int fsl_edma_suspend_late(struct device *dev)
 630 {
 631         struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
 632         struct fsl_edma_chan *fsl_chan;
 633         unsigned long flags;
 634         int i;
 635
 636         for (i = 0; i < fsl_edma->n_chans; i++) {
 637                 fsl_chan = &fsl_edma->chans[i];
 638                 if (fsl_edma->chan_masked & BIT(i))
 639                         continue;
 640                 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 641                 /* Make sure chan is idle or will force disable. */
 642                 if (unlikely(!fsl_chan->idle)) {
 643                         dev_warn(dev, "WARN: There is non-idle channel.");
 644                         fsl_edma_disable_request(fsl_chan);
 645                         fsl_edma_chan_mux(fsl_chan, 0, false);
 646                 }
 647
 648                 fsl_chan->pm_state = SUSPENDED;
 649                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 650         }
 651
 652         return 0;
 653 }
 654
 655 static int fsl_edma_resume_early(struct device *dev)
 656 {
 657         struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
 658         struct fsl_edma_chan *fsl_chan;
 659         struct edma_regs *regs = &fsl_edma->regs;
 660         int i;
 661
 662         for (i = 0; i < fsl_edma->n_chans; i++) {
 663                 fsl_chan = &fsl_edma->chans[i];
 664                 if (fsl_edma->chan_masked & BIT(i))
 665                         continue;
 666                 fsl_chan->pm_state = RUNNING;
 667                 edma_write_tcdreg(fsl_chan, 0, csr);
 668                 if (fsl_chan->slave_id != 0)
 669                         fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
 670         }
 671
 672         if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
 673                 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
 674
 675         return 0;
 676 }
 677
 678 /*
 679  * eDMA provides the service to others, so it should be suspend late
 680  * and resume early. When eDMA suspend, all of the clients should stop
 681  * the DMA data transmission and let the channel idle.
 682  */
 683 static const struct dev_pm_ops fsl_edma_pm_ops = {
 684         .suspend_late   = fsl_edma_suspend_late,
 685         .resume_early   = fsl_edma_resume_early,
 686 };
 687
 688 static struct platform_driver fsl_edma_driver = {
 689         .driver         = {
 690                 .name   = "fsl-edma",
 691                 .of_match_table = fsl_edma_dt_ids,
 692                 .pm     = &fsl_edma_pm_ops,
 693         },
 694         .probe          = fsl_edma_probe,
 695         .remove_new     = fsl_edma_remove,
 696 };
 697
 698 static int __init fsl_edma_init(void)
 699 {
 700         return platform_driver_register(&fsl_edma_driver);
 701 }
 702 subsys_initcall(fsl_edma_init);
 703
 704 static void __exit fsl_edma_exit(void)
 705 {
 706         platform_driver_unregister(&fsl_edma_driver);
 707 }
 708 module_exit(fsl_edma_exit);
 709
 710 MODULE_ALIAS("platform:fsl-edma");
 711 MODULE_DESCRIPTION("Freescale eDMA engine driver");
 712 MODULE_LICENSE("GPL v2");