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2018-10-31	Palmer Dabbelt	lib: Remove umoddi3 and udivmoddi4 Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-31	Palmer Dabbelt	Move EM_RISCV into elf-em.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-31	Andreas Schwab	RISC-V: properly determine hardware caps Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-31	Palmer Dabbelt	Revert "lib: Add umoddi3 and udivmoddi4 of GCC library... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-31	Palmer Dabbelt	Revert "RISC-V: Select GENERIC_LIB_UMODDI3 on RV32" Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: SMP cleanup and new features Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Fix some RV32 bugs and build failures Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	riscv: Add support to no-FPU systems Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Nick Kossifidis	RISC-V: Cosmetic menuconfig changes Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Masahiro Yamada	riscv: move GCC version check for ARCH_SUPPORTS_INT128... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Christoph Hellwig	RISC-V: remove the unused return_to_handler export Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Jim Wilson	RISC-V: Add futex support. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Jim Wilson	RISC-V: Add FP register ptrace support for gdb. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Mask out the F extension on systems without D Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Don't set cacheinfo.{physical_line_partition... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Anup Patel	RISC-V: Show IPI stats Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Anup Patel	RISC-V: Show CPU ID and Hart ID separately in /proc... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Atish Patra	RISC-V: Use Linux logical CPU number instead of hartid Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Atish Patra	RISC-V: Add logical CPU indexing for RISC-V Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Atish Patra	RISC-V: Use WRITE_ONCE instead of direct access Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Use mmgrab() Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Rename riscv_of_processor_hart to riscv_of_processor... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Provide a cleaner raw_smp_processor_id() Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Atish Patra	RISC-V: Disable preemption before enabling interrupts Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Comment on the TLB flush in smp_callin() Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Filter ISA and MMU values in cpuinfo Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Palmer Dabbelt	RISC-V: Don't set cacheinfo.{physical_line_partition... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Anup Patel	RISC-V: No need to pass scause as arg to do_IRQ() Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Vincent Chen	RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Zong Li	RISC-V: Select GENERIC_LIB_UMODDI3 on RV32 Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Zong Li	lib: Add umoddi3 and udivmoddi4 of GCC library routines Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Zong Li	RISC-V: Use swiotlb on RV64 only Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Zong Li	RISC-V: Build tishift only on 64-bit Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Alan Kao	Auto-detect whether a FPU exists Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Alan Kao	Allow to disable FPU support Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Alan Kao	Cleanup ISA string setting Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Alan Kao	Refactor FPU code in signal setup/return procedures Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-23	Alan Kao	Extract FPU context operations from entry.S Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-10-02	Atish Patra	RISCV: Fix end PFN for low memory Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-09-24	James Cowgill	RISC-V: include linux/ftrace.h in asm-prototypes.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-09-05	Guenter Roeck	riscv: Do not overwrite initrd_start and initrd_end Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-28	Palmer Dabbelt	RISC-V: Use a less ugly workaround for unused variable... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-28	Will Deacon	riscv: tlb: Provide definition of tlb_flush() before... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-28	Palmer Dabbelt	dt-bindings: riscv,cpu-intc: Cleanups from a missed... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-20	Palmer Dabbelt	RISC-V: Fix sys_riscv_flush_icache	commit \| commitdiff \| tree
2018-08-20	Deepa Dinamani	riscv: Delete asm/compat.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-20	Palmer Dabbelt	RISC-V: Don't use a global include guard for uapi/asm... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-20	Palmer Dabbelt	RISC-V: Define sys_riscv_flush_icache when SMP=n Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Palmer Dabbelt	dt-bindings: interrupt-controller: SiFive Plaform Level... Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Palmer Dabbelt	dt-bindings: interrupt-controller: RISC-V local interrupt... Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Atish Patra	RISC-V: Fix !CONFIG_SMP compilation error Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Christoph Hellwig	irqchip: add a SiFive PLIC driver ...driver in the RISC-V tree from Palmer Dabbelt, Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Zong Li	RISC-V: Add the directive for alignment of stvec's... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Palmer Dabbelt	clocksource: new RISC-V SBI timer driver Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Christoph Hellwig	RISC-V: implement low-level interrupt handling Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Christoph Hellwig	RISC-V: add a definition for the SIE SEIE bit Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Christoph Hellwig	RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Christoph Hellwig	RISC-V: simplify software interrupt / IPI code Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Christoph Hellwig	RISC-V: remove timer leftovers Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Palmer Dabbelt	RISC-V: Add early printk support via the SBI console Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Jim Wilson	RISC-V: Don't increment sepc after breakpoint. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Alex Guo	RISC-V: implement __lshrti3. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-08-13	Palmer Dabbelt	RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-07-04	Palmer Dabbelt	RISC-V: Fix the rv32i kernel build	commit \| commitdiff \| tree
2018-07-04	Jim Wilson	RISC-V: Fix PTRACE_SETREGSET bug. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-07-04	Palmer Dabbelt	RISC-V: Don't include irq-riscv-intc.h Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-07-04	Rob Herring	riscv: remove unnecessary of_platform_populate call Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-07-04	Andreas Schwab	RISC-V: fix R_RISCV_ADD32/R_RISCV_SUB32 relocations Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-07-04	Zong Li	RISC-V: Change variable type for 32-bit compatible Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-07-04	Zong Li	RISC-V: Add definiion of extract symbol's index and... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-07-04	Zong Li	RISC-V: Select GENERIC_UCMPDI2 on RV32I Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-07-04	Zong Li	RISC-V: Add conditional macro for zone of DMA32 Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-11	Palmer Dabbelt	RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-11	Palmer Dabbelt	RISC-V: Make our port sparse-clean Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>	commit \| commitdiff \| tree
2018-06-11	Palmer Dabbelt	MAINTAINERS: RISC-V Updates Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-11	Andreas Schwab	RISC-V: Handle R_RISCV_32 in modules Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-11	Alan Kao	riscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-11	Luc Van Oostenryck	riscv: add riscv-specific predefines to CHECKFLAGS Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-09	Luc Van Oostenryck	riscv: split the declaration of __copy_user Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-07	Luc Van Oostenryck	riscv: no __user for probe_kernel_address() Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-07	Luc Van Oostenryck	riscv: use NULL instead of a plain 0 Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-04	Palmer Dabbelt	RISC-V: Preliminary Perf Support Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-04	Alan Kao	perf: riscv: Add Document for Future Porting Guide Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-04	Alan Kao	perf: riscv: preliminary RISC-V support Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-04	Palmer Dabbelt	MAINTAINERS: Update Albert's email, he's back at Berkeley Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-04	Palmer Dabbelt	MAINTAINERS: Add myself as a maintainer for SiFive... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-06-04	Alan Kao	riscv: Fix the bug in memory access fixup code Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-04-24	Aurelien Jarno	RISC-V: build vdso-dummy.o with -no-pie Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-04-24	Christoph Hellwig	riscv: there is no <asm/handle_irq.h> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-04-24	Christoph Hellwig	riscv: select DMA_DIRECT_OPS instead of redefining it Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-04-03	Palmer Dabbelt	RISC-V: Rename CONFIG_CMDLINE_OVERRIDE to CONFIG_CMDLINE_FORCE Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-04-03	Palmer Dabbelt	RISC-V: Fixes to module loading	commit \| commitdiff \| tree
2018-04-03	Palmer Dabbelt	RISC-V: Assorted memory model fixes	commit \| commitdiff \| tree
2018-04-03	Palmer Dabbelt	RISC-V: Add dynamic ftrace support for RISC-V platforms	commit \| commitdiff \| tree
2018-04-03	Zong Li	RISC-V: Add definition of relocation types Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-04-03	Zong Li	RISC-V: Enable module support in defconfig Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-04-03	Zong Li	RISC-V: Support SUB32 relocation type in kernel module Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-04-03	Zong Li	RISC-V: Support ADD32 relocation type in kernel module Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
2018-04-03	Zong Li	RISC-V: Support ALIGN relocation type in kernel module Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	commit \| commitdiff \| tree
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