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Merge branch 'drm-intel-next-queued' into gvt-next
2018-05-13 Zhi WangMerge branch 'drm-intel-next-queued' into gvt-next
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2018-03-19 Zhi Wangdrm/i915/gvt: Update PDPs after a vGPU mm object is...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2018-01-04 Zhi Wangdrm/i915/gvt: Clear the shadow page table entry after...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-12-06 Zhi Wangdrm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Refine broken PPGTT scratch
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Introduce ops->set_present()
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Introduce page table type of current...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Fix a bug of unexpectedly clear scratch...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Let the caller choose if a shadow page...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Use I915_GTT_PAGE_SIZE
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Factor intel_vgpu_page_track
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Refine find_bb_size()
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Use BIT() to make klockwork happy
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Move clean_workloads() into scheduler.c
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Introduce intel_vgpu_reset_submission
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Introduce vGPU submission ops
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Remove one extra declaration in scheduler.h
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Move common vGPU workload creation into...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Move common workload preparation into...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Factor out prepare_workload()
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Factor out vGPU workload creation/destroy
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Do not allocate initial ring scan buffer
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Move ring scan buffers into intel_vgpu_submission
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Rename reserved ring buffer
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Fix a memory leak in cmd_parser.c
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Move tlb_handle_pending into intel_vgpu_submission
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Introduce intel_vgpu_submission
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Move workload cache init/clean into intel_vgpu...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Rename intel_vgpu_{init, clean}_gvt_context()
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-11-16 Zhi Wangdrm/i915/gvt: Make elsp_dwords in the right order
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-10-26 Zhi Wangdrm/i915/gvt: Refine MMIO_RING_F()
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-09-18 Zhi Wangdrm/i915: Return the correct score in i915_ppat_get()
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1505741794-10593-1-git-send-email-zhi.a.wang@intel.com
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2017-09-14 Zhi Wangdrm/i915: Remove the "INDEX" suffix from PPAT marcos
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1505392783-4084-2-git-send-email-zhi.a.wang@intel.com
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2017-09-14 Zhi Wangdrm/i915: Introduce private PAT management
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1505392783-4084-1-git-send-email-zhi.a.wang@intel.com
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2017-09-12 Zhi Wangdrm/i915: Factor out setup_private_pat()
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1505202148-22959-1-git-send-email-zhi.a.wang@intel.com
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2017-09-05 Zhi Wangdrm/i915: Fix the missing PPAT cache attributes on CNL
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1504208177-27784-1-git-send-email-zhi.a.wang@intel.com
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2017-09-02 Zhi Wangdrm/i915: Fix the missing PPAT cache attributes on CNL
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1504208177-27784-1-git-send-email-zhi.a.wang@intel.com
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2017-04-01 Zhi Wangdrm/i915/gvt: Fix firmware loading interface for GVT...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-03-30 Zhi Wangdrm/i915/gvt: Activate/de-activate vGPU in mdev ops.
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2017-02-16 Zhi Wangdrm/i915: A hotfix for making aliasing PPGTT work for...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1486559013-25251-2-git-send-email-zhi.a.wang@intel.com
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2017-02-16 Zhi Wangdrm/i915: Let execlist_update_context() cover !FULL_PPGTT...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1486377436-15380-1-git-send-email-zhi.a.wang@intel.com
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2017-02-09 Zhi Wangdrm/i915: A hotfix for making aliasing PPGTT work for...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1486559013-25251-2-git-send-email-zhi.a.wang@intel.com
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2017-02-06 Zhi Wangdrm/i915: Let execlist_update_context() cover !FULL_PPGTT...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1486377436-15380-1-git-send-email-zhi.a.wang@intel.com
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2016-11-29 Zhi Wangdrm/i915: Move the release of PT page to the upper...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1479728666-25333-1-git-send-email-zhi.a.wang@intel.com
...1480402516-22275-1-git-send-email-zhi.a.wang@intel.com
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2016-10-14 Zhi Wangdrm/i915/gvt: Support GVT-g on Skylake
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU command scanner
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU context switch
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU schedule policy framework
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU workload scheduler
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU workload submission
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU execlist virtualization
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU display virtualization
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU MMIO virtualization
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU PCI configuration space virtualization
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU graphics memory virtualization
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU interrupt virtualization.
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: trace stub
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: Introduce basic vGPU life cycle management
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: golden virtual HW state management
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: Introduce a framework for tracking HW...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-10-14 Zhi Wangdrm/i915/gvt: vGPU HW resource management
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-09-06 Zhi Wangdrm/i915: disable 48bit full PPGTT when vGPU is active
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-09-06 Zhi Wangdrm/i915: disable 48bit full PPGTT when vGPU is active
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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2016-06-21 Zhi Wangdrm/i915: Set the access right of kernel param "i915...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466425022-3709-1-git-send-email-zhi.a.wang@intel.com
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2016-06-17 Zhi Wangdrm/i915: Introduce GVT context creation API
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466078825-6662-10-git-send-email-zhi.a.wang@intel.com
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2016-06-17 Zhi Wangdrm/i915: Support LRC context single submission
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466078825-6662-9-git-send-email-zhi.a.wang@intel.com
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2016-06-17 Zhi Wangdrm/i915: Introduce execlist context status change...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466078825-6662-8-git-send-email-zhi.a.wang@intel.com
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2016-06-17 Zhi Wangdrm/i915: Make addressing mode bits in context descriptor...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466078825-6662-7-git-send-email-zhi.a.wang@intel.com
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2016-06-17 Zhi Wangdrm/i915: Make ring buffer size of a LRC context configurable
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466078825-6662-6-git-send-email-zhi.a.wang@intel.com
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2016-06-17 Zhi Wangdrm/i915: gvt: Introduce the basic architecture of...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466078825-6662-5-git-send-email-zhi.a.wang@intel.com
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2016-06-17 Zhi Wangdrm/i915: Fold vGPU active check into inner functions
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466078825-6662-4-git-send-email-zhi.a.wang@intel.com
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2016-06-17 Zhi Wangdrm/i915: Use offsetof() to calculate the offset of...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466078825-6662-3-git-send-email-zhi.a.wang@intel.com
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2016-06-17 Zhi Wangdrm/i915: Factor out i915_pvinfo.h
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
...1466078825-6662-2-git-send-email-zhi.a.wang@intel.com
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2015-02-13 Zhi Wangdrm/i915: Introduce bit definitions of CTXT_SR_CTRL...
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
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