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drm/dsc: Modify DRM helper to return complete DSC color depth capabilities
2018-11-27 Manasi Navaredrm/dsc: Modify DRM helper to return complete DSC color...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181127214125.17658-1-manasi.d.navare@intel.com
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2018-11-06 Manasi Navaredrm/i915/icl: Fix the macros for DFLEXDPMLE register...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181023191248.26418-1-manasi.d.navare@intel.com
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2018-10-31 Manasi Navaredrm/i915/ICL: Add pre_pll_enable hook for ICL and set...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181023191248.26418-2-manasi.d.navare@intel.com
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2018-10-31 Manasi Navaredrm/i915/icl: Fix the macros for DFLEXDPMLE register...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181023191248.26418-1-manasi.d.navare@intel.com
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2018-10-31 Manasi Navaredrm/dp: Define payload size for DP SDP PPS packet
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181031001923.31442-7-manasi.d.navare@intel.com
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2018-10-31 Manasi Navaredrm/i915/dp: Validate modes using max Output BPP and...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181031001923.31442-6-manasi.d.navare@intel.com
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2018-10-31 Manasi Navaredrm/i915/dp: Add helpers for Compressed BPP and Slice...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181031001923.31442-5-manasi.d.navare@intel.com
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2018-10-31 Manasi Navaredrm/dp: DRM DP helper/macros to get DP sink DSC parameters
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181031001923.31442-4-manasi.d.navare@intel.com
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2018-10-31 Manasi Navaredrm/i915/dp: Cache the DP/eDP DSC DPCD register set...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181031001923.31442-3-manasi.d.navare@intel.com
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2018-10-31 Manasi Navaredrm/dp: Add DP DSC DPCD receiver capability size define...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181031001923.31442-2-manasi.d.navare@intel.com
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2018-10-20 Manasi Navaredrm/dp: Add definitions for eDP Rev 1.4a and 1.4b
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181009002351.23085-1-manasi.d.navare@intel.com
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2018-10-18 Manasi Navaredrm/i915/dp: Link train Fallback on eDP only if fallback...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181009212804.702-1-manasi.d.navare@intel.com
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2018-10-09 Manasi Navaredrm/i915/dp: Link train Fallback on eDP only if fallback...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181009212804.702-1-manasi.d.navare@intel.com
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2018-10-03 Manasi Navaredrm: Fix kernel doc for DRM_MODE_PROP_IMMUTABLE
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20181002215055.8652-1-manasi.d.navare@intel.com
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2018-09-04 Manasi Navaredrm/i915/dsc: Fix PPS register definition macros for...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20180824014807.14681-1-manasi.d.navare@intel.com
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2018-08-28 Manasi Navaredrm/i915/dsc: Fix PPS register definition macros for...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...msgid/20180824014807.14681-1-manasi.d.navare@intel.com
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2018-08-20 Manasi Navaredrm/i915/icl: Get DDI clock for ICL for MG PLL and...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-08-20 Manasi Navaredrm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_P...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-07-24 Manasi Navaredrm/i915/icl: Implement voltage swing programming sequence...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1530225344-20373-2-git-send-email-manasi.d.navare@intel.com
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2018-07-24 Manasi Navaredrm/i915/icl: Add remaining registers and bitfields...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1531510993-6606-1-git-send-email-manasi.d.navare@intel.com
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2018-06-14 Manasi Navaredrm/i915/dp: Add support for HBR3 and TPS4 during link...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-06-14 Manasi Navaredrm/i915/icl: Add allowed DP rates for Icelake
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-06-12 Manasi Navaredrm/i915/icl: Add DDI HDMI level selection for ICL
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-06-01 Manasi Navaredrm/i915/icl: Get DDI clock for ICL based on PLLs.
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-06-01 Manasi Navaredrm/i915/icl: Add register definition for DFLEXDPMLE
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1527275032-4555-1-git-send-email-manasi.d.navare@intel.com
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2018-04-30 Manasi Navaredrm/i915/icl: Fix the DP Max Voltage for ICL
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-04-30 Manasi Navaredrm/i915/icl: Implement voltage swing programming sequence...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-04-27 Manasi Navaredrm/dp: Rename the edp_sdp_header as dp_sdp_header
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1524770868-16869-1-git-send-email-manasi.d.navare@intel.com
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2018-03-23 Manasi Navaredrm/i915/icl: Add Voltage swing table for MG PHY DDI...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-03-23 Manasi Navaredrm/i915/icl: Add register defs for voltage swing sequences...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-03-23 Manasi Navaredrm/i915/icl: Add Combo PHY DDI Buffer translation...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-03-23 Manasi Navaredrm/i915/icl: Add register definitions for Combo PHY...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2018-03-01 Manasi Navaredrm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1519857110-26916-1-git-send-email-manasi.d.navare@intel.com
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2018-02-27 Manasi Navaredrm/i915/dp: Fix the order of platforms for setting...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1519701075-9894-1-git-send-email-manasi.d.navare@intel.com
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2018-02-01 Manasi Navaredrm/i915/edp: Do not do link training fallback or prune...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1507835618-23051-1-git-send-email-manasi.d.navare@intel.com
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2018-01-26 Manasi Navaredrm/dp: Add definitions for TPS4 bits and macros to...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1516660991-20697-2-git-send-email-manasi.d.navare@intel.com
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2018-01-26 Manasi Navaredrm/dp: Add HBR3 support in existing DRM DP helpers
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1516660991-20697-1-git-send-email-manasi.d.navare@intel.com
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2018-01-22 Manasi Navaredrm/i915/edp: Do not do link training fallback or prune...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1507835618-23051-1-git-send-email-manasi.d.navare@intel.com
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2017-10-30 Manasi Navaredrm/i915: Cancel the modeset retry work during modeset...
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1509054720-25325-1-git-send-email-manasi.d.navare@intel.com
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2017-10-26 Manasi Navaredrm/i915: Cancel the modeset retry work during modeset...
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1509054720-25325-1-git-send-email-manasi.d.navare@intel.com
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2017-10-09 Manasi Navaredrm/i915/edp: Increase the T12 delay quirk to 1300ms
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1507073845-13420-2-git-send-email-manasi.d.navare@intel.com
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2017-10-09 Manasi Navaredrm/i915/edp: Get the Panel Power Off timestamp after...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1507135706-17147-1-git-send-email-manasi.d.navare@intel.com
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2017-10-05 Manasi Navaredrm/i915/edp: Increase the T12 delay quirk to 1300ms
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1507073845-13420-2-git-send-email-manasi.d.navare@intel.com
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2017-10-05 Manasi Navaredrm/i915/edp: Get the Panel Power Off timestamp after...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1507135706-17147-1-git-send-email-manasi.d.navare@intel.com
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2017-09-14 Manasi Navaredrm/i915/cnl: Change the macro name to DPLL_CFGCR0_DCO_FRACT...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1505413899-30876-1-git-send-email-manasi.d.navare@intel.com
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2017-09-01 Manasi Navaredrm/i915/edp: Increase T12 panel delay to 900 ms to...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1502823591-25310-1-git-send-email-manasi.d.navare@intel.com
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2017-08-31 Manasi Navaredrm/i915/edp: Increase T12 panel delay to 900 ms to...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1502823591-25310-1-git-send-email-manasi.d.navare@intel.com
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2017-08-15 Manasi Navaredrm/i915/dp: Validate the compliance test link parameters
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1496954463-18038-2-git-send-email-manasi.d.navare@intel.com
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2017-08-15 Manasi Navaredrm/i915/dp: Generalize intel_dp_link_params function...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1496954463-18038-1-git-send-email-manasi.d.navare@intel.com
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2017-07-27 Navare, Manasi Ddrm/i915/cnl: Fix loadgen select programming on ddi...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1500329122-32662-1-git-send-email-manasi.d.navare@intel.com
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2017-07-27 Navare, Manasi Ddrm/i915/cnl: Fix loadgen select programming on ddi...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1500329122-32662-1-git-send-email-manasi.d.navare@intel.com
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2017-07-04 Manasi Navaredrm/i915/edp: Add a T12 panel delay quirk to fix DP...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1498840428-23176-1-git-send-email-manasi.d.navare@intel.com
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2017-07-03 Navare, Manasi Ddrm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1498785241-21138-1-git-send-email-manasi.d.navare@intel.com
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2017-06-30 Navare, Manasi Ddrm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1498785241-21138-1-git-send-email-manasi.d.navare@intel.com
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2017-06-27 Manasi Navaredrm/i915/dp: Remove -1/+1 from t11_t12 for Gen9_LP...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1498504905-21067-2-git-send-email-manasi.d.navare@intel.com
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2017-06-27 Manasi Navaredrm/i915/dp: Fix the t11_t12 panel power cycle delay...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1498504905-21067-1-git-send-email-manasi.d.navare@intel.com
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2017-04-20 Navare, Manasi Ddrm: Add DPCD definitions for DP 1.4 DSC feature
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1491259870-25613-1-git-send-email-manasi.d.navare@intel.com
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2017-04-13 Manasi Navaredrm/i915: Implement Link Rate fallback on Link training...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2017-04-12 Manasi Navaredrm/i915/dp: Validate cached link rate and lane count...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1491512412-30016-1-git-send-email-manasi.d.navare@intel.com
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2017-03-01 Manasi Navaredrm/i915: Implement Link Rate fallback on Link training...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2017-03-01 Manasi Navaredrm: Fix the kernel doc warning for drm_link_status
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1488379510-15059-1-git-send-email-manasi.d.navare@intel.com
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2017-02-27 Manasi Navaredrm: Add a new connector atomic property for link status
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2017-02-15 Manasi Navaredrm/i915/dp: Reset the link params on HPD/connected...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1486515251-23469-1-git-send-email-manasi.d.navare@intel.com
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2017-01-26 Manasi Navaredrm/i915: Add support for DP Video pattern compliance...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1485274909-17470-1-git-send-email-manasi.d.navare@intel.com
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2017-01-26 Manasi Navaredrm: Add definitions for DP compliance Video pattern...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1484968170-12467-4-git-send-email-manasi.d.navare@intel.com
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2017-01-26 Manasi Navaredrm/i915: Fixes to support DP Compliance EDID tests
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1484968170-12467-3-git-send-email-manasi.d.navare@intel.com
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2017-01-26 Manasi Navaredrm/i915: Add support for DP link training compliance
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1485274594-17361-1-git-send-email-manasi.d.navare@intel.com
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2016-12-13 Manasi Navaredrm/i915: Move all the DP compliance data to a separate...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1481329371-16306-1-git-send-email-manasi.d.navare@intel.com
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2016-12-13 Manasi Navaredrm/i915: Find fallback link rate/lane count
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1481252712-12925-1-git-send-email-manasi.d.navare@intel.com
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2016-12-13 Manasi Navaredrm/i915: Compute sink's max lane count/link BW at...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1480984058-552-3-git-send-email-manasi.d.navare@intel.com
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2016-10-28 Navare, Manasi Ddrm/i915: Change the placement of some static functions...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1477524358-16563-4-git-send-email-manasi.d.navare@intel.com
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2016-09-28 Navare, Manasi Ddrm/i915: Code cleanup to use dev_priv and INTEL_GEN
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1475019413-19811-1-git-send-email-manasi.d.navare@intel.com
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2016-09-13 Navare, Manasi Ddrm/i915: Add support for Kabylake to function obtaining...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
...1473728663-14355-1-git-send-email-manasi.d.navare@intel.com
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2016-09-09 Navare, Manasi Ddrm/i915: Make DP link training channel equalization...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2016-09-07 Manasi Navaredrm/i915: Split hsw_get_dpll()
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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2016-09-07 Manasi Navaredrm/i915: Split intel_ddi_pre_enable() into DP and...
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
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