sfrench/cifs-2.6.git
5 years agoclk: fix comment of devm_clk_hw_register()
Masahiro Yamada [Sun, 1 May 2016 10:56:08 +0000 (19:56 +0900)]
clk: fix comment of devm_clk_hw_register()

Unlike devm_clk_register(), devm_clk_hw_register() returns integer.
So, the statement "Clocks returned from this function ..." sounds
odd.  Adjust the comment for this new API.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoMerge tag 'clk-renesas-for-v4.7-tag3' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Tue, 3 May 2016 00:05:23 +0000 (17:05 -0700)]
Merge tag 'clk-renesas-for-v4.7-tag3' of git://git./linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Support for CSI2 and VIN module clocks on R-Car H3,
  - Renesas CPG/MSTP and CPG/MSSR Clock Domain fixes.

* tag 'clk-renesas-for-v4.7-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Use always-on governor for Clock Domain
  clk: renesas: cpg-mssr: Postpone call to pm_genpd_init()
  clk: renesas: mstp: Use always-on governor for Clock Domain
  clk: renesas: mstp: Postpone call to pm_genpd_init()
  clk: renesas: r8a7795: Add VIN clocks
  clk: renesas: r8a7795: Add CSI2 clocks

5 years agoMerge tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git...
Stephen Boyd [Tue, 3 May 2016 00:03:08 +0000 (17:03 -0700)]
Merge tag 'sunxi-clocks-for-4.7' of https://git./linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock driver updates from Maxime Ripard:

As usual, a bunch of clocks patches for 4.7, mostly fixes and cleanups, and
display-related clocks.

* tag 'sunxi-clocks-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi: Let divs clocks read the base factor clock name from devicetree
  clk: sunxi: Add TCON channel1 clock
  clk: sunxi: Add PLL3 clock
  dt-bindings: clk: sun5i: add DRAM gates compatible
  clk: sunxi: Use resource_size
  clk: sunxi: Add sun6i/8i display support
  clk: sunxi: mod1 clock should modify it's parent

5 years agoMerge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra...
Stephen Boyd [Mon, 2 May 2016 23:53:02 +0000 (16:53 -0700)]
Merge tag 'tegra-for-4.7-clk' of git://git./linux/kernel/git/tegra/linux into clk-next

Pull tegra clk driver changes from Thierry Reding:

This set of changes contains a bunch of cleanups and minor fixes along
with some new clocks, mainly on Tegra210, in preparation for supporting
DisplayPort and HDMI 2.0.

* tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: dfll: Reformat CVB frequency table
  clk: tegra: dfll: Properly clean up on failure and removal
  clk: tegra: dfll: Make code more comprehensible
  clk: tegra: dfll: Reference CVB table instead of copying data
  clk: tegra: dfll: Update kerneldoc
  clk: tegra: Fix PLL_U post divider and initial rate on Tegra30
  clk: tegra: Initialize PLL_C to sane rate on Tegra30
  clk: tegra: Fix pllre Tegra210 and add pll_re_out1
  clk: tegra: Add sor_safe clock
  clk: tegra: dpaux and dpaux1 are fixed factor clocks
  clk: tegra: Add dpaux1 clock
  clk: tegra: Use correct parent for dpaux clock
  clk: tegra: Add fixed factor peripheral clock type
  clk: tegra: Special-case mipi-cal parent on Tegra114
  clk: tegra: Remove trailing blank line
  clk: tegra: Constify peripheral clock registers
  clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs

5 years agoMerge tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind...
Stephen Boyd [Mon, 2 May 2016 23:43:03 +0000 (16:43 -0700)]
Merge tag 'v4.7-rockchip-clk3' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk updates from Heiko Stuebner:

A spelling fix and a bunch of rk3399 clock fixes.

* tag 'v4.7-rockchip-clk3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix the rk3399 cifout clock
  clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
  clk: rockchip: add some frequencies on the rk3399 PLL table
  clk: rockchip: assign more necessary rk3399 clock ids
  clk: rockchip: export some necessary rk3399 clock ids
  clk: rockchip: rename rga clock-id on rk3399
  clk: rockchip: add general gpu soft-reset on rk3399
  clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
  clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type

5 years agoclk: tegra: dfll: Reformat CVB frequency table
Thierry Reding [Fri, 8 Apr 2016 13:17:27 +0000 (15:17 +0200)]
clk: tegra: dfll: Reformat CVB frequency table

Increase the readability of the CVB frequency table by reformatting it a
little.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: dfll: Properly clean up on failure and removal
Thierry Reding [Fri, 8 Apr 2016 13:16:28 +0000 (15:16 +0200)]
clk: tegra: dfll: Properly clean up on failure and removal

Upon failure to probe the DFLL, the OPP table will not be cleaned up
properly. Fix this and while at it make sure the OPP table will also be
cleared upon driver removal.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: dfll: Make code more comprehensible
Thierry Reding [Fri, 8 Apr 2016 13:09:56 +0000 (15:09 +0200)]
clk: tegra: dfll: Make code more comprehensible

Rename some variables and structure fields to make the code more
comprehensible. Also change the prototype of internal functions to be
more in line with the OPP core functions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: dfll: Reference CVB table instead of copying data
Thierry Reding [Fri, 8 Apr 2016 13:02:06 +0000 (15:02 +0200)]
clk: tegra: dfll: Reference CVB table instead of copying data

Instead of copying parts of the CVB table into a separate structure,
keep track of the selected CVB table and directly reference data from
it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: dfll: Update kerneldoc
Thierry Reding [Fri, 8 Apr 2016 12:57:09 +0000 (14:57 +0200)]
clk: tegra: dfll: Update kerneldoc

The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to
match the current structure definition.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Fix PLL_U post divider and initial rate on Tegra30
Lucas Stach [Mon, 29 Feb 2016 20:46:07 +0000 (21:46 +0100)]
clk: tegra: Fix PLL_U post divider and initial rate on Tegra30

The post divider value in the frequency table is wrong as it would lead
to the PLL producing an output rate of 960 MHz instead of the desired
480 MHz. This wasn't a problem as nothing used the table to actually
initialize the PLL rate, but the bootloader configuration was used
unaltered.

If the bootloader does not set up the PLL it will fail to come when used
under Linux. To fix this don't rely on the bootloader, but set the
correct rate in the clock driver.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Initialize PLL_C to sane rate on Tegra30
Lucas Stach [Mon, 29 Feb 2016 20:46:06 +0000 (21:46 +0100)]
clk: tegra: Initialize PLL_C to sane rate on Tegra30

If the bootloader does not touch PLL_C it will stay in its reset state,
failing to lock when enabled. This leads to consumers of this clock to
fail probing. Fix this by always programming the PLL with a sane rate,
which allows it to lock, at startup.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Fix pllre Tegra210 and add pll_re_out1
Rhyland Klein [Mon, 21 Mar 2016 19:58:52 +0000 (15:58 -0400)]
clk: tegra: Fix pllre Tegra210 and add pll_re_out1

Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.

Additionally define PLL_RE_OUT1 on Tegra210.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: define PLLRE_OUT1 register offset]
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Add sor_safe clock
Thierry Reding [Mon, 20 Apr 2015 13:13:36 +0000 (15:13 +0200)]
clk: tegra: Add sor_safe clock

The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: dpaux and dpaux1 are fixed factor clocks
Thierry Reding [Mon, 20 Apr 2015 13:10:43 +0000 (15:10 +0200)]
clk: tegra: dpaux and dpaux1 are fixed factor clocks

The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Add dpaux1 clock
Thierry Reding [Mon, 20 Apr 2015 13:05:33 +0000 (15:05 +0200)]
clk: tegra: Add dpaux1 clock

This clock is of the same type as dpaux and is added to feed into the
second DPAUX block used in conjunction with SOR1.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Use correct parent for dpaux clock
Thierry Reding [Mon, 20 Apr 2015 12:47:25 +0000 (14:47 +0200)]
clk: tegra: Use correct parent for dpaux clock

The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Add fixed factor peripheral clock type
Thierry Reding [Mon, 20 Apr 2015 12:34:57 +0000 (14:34 +0200)]
clk: tegra: Add fixed factor peripheral clock type

Some of the peripheral clocks on Tegra are derived from one of the top-
level PLLs with a fixed factor. Support these clocks by implementing the
->enable() and ->disable() callbacks using the peripheral clock register
banks and the ->recalc_rate() by dividing the parent rate by the fixed
factor.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Special-case mipi-cal parent on Tegra114
Thierry Reding [Wed, 8 Apr 2015 14:48:26 +0000 (16:48 +0200)]
clk: tegra: Special-case mipi-cal parent on Tegra114

Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its
source. On Tegra114 this clock's parent was clk_m, so it is the one-off
chip.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Remove trailing blank line
Thierry Reding [Mon, 20 Apr 2015 13:26:42 +0000 (15:26 +0200)]
clk: tegra: Remove trailing blank line

Trailing blank lines are undesirable (several tools, such as git,
complain about them), so remove it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Constify peripheral clock registers
Thierry Reding [Mon, 20 Apr 2015 12:38:39 +0000 (14:38 +0200)]
clk: tegra: Constify peripheral clock registers

The peripheral clock registers are defined in static tables. These
tables never need to be modified at runtime, so they can reside in
read-only memory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
Andrew Bresticker [Thu, 18 Jun 2015 21:28:40 +0000 (17:28 -0400)]
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs

On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence.  Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 years agoclk: renesas: cpg-mssr: Use always-on governor for Clock Domain
Geert Uytterhoeven [Fri, 22 Apr 2016 12:59:10 +0000 (14:59 +0200)]
clk: renesas: cpg-mssr: Use always-on governor for Clock Domain

As a pure Clock Domain does not have the concept of powering the domain
itself, the CPG/MSTP driver does not provide power_off() and power_on()
callbacks.
However, the genpd core may still perform a dummy power down, causing
/sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's
status being "off-0".

Use the always-on governor to make sure the domain is never powered
down, and always shows up as "on" in pm_genpd_summary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agoclk: renesas: cpg-mssr: Postpone call to pm_genpd_init()
Geert Uytterhoeven [Fri, 22 Apr 2016 12:46:51 +0000 (14:46 +0200)]
clk: renesas: cpg-mssr: Postpone call to pm_genpd_init()

All local setup of the generic_pm_domain structure should have been
completed before calling pm_genpd_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agoclk: renesas: mstp: Use always-on governor for Clock Domain
Geert Uytterhoeven [Fri, 22 Apr 2016 12:57:29 +0000 (14:57 +0200)]
clk: renesas: mstp: Use always-on governor for Clock Domain

As a pure Clock Domain does not have the concept of powering the domain
itself, the CPG/MSTP driver does not provide power_off() and power_on()
callbacks.
However, the genpd core may still perform a dummy power down, causing
/sys/kernel/debug/pm_genpd/pm_genpd_summary to report the domain's
status being "off-0".

Use the always-on governor to make sure the domain is never powered
down, and always shows up as "on" in pm_genpd_summary.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agoclk: renesas: mstp: Postpone call to pm_genpd_init()
Geert Uytterhoeven [Fri, 22 Apr 2016 12:45:45 +0000 (14:45 +0200)]
clk: renesas: mstp: Postpone call to pm_genpd_init()

All local setup of the generic_pm_domain structure should have been
completed before calling pm_genpd_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
5 years agoclk: renesas: r8a7795: Add VIN clocks
Niklas Söderlund [Mon, 25 Apr 2016 11:39:20 +0000 (13:39 +0200)]
clk: renesas: r8a7795: Add VIN clocks

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 years agoclk: renesas: r8a7795: Add CSI2 clocks
Niklas Söderlund [Mon, 25 Apr 2016 11:39:19 +0000 (13:39 +0200)]
clk: renesas: r8a7795: Add CSI2 clocks

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 years agoclk: rockchip: fix the rk3399 cifout clock
Xing Zheng [Wed, 20 Apr 2016 11:11:32 +0000 (19:11 +0800)]
clk: rockchip: fix the rk3399 cifout clock

The cifout clock is incorrect due to the manual error, we need to
fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399
Xing Zheng [Wed, 20 Apr 2016 11:06:51 +0000 (19:06 +0800)]
clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399

We don't need to many clocks enable after startup, to reduce some
power consumption.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: add some frequencies on the rk3399 PLL table
Xing Zheng [Wed, 20 Apr 2016 11:06:50 +0000 (19:06 +0800)]
clk: rockchip: add some frequencies on the rk3399 PLL table

This patch add some necessary frequencies for the RK3399 clock.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: assign more necessary rk3399 clock ids
Xing Zheng [Wed, 20 Apr 2016 11:06:49 +0000 (19:06 +0800)]
clk: rockchip: assign more necessary rk3399 clock ids

Assign newly added clock ids.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoMerge branch 'v4.7-shared/clkids' into v4.7-clk/next
Heiko Stuebner [Mon, 25 Apr 2016 20:48:19 +0000 (22:48 +0200)]
Merge branch 'v4.7-shared/clkids' into v4.7-clk/next

5 years agoclk: rockchip: export some necessary rk3399 clock ids
Xing Zheng [Wed, 20 Apr 2016 11:06:49 +0000 (19:06 +0800)]
clk: rockchip: export some necessary rk3399 clock ids

We export some clock IDs for the reference drivers need them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: rename rga clock-id on rk3399
Xing Zheng [Wed, 20 Apr 2016 11:06:49 +0000 (19:06 +0800)]
clk: rockchip: rename rga clock-id on rk3399

The rga clock supplying the working clock on the rk3399 is actually
called rga-core in the manual. As the clock id has neither been
assigned nor released with a full kernel release, we can still change
the id to the more appropriate naming.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: add general gpu soft-reset on rk3399
Xing Zheng [Wed, 20 Apr 2016 11:06:49 +0000 (19:06 +0800)]
clk: rockchip: add general gpu soft-reset on rk3399

Add the id for the general gpu soft-reset, that got documented only in
newer TRM versions.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399
Xing Zheng [Wed, 20 Apr 2016 11:12:10 +0000 (19:12 +0800)]
clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399

The gate bits of the i2c4 and i2c8 are incorrect due to the manual
error, we need to fix them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: sunxi: Let divs clocks read the base factor clock name from devicetree
Jens Kuske [Fri, 18 Mar 2016 09:44:15 +0000 (09:44 +0000)]
clk: sunxi: Let divs clocks read the base factor clock name from devicetree

Currently, the sunxi clock driver gets the name for the base factor clock
of divs clocks from the name field in factors_data. This prevents reusing
of the factor clock for clocks with same properties, but different name.

This commit makes the divs setup function try to get a name from
clock-output-names in the devicetree. It also removes the name field where
possible and merges the sun4i PLL5 and PLL6 clocks.

[Andre: Make temporary name allocation dynamic.]

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: rockchip: fix of spelling mistake on unsuccessful in pll clock type
Colin Ian King [Sun, 24 Apr 2016 22:44:13 +0000 (23:44 +0100)]
clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type

fix spelling mistake, unsucessful -> unsuccessful

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: sunxi: Add TCON channel1 clock
Maxime Ripard [Wed, 1 Jul 2015 13:48:37 +0000 (15:48 +0200)]
clk: sunxi: Add TCON channel1 clock

The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.

It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).

Add a driver for the channel 1 clock.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: sunxi: Add PLL3 clock
Maxime Ripard [Wed, 23 Mar 2016 16:38:26 +0000 (17:38 +0100)]
clk: sunxi: Add PLL3 clock

The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)

Add a driver for it.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agodt-bindings: clk: sun5i: add DRAM gates compatible
Maxime Ripard [Wed, 23 Mar 2016 16:38:28 +0000 (17:38 +0100)]
dt-bindings: clk: sun5i: add DRAM gates compatible

The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).

Use a simple gates driver to support the one found in the A13 / R8 SoCs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: sunxi: Use resource_size
Vaishali Thakkar [Mon, 11 Apr 2016 04:53:03 +0000 (10:23 +0530)]
clk: sunxi: Use resource_size

Use the function resource_size instaed of explicit computation.

Problem found using Coccinelle.

Signed-off-by: Vaishali Thakkar <vaishali.thakkar@oracle.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: sunxi: Add sun6i/8i display support
Jean-Francois Moine [Wed, 30 Mar 2016 16:43:29 +0000 (18:43 +0200)]
clk: sunxi: Add sun6i/8i display support

Add the clock type which is used by the sun6i/8i families for video display.

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: sunxi: mod1 clock should modify it's parent
Andrea Venturi [Mon, 21 Mar 2016 16:10:38 +0000 (17:10 +0100)]
clk: sunxi: mod1 clock should modify it's parent

add CLK_SET_RATE_PARENT to modify the rate on clk upstream

Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoMerge branch 'clk-hw-register' (early part) into clk-next
Stephen Boyd [Thu, 21 Apr 2016 21:47:18 +0000 (14:47 -0700)]
Merge branch 'clk-hw-register' (early part) into clk-next

* 'clk-hw-register' (early part):
  clk: fixed-rate: Add hw based registration APIs
  clk: gpio: Add hw based registration APIs
  clk: composite: Add hw based registration APIs
  clk: fractional-divider: Add hw based registration APIs
  clk: fixed-factor: Add hw based registration APIs
  clk: mux: Add hw based registration APIs
  clk: gate: Add hw based registration APIs
  clk: divider: Add hw based registration APIs
  clkdev: Add clk_hw based registration APIs
  clk: Add clk_hw OF clk providers
  clk: Add {devm_}clk_hw_{register,unregister}() APIs
  clkdev: Remove clk_register_clkdevs()

5 years agoMerge branch 'clk-composite-unregister' into clk-next
Stephen Boyd [Thu, 21 Apr 2016 21:43:56 +0000 (14:43 -0700)]
Merge branch 'clk-composite-unregister' into clk-next

* clk-composite-unregister:
  clk: composite: Add unregister function

5 years agoclk: composite: Add unregister function
Maxime Ripard [Wed, 23 Mar 2016 16:38:24 +0000 (17:38 +0100)]
clk: composite: Add unregister function

The composite clock didn't have any unregistration function, which forced
us to use clk_unregister directly on it.

While it was already not great from an API point of view, it also meant
that we were leaking the clk_composite structure allocated in
clk_register_composite.

Add a clk_unregister_composite function to fix this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agodt-bindings: Add Oxford Semiconductor OXNAS Standard Clocks bindings
Neil Armstrong [Mon, 18 Apr 2016 10:01:36 +0000 (12:01 +0200)]
dt-bindings: Add Oxford Semiconductor OXNAS Standard Clocks bindings

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: Add Oxford Semiconductor OXNAS Standard Clocks
Neil Armstrong [Mon, 18 Apr 2016 10:01:35 +0000 (12:01 +0200)]
clk: Add Oxford Semiconductor OXNAS Standard Clocks

Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: Drop NULL/continue check in registration
loop]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoMerge tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Wed, 20 Apr 2016 18:44:03 +0000 (11:44 -0700)]
Merge tag 'clk-renesas-for-v4.7-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into clk-next

clk: renesas: R-Car SYSC PM Domain Preparation

  - Export the CPG/MSSR and CPG/MSTP attach/detach_dev callbacks, so
    they can be called by the R-Car SYSC PM Domain driver.

* tag 'clk-renesas-for-v4.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
  clk: renesas: mstp: Provide dummy attach/detach_dev callbacks
  clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support

5 years agoMerge tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind...
Stephen Boyd [Wed, 20 Apr 2016 18:41:37 +0000 (11:41 -0700)]
Merge tag 'v4.7-rockchip-clk2' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next

Pull some checkpatch silencers from Heiko Stuebner:

Fix quite some checkpatch warnings in the newly added
rk3399 header and also in the clock code itself.

* tag 'v4.7-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: fix checkpatch warning in core code
  clk: rockchip: drop unnecessary header comment
  clk: rockchip: reign in some overly long lines in the rk3399 controller
  clk: rockchip: fix checkpatch errors in rk3399 dt-binding header

5 years agoclk: rockchip: fix checkpatch warning in core code
Heiko Stuebner [Tue, 19 Apr 2016 19:29:27 +0000 (21:29 +0200)]
clk: rockchip: fix checkpatch warning in core code

We seem to have accumulated a bunch of checkpatch warnings, with mainly
overlong lines and two unnecessary allocation error messages.
Most were introduced with the recent multi-controller-support but some
were quite a bit older.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()
Geert Uytterhoeven [Fri, 4 Mar 2016 16:03:46 +0000 (17:03 +0100)]
clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()

The R-Car SYSC PM Domain driver has to power manage devices in power
areas using clocks. To reuse code and to share knowledge of clocks
suitable for power management, this is ideally done through the existing
cpg_mssr_attach_dev() and cpg_mssr_detach_dev() callbacks.

Hence these callbacks can no longer rely on their "domain" parameter
pointing to the CPG/MSSR Clock Domain. To handle this, keep a pointer to
the clock domain in a static variable. cpg_mssr_attach_dev() has to
support probe deferral, as the R-Car SYSC PM Domain may be initialized,
and devices may be added to it, before the CPG/MSSR Clock Domain is
initialized.

Dummy callbacks are provided for the case where CPG/MSTP support is not
included, so the rcar-sysc driver won't have to care about this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 years agoclk: renesas: mstp: Provide dummy attach/detach_dev callbacks
Geert Uytterhoeven [Wed, 13 Apr 2016 09:18:06 +0000 (11:18 +0200)]
clk: renesas: mstp: Provide dummy attach/detach_dev callbacks

Provide dummy cpg_mstp_{at,de}tach_dev() PM Domain callbacks if CPG/MSTP
support is not included, so the rcar-sysc driver won't have to care
about this.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 years agoclk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support
Geert Uytterhoeven [Wed, 13 Apr 2016 09:08:42 +0000 (11:08 +0200)]
clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support

Currently the decision whether to build the renesas-cpg-mssr and
clk-mstp drivers is handled by Makefile logic.  However, the rcar-sysc
driver will need to know whether CPG/MSSR and/or CPG/MSTP support are
available or not.

To avoid having to duplicate this logic, move it to Kconfig. Provide
non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig
symbols, which can be used by both Makefiles and C code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 years agoclk: bcm2835: Fix PLL poweron
Eric Anholt [Wed, 13 Apr 2016 20:05:03 +0000 (13:05 -0700)]
clk: bcm2835: Fix PLL poweron

In poweroff, we set the reset bit and the power down bit, but only
managed to unset the reset bit for poweron.  This meant that if HDMI
did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the
PLLH (that had been on at boot time) and never recover.

Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: stable@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: bcm2835: Fix compiler warnings on 64-bit builds
Eric Anholt [Wed, 13 Apr 2016 20:05:02 +0000 (13:05 -0700)]
clk: bcm2835: Fix compiler warnings on 64-bit builds

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: qoriq: add __init attribute
Julia Lawall [Mon, 18 Apr 2016 14:55:34 +0000 (16:55 +0200)]
clk: qoriq: add __init attribute

Add __init attribute on a function that is only called from other __init
functions and that is not inlined, at least with gcc version 4.8.4 on an
x86 machine with allyesconfig.  Currently, the function is put in the
.text.unlikely segment.  Declaring it as __init will cause it to be put in
the .init.text and to disappear after initialization.

The result of objdump -x on the function before the change is as follows:

0000000000000000 l     F .text.unlikely 0000000000000071 sysclk_from_fixed.constprop.5

And after the change it is as follows:

0000000000000480 l     F .init.text 000000000000006c sysclk_from_fixed.constprop.5

Done with the help of Coccinelle.  The semantic patch checks for local
static non-init functions that are called from an __init function and are
not called from any other function.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: ti: dra7-atl-clock: Fix of_node reference counting
Peter Ujfalusi [Fri, 11 Mar 2016 14:13:32 +0000 (16:13 +0200)]
clk: ti: dra7-atl-clock: Fix of_node reference counting

of_find_node_by_name() will call of_node_put() on the node so we need to
get it first to avoid warnings.
The cfg_node needs to be put after we have finished processing the
properties.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: fixed-rate: Add hw based registration APIs
Stephen Boyd [Sun, 7 Feb 2016 08:34:13 +0000 (00:34 -0800)]
clk: fixed-rate: Add hw based registration APIs

Add registration APIs in the clk fixed-rate code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: gpio: Add hw based registration APIs
Stephen Boyd [Sun, 7 Feb 2016 08:27:55 +0000 (00:27 -0800)]
clk: gpio: Add hw based registration APIs

Add registration APIs in the clk gpio code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: composite: Add hw based registration APIs
Stephen Boyd [Sun, 7 Feb 2016 08:20:31 +0000 (00:20 -0800)]
clk: composite: Add hw based registration APIs

Add registration APIs in the clk composite code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: fractional-divider: Add hw based registration APIs
Stephen Boyd [Sun, 7 Feb 2016 08:15:09 +0000 (00:15 -0800)]
clk: fractional-divider: Add hw based registration APIs

Add registration APIs in the clk fractional divider code to
return struct clk_hw pointers instead of struct clk pointers.
This way we hide the struct clk pointer from providers unless
they need to use consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: fixed-factor: Add hw based registration APIs
Stephen Boyd [Sun, 7 Feb 2016 08:11:06 +0000 (00:11 -0800)]
clk: fixed-factor: Add hw based registration APIs

Add registration APIs in the clk fixed-factor code to return
struct clk_hw pointers instead of struct clk pointers. This way
we hide the struct clk pointer from providers unless they need to
use consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: mux: Add hw based registration APIs
Stephen Boyd [Sun, 7 Feb 2016 08:05:48 +0000 (00:05 -0800)]
clk: mux: Add hw based registration APIs

Add registration APIs in the clk mux code to return struct clk_hw
pointers instead of struct clk pointers. This way we hide the
struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: gate: Add hw based registration APIs
Stephen Boyd [Sun, 7 Feb 2016 07:54:45 +0000 (23:54 -0800)]
clk: gate: Add hw based registration APIs

Add registration APIs in the clk gate code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: divider: Add hw based registration APIs
Stephen Boyd [Sun, 7 Feb 2016 07:26:37 +0000 (23:26 -0800)]
clk: divider: Add hw based registration APIs

Add registration APIs in the clk divider code to return struct
clk_hw pointers instead of struct clk pointers. This way we hide
the struct clk pointer from providers unless they need to use
consumer facing APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclkdev: Add clk_hw based registration APIs
Stephen Boyd [Mon, 8 Feb 2016 22:59:49 +0000 (14:59 -0800)]
clkdev: Add clk_hw based registration APIs

Now that we have a clk registration API that doesn't return
struct clks, we need to have some way to hand out struct clks via
the clk_get() APIs that doesn't involve associating struct clk
pointers with a struct clk_lookup. Luckily, clkdev already
operates on struct clk_hw pointers, except for the registration
facing APIs where it converts struct clk pointers into struct
clk_hw pointers almost immediately.

Let's add clk_hw based registration APIs so that we can skip the
conversion step and provide a way for clk provider drivers to
operate exclusively on clk_hw structs. This way we clearly
split the API between consumers and providers.

Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: Add clk_hw OF clk providers
Stephen Boyd [Sat, 6 Feb 2016 01:38:26 +0000 (17:38 -0800)]
clk: Add clk_hw OF clk providers

Now that we have a clk registration API that doesn't return
struct clks, we need to have some way to hand out struct clks via
the clk_get() APIs that doesn't involve associating struct clk
pointers with an OF node. Currently we ask the OF provider to
give us a struct clk pointer for some clkspec, turn that struct
clk into a struct clk_hw and then allocate a new struct clk to
return to the caller.

Let's add a clk_hw based OF provider hook that returns a struct
clk_hw directly, so that we skip the intermediate step of
converting from struct clk to struct clk_hw. Eventually when
we've converted all OF clk providers to struct clk_hw based APIs
we can remove the struct clk based ones.

It should also be noted that we change the onecell provider to
have a flex array instead of a pointer for the array of clk_hw
pointers. This allows providers to allocate one structure of the
correct length in one step instead of two.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: Add {devm_}clk_hw_{register,unregister}() APIs
Stephen Boyd [Sat, 6 Feb 2016 01:02:52 +0000 (17:02 -0800)]
clk: Add {devm_}clk_hw_{register,unregister}() APIs

We've largely split the clk consumer and provider APIs along
struct clk and struct clk_hw, but clk_register() still returns a
struct clk pointer for each struct clk_hw that's registered.
Eventually we'd like to only allocate struct clks when there's a
user, because struct clk is per-user now, so clk_register() needs
to change.

Let's add new APIs to register struct clk_hws, but this time
we'll hide the struct clk from the caller by returning an int
error code. Also add an unregistration API that takes the clk_hw
structure that was passed to the registration API. This way
provider drivers never have to deal with a struct clk pointer
unless they're using the clk consumer APIs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclkdev: Remove clk_register_clkdevs()
Stephen Boyd [Sat, 6 Feb 2016 00:40:47 +0000 (16:40 -0800)]
clkdev: Remove clk_register_clkdevs()

Now that we've converted the only caller over to another clkdev
API, remove this one.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: rockchip: drop unnecessary header comment
Heiko Stuebner [Tue, 19 Apr 2016 19:17:55 +0000 (21:17 +0200)]
clk: rockchip: drop unnecessary header comment

The internal clk header did contain a comment indicating that some of the
defined registers were shared over multiple clock controller variants.
In recent times, it was simply extended all the time and stopped providing
any meaningful information, so drop it and it's overlong line.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: reign in some overly long lines in the rk3399 controller
Heiko Stuebner [Tue, 19 Apr 2016 19:07:01 +0000 (21:07 +0200)]
clk: rockchip: reign in some overly long lines in the rk3399 controller

We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.

Fix the newly added rk3399 clock code to respect that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoMerge branch 'v4.7-shared/clkids' into v4.7-clk/next
Heiko Stuebner [Sat, 16 Apr 2016 01:04:15 +0000 (03:04 +0200)]
Merge branch 'v4.7-shared/clkids' into v4.7-clk/next

5 years agoclk: rockchip: fix checkpatch errors in rk3399 dt-binding header
Heiko Stuebner [Sat, 16 Apr 2016 00:54:52 +0000 (02:54 +0200)]
clk: rockchip: fix checkpatch errors in rk3399 dt-binding header

Some "please, no space before tabs" checkpatch warnings slipped through
the recent addition of the rk3399 dt-binding header, so fix them.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: ti: dra7: fix kernel boot with arg 'clocksource=gp_timer'
Grygorii Strashko [Thu, 10 Dec 2015 17:03:45 +0000 (19:03 +0200)]
clk: ti: dra7: fix kernel boot with arg 'clocksource=gp_timer'

The OMAP Platform code provides possibility to select GP Timer as
default clocksource instead of counter_32K by using bootcmd parameter
'clocksource', but the system will crash during early boot when this
option is used on dra7 or omap5 platforms, because it will hit BUG()
statement:

 omap2_gptimer_clocksource_init
  ->BUG_ON(res);

This happens because clk_dev alias "sys_clkin_ck" is not registered.
Hence, fix it by adding missing "sys_clkin_ck" clk_dev aliases
definitions for omap5 and dra7.

Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
Tero Kristo [Wed, 16 Mar 2016 19:54:56 +0000 (21:54 +0200)]
clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec

AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.

[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: ti: dpll: add support for specifying max rate for DPLLs
Tero Kristo [Wed, 16 Mar 2016 19:54:55 +0000 (21:54 +0200)]
clk: ti: dpll: add support for specifying max rate for DPLLs

DPLLs typically have a maximum rate they can support, and this varies
from DPLL to DPLL. Add support of the maximum rate value to the DPLL
data struct, and also add check for this in the DPLL round_rate function.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: tango4: improve clkgen driver
Marc Gonzalez [Mon, 4 Apr 2016 09:21:09 +0000 (11:21 +0200)]
clk: tango4: improve clkgen driver

Add support for USB and SDIO clocks.
Report unsupported setups and panic.

Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: at91: fix check of clk_register() returned value
Vladimir Zapolskiy [Mon, 7 Mar 2016 23:41:29 +0000 (01:41 +0200)]
clk: at91: fix check of clk_register() returned value

The clk_register() function returns a valid pointer to struct clk or
ERR_PTR() error code, this makes a check for returned NULL value
useless and may lead to oops on error path.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: bcc5fd49a0fd ("clk: at91: add a driver for the h32mx clock")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: xgene: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:26 +0000 (11:00 -0800)]
clk: xgene: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: wm831x: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:25 +0000 (11:00 -0800)]
clk: wm831x: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: twl6040: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:24 +0000 (11:00 -0800)]
clk: twl6040: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: rk808: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:20 +0000 (11:00 -0800)]
clk: rk808: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: qoriq: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:19 +0000 (11:00 -0800)]
clk: qoriq: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Hou Zhiqiang <B48286@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: palmas: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:17 +0000 (11:00 -0800)]
clk: palmas: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: nspire: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:16 +0000 (11:00 -0800)]
clk: nspire: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Daniel Tang <dt.tangr@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: ls1x: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:13 +0000 (11:00 -0800)]
clk: ls1x: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: clps711x: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:10 +0000 (11:00 -0800)]
clk: clps711x: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: zte: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:08 +0000 (11:00 -0800)]
clk: zte: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: sunxi: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 19:00:01 +0000 (11:00 -0800)]
clk: sunxi: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: sirf: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 18:59:59 +0000 (10:59 -0800)]
clk: sirf: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Guo Zeng <Guo.Zeng@csr.com>
Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: mmp: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 18:59:52 +0000 (10:59 -0800)]
clk: mmp: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: meson: Remove CLK_IS_ROOT
Stephen Boyd [Tue, 1 Mar 2016 18:59:51 +0000 (10:59 -0800)]
clk: meson: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Carlo Caione <carlo@caione.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoMerge branch 'clk-artpec6' into clk-next
Stephen Boyd [Fri, 15 Apr 2016 23:02:46 +0000 (16:02 -0700)]
Merge branch 'clk-artpec6' into clk-next

* clk-artpec6:
  clk: add artpec-6 clock controller
  clk: add device tree binding for Artpec-6 clock controller

5 years agoclk: add artpec-6 clock controller
Lars Persson [Mon, 4 Apr 2016 09:23:23 +0000 (11:23 +0200)]
clk: add artpec-6 clock controller

Add a driver for the main clock controller of the Artpec-6 Soc.

Signed-off-by: Lars Persson <larper@axis.com>
[sboyd@codeaurora.org: Reformatted driver structure and of match]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: add device tree binding for Artpec-6 clock controller
Lars Persson [Mon, 4 Apr 2016 09:23:22 +0000 (11:23 +0200)]
clk: add device tree binding for Artpec-6 clock controller

Add device tree documentation for the main clock controller in the
Artpec-6 SoC.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lars Persson <larper@axis.com>
[sboyd@codeaurora.org: Added unit address to binding example]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: ti: dflt: remove redundant unlikely
Suman Anna [Tue, 5 Apr 2016 18:28:57 +0000 (13:28 -0500)]
clk: ti: dflt: remove redundant unlikely

Commit 7aba4f5201d1 ("clk: ti: dflt: fix enable_reg validity check")
fixed a validation check by using an IS_ERR() macro within the
existing unlikely expression, but IS_ERR() macro already has an
unlikely inside it, so get rid of the redundant unlikely macro
from the validation check.

Reported-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoMerge tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind...
Stephen Boyd [Fri, 15 Apr 2016 22:47:54 +0000 (15:47 -0700)]
Merge tag 'v4.7-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk updates from Heiko Stuebner:

This is first big chunk of Rockchip clock-related changes for 4.7.

Main change is probably the added support for the new rk3399 soc
and necessary infrastructure changes surrounding it.

The biggest chunk is probably that clock code is now able to
handle multiple clock providers in one system, as the rk3399
has two of those. A general one and another smaller one in a
separate power domain. The rk3399 also uses another new pll type.
Thankfully it just fits nicely into our current structure.
It also needs some parts like the cpuclk mux parameters to be
a bit more flexible and an new fractional divider subtype without
gate.

Apart from this big change we have some more fixes and removal
of forgotten variables.

* tag 'v4.7-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add clock controller for the RK3399
  dt-bindings: add bindings for rk3399 clock controller
  clk: rockchip: add dt-binding header for rk3399
  clk: rockchip: release io resource when failing to init clk
  clk: rockchip: remove redundant checking of device_node
  clk: rockchip: fix warning reported by kernel-doc
  clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data
  clk: rockchip: add new pll-type for rk3399 and similar socs
  clk: rockchip: Add support for multiple clock providers
  clk: rockchip: allow varying mux parameters for cpuclk pll-sources
  clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type