sfrench/cifs-2.6.git
5 years agoarm: omap2+ remove dead clock code
Michael Turquette [Thu, 29 Jan 2015 19:50:30 +0000 (11:50 -0800)]
arm: omap2+ remove dead clock code

Remove omap_clocks_register and dummy_ck. The former is not used anymore
now that the statically defined clk stuctures are replaced with proper
descriptors and registered with the framework.

The dummy clock in arch/arm/mach-omap2 is made redundant by the OMAP3+
clock data that migrated to drivers/clk.

An additional benefit to this clean-up is removing the references to
clk-private.h which will be removed.

Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoMerge branch 'clk-omap-legacy' into clk-next
Michael Turquette [Fri, 30 Jan 2015 18:57:21 +0000 (10:57 -0800)]
Merge branch 'clk-omap-legacy' into clk-next

Conflicts:
arch/arm/mach-omap2/cclock3xxx_data.c

5 years agoclk: Make clk API return per-user struct clk instances
Tomeu Vizoso [Fri, 23 Jan 2015 11:03:30 +0000 (12:03 +0100)]
clk: Make clk API return per-user struct clk instances

Moves clock state to struct clk_core, but takes care to change as little API as
possible.

struct clk_hw still has a pointer to a struct clk, which is the
implementation's per-user clk instance, for backwards compatibility.

The struct clk that clk_get_parent() returns isn't owned by the caller, but by
the clock implementation, so the former shouldn't call clk_put() on it.

Because some boards in mach-omap2 still register clocks statically, their clock
registration had to be updated to take into account that the clock information
is stored in struct clk_core now.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: adapted clk_has_parent to struct clk_core
                        applied OMAP3+ DPLL fix from Tero & Tony]

5 years agoARM: OMAP3: remove legacy clock data
Tero Kristo [Tue, 16 Dec 2014 16:20:56 +0000 (18:20 +0200)]
ARM: OMAP3: remove legacy clock data

This is no longer used for anything, thus it can be removed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoARM: OMAP3: use clock data from TI clock driver for legacy boot
Tero Kristo [Tue, 16 Dec 2014 16:20:55 +0000 (18:20 +0200)]
ARM: OMAP3: use clock data from TI clock driver for legacy boot

As the clock data is now available for the legacy boot also from the
clock driver, use this rather than the data under the mach folder.
This allows us to get rid of the old clock data completely.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoARM: OMAP3: PRM: add support for legacy iomapping init
Tero Kristo [Tue, 16 Dec 2014 16:20:54 +0000 (18:20 +0200)]
ARM: OMAP3: PRM: add support for legacy iomapping init

As the legacy clock data is being moved under clock driver, the
clock data will be using the same low level infrastructure for
register accesses. This requires the clk_memmaps to be initialized
properly. This patch adds a support hook to the PRM driver to
initialize the mappings.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ti: add omap3 legacy clock data
Tero Kristo [Thu, 29 Jan 2015 20:25:40 +0000 (22:25 +0200)]
clk: ti: add omap3 legacy clock data

Introduces omap3 legacy clock data under clock driver. The clock data
is also in new format, which makes it possible to get rid of the
clk-private.h header. This patch also introduces SoC specific init
functions that shall be called from the low level init.

The data format used in this file has two possible evolution paths;
it can either be removed completely once no longer needed, or it will
be possible to retain the format and modify the TI clock driver to be
a loadable module at some point. The actual path to be followed
will be decided later.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ti: composite: add support for legacy composite clock init
Tero Kristo [Tue, 16 Dec 2014 16:20:52 +0000 (18:20 +0200)]
clk: ti: composite: add support for legacy composite clock init

Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ti: dpll: add support for legacy DPLL init
Tero Kristo [Thu, 29 Jan 2015 20:24:28 +0000 (22:24 +0200)]
clk: ti: dpll: add support for legacy DPLL init

Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ti: divider: add support for legacy divider init
Tero Kristo [Tue, 16 Dec 2014 16:20:50 +0000 (18:20 +0200)]
clk: ti: divider: add support for legacy divider init

Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ti: interface: add support for legacy interface clock init
Tero Kristo [Tue, 16 Dec 2014 16:20:49 +0000 (18:20 +0200)]
clk: ti: interface: add support for legacy interface clock init

Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this. The interface clock descriptor
itself is overloading the gate clock descriptor, thus it needs to
be called from the gate setup.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ti: gate: add support for legacy gate init
Tero Kristo [Tue, 16 Dec 2014 16:20:48 +0000 (18:20 +0200)]
clk: ti: gate: add support for legacy gate init

Legacy clock data is initialialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ti: mux: add support for legacy mux init
Tero Kristo [Tue, 16 Dec 2014 16:20:47 +0000 (18:20 +0200)]
clk: ti: mux: add support for legacy mux init

Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ti: add core support for initializing legacy clocks
Tero Kristo [Tue, 16 Dec 2014 16:20:46 +0000 (18:20 +0200)]
clk: ti: add core support for initializing legacy clocks

Legacy clock data for OMAP3 is being moved under clock driver, thus
base support for this is needed. This patch adds basic definitions for
clock init descriptors and core infrastructure for initialization,
which will be called from the OMAP3 clock init.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: Remove __clk_register
Tomeu Vizoso [Fri, 23 Jan 2015 11:03:29 +0000 (12:03 +0100)]
clk: Remove __clk_register

As it has never been used.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: Remove unneeded NULL checks
Tomeu Vizoso [Fri, 23 Jan 2015 11:03:28 +0000 (12:03 +0100)]
clk: Remove unneeded NULL checks

As clk_unprepare_unused_subtree and clk_disable_unused_subtree are
always called with a valid struct clk.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qoriq: Use pr_fmt()
Emil Medve [Wed, 21 Jan 2015 10:03:29 +0000 (04:03 -0600)]
clk: qoriq: Use pr_fmt()

Currently a mix of clk-qoriq/qoriq-clk and no prefix is used

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qoriq: Replace kzalloc() with kmalloc()
Emil Medve [Wed, 21 Jan 2015 10:03:28 +0000 (04:03 -0600)]
clk: qoriq: Replace kzalloc() with kmalloc()

Where the memset() is not necessary

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qoriq: Make local symbol 'static'
Emil Medve [Wed, 21 Jan 2015 10:03:27 +0000 (04:03 -0600)]
clk: qoriq: Make local symbol 'static'

drivers/clk/clk-qoriq.c:59:22: warning: symbol 'cmux_ops' was not declared. Should it be static?

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qoriq: Fix checkpatch type OOM_MESSAGE
Emil Medve [Wed, 21 Jan 2015 10:03:26 +0000 (04:03 -0600)]
clk: qoriq: Fix checkpatch type OOM_MESSAGE

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!parent_names) {
+               pr_err("%s: could not allocate parent_names\n", __func__);

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!cmux_clk) {
+               pr_err("%s: could not allocate cmux_clk\n", __func__);

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!subclks) {
+               pr_err("%s: could not allocate subclks\n", __func__);

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!onecell_data) {
+               pr_err("%s: could not allocate onecell_data\n", __func__);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qoriq: Fix checkpatch type ALLOC_SIZEOF_STRUCT
Emil Medve [Wed, 21 Jan 2015 10:03:25 +0000 (04:03 -0600)]
clk: qoriq: Fix checkpatch type ALLOC_SIZEOF_STRUCT

CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*cmux_clk)...) over kzalloc(sizeof(struct cmux_clk)...)
+       cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL);

CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*onecell_data)...) over kzalloc(sizeof(struct clk_onecell_data)...)
+       onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLY
Emil Medve [Wed, 21 Jan 2015 10:03:24 +0000 (04:03 -0600)]
clk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLY

WARNING:ALLOC_WITH_MULTIPLY: Prefer kcalloc over kzalloc with multiply
+       subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENT
Emil Medve [Wed, 21 Jan 2015 10:03:23 +0000 (04:03 -0600)]
clk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENT

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+       rc = of_property_read_string_index(np, "clock-output-names",
+                       0, &clk_name);

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+               pr_err("Could not register clock provider for node:%s\n",
+                        np->name);

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+               rc = of_property_read_string_index(np, "clock-output-names",
+                               i, &clk_name);

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+               pr_err("Could not register clk provider for node:%s\n",
+                        np->name);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: pxa: add pxa3xx clock driver
Robert Jarzmik [Tue, 6 Jan 2015 20:45:38 +0000 (21:45 +0100)]
clk: pxa: add pxa3xx clock driver

Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk.
In the move :
 - convert to new clock framework legacy clocks
 - provide clocks as before for platform data based boards
 - provide clocks through devicetree with clk-pxa-dt

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: zynq: Force CPU_2X clock to be ungated
Soren Brinkmann [Tue, 27 Jan 2015 19:05:27 +0000 (11:05 -0800)]
clk: zynq: Force CPU_2X clock to be ungated

The CPU_2X clock does not have a classical in-kernel user, but is,
amongst other things, required for OCM and debug access. Make sure this
clock is not mistakenly disabled during boot up by enabling it in the
platform's clock driver.

Cc: stable@vger.kernel.org # 3.11+
Fixes: 0ee52b157b8e 'clk: zynq: Add clock controller driver'
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoMerge tag 'sunxi-clocks-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel...
Michael Turquette [Wed, 28 Jan 2015 00:33:45 +0000 (16:33 -0800)]
Merge tag 'sunxi-clocks-for-3.20' of https://git./linux/kernel/git/mripard/linux into clk-next

Allwinner clock changes for 3.20

The set of clock changes for the 3.20 merge window, with mostly:
  - Some PLL fixes for the A80 and A31
  - The MMC custom phase functions are removed, and moved over to the generic
    phase API.
  - Add the A80 MMC clocks

Some DT changes slipped here as well, to preserve bisectability.

5 years agoMerge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git...
Michael Turquette [Wed, 28 Jan 2015 00:26:12 +0000 (16:26 -0800)]
Merge tag 'v3.20-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next

The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.

Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.

5 years agoclk: ti: Drop use of clk-private.h
Stephen Boyd [Thu, 22 Jan 2015 23:40:20 +0000 (15:40 -0800)]
clk: ti: Drop use of clk-private.h

These modules don't need to include clk-private.h. Replace the
include with clk.h because these modules are clock consumers and
also include clk-provider.h in clk/ti.h because struct
clk_hw_omap has a struct clk_hw embedded in it.

Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ux500: Drop use of clk-private.h
Stephen Boyd [Thu, 22 Jan 2015 19:34:19 +0000 (11:34 -0800)]
clk: ux500: Drop use of clk-private.h

These drivers don't need to include clk-private.h. Remove the
include.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: Export phase functions
Maxime Ripard [Tue, 20 Jan 2015 21:23:43 +0000 (22:23 +0100)]
clk: Export phase functions

The phase setter and getter were not exported until now, which was causing
build breakages when callers were compiled as module. Export these two
functions.

Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agodevicetree: bindings: Document qcom,lcc
Rajendra Nayak [Tue, 20 Jan 2015 02:05:35 +0000 (18:05 -0800)]
devicetree: bindings: Document qcom,lcc

Document the LPASS (low power audio subsystem) clock controller
found on Qualcomm devices.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver
Stephen Boyd [Tue, 20 Jan 2015 02:05:34 +0000 (18:05 -0800)]
clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver

Add an LCC driver for MSM8960/APQ8064 that supports the i2s,
slimbus, and pcm clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qcom: Add IPQ806X LPASS clock controller (LCC) driver
Rajendra Nayak [Tue, 20 Jan 2015 02:05:33 +0000 (18:05 -0800)]
clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver

Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and
pcm clocks.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
[sboyd@codeaurora.org: Reworded commit text, added Kconfig
select, fleshed out Kconfig description a bit more, added pll4
configuration and reworked probe for it, added muxes, split out
dt-binding file]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agodt-bindings: Add #defines for IPQ806x lpass clock control
Rajendra Nayak [Tue, 20 Jan 2015 02:05:32 +0000 (18:05 -0800)]
dt-bindings: Add #defines for IPQ806x lpass clock control

Add defines to make more human readable numbers for the lpass
clock controller found on IPQ806x SoCs. Also remove the PLL4
define in gcc to avoid #define conflicts because that clock
doesn't exist in gcc, instead it lives in lcc.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Split off into separate patch]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qcom: Add simple regmap based muxes
Stephen Boyd [Tue, 20 Jan 2015 02:05:31 +0000 (18:05 -0800)]
clk: qcom: Add simple regmap based muxes

Add support for muxes that use regmap instead of readl/writel
directly. We don't support as many features as clk-mux.c, but
this is good enough to support getting and setting parents.
Adding a table based lookup can be added in the future if needed.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: qcom: Add support for regmap divider clocks
Josh Cartwright [Tue, 20 Jan 2015 02:05:30 +0000 (18:05 -0800)]
clk: qcom: Add support for regmap divider clocks

Add support for dividers that use regmap instead of readl/writel.

Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Switch to using generic divider code, drop
enable/disable, reword commit text]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: divider: Make generic for usage elsewhere
Stephen Boyd [Tue, 20 Jan 2015 02:05:29 +0000 (18:05 -0800)]
clk: divider: Make generic for usage elsewhere

Some devices don't use mmio to interact with dividers. Split out the
logic from the register read/write parts so that we can reuse the
division logic elsewhere.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: Add __clk_mux_determine_rate_closest
Stephen Boyd [Tue, 20 Jan 2015 02:05:28 +0000 (18:05 -0800)]
clk: Add __clk_mux_determine_rate_closest

Some clock drivers want to find the closest rate on the input of
a mux instead of a rate that's less than or equal to the desired
rate. Add a generic mux function to support this.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: Fix debugfs clk removal before inited
Srinivas Kandagatla [Mon, 19 Jan 2015 09:57:13 +0000 (09:57 +0000)]
clk: Fix debugfs clk removal before inited

Some of the clks can be registered & unregistered before the clk related debugfs
entries are initialized at late_initcall. In the unregister path checking for only
dentry before clk_debug_init() would lead dangling pointers in the debug clk list,
because the list is already populated in register path and the clk pointer freed in
unregister path.
The side effect of not removing it from the list is either a null pointer
dereference or if lucky to boot the system, the number of clk entries in
debugfs disappear.

We could add more checks like if (inited && !clk->dentry) but just removing
the check for dentry made more sense as debugfs_remove_recursive() seems to be
safe with null pointers. This will ensure that the unregistering clk would be
removed from the debug list in all the code paths.

Without this patch kernel would crash with log:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0204000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 1 PID: 1 Comm: swapper/0 Tainted: G    B          3.19.0-rc3-00007-g412f9ba-dirty #840
Hardware name: Qualcomm (Flattened Device Tree)
task: ed948000 ti: ed944000 task.ti: ed944000
PC is at strlen+0xc/0x40
LR is at __create_file+0x64/0x1dc
pc : [<c04ee604>]    lr : [<c049f1c4>]    psr: 60000013
sp : ed945e40  ip : ed945e50  fp : ed945e4c
r10: 00000000  r9 : c1006094  r8 : 00000000
r7 : 000041ed  r6 : 00000000  r5 : ed4af998  r4 : c11b5e28
r3 : 00000000  r2 : ed945e38  r1 : a0000013  r0 : 00000000
Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5787d  Table: 8020406a  DAC: 00000015
Process swapper/0 (pid: 1, stack limit = 0xed944248)
Stack: (0xed945e40 to 0xed946000)
5e40: ed945e7c ed945e50 c049f1c4 c04ee604 c0fc2fa4 00000000 ecb748c0 c11c2b80
5e60: c0beec04 0000011c c0fc2fa4 00000000 ed945e94 ed945e80 c049f3e0 c049f16c
5e80: 00000000 00000000 ed945eac ed945e98 c08cbc50 c049f3c0 ecb748c0 c11c2b80
5ea0: ed945ed4 ed945eb0 c0fc3080 c08cbc30 c0beec04 c107e1d8 ecdf0600 c107e1d8
5ec0: c107e1d8 ecdf0600 ed945f54 ed945ed8 c0208ed4 c0fc2fb0 c026a784 c04ee628
5ee0: ed945f0c ed945ef0 c0f5d600 c04ee604 c0f5d5ec ef7fcc7d c0b40ecc 0000011c
5f00: ed945f54 ed945f10 c026a994 c0f5d5f8 c04ecc00 00000007 ef7fcc95 00000007
5f20: c0e90744 c0dd0884 ed945f54 c106cde0 00000007 c117f8c0 0000011c c0f5d5ec
5f40: c1006094 c100609c ed945f94 ed945f58 c0f5de34 c0208e50 00000007 00000007
5f60: c0f5d5ec be9b5ae0 00000000 c117f8c0 c0af1680 00000000 00000000 00000000
5f80: 00000000 00000000 ed945fac ed945f98 c0af169c c0f5dd2c ed944000 00000000
5fa0: 00000000 ed945fb0 c020f298 c0af168c 00000000 00000000 00000000 00000000
5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 ebcc6d33 bfffca73
[<c04ee604>] (strlen) from [<c049f1c4>] (__create_file+0x64/0x1dc)
[<c049f1c4>] (__create_file) from [<c049f3e0>] (debugfs_create_dir+0x2c/0x34)
[<c049f3e0>] (debugfs_create_dir) from [<c08cbc50>] (clk_debug_create_one+0x2c/0x16c)
[<c08cbc50>] (clk_debug_create_one) from [<c0fc3080>] (clk_debug_init+0xdc/0x144)
[<c0fc3080>] (clk_debug_init) from [<c0208ed4>] (do_one_initcall+0x90/0x1e0)
[<c0208ed4>] (do_one_initcall) from [<c0f5de34>] (kernel_init_freeable+0x114/0x1e0)
[<c0f5de34>] (kernel_init_freeable) from [<c0af169c>] (kernel_init+0x1c/0xfc)
[<c0af169c>] (kernel_init) from [<c020f298>] (ret_from_fork+0x14/0x3c)
Code: c0b40ecc e1a0c00d e92dd800 e24cb004 (e5d02000)
---[ end trace b940e45b5e25c1e7 ]---

Fixes: 6314b6796e3c "clk: Don't hold prepare_lock across debugfs creation"
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoMerge branch 'clk-shmobile-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel...
Michael Turquette [Tue, 27 Jan 2015 19:34:41 +0000 (11:34 -0800)]
Merge branch 'clk-shmobile-for-3.20' of git://git./linux/kernel/git/geert/renesas-drivers into clk-next

5 years agosunxi: clk: Set sun6i-pll1 n_start = 1
Hans de Goede [Sat, 24 Jan 2015 11:56:32 +0000 (12:56 +0100)]
sunxi: clk: Set sun6i-pll1 n_start = 1

For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as
it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set
for sun6i pll6, but was missing for pll1, this commit fixes this.

Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: sunxi: rewrite sun9i_a80_get_pll4_factors()
Hans de Goede [Sat, 24 Jan 2015 11:56:31 +0000 (12:56 +0100)]
clk: sunxi: rewrite sun9i_a80_get_pll4_factors()

The old implementation of sun9i_a80_get_pll4_factors() has several issues,
it checks against 256 / 512 in various places where it should use 255 / 511,
it does the wrong thing for low frequencies which are an even multiple of
6 MHz, e.g. if you ask it for 72 MHz it will result in 144 Mhz, and it does
not take into account that n must be at least 12. Moreover it is quite hard
to read / follow it.

This commit rewrites it to be correct in all cases, and makes it much easier
to follow the code / to read.

Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoMerge branch 'clk-has-parent' into clk-next
Michael Turquette [Sun, 25 Jan 2015 00:58:40 +0000 (16:58 -0800)]
Merge branch 'clk-has-parent' into clk-next

5 years agoclk: Introduce clk_has_parent()
Thierry Reding [Wed, 21 Jan 2015 16:13:00 +0000 (17:13 +0100)]
clk: Introduce clk_has_parent()

This new function is similar to clk_set_parent(), except that it doesn't
actually change the parent. It merely checks that the given parent clock
can be a parent for the given clock.

A situation where this is useful is to check that a particular setup is
valid before switching to it. One specific use-case for this is atomic
modesetting in the DRM framework where setting a mode is divided into a
check phase where a given configuration is validated before applying
changes to the hardware.

Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: rockchip: add a dummy clock for the watchdog pclk on rk3288
Heiko Stuebner [Tue, 20 Jan 2015 20:06:55 +0000 (21:06 +0100)]
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288

The pclk supplying the watchdog is controlled via the SGRF register area.
Currently we don't have any clock-type handling external clock bits like
this one. Additionally the SGRF isn't even writable in every boot mode.

But still the clock control is available and in the future someone might
want to use it. Therefore define a simple clock for the time being so
that the watchdog driver can read its rate.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: add PVTM clocks on rk3288
huang lin [Fri, 19 Dec 2014 00:13:46 +0000 (16:13 -0800)]
clk: rockchip: add PVTM clocks on rk3288

Process-Voltage-Temperatiure Monitor block on RK3288 has two clocks:
PVTM_CORE and PVTM_GPU.

Signed-off-by: Huang Lin <hl@rock-chips.com>
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: use the clock ID for usbphy480m_src
Kever Yang [Thu, 13 Nov 2014 07:22:37 +0000 (15:22 +0800)]
clk: rockchip: use the clock ID for usbphy480m_src

Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoMerge branch 'v3.20-clk/new-ids' into v3.20-clk/next
Heiko Stuebner [Thu, 22 Jan 2015 14:41:06 +0000 (15:41 +0100)]
Merge branch 'v3.20-clk/new-ids' into v3.20-clk/next

5 years agoclk: rockchip: add id for watchdog pclk on rk3288
Heiko Stuebner [Tue, 20 Jan 2015 20:05:51 +0000 (21:05 +0100)]
clk: rockchip: add id for watchdog pclk on rk3288

Adds a new id for the pclk supplying the watchdog on rk3288 socs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
5 years agoARM: clk: add clk-asm9260 driver
Oleksij Rempel [Tue, 20 Jan 2015 09:23:02 +0000 (10:23 +0100)]
ARM: clk: add clk-asm9260 driver

Provide CLK support for Alphascale ASM9260 SoC.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: st: STiH410: Fix pdiv and fdiv divisor when setting rate
Peter Griffin [Tue, 20 Jan 2015 15:32:41 +0000 (15:32 +0000)]
clk: st: STiH410: Fix pdiv and fdiv divisor when setting rate

Debugging eMMC on upstream kernels it has been noticed that when the
targetpack configures MMC0 clock to 200Mhz (required to switch to
HS200) then everything works OK. However if the kernel sets the
clock rate using clk_set_rate, then the eMMC card initialisation
fails with timeouts. Lower clock speeds (the default being 50Mhz)
work ok, but they we fail to get good eMMC transfer rates.

Looking through the vendor kernel clock driver reveals Giuseppe
had already fixed this issue, but the patch hasn't made its way
upstream.

The issue is fixed by changing the logic to manage the pdiv and
fdiv divisors used for setting the rate inside the flexgen driver code.

Pdiv is mainly targeted for low freq results, while fdiv should be
used for divs =< 64. The other way can lead to 'duty cycle'
issues.

I have changed the original patch to keep the original behaviour
in cases where the div is >64 which matches the original comment
and patch description more closely. Although no clocks appear to hit
this case currently when booting an upstream kernel.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ppc-corenet: rename driver to clk-qoriq
Tang Yuantian [Thu, 15 Jan 2015 06:03:41 +0000 (14:03 +0800)]
clk: ppc-corenet: rename driver to clk-qoriq

Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclock: redefine variable clocks_per_pll as a struct member
Tang Yuantian [Thu, 15 Jan 2015 06:03:40 +0000 (14:03 +0800)]
clock: redefine variable clocks_per_pll as a struct member

redefine variable clocks_per_pll as a struct member

If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoMerge tag 'for-v3.20-exynos7-clk' of git://linuxtv.org/snawrocki/samsung into clk...
Michael Turquette [Mon, 19 Jan 2015 16:36:52 +0000 (08:36 -0800)]
Merge tag 'for-v3.20-exynos7-clk' of git://linuxtv.org/snawrocki/samsung into clk-next

- Clock definitions for Exynos7 SoC peripheral devices:
  video scaler, USB, DMA, SPI and the audio subsystem.

5 years agoclk: ti: Initialize clocks for dm816x
Tony Lindgren [Tue, 13 Jan 2015 22:51:28 +0000 (14:51 -0800)]
clk: ti: Initialize clocks for dm816x

The clocks on ti81xx are not compatible with omap3. On dm816x
the clock source is a FAPLL (Flying Adder PLL), and on dm814x
there seems to be an APLL (All Digital PLL).

Let's fix up things for dm816x in preparation for adding the
FAPLL support. As we already have a dummy ti81xx_dt_clk_init()
in place, let's use that for now to avoid adding a dependency
to the omap patches.

Later on if somebody adds dm814x support we can split the
ti81xx_dt_clk_init() clock init function as needed.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ti: Add support for FAPLL on dm816x
Tony Lindgren [Tue, 13 Jan 2015 22:51:27 +0000 (14:51 -0800)]
clk: ti: Add support for FAPLL on dm816x

On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers
   into bypass mode. As the bypass rate can also be generated by
   the PLL in regular mode, there's no way for the child synthesizers
   to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child
   syntheriser.

Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: Skip fetching index for single parent clocks
Stephen Boyd [Mon, 22 Dec 2014 19:26:42 +0000 (11:26 -0800)]
clk: Skip fetching index for single parent clocks

We don't need to fetch the parent index for clocks if they only
have one parent. Doing this also avoid an unnecessary allocation
for the parent cache.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk-gate: fix bit # check in clk_register_gate()
Sergei Shtylyov [Wed, 24 Dec 2014 14:43:27 +0000 (17:43 +0300)]
clk-gate: fix bit # check in clk_register_gate()

In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit #
should be no higher than 15, however the corresponding check is obviously off-
by-one.

Fixes: 045779942c04 ("clk: gate: add CLK_GATE_HIWORD_MASK")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: ppc-corenet: fix section mismatch warning
Kevin Hao [Wed, 3 Dec 2014 08:53:53 +0000 (16:53 +0800)]
clk: ppc-corenet: fix section mismatch warning

In order to fix the following section mismatch warning:
  WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe()
  The variable ppc_corenet_clk_driver references
  the function __init ppc_corenet_clk_probe()
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

  WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids
  The variable ppc_corenet_clk_driver references
  the variable __initconst ppc_clk_ids
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

We can't just add the __init annotation to ppc_corenet_clk_driver or
remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids.
So choose to use CLK_OF_DECLARE to scan and init the clock devices.

Signed-off-by: Kevin Hao <haokexin@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agopowerpc: call of_clk_init() from time_init()
Kevin Hao [Wed, 3 Dec 2014 08:53:52 +0000 (16:53 +0800)]
powerpc: call of_clk_init() from time_init()

So the boards which has COMMON_CLK enabled don't have to
invoke this in its board specific file.

Signed-off-by: Kevin Hao <haokexin@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: sunxi: Add driver for A80 MMC config clocks/resets
Chen-Yu Tsai [Tue, 20 Jan 2015 15:46:31 +0000 (23:46 +0800)]
clk: sunxi: Add driver for A80 MMC config clocks/resets

On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.

This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: sunxi: Add mod0 and mmc module clock support for A80
Chen-Yu Tsai [Sat, 17 Jan 2015 05:19:26 +0000 (13:19 +0800)]
clk: sunxi: Add mod0 and mmc module clock support for A80

The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.

As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.

This patch adds support for both.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: exynos-audss: Fix memory leak on driver unbind or probe failure
Krzysztof Kozlowski [Mon, 5 Jan 2015 09:52:41 +0000 (10:52 +0100)]
clk: exynos-audss: Fix memory leak on driver unbind or probe failure

The memory allocated by basic clock divider/gate/mux (struct clk_gate,
clk_divider and clk_mux) was leaking. During driver unbind or probe
failure the driver only unregistered the clocks.

Use clk_unregister_{gate,divider,mux} to release all resources.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: Add clk_unregister_{divider, gate, mux} to close memory leak
Krzysztof Kozlowski [Mon, 5 Jan 2015 09:52:40 +0000 (10:52 +0100)]
clk: Add clk_unregister_{divider, gate, mux} to close memory leak

The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.

Add corresponding unregister functions which will release all resources.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: TI CDCE706 clock synthesizer driver
Max Filippov [Mon, 12 Jan 2015 07:20:46 +0000 (10:20 +0300)]
clk: TI CDCE706 clock synthesizer driver

The driver allows using CDCE706 in its default configuration recorded in
EEPROM and adjusting of synthesized clocks by consumers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: fix possible null pointer dereference
Stanimir Varbanov [Mon, 5 Jan 2015 16:04:23 +0000 (18:04 +0200)]
clk: fix possible null pointer dereference

The commit 646cafc6 (clk: Change clk_ops->determine_rate to
return a clk_hw as the best parent) opens a possibility for
null pointer dereference, fix this.

Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoRevert "clk: ppc-corenet: Fix Section mismatch warning"
Kevin Hao [Wed, 3 Dec 2014 08:53:51 +0000 (16:53 +0800)]
Revert "clk: ppc-corenet: Fix Section mismatch warning"

This reverts commit da788acb28386aa896224e784954bb73c99ff26c.

That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the memories occupied by this struct
after boot while this driver is still registered in the driver core.
The kernel would panic when accessing this driver struct.

Cc: stable@vger.kernel.org # 3.17
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: rockchip: fix deadlock possibility in cpuclk
Heiko Stübner [Fri, 16 Jan 2015 16:52:44 +0000 (17:52 +0100)]
clk: rockchip: fix deadlock possibility in cpuclk

Lockdep reported a possible deadlock between the cpuclk lock and for example
the i2c driver.

       CPU0                    CPU1
       ----                    ----
  lock(clk_lock);
                               local_irq_disable();
                               lock(&(&i2c->lock)->rlock);
                               lock(clk_lock);
  <Interrupt>
    lock(&(&i2c->lock)->rlock);

 *** DEADLOCK ***

The generic clock-types of the core ccf already use spin_lock_irqsave when
touching clock registers, so do the same for the cpuclk.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: removed initialization of "flags"]

5 years agoclk: samsung: exynos7: add clocks for audio block
Padmavathi Venna [Tue, 13 Jan 2015 11:27:42 +0000 (16:57 +0530)]
clk: samsung: exynos7: add clocks for audio block

Add required clk support for I2S, PCM and SPDIF.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
5 years agoclk: samsung: exynos7: add clocks for SPI block
Padmavathi Venna [Tue, 13 Jan 2015 11:27:41 +0000 (16:57 +0530)]
clk: samsung: exynos7: add clocks for SPI block

Add clock support for 5 SPI channels.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
5 years agoclk: samsung: exynos7: add gate clock for DMA block
Padmavathi Venna [Tue, 13 Jan 2015 11:27:40 +0000 (16:57 +0530)]
clk: samsung: exynos7: add gate clock for DMA block

Add support for PDMA0 and PDMA1 gate clks.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
5 years agoclk: sunxi: Add a common setup function for mmc module clocks
Chen-Yu Tsai [Tue, 13 Jan 2015 01:37:23 +0000 (09:37 +0800)]
clk: sunxi: Add a common setup function for mmc module clocks

The only difference between module clocks on different platforms is the
width of the mux register bits and the valid values, which are passed in
through struct factors_data. The phase clocks parts are identical.

This patch generalizes the setup function, so most of the code can be
reused when adding sun9i support, which has a wider mux register.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: sunxi: Remove custom phase function
Maxime Ripard [Sat, 12 Jul 2014 10:10:04 +0000 (12:10 +0200)]
clk: sunxi: Remove custom phase function

Now that we don't have any user left for our custom phase function, we can
safely remove this hack from the code.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
5 years agommc: sunxi: Convert MMC driver to the standard clock phase API
Maxime Ripard [Sat, 12 Jul 2014 10:01:33 +0000 (12:01 +0200)]
mmc: sunxi: Convert MMC driver to the standard clock phase API

Now that we have proper support to use the generic phase API in our clock
driver, switch the MMC driver to use it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
5 years agoARM: sunxi: dt: Add sample and output mmc clocks
Maxime Ripard [Fri, 11 Jul 2014 17:39:06 +0000 (19:39 +0200)]
ARM: sunxi: dt: Add sample and output mmc clocks

Add the sample and output clocks for the MMC phase support.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
5 years agoclk: sunxi: Rework MMC phase clocks
Maxime Ripard [Sun, 7 Dec 2014 16:43:04 +0000 (17:43 +0100)]
clk: sunxi: Rework MMC phase clocks

Instead of having three different clocks for the main MMC clock and the two
phase sub-clocks, which involved having three different drivers sharing the
same register, rework it to have the same single driver registering three
different clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
5 years agoclk: berlin: bg2q: remove non-exist "smemc" gate clock
Jisheng Zhang [Wed, 31 Dec 2014 08:57:52 +0000 (16:57 +0800)]
clk: berlin: bg2q: remove non-exist "smemc" gate clock

The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
register is for nfc. Current code use bit19 for non-exist "smemc"
incorrectly, this prevents eMMC from working due to the sdhci's
"core" clk is still gated.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Cc: stable@vger.kernel.org # 3.16+
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoclk: at91: keep slow clk enabled to prevent system hang
Boris Brezillon [Tue, 13 Jan 2015 14:44:06 +0000 (15:44 +0100)]
clk: at91: keep slow clk enabled to prevent system hang

All slow clk users are not properly claiming it (get + prepare + enable)
before using it.
If all users properly claiming this clock release it, the clock is
disabled, but faulty users still depends on it, and the system hangs.

This fix prevents the slow clock from being disabled, and should solve the
hanging issue, but offending drivers should be patched to properly claim
this clock.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: Bo Shen <voice.shen@atmel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Michael Turquette <mturquette@linaro.org>
5 years agoMerge tag 'v3.19-rockhip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel...
Michael Turquette [Mon, 12 Jan 2015 22:52:45 +0000 (14:52 -0800)]
Merge tag 'v3.19-rockhip-clkfixes1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-fixes

- two currently unused clocks that need to stay enabled
- fix the lock bit locations of the rk3066 plls
- fix rk3288 core divider values to the ones actually
  specified by the soc vendor

5 years agoclk: rockchip: add clock IDs for the PVTM clocks
Huang Lin [Fri, 19 Dec 2014 00:13:45 +0000 (16:13 -0800)]
clk: rockchip: add clock IDs for the PVTM clocks

Process-Voltage-Temperature Monitor has two clocks, PVTM_CORE and
PVTM_GPU.

Signed-off-by: Huang Lin <hl@rock-chips.com>
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: add clock ID for usbphy480m_src
Kever Yang [Thu, 13 Nov 2014 07:22:36 +0000 (15:22 +0800)]
clk: rockchip: add clock ID for usbphy480m_src

There are 3 different parent clock from different usbphy,
all of them are fixed 480MHz, it is not able to auto select
by clock core to the 2nd and the 3rd parent.
For different use case for different board, we may need to
select different usbphy clock out as parent manually.

Add the clock ID for it so that we can use in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: shmobile: Add R-Car Gen2 ADSP clock support
Sergei Shtylyov [Tue, 6 Jan 2015 22:39:52 +0000 (01:39 +0300)]
clk: shmobile: Add R-Car Gen2 ADSP clock support

Add the ADSP clock support to the R-Car generation 2 CPG driver.  This clock
gets derived from  PLL1.  The layout of the ADSPCKCR register is  similar to
those of the clocks supported by the 'clk-div6' driver but the divider encoding
is non-linear, so can't be supported by that driver...

Based on the original patch by Konstantin Kozhevnikov
<konstantin.kozhevnikov@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 years agoclk: shmobile: Add R-Car Gen2 RCAN clock support
Sergei Shtylyov [Mon, 5 Jan 2015 21:25:08 +0000 (00:25 +0300)]
clk: shmobile: Add R-Car Gen2 RCAN clock support

Add the RCAN clock support to the R-Car generation 2 CPG driver.  This clock
gets derived from  the USB_EXTAL clock, dividing  it by 6.  The layout of the
RCANCKCR register is similar to those of the clocks supported by the 'clk-div6'
driver but has no divider field, and so can't be supported by that driver...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 years agoclk: shmobile: Add r8a73a4 SoC to MSTP bindings
Ulrich Hecht [Wed, 17 Dec 2014 16:18:50 +0000 (17:18 +0100)]
clk: shmobile: Add r8a73a4 SoC to MSTP bindings

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 years agoclk: shmobile: r8a73a4 common clock framework implementation
Ulrich Hecht [Wed, 17 Dec 2014 16:18:49 +0000 (17:18 +0100)]
clk: shmobile: r8a73a4 common clock framework implementation

Driver for the R8A73A4's clocks that are too specific to be supported by a
generic driver.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 years agoclk: shmobile: r8a7793: document CPG clock support
Yoshihiro Kaneko [Wed, 10 Dec 2014 11:55:02 +0000 (20:55 +0900)]
clk: shmobile: r8a7793: document CPG clock support

Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 years agoclk: shmobile: Add r8a7793 support
Hisashi Nakamura [Mon, 8 Dec 2014 10:42:43 +0000 (19:42 +0900)]
clk: shmobile: Add r8a7793 support

R-Car M2N (r8a7793) clock is handled in R-Car Gen2 clock driver.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 years agoclk: shmobile: div6: Avoid changing divisor in .disable()
Geert Uytterhoeven [Mon, 24 Nov 2014 14:57:59 +0000 (15:57 +0100)]
clk: shmobile: div6: Avoid changing divisor in .disable()

While DIV6 clocks require the divisor field to be non-zero when stopping
the clock, some clocks (e.g. ZB on sh73a0) fail to be re-enabled later
if the divisor field is changed when stopping the clock.
The reason for this is unknown.

To fix this, do not touch the divisor field if it's already non-zero.

On kzm9g, the smsc911x Ethernet controller is connected to the sh73a0
Bus State Controller, which is clocked by the ZB clock. Without this
fix, if the ZB clock is disabled during system suspend, and re-enabled
during resume, the kernel locks up when the smsc911x driver tries to
access the Ethernet registers.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 years agoclk: sunxi: Propagate rate changes to parent for mux clocks
Chen-Yu Tsai [Tue, 6 Jan 2015 02:35:12 +0000 (10:35 +0800)]
clk: sunxi: Propagate rate changes to parent for mux clocks

The cpu clock on sunxi machines is just a mux clock, which is normally
fed by the main PLL, but can be muxed to the main or low power oscillator.

Make the mux clock propagate rate changes to its parent, so we can
change the clock rate of the PLL, and thus actually implement rate
changing on the cpu clock.

This patch also removes the no reparenting limit.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: sunxi: Make the mod0 clk driver also a platform driver
Hans de Goede [Sat, 20 Dec 2014 10:36:49 +0000 (11:36 +0100)]
clk: sunxi: Make the mod0 clk driver also a platform driver

With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated
through the mfd framework, and as such do not work with of_clk_declare, since
they do not have registers assigned to them yet at of_clk_declare init time.

Silence the error on not finding registers in the of_clk_declare mod0 clk
setup method, and also register mod0-clk support as a platform driver to work
properly with mfd instantiated mod0 clocks.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode
Doug Anderson [Mon, 22 Dec 2014 19:31:48 +0000 (11:31 -0800)]
clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode

We've been seeing some crashes at resume time on rk3288-based systems.
On some machines they simply never wake up from suspend.  Symptoms
include:

- System clearly got to sleep OK.  Power consumption is low, the PWM
  for the PWM regulator has stopped, and the "global_pwroff" output
  shows that the system is down.

- When system tries to wake up power consumption goes up.

- No kernel resume code (which was left in PMU SRAM) ran.  We added
  some basic logging to this code (write to a location in SRAM right
  at resume time) and didn't see the logging run.

It appears that we can fix the problem by slowing down APLL before we
suspend.  On the system I tested things seemed reliable if I disabled
1.8GHz and 1.7GHz.  The Mask ROM itself tries to slow things down
(which is why PLLs are in slow mode by the time we get to the kernel),
but apparently it is crashing before it even gets there.

We'll be super paranoid and not just go down to 1.6GHz but we'll match
what the Mask ROM seems to be doing and go into slow mode.  We'll also
be safe and put all PLLs (not just APLL) into slow mode (well, except
DPLL which is needed for SDRAM).  We'll even put NPLL into slow mode
which the Mask ROM didn't do (not that it's used for much important
stuff at early resume time).

Note that the old Rockchip reference code did something just like
this, though they jammed it into pm.c instead of putting it in the
syscore ops of the clock driver.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agoclk: rockchip: fix rk3288 cpuclk core dividers
Heiko Stuebner [Thu, 18 Dec 2014 19:06:57 +0000 (20:06 +0100)]
clk: rockchip: fix rk3288 cpuclk core dividers

Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.

Reported-by: Sonny Rao <sonnyrao@chromium.org>
Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Cc: stable@vger.kernel.org
5 years agoclk: rockchip: fix rk3066 pll lock bit location
Heiko Stuebner [Wed, 24 Dec 2014 13:31:06 +0000 (14:31 +0100)]
clk: rockchip: fix rk3066 pll lock bit location

The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.

The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.

Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Fixes: 2c14736c75db ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: FUKAUMI Naoki <naobsd@gmail.com>
Cc: stable@vger.kernel.org
5 years agoclk: samsung: exynos7: Add required clock tree for USB
Vivek Gautam [Fri, 21 Nov 2014 13:35:51 +0000 (19:05 +0530)]
clk: samsung: exynos7: Add required clock tree for USB

Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
5 years agoclk: samsung: exynos7: Add clocks for MSCL block
Tony K Nadackal [Wed, 17 Dec 2014 07:33:37 +0000 (13:03 +0530)]
clk: samsung: exynos7: Add clocks for MSCL block

Add clock support for the MSCL block for Exynos7.

Signed-off-by: Tony K Nadackal <tony.kn@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
5 years agoclk: sunxi: Fix factor clocks usage for sun9i core clocks
Chen-Yu Tsai [Thu, 27 Nov 2014 09:29:30 +0000 (17:29 +0800)]
clk: sunxi: Fix factor clocks usage for sun9i core clocks

The sunxi factor clocks usage was changed in

    clk: sunxi: Give sunxi_factors_register a registers parameter

However the sun9i core clocks were not fixed up in that patch,
resulting in breakage. This patch fixes that.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoclk: sunxi: Give sunxi_factors_register a registers parameter
Hans de Goede [Sun, 23 Nov 2014 13:38:07 +0000 (14:38 +0100)]
clk: sunxi: Give sunxi_factors_register a registers parameter

Before this commit sunxi_factors_register uses of_iomap(node, 0) to get
the clk registers. The sun6i prcm has factor clocks, for which we want to
use sunxi_factors_register, but of_iomap(node, 0) does not work for the prcm
factor clocks, because the prcm uses the mfd framework, so the registers
are not part of the dt-node, instead they are added to the platform_device,
as platform_device resources.

This commit makes getting the registers the callers duty, so that
sunxi_factors_register can be used with mfd instantiated platform device too.

While at it also add error checking to the of_iomap calls.

This commit also drops the __init function from sunxi_factors_register since
platform driver probe functions are not __init.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoARM: dts: sun8i: Add PLL6 and MBUS clock nodes
Chen-Yu Tsai [Mon, 24 Nov 2014 07:58:58 +0000 (15:58 +0800)]
ARM: dts: sun8i: Add PLL6 and MBUS clock nodes

Now that the clock driver supports PLL6 and MBUS on sun8i correctly,
add the corresponding clock nodes to the dtsi.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoARM: dts: sun8i: Unify ahb1 clock nodes
Chen-Yu Tsai [Wed, 26 Nov 2014 07:16:54 +0000 (15:16 +0800)]
ARM: dts: sun8i: Unify ahb1 clock nodes

The clock driver has unified support for the ahb1 clock.
Unify the clock nodes so it works.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
5 years agoARM: dts: sun6i: Unify ahb1 clock nodes
Chen-Yu Tsai [Wed, 26 Nov 2014 07:16:53 +0000 (15:16 +0800)]
ARM: dts: sun6i: Unify ahb1 clock nodes

The clock driver has unified support for the ahb1 clock.
Unify the clock nodes so it works.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>