sfrench/cifs-2.6.git
5 years agoclk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method
Gabriel Fernandez [Wed, 14 Dec 2016 14:22:28 +0000 (15:22 +0100)]
clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method

Clock and reset controller use same compatible strings (same IP).

Since commit 989eafd0b609 ("clk: core: Avoid double initialization of
clocks") the OF core flags clock controllers registered with the
CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same
compatible string will not be registered.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: renesas: mstp: Support 8-bit registers for r7s72100
Chris Brandt [Thu, 15 Dec 2016 17:00:27 +0000 (12:00 -0500)]
clk: renesas: mstp: Support 8-bit registers for r7s72100

The RZ/A1 is different than the other Renesas SOCs because the MSTP
registers are 8-bit instead of 32-bit and if you try writing values as
32-bit nothing happens...meaning this driver never worked for r7s72100.

Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
5 years agoclk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_prate()
Boris Brezillon [Mon, 12 Dec 2016 08:00:53 +0000 (09:00 +0100)]
clk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_prate()

best_rate is reported as potentially uninitialized by gcc.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 155e8b3b0ee3 ("clk: bcm: Support rate change propagation on bcm2835 clocks")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: add devm_get_clk_from_child() API
Kuninori Morimoto [Mon, 5 Dec 2016 05:23:20 +0000 (05:23 +0000)]
clk: add devm_get_clk_from_child() API

Some driver is using this type of DT bindings for clock (more detail,
see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt).

sound_soc {
...
cpu {
clocks = <&xxx>;
...
};
codec {
clocks = <&xxx>;
...
};
};

Current driver in this case uses of_clk_get() for each node, but there
is no devm_of_clk_get() today.
OTOH, the problem of having devm_of_clk_get() is that it encourages the
use of of_clk_get() when clk_get() is more desirable.

Thus, this patch adds new devm_get_clk_from_chile() which explicitly
reads as get a clock from a child node of this device.
By this function, we can also use this type of DT bindings

sound_soc {
clocks = <&xxx>, <&xxx>;
clock-names = "cpu", "codec";
clock-ranges;
...
cpu {
...
};
codec {
...
};
};

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[sboyd@codeurora.org: Rename subject to clk + add API]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: st: clk-flexgen: Unmap region obtained by of_iomap
Arvind Yadav [Mon, 19 Sep 2016 08:21:24 +0000 (13:51 +0530)]
clk: st: clk-flexgen: Unmap region obtained by of_iomap

Free memory mapping, if probe is not successful.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: keystone: pll: Unmap region obtained by of_iomap
Arvind Yadav [Tue, 20 Sep 2016 11:46:55 +0000 (17:16 +0530)]
clk: keystone: pll: Unmap region obtained by of_iomap

Free memory mapping, if of_pll_div_clk_init is not successful.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk:mmp:clk-of-mmp2: Free memory and Unmap region obtained by kzalloc and of_iomap
Arvind Yadav [Tue, 20 Sep 2016 11:08:58 +0000 (16:38 +0530)]
clk:mmp:clk-of-mmp2: Free memory and Unmap region obtained by kzalloc and of_iomap

Free memory and memory mapping , if mmp2_clk_init is not successful.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
[sboyd@codeaurora.org: Put return at the right place]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk:mmp:clk-of-pxa910: Free memory and Unmap region obtained by kzmalloc and of_iomap
Arvind Yadav [Tue, 20 Sep 2016 10:59:38 +0000 (16:29 +0530)]
clk:mmp:clk-of-pxa910: Free memory and Unmap region obtained by kzmalloc and of_iomap

Free memory and memory mapping , if pxa910_clk_init is not successful.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: mmp: clk-of-pxa1928: Free memory obtained by kzalloc
Arvind Yadav [Tue, 20 Sep 2016 09:52:48 +0000 (15:22 +0530)]
clk: mmp: clk-of-pxa1928: Free memory obtained by kzalloc

Free memory, if init is not successful.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: cdce925: Fix limit check
Christophe JAILLET [Fri, 11 Nov 2016 21:49:05 +0000 (22:49 +0100)]
clk: cdce925: Fix limit check

It is likely that instead of '1>64', 'q>64' was expected.

Moreover, according to datasheet,
   http://www.ti.com/lit/ds/symlink/cdce925.pdf
   SCAS847I - JULY 2007 - REVISED OCTOBER 2016
PLL settings limits are: 16 <= q <= 63
So change the upper limit check from 64 to 63.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: bcm: Make COMMON_CLK_IPROC into a library
Stephen Boyd [Wed, 23 Nov 2016 22:41:59 +0000 (14:41 -0800)]
clk: bcm: Make COMMON_CLK_IPROC into a library

The broadcom clk driver Kconfig file selects and depends on the
COMMON_CLK_IPROC config for different SoC specific drivers. Let's
simplify this by always selecting the COMMON_CLK_IPROC config,
turning it into a set of library code. We still want to retain
the SoC specific options, so we leave those in place. Since we're
here we also drop COMMON_CLK dependency because that's implicitly
handled by including this file in drivers/clk/Kconfig in the
right place and also make CLK_BCM_KONA default to y on the
architecture it exists for instead of plain default y.

Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <ray.jui@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: qoriq: added ls1012a clock configuration
Tang Yuantian [Thu, 24 Nov 2016 02:36:55 +0000 (10:36 +0800)]
clk: qoriq: added ls1012a clock configuration

Acked-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[sboyd@codeaurora.org: Sorted list]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: ti: dra7: fix "failed to lookup clock node gmac_gmii_ref_clk_div" boot message
Grygorii Strashko [Tue, 29 Nov 2016 23:07:57 +0000 (17:07 -0600)]
clk: ti: dra7: fix "failed to lookup clock node gmac_gmii_ref_clk_div" boot message

Prevent creating clk alias for non existing gmac_gmii_ref_clk_div clock and,
this way, eliminate excessive error message during boot:

 "ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div"

Fixes: c097338ebd3f ("ARM: dts: dra7: cpsw: fix clocks tree")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock
Boris Brezillon [Thu, 1 Dec 2016 21:00:20 +0000 (22:00 +0100)]
clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock

The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: bcm: Support rate change propagation on bcm2835 clocks
Boris Brezillon [Thu, 1 Dec 2016 21:00:19 +0000 (22:00 +0100)]
clk: bcm: Support rate change propagation on bcm2835 clocks

Some peripheral clocks, like the VEC (Video EnCoder) clock need to be set
to a precise rate (in our case 108MHz). With the current implementation,
where peripheral clocks are not allowed to forward rate change requests
to their parents, it is impossible to match this requirement unless the
bootloader has configured things correctly, or a specific rate has been
assigned through the DT (with the assigned-clk-rates property).

Add a new field to struct bcm2835_clock_data to specify which parent
clocks accept rate change propagation, and support set rate propagation
in bcm2835_clock_determine_rate().

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk
Boris Brezillon [Thu, 1 Dec 2016 19:27:21 +0000 (20:27 +0100)]
clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk

bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
to zero when disabling the clock.

Make sure we preserve this value by reading the previous a2w_reg value
first and ORing the result with A2W_PLL_CHANNEL_DISABLE.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: ti: omap36xx: Work around sprz319 advisory 2.1
Richard Watts [Fri, 2 Dec 2016 21:14:38 +0000 (23:14 +0200)]
clk: ti: omap36xx: Work around sprz319 advisory 2.1

The OMAP36xx DPLL5, driving EHCI USB, can be subject to a long-term
frequency drift. The frequency drift magnitude depends on the VCO update
rate, which is inversely proportional to the PLL divider. The kernel
DPLL configuration code results in a high value for the divider, leading
to a long term drift high enough to cause USB transmission errors. In
the worst case the USB PHY's ULPI interface can stop responding,
breaking USB operation completely. This manifests itself on the
Beagleboard xM by the LAN9514 reporting 'Cannot enable port 2. Maybe the
cable is bad?' in the kernel log.

Errata sprz319 advisory 2.1 documents PLL values that minimize the
drift. Use them automatically when DPLL5 is used for USB operation,
which we detect based on the requested clock rate. The clock framework
will still compute the PLL parameters and resulting rate as usual, but
the PLL M and N values will then be overridden. This can result in the
effective clock rate being slightly different than the rate cached by
the clock framework, but won't cause any adverse effect to USB
operation.

Signed-off-by: Richard Watts <rrw@kynesim.co.uk>
[Upported from v3.2 to v4.9]
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: clk-wm831x: fix a logic error
Pan Bian [Thu, 1 Dec 2016 06:25:44 +0000 (14:25 +0800)]
clk: clk-wm831x: fix a logic error

Fix bug https://bugzilla.kernel.org/show_bug.cgi?id=188561. Function
wm831x_clkout_is_prepared() returns "true" when it fails to read
CLOCK_CONTROL_1. "true" means the device is already prepared. So
return "true" on the read failure seems improper.

Signed-off-by: Pan Bian <bianpan2016@163.com>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Fixes: f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: uniphier: add cpufreq data for LD11, LD20 SoCs
Masahiro Yamada [Wed, 7 Dec 2016 01:32:33 +0000 (10:32 +0900)]
clk: uniphier: add cpufreq data for LD11, LD20 SoCs

Add more data to 64bit SoCs for the cpufreq support.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: uniphier: add CPU-gear change (cpufreq) support
Masahiro Yamada [Wed, 7 Dec 2016 01:32:32 +0000 (10:32 +0900)]
clk: uniphier: add CPU-gear change (cpufreq) support

Core support code for CPU frequency changes, which will be used by
the generic cpufreq driver.

The register view is different from the generic clk-mux; it has
a separate status register, and an update bit to load the register
setting.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoMerge tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git...
Stephen Boyd [Wed, 30 Nov 2016 22:38:00 +0000 (14:38 -0800)]
Merge tag 'v4.10-rockchip-clk2' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP),
a fix making sure the cpuclk rate is actually valid, before trying to
set it and a copy-paste fix for the rk3399's testclk.

* tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add clock controller for rk1108
  dt-bindings: add documentation for rk1108 cru
  clk: rockchip: add dt-binding header for rk1108
  clk: rockchip: fix copy-paste error in rk3399 testclk
  clk: rockchip: validity should be checked prior to cpu clock rate change

6 years agoclk: qcom: Put venus core0/1 gdscs to hw control mode
Sricharan R [Fri, 18 Nov 2016 12:28:27 +0000 (17:58 +0530)]
clk: qcom: Put venus core0/1 gdscs to hw control mode

The venus video ip's internal core blocks are under the
control of the firmware and their powerdomains needs to be
'ON' only when used by the firmware. So putting it into
hw controlled mode lets this to happen, otherwise the firmware
hangs checking for this.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: qcom: gdsc: Add support for gdscs with HW control
Rajendra Nayak [Fri, 18 Nov 2016 12:28:26 +0000 (17:58 +0530)]
clk: qcom: gdsc: Add support for gdscs with HW control

Some GDSCs might support a HW control mode, where in the power
domain (gdsc) is brought in and out of low power state (while
unsued) without any SW assistance, saving power.
Such GDSCs can be configured in a HW control mode when powered on
until they are explicitly requested to be powered off by software.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoMerge branch 'clk-fixes' into clk-next
Stephen Boyd [Wed, 23 Nov 2016 22:31:45 +0000 (14:31 -0800)]
Merge branch 'clk-fixes' into clk-next

* clk-fixes:
  clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX
  clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock
  clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it

6 years agoclk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX
Florian Fainelli [Tue, 22 Nov 2016 17:43:27 +0000 (09:43 -0800)]
clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX

With commit f4e871509959 ("clk: iproc: Make clocks visible options"),
COMMON_CLK_IPROC gained a dependency on ARCH_BCM_IPROC, yet CLK_BCM_63XX
also selects that option, this causes the following Kconfig warning:

warning: (CLK_BCM_63XX) selects COMMON_CLK_IPROC which has unmet direct
dependencies ((ARCH_BCM_IPROC || COMPILE_TEST) && COMMON_CLK)

Fix this by adding proper depends for COMMON_CLK_IPROC

Fixes: f4e871509959 ("clk: iproc: Make clocks visible options")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
[sboyd@codeaurora.org: Drop default part as it's redundant]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock
Icenowy Zheng [Thu, 17 Nov 2016 16:49:54 +0000 (00:49 +0800)]
clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock

In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control
register is called "LDO{1,2}_EN", and according to the BSP source code
from Allwinner [1], the LDOs are enabled during the clock's enabling
process.

The clock failed to generate output if the two LDOs are not enabled.

Add the two bits to the clock's gate bits, so that the LDOs are enabled
when the PLL is enabled.

[1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429

Fixes: d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
6 years agoclk: bcm2835: Fix ->fixed_divider of pllh_aux
Boris Brezillon [Tue, 22 Nov 2016 20:45:28 +0000 (12:45 -0800)]
clk: bcm2835: Fix ->fixed_divider of pllh_aux

There is no fixed divider on pllh_aux.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: qcom: clk-rpm: Fix clk_hw references
Georgi Djakov [Wed, 23 Nov 2016 14:52:49 +0000 (16:52 +0200)]
clk: qcom: clk-rpm: Fix clk_hw references

Fix the clk_hw references to the actual clocks and add a xlate function
to return the hw pointers from the already existing static array.

Reported-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: qcom: clk-smd-rpm: Fix clk_hw references
Georgi Djakov [Wed, 23 Nov 2016 14:52:48 +0000 (16:52 +0200)]
clk: qcom: clk-smd-rpm: Fix clk_hw references

Fix the clk_hw references to the actual clocks and add a xlate function
to return the hw pointers from the already existing static array.

Reported-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops
Rajendra Nayak [Mon, 21 Nov 2016 06:37:12 +0000 (12:07 +0530)]
clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops

The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084
expects a clk_set_rate() on the sdcc rcg clk to set
a floor value of supported clk rate closest to the requested
rate, by looking up the frequency table.
So move all the sdcc rcgs on all these platforms to use the
newly introduced clk_rcg2_floor_ops

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: qcom: Add rcg ops to return floor value closest to the requested rate
Rajendra Nayak [Mon, 21 Nov 2016 06:37:11 +0000 (12:07 +0530)]
clk: qcom: Add rcg ops to return floor value closest to the requested rate

The default behaviour with clk_rcg2_ops is for the
clk_round_rate()/clk_set_rate() to return/set a ceil clock
rate closest to the requested rate by looking up the corresponding
frequency table.
However, we do have some instances (mainly sdcc on various platforms)
of clients expecting a clk_set_rate() to set a floor value instead.
Add a new clk_rcg2_floor_ops to handle this for such specific
rcg instances

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoMerge tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung into clk...
Stephen Boyd [Tue, 22 Nov 2016 01:27:02 +0000 (17:27 -0800)]
Merge tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung into clk-next

Pull Exynos5433 SoC updates from Sylwester Nawrocki:

 - addition of missing documentation and DT properties for the CMU_AUD
   block source clocks,
 - correction of CMU_FSYS parent clock definition,
 - marking as critical clocks which have to be enabled in order
   to access control registers of child CMUs.

* tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung:
  clk: exynos5433: Mark some clocks as critical
  clk: exynos5433: Add documentation for the audio block parent clocks
  clk: exynos5433: Fix parent clocks for FSYS block

6 years agoclk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it
Chen-Yu Tsai [Fri, 18 Nov 2016 07:15:57 +0000 (15:15 +0800)]
clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it

The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.

Add the 2 LDO enable bits to the gate bits. This fixes issues with
the TCON not sending vblank interrupts when the tcon and dot clock are
indirectly clocked from the PLL-MIPI clock.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
6 years agoclk: exynos5433: Mark some clocks as critical
Marek Szyprowski [Fri, 18 Nov 2016 10:04:18 +0000 (11:04 +0100)]
clk: exynos5433: Mark some clocks as critical

Some parent clocks of the Exynos5433 CMUs must be always enabled to access
any register in the given CMU or devices connected to it. For the time
being, until a proper solution based on runtime PM is applied, mark those
clocks as critical (instead of ignore unused) to prevent disabling them.

Reported-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
6 years agoMerge tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Thu, 17 Nov 2016 23:07:23 +0000 (15:07 -0800)]
Merge tag 'clk-renesas-for-v4.10-tag3' of git://git./linux/kernel/git/geert/renesas-drivers into clk-next

Pull more clk driver updates from Geert Uytterhoeven:

  - CSI2 and VIN clocks for R-Car M3-W,
  - Clock drivers for new RZ/G1M and RZ/G1E SoCs,
  - Minor bug fix for R-Car H3.

* tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Add R8A7745 support
  clk: renesas: cpg-mssr: Add R8A7743 support
  clk: renesas: cpg-mssr: Add common R-Car Gen2 support
  clk: renesas: r8a7795: Fix HDMI parent clock
  clk: renesas: r8a7796: Add VIN clocks
  clk: renesas: r8a7796: Add CSI2 clocks

6 years agoMerge tag 'clk-renesas-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Thu, 17 Nov 2016 21:31:07 +0000 (13:31 -0800)]
Merge tag 'clk-renesas-for-v4.10-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geerty Uytterhoeven:

  - Add R-Car RST driver for obtaining mode pin state, and move the
    related functionality from platform code to DT,
  - Add r8a7743 and r8a7745 CPG Core Clock Definitions.

The commits here are intermingled with arm-soc material because
of the hard dependency we're breaking between mach code and
driver code. We're replacing that with a driver dependency
between the soc driver and the clk driver.

* tag 'clk-renesas-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (25 commits)
  clk: renesas: Add r8a7745 CPG Core Clock Definitions
  clk: renesas: Add r8a7743 CPG Core Clock Definitions
  clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init()
  clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init()
  clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init()
  ARM: shmobile: rcar-gen2: Stop passing mode pins state to clock driver
  ARM: shmobile: r8a7779: Stop passing mode pins state to clock driver
  ARM: shmobile: r8a7778: Stop passing mode pins state to clock driver
  clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()
  clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver
  clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driver
  clk: renesas: rcar-gen2: Obtain mode pin values using RST driver
  clk: renesas: r8a7779: Obtain mode pin values from R-Car RST driver
  clk: renesas: r8a7778: Obtain mode pin values using R-Car RST driver
  arm64: renesas: r8a7796 dtsi: Add device node for RST module
  arm64: renesas: r8a7795 dtsi: Add device node for RST module
  ARM: dts: r8a7794: Add device node for RST module
  ARM: dts: r8a7793: Add device node for RST module
  ARM: dts: r8a7792: Add device node for RST module
  ARM: dts: r8a7791: Add device node for RST module
  ...

6 years agoclk: exynos5433: Add documentation for the audio block parent clocks
Marek Szyprowski [Thu, 17 Nov 2016 11:42:53 +0000 (12:42 +0100)]
clk: exynos5433: Add documentation for the audio block parent clocks

Audio block requires access to two parent clocks: audio PLL and oscillator,
so add this information to device tree bindings documentation.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
6 years agoclk: exynos5433: Fix parent clocks for FSYS block
Marek Szyprowski [Thu, 17 Nov 2016 11:42:52 +0000 (12:42 +0100)]
clk: exynos5433: Fix parent clocks for FSYS block

The proper parent clock for FSYS block is "aclk_fsys_200"
according to the Exynos5433 reference manual.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
6 years agoclk: sunxi-ng: Mark structs static and cleanup spaces
Stephen Boyd [Wed, 16 Nov 2016 19:27:28 +0000 (11:27 -0800)]
clk: sunxi-ng: Mark structs static and cleanup spaces

Some checkpatch warnings about spaces were missed and we didn't
mark two structs as static. Clean it up.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoMerge tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git...
Stephen Boyd [Wed, 16 Nov 2016 19:19:20 +0000 (11:19 -0800)]
Merge tag 'sunxi-clk-for-4.10' of https://git./linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock changes from Maxime Ripard:

The usual patches from us, but most notably the introduction of the A64
clocks unit.

* tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks
  clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks
  clk: sunxi-ng: Add A64 clocks
  clk: sunxi-ng: Implement minimum for multipliers
  clk: sunxi-ng: Add minimums for all the relevant structures and clocks
  clk: sunxi-ng: Finish to convert to structures for arguments
  clk: sunxi-ng: Remove the use of rational computations
  clk: sunxi-ng: Rename the internal structures
  clk: sunxi: mod0: improve function-level documentation

6 years agoMerge tag 'imx-clk-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo...
Stephen Boyd [Wed, 16 Nov 2016 19:16:07 +0000 (11:16 -0800)]
Merge tag 'imx-clk-4.10' of git://git./linux/kernel/git/shawnguo/linux into clk-next

Pull i.MX clock updates from Shawn Guo:

 - A patch series to fix the long standing issue with glitchy parent
   mux of ldb_di_clk, which can hang up LVDS display when ipu_di_clk
   is sourced from ldb_di_clk.
 - A patch to add imx6ull clock support on top of imx6ul clock driver.

* tag 'imx-clk-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx: clk-imx6ul: add clk support for imx6ull
  clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK
  clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only
  clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf

6 years agoMerge branch 'clk-fixes' into clk-next
Stephen Boyd [Wed, 16 Nov 2016 19:15:58 +0000 (11:15 -0800)]
Merge branch 'clk-fixes' into clk-next

* clk-fixes:
  clk: efm32gg: Pass correct type to hw provider registration
  clk: berlin: Pass correct type to hw provider registration
  clk: sunxi: Fix M factor computation for APB1
  clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent

6 years agoMerge tag 'sunxi-clk-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Wed, 16 Nov 2016 19:10:58 +0000 (11:10 -0800)]
Merge tag 'sunxi-clk-fixes-for-4.9' of https://git./linux/kernel/git/mripard/linux into clk-fixes

Pull Allwinner clock fixes from Maxime Ripard:

Two fixes, one for the old clock code, one for the new implementation.

* tag 'sunxi-clk-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi: Fix M factor computation for APB1
  clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent

6 years agoclk: efm32gg: Pass correct type to hw provider registration
Stephen Boyd [Wed, 16 Nov 2016 19:02:00 +0000 (11:02 -0800)]
clk: efm32gg: Pass correct type to hw provider registration

Dan Carpenter reports that we're passing a pointer to a pointer
here when we should just be passing a pointer. Pass the right
pointer so that the of_clk_hw_onecell_get() sees the appropriate
data pointer on its end.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Stephen Boyd <stephen.boyd@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Fixes: 9337631f52a8 ("clk: efm32gg: Migrate to clk_hw based OF and registration APIs")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: berlin: Pass correct type to hw provider registration
Stephen Boyd [Wed, 16 Nov 2016 19:02:00 +0000 (11:02 -0800)]
clk: berlin: Pass correct type to hw provider registration

Dan Carpenter reports that we're passing a pointer to a pointer
here when we should just be passing a pointer. Pass the right
pointer so that the of_clk_hw_onecell_get() sees the appropriate
data pointer on its end.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Jisheng Zhang <jszhang@marvell.com>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Stephen Boyd <stephen.boyd@linaro.org>
Fixes: f6475e298297 ("clk: berlin: Migrate to clk_hw based registration and OF APIs")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: rockchip: add clock controller for rk1108
Shawn Lin [Wed, 16 Nov 2016 08:49:23 +0000 (16:49 +0800)]
clk: rockchip: add clock controller for rk1108

Add the clock tree definition and driver for rk1108 SoC.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Jacob Chen <jacob2.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
6 years agodt-bindings: add documentation for rk1108 cru
Shawn Lin [Wed, 16 Nov 2016 08:49:21 +0000 (16:49 +0800)]
dt-bindings: add documentation for rk1108 cru

This adds the dt-binding documentation for the clock and reset unit
found on Rockchip rk1108 SoCs.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
6 years agoMerge branch 'v4.10-shared/clkids' into v4.10-clk/next
Heiko Stuebner [Wed, 16 Nov 2016 11:19:20 +0000 (12:19 +0100)]
Merge branch 'v4.10-shared/clkids' into v4.10-clk/next

6 years agoclk: rockchip: add dt-binding header for rk1108
Shawn Lin [Wed, 16 Nov 2016 08:49:22 +0000 (16:49 +0800)]
clk: rockchip: add dt-binding header for rk1108

Add the dt-bindings header for the rk1108, that gets shared
between the clock controller and the clock references in the dts.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
6 years agoclk: rockchip: fix copy-paste error in rk3399 testclk
Jianqun Xu [Wed, 16 Nov 2016 00:19:41 +0000 (08:19 +0800)]
clk: rockchip: fix copy-paste error in rk3399 testclk

Fix RK3368_* to RK3399_* for rk3399 clk_test clock.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
6 years agoclk: Hi6220: enable stub clock driver for ARCH_HISI
Leo Yan [Wed, 31 Aug 2016 08:50:15 +0000 (16:50 +0800)]
clk: Hi6220: enable stub clock driver for ARCH_HISI

In current kernel config 'CONFIG_STUB_CLK_HI6220' is disabled by
default, as result stub clock driver has not been registered and
CPUFreq driver cannot work.

This patch is to enable stub clock driver in config for ARCH_HISI.

Reported-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoMerge tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git...
Stephen Boyd [Tue, 15 Nov 2016 02:38:35 +0000 (18:38 -0800)]
Merge tag 'v4.10-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next

Pull Rockchip clk driver updates from Heiko Stuebner:

PLL initialization for PLLs having both an integral and fractional mode
(rk3036, rk3399) does now take into account the mode that the PLL is
actually running at.

As always also some additional and optimized PLL rates for rk3066 and
rk3399, some additional clock ids for rk3066 and some additional clocks
on rk3399 are now sucessfully handled inside their respective driver.

* tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused
  clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree
  clk: rockchip: add 400MHz to rk3066 clock rates table
  clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399
  clk: rockchip: Use clock ids for cpu and peri clocks on rk3066
  clk: rockchip: Add binding ids for cpu and peri clocks on rk3066
  clk: rockchip: add 533.25MHz to rk3399 clock rates table

6 years agoMerge tag 'clk-renesas-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Tue, 15 Nov 2016 02:35:42 +0000 (18:35 -0800)]
Merge tag 'clk-renesas-for-v4.10-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - SYS-DMAC, (H)SCIF, I2C, DRIF, and graphics related clocks for R-Car
    M3-W,
  - Minor fixes and cleanups.

* tag 'clk-renesas-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add DU and LVDS clocks
  clk: renesas: r8a7796: Add VSP clocks
  clk: renesas: r8a7796: Add FCP clocks
  clk: renesas: cpg-mssr: Remove bogus commas from error messages
  clk: renesas: r8a7796: Add DRIF clock
  clk: renesas: cpg-mssr: Fix inverted debug check
  clk: renesas: rcar-gen3-cpg: Always use readl()/writel()
  clk: renesas: cpg-mssr: Always use readl()/writel()
  clk: renesas: r8a7796: Add I2C clocks
  clk: renesas: r8a7796: Add HSCIF clocks
  clk: renesas: r8a7796: Add SCIF clocks
  clk: renesas: r8a7796: Add SYS-DMAC clocks

6 years agoclk: imx: clk-imx6ul: add clk support for imx6ull
Bai Ping [Mon, 14 Nov 2016 07:04:22 +0000 (15:04 +0800)]
clk: imx: clk-imx6ul: add clk support for imx6ull

imx6ull is the derived SoC from imx6ul

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
6 years agoMerge branch 'clk-hisi' into clk-next
Stephen Boyd [Mon, 14 Nov 2016 22:25:11 +0000 (14:25 -0800)]
Merge branch 'clk-hisi' into clk-next

* clk-hisi:
  clk: hisilicon: add CRG driver for Hi3516CV300 SoC
  clk: hisilicon: add CRG driver for Hi3798CV200 SoC

6 years agoclk: hisilicon: add CRG driver for Hi3516CV300 SoC
Pan Wen [Mon, 14 Nov 2016 02:49:54 +0000 (10:49 +0800)]
clk: hisilicon: add CRG driver for Hi3516CV300 SoC

Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.

Signed-off-by: Pan Wen <wenpan@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: rockchip: validity should be checked prior to cpu clock rate change
Elaine Zhang [Tue, 8 Nov 2016 09:10:14 +0000 (17:10 +0800)]
clk: rockchip: validity should be checked prior to cpu clock rate change

If validity is not checked prior to clock rate change, clk_set_rate(
cpu_clk, unsupported_rate) will return success, but the real clock rate
change operation is prohibited in post clock change event. Alough post
clock change event will report error due to unsupported clock rate is
set, but this error message is ignored by clock framework.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Tested-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
6 years agoclk: hisilicon: add CRG driver for Hi3798CV200 SoC
Jiancheng Xue [Sat, 29 Oct 2016 06:13:37 +0000 (14:13 +0800)]
clk: hisilicon: add CRG driver for Hi3798CV200 SoC

Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks
Chen-Yu Tsai [Fri, 11 Nov 2016 10:05:58 +0000 (18:05 +0800)]
clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks

The audio module clocks are supposed to be set according to the sample
rate of the audio stream. The audio PLL provides the clock signal for
these module clocks, and only it is freely tunable.

Set CLK_SET_RATE_PARENT for the audio module clocks so their users can
properly tune the clock rate.

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
6 years agoclk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks
Chen-Yu Tsai [Fri, 11 Nov 2016 10:05:57 +0000 (18:05 +0800)]
clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks

The audio module clocks are supposed to be set according to the sample
rate of the audio stream. The audio PLL provides the clock signal for
these module clocks, and only it is freely tunable.

Set CLK_SET_RATE_PARENT for the audio module clocks so their users can
properly tune the clock rate.

Fixes: 5690879d93e8 ("clk: sunxi-ng: Add A23 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
6 years agoMerge branch 'clk-qcom-rpm' into clk-next
Stephen Boyd [Fri, 11 Nov 2016 00:50:16 +0000 (16:50 -0800)]
Merge branch 'clk-qcom-rpm' into clk-next

* clk-qcom-rpm:
  clk: qcom: Add support for RPM Clocks
  clk: qcom: Add support for SMD-RPM Clocks
  clk: qcom: Always add factor clock for xo clocks

6 years agoclk: qcom: Add support for RPM Clocks
Georgi Djakov [Wed, 2 Nov 2016 15:56:57 +0000 (17:56 +0200)]
clk: qcom: Add support for RPM Clocks

This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_rpm driver to communicate with RPM.
Such platforms are apq8064 and msm8960.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: qcom: Add support for SMD-RPM Clocks
Georgi Djakov [Wed, 2 Nov 2016 15:56:56 +0000 (17:56 +0200)]
clk: qcom: Add support for SMD-RPM Clocks

This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_smd_rpm driver to communicate with RPM.
Such platforms are msm8916, apq8084 and msm8974.

The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.

This driver is based on the codeaurora.org driver:
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Remove useless braces for single line if]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: qcom: Always add factor clock for xo clocks
Georgi Djakov [Wed, 2 Nov 2016 15:56:58 +0000 (17:56 +0200)]
clk: qcom: Always add factor clock for xo clocks

Currently the RPM/RPM-SMD clock drivers do not register the xo clocks,
so we should always add factor clock. When we later add xo clocks support
into the drivers, we should update this function to skip registration.
By doing so we avoid any DT dependencies.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoMerge branch 'clk-qcom-8994' into clk-next
Stephen Boyd [Thu, 10 Nov 2016 23:47:56 +0000 (15:47 -0800)]
Merge branch 'clk-qcom-8994' into clk-next

* clk-qcom-8994:
  clk: qcom: Add support for msm8994 global clock controller
  dt-bindings: qcom: clocks: Add msm8994 clock bindings

6 years agoclk: qcom: Add support for msm8994 global clock controller
Bastian Köcher [Fri, 4 Nov 2016 20:56:35 +0000 (13:56 -0700)]
clk: qcom: Add support for msm8994 global clock controller

The clock definition was ported from the Google 3.10 kernel tree to
work with the latest kernel.

Signed-off-by: Bastian Köcher <mail@kchr.de>
[jeremymc@redhat.com: created new commit of just dt-bindings]
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
[sboyd@codeaurora.org: Tidy up commit text and Kconfig help]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agodt-bindings: qcom: clocks: Add msm8994 clock bindings
Jeremy McNicoll [Fri, 4 Nov 2016 20:56:32 +0000 (13:56 -0700)]
dt-bindings: qcom: clocks: Add msm8994 clock bindings

Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
[sboyd@codeaurora.org: Dropped unused and incorrect GDSC defines]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: tegra: dfll: Use builtin_platform_driver to simplify the code
Wei Yongjun [Thu, 10 Nov 2016 15:20:24 +0000 (15:20 +0000)]
clk: tegra: dfll: Use builtin_platform_driver to simplify the code

Use the builtin_platform_driver() macro to make the code simpler.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: renesas: cpg-mssr: Add R8A7745 support
Sergei Shtylyov [Tue, 8 Nov 2016 21:25:08 +0000 (00:25 +0300)]
clk: renesas: cpg-mssr: Add R8A7745 support

Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
6 years agoclk: renesas: cpg-mssr: Add R8A7743 support
Sergei Shtylyov [Tue, 8 Nov 2016 21:21:50 +0000 (00:21 +0300)]
clk: renesas: cpg-mssr: Add R8A7743 support

Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
6 years agoclk: renesas: cpg-mssr: Add common R-Car Gen2 support
Sergei Shtylyov [Tue, 8 Nov 2016 21:17:25 +0000 (00:17 +0300)]
clk: renesas: cpg-mssr: Add common R-Car Gen2 support

Add the common R-Car Gen2 (and RZ/G) Clock Pulse Generator / Module
Standby and Software Reset support code, using the CPG/MSSR driver
core.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
6 years agoclk: qcom: ipq806x: Fix board clk rates
Stephen Boyd [Thu, 10 Nov 2016 01:08:28 +0000 (17:08 -0800)]
clk: qcom: ipq806x: Fix board clk rates

The clocks on these boards run at 25 MHz, not 19.2 and 27 like
other platforms. Unfortunately I copy/pasted from other similar
SoCs but forgot this one is different. Fix it.

Fixes: a085f877a882 ("clk: qcom: Move cxo/pxo/xo into dt files")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: pxa: Use __iomem properly and staticize lock variable
Stephen Boyd [Tue, 8 Nov 2016 22:47:56 +0000 (14:47 -0800)]
clk: pxa: Use __iomem properly and staticize lock variable

This function is passed an __iomem pointer but we use a u32
pointer instead which makes checkers like spare complain.
Furthermore, "lock" is a pretty poor variable name for a string
that will go into lockdep reports and the symbol isn't marked
static. Cleanup all this.

Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: gate: fix coding style
Uwe Kleine-König [Wed, 9 Nov 2016 11:00:46 +0000 (12:00 +0100)]
clk: gate: fix coding style

The : of the ?: operator should have a leading space.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
[sboyd@codeaurora.org: Also remove useless parenthesis]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: pxa: fix pxa2xx_determine_rate return
Arnd Bergmann [Tue, 8 Nov 2016 14:49:31 +0000 (15:49 +0100)]
clk: pxa: fix pxa2xx_determine_rate return

The new pxa2xx_determine_rate() function seems lacking in a few
regards:

- For an exact match or no match at all, the rate is uninitialized
  as reported by gcc -Wmaybe-unintialized:
   drivers/clk/pxa/clk-pxa.c: In function 'pxa2xx_determine_rate':
   drivers/clk/pxa/clk-pxa.c:243:5: error: 'rate' may be used uninitialized in this function

- If we get a non-exact match, the req->rate output is never set
  to the actual rate but remains at the requested rate.

- We should not attempt to print a rate if none could be found

This rewrites the logic accordingly.

Fixes: 9fe694295098 ("clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoreset: mediatek: Add MT2701 reset driver
Shunli Wang [Fri, 4 Nov 2016 07:43:06 +0000 (15:43 +0800)]
reset: mediatek: Add MT2701 reset driver

In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.

Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Tested-by: John Crispin <blogic@openwrt.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: mediatek: Add MT2701 clock support
Shunli Wang [Fri, 4 Nov 2016 07:43:05 +0000 (15:43 +0800)]
clk: mediatek: Add MT2701 clock support

Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Tested-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: pxa mark dummy helper as 'inline'
Arnd Bergmann [Tue, 8 Nov 2016 14:49:30 +0000 (15:49 +0100)]
clk: pxa mark dummy helper as 'inline'

The dummy_clk_set_parent function is marked as 'static' but is
no longer referenced from the pxa25x clk driver after the last use
of the RATE_RO_OPS() macro is gone from this file, causing a
harmless build warning:

In file included from drivers/clk/pxa/clk-pxa25x.c:24:0:
drivers/clk/pxa/clk-pxa.h:146:12: error: 'dummy_clk_set_parent' defined but not used [-Werror=unused-function]

This marks the functon as 'inline', which lets the compiler simply
drop it when it gets referenced.

Fixes: 9fe694295098 ("clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: renesas: r8a7795: Fix HDMI parent clock
Takeshi Kihara [Fri, 4 Nov 2016 13:58:07 +0000 (14:58 +0100)]
clk: renesas: r8a7795: Fix HDMI parent clock

Correct HDMI parent clock so that the rate of the
HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
as per the v0.52 (Jun, 15) manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
6 years agoclk: renesas: r8a7796: Add VIN clocks
Niklas Söderlund [Tue, 1 Nov 2016 20:12:25 +0000 (21:12 +0100)]
clk: renesas: r8a7796: Add VIN clocks

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
6 years agoclk: renesas: r8a7796: Add CSI2 clocks
Niklas Söderlund [Tue, 1 Nov 2016 20:12:24 +0000 (21:12 +0100)]
clk: renesas: r8a7796: Add CSI2 clocks

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
6 years agoMerge branch 'rzg-clock-defs' into clk-renesas-for-v4.10
Geert Uytterhoeven [Mon, 7 Nov 2016 14:15:33 +0000 (15:15 +0100)]
Merge branch 'rzg-clock-defs' into clk-renesas-for-v4.10

Add r8a7743 and r8a7745 CPG Core Clock Definitions

6 years agoclk: renesas: Add r8a7745 CPG Core Clock Definitions
Sergei Shtylyov [Thu, 27 Oct 2016 20:42:51 +0000 (23:42 +0300)]
clk: renesas: Add r8a7745 CPG Core Clock Definitions

Add macros usable by the device tree sources to reference the R8A7745
CPG clocks by index. The data comes from Table 7.2c in revision 1.00 of
the RZ/G Series User's Manual.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
6 years agoclk: renesas: Add r8a7743 CPG Core Clock Definitions
Sergei Shtylyov [Thu, 27 Oct 2016 20:23:35 +0000 (23:23 +0300)]
clk: renesas: Add r8a7743 CPG Core Clock Definitions

Add macros usable by the device tree sources to reference the R8A7743 CPG
clocks by index. The data comes from Table 7.2b in revision 1.00 of the
RZ/G Series User's Manual.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
6 years agoclk: rockchip: Ignore frac divisor for PLL equivalence when it's unused
Julius Werner [Wed, 2 Nov 2016 23:43:24 +0000 (16:43 -0700)]
clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused

Rockchip RK3399 PLLs can be used in two separate modes: integral and
fractional. We can select between these two modes with the unambiguously
named DSMPD bit.

During boot, we check all PLL settings to confirm that they match our
PLL table for that frequency, and reinitialize the PLLs where they
don't. The settings checked for this include the fractional divider
field that is only used in fractional mode, even if we're in integral
mode (DSMPD = 1) and that field has no effect.

This patch changes the check to only compare the fractional divider if
we're actually in fractional mode. This way, we won't reinitialize the
PLL in cases where there's absolutely no reason for that, which may
avoid glitching child clocks that should better not be glitched (e.g.
PWM regulators).

Signed-off-by: Julius Werner <jwerner@chromium.org>
[cloned the fix to the pretty similar rk3036 pll]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
6 years agoclk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree
Jianqun Xu [Thu, 3 Nov 2016 03:38:53 +0000 (11:38 +0800)]
clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree

Optimize rk3399 clocktree by removing CLK_IGNORE_UNUSED of some clocks.

clocks will managered by usb:
- clk_usbphy0_480m_src
- clk_usbphy1_480m_src
- clk_usbphy_480m

clocks will be managered by pvtm:
- clk_pvtm_core_l
- clk_pvtm_core_b
- clk_pvtm_ddr

clocks will be managered by dfi:
- pclk_ddr_mon
- clk_dfimon0_timer
- clk_dfimon1_timer
- aclk_dcf
- pclk_dcf

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
6 years agoclk: rockchip: add 400MHz to rk3066 clock rates table
Paweł Jarosz [Fri, 4 Nov 2016 13:10:56 +0000 (14:10 +0100)]
clk: rockchip: add 400MHz to rk3066 clock rates table

We need this to init PLL_CPLL to 400MHz at boot.

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
6 years agoclk: ti: make clk-dra7-atl explicitly non-modular
Paul Gortmaker [Mon, 4 Jul 2016 21:12:20 +0000 (17:12 -0400)]
clk: ti: make clk-dra7-atl explicitly non-modular

The Kconfig currently controlling compilation of this code is:

arch/arm/mach-omap2/Kconfig:config SOC_DRA7XX
arch/arm/mach-omap2/Kconfig:    bool "TI DRA7XX"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tags etc. since all that information
is already contained at the top of the file in the comments.

Cc: Tero Kristo <t-kristo@ti.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-omap@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modular
Paul Gortmaker [Mon, 4 Jul 2016 21:12:19 +0000 (17:12 -0400)]
clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modular

The Kconfig currently controlling compilation of this code is:

arch/arm/mach-tegra/Kconfig:config ARCH_TEGRA_124_SOC
arch/arm/mach-tegra/Kconfig:    bool "Enable support for Tegra124 family"

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

Since module_init translates to device_initcall in the non-modular
case, the init ordering remains unchanged with this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tags etc. since all that information
is already contained at the top of the file in the comments.

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Aleksandr Frid <afrid@nvidia.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: mvebu: make ap806-system-controller explicitly non-modular
Paul Gortmaker [Mon, 4 Jul 2016 21:12:14 +0000 (17:12 -0400)]
clk: mvebu: make ap806-system-controller explicitly non-modular

The Kconfig currently controlling compilation of this code is:

drivers/clk/mvebu/Kconfig:config ARMADA_AP806_SYSCON
drivers/clk/mvebu/Kconfig:      bool

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: mvebu: make cp110-system-controller explicitly non-modular
Paul Gortmaker [Mon, 4 Jul 2016 21:12:13 +0000 (17:12 -0400)]
clk: mvebu: make cp110-system-controller explicitly non-modular

The Kconfig currently controlling compilation of this code is:

drivers/clk/mvebu/Kconfig:config ARMADA_CP110_SYSCON
drivers/clk/mvebu/Kconfig:      bool

...meaning that it currently is not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.

We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: pxa: transfer CPU clock setting from pxa2xx-cpufreq
Robert Jarzmik [Wed, 2 Nov 2016 21:33:06 +0000 (22:33 +0100)]
clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq

This is the initial stage to transfer the pxa25x and pxa27x CPU clocks
handling from cpufreq to the clock API. More precisely, the clocks
transferred are :
 - cpll : core pll, known also as the CPU core turbo frequency
 - core : core, known also as the CPU actual frequency, being either the
          CPU core turbo frequency or the CPU core run frequency

This transfer is a prequel to shrink the code in pxa2xx-cpufreq.c, so
that it can become, at least in devicetree builds, the casual cpufreq-dt
driver.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: sunxi: Fix M factor computation for APB1
Stéphan Rafin [Thu, 3 Nov 2016 23:53:56 +0000 (00:53 +0100)]
clk: sunxi: Fix M factor computation for APB1

commit cfa636886033 ("clk: sunxi: factors: Consolidate get_factors
parameters into a struct") introduced a regression for m factor
computation in sun4i_get_apb1_factors function.

The old code reassigned the "parent_rate" parameter to the targeted
divisor value and was buggy for the returned frequency but not for the
computed factors. Now, returned frequency is good but m factor is
incorrectly computed (its max value 31 is always set resulting in a
significantly slower frequency than the requested one...)

This patch simply restores the original proper computation for m while
keeping the good changes for returned rate.

Fixes: cfa636886033 ("clk: sunxi: factors: Consolidate get_factors parameters into a struct")
Signed-off-by: Stéphan Rafin <stephan@soliotek.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
6 years agoclk: sunxi-ng: Add A64 clocks
Maxime Ripard [Wed, 6 Jul 2016 06:31:34 +0000 (08:31 +0200)]
clk: sunxi-ng: Add A64 clocks

Add the A64 CCU clocks set.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
6 years agoclk: qcom: Add freq tables for a few rcgs
Rajendra Nayak [Wed, 19 Oct 2016 11:28:40 +0000 (16:58 +0530)]
clk: qcom: Add freq tables for a few rcgs

Add frequency tables for a few RCG clocks in msm8996

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoclk: qcom: Add .is_enabled ops for clk-alpha-pll
Rajendra Nayak [Thu, 29 Sep 2016 08:35:46 +0000 (14:05 +0530)]
clk: qcom: Add .is_enabled ops for clk-alpha-pll

This would be useful in subsequent patches when the .set_rate operation
would need to identify if the PLL is actually enabled

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Simplify return statement of is_enabled op]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
6 years agoMerge branch 'rcar-rst' into clk-renesas-for-v4.10
Geert Uytterhoeven [Wed, 2 Nov 2016 19:53:26 +0000 (20:53 +0100)]
Merge branch 'rcar-rst' into clk-renesas-for-v4.10

soc: renesas: Add R-Car RST driver for obtaining mode pin state

6 years agoclk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init()
Geert Uytterhoeven [Wed, 1 Jun 2016 13:26:53 +0000 (15:26 +0200)]
clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init()

The R-Car Gen2 board code no longer calls rcar_gen2_clocks_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
6 years agoclk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init()
Geert Uytterhoeven [Wed, 1 Jun 2016 13:24:58 +0000 (15:24 +0200)]
clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init()

The R-Car H1 board code no longer calls r8a7779_clocks_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
6 years agoclk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init()
Geert Uytterhoeven [Wed, 1 Jun 2016 13:23:22 +0000 (15:23 +0200)]
clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init()

The R-Car M1A board code no longer calls r8a7778_clocks_init().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>