openrisc: add tick timer multi-core sync logic
[sfrench/cifs-2.6.git] / arch / openrisc / kernel / smp.c
2017-11-03 Stafford Horneopenrisc: add tick timer multi-core sync logic
2017-11-03 Jan Henrik Weinstockopenrisc: add cacheflush support to fix icache aliasing
2017-11-03 Stafford Horneopenrisc: sleep instead of spin on secondary wait
2017-11-03 Stafford Horneopenrisc: fix initial preempt state for secondary cpu...
2017-11-03 Stefan Kristianssonopenrisc: initial SMP support