ARM64: dts: Add QSPI Device Tree node for NS2

Adding QSPI node compatible with the new spi-bcm-qspi driver for the Broadcom's
Northstar2 SoC.

Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index 2d7872a36b91232c1007358dfdea212052dac0b1..730848740f74279d21f05941ed7797784549c6fa 100644 (file)
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -185,3 +185,37 @@
                groups = "nand_grp";
        };
 };
+
+&qspi {
+       bspi-sel = <0>;
+       flash: m25p80@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "m25p80";
+               reg = <0x0>;
+               spi-max-frequency = <12500000>;
+               m25p,fast-read;
+               spi-cpol;
+               spi-cpha;
+
+               partition@0 {
+                       label = "boot";
+                       reg = <0x00000000 0x000a0000>;
+               };
+
+               partition@a0000 {
+                       label = "env";
+                       reg = <0x000a0000 0x00060000>;
+               };
+
+               partition@100000 {
+                       label = "system";
+                       reg = <0x00100000 0x00600000>;
+               };
+
+               partition@700000 {
+                       label = "rootfs";
+                       reg = <0x00700000 0x01900000>;
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index d95dc408629ad5ab93a37fb01c1a5d2182b2aedf..ae6c920da56ca813781626131234e15c70b722b8 100644 (file)
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -565,5 +565,23 @@
 
                        brcm,nand-has-wp;
                };
+
+               qspi: spi@66470200 {
+                       compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
+                       reg = <0x66470200 0x184>,
+                               <0x66470000 0x124>,
+                               <0x67017408 0x004>,
+                               <0x664703a0 0x01c>;
+                       reg-names = "mspi", "bspi", "intr_regs",
+                               "intr_status_reg";
+                       interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "spi_l1_intr";
+                       clocks = <&iprocmed>;
+                       clock-names = "iprocmed";
+                       num-cs = <2>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
        };
 };